2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <plat/clock.h>
28 #include <plat/clockdomain.h>
30 #include <plat/prcm.h>
31 #include <asm/div64.h>
33 #include <plat/sdrc.h>
37 #include "prm-regbits-24xx.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
42 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
43 #define DPLL_MIN_MULTIPLIER 1
44 #define DPLL_MIN_DIVIDER 1
46 /* Possible error results from _dpll_test_mult */
47 #define DPLL_MULT_UNDERFLOW -1
50 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
51 * The higher the scale factor, the greater the risk of arithmetic overflow,
52 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
53 * must be a power of DPLL_SCALE_BASE.
55 #define DPLL_SCALE_FACTOR 64
56 #define DPLL_SCALE_BASE 2
57 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
58 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
60 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
61 #define DPLL_FINT_BAND1_MIN 750000
62 #define DPLL_FINT_BAND1_MAX 2100000
63 #define DPLL_FINT_BAND2_MIN 7500000
64 #define DPLL_FINT_BAND2_MAX 21000000
66 /* _dpll_test_fint() return codes */
67 #define DPLL_FINT_UNDERFLOW -1
68 #define DPLL_FINT_INVALID -2
72 /*-------------------------------------------------------------------------
73 * OMAP2/3 specific clock functions
74 *-------------------------------------------------------------------------*/
77 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
80 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
81 * don't take effect until the VALID_CONFIG bit is written, write the
82 * VALID_CONFIG bit and wait for the write to complete. No return value.
84 static void _omap2xxx_clk_commit(struct clk *clk)
86 if (!cpu_is_omap24xx())
89 if (!(clk->flags & DELAYED_APP))
92 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
93 OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
95 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
99 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
100 * @clk: DPLL struct clk to test
101 * @n: divider value (N) to test
103 * Tests whether a particular divider @n will result in a valid DPLL
104 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
105 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
106 * (assuming that it is counting N upwards), or -2 if the enclosing loop
107 * should skip to the next iteration (again assuming N is increasing).
109 static int _dpll_test_fint(struct clk *clk, u8 n)
111 struct dpll_data *dd;
117 /* DPLL divider must result in a valid jitter correction val */
118 fint = clk->parent->rate / (n + 1);
119 if (fint < DPLL_FINT_BAND1_MIN) {
121 pr_debug("rejecting n=%d due to Fint failure, "
122 "lowering max_divider\n", n);
124 ret = DPLL_FINT_UNDERFLOW;
126 } else if (fint > DPLL_FINT_BAND1_MAX &&
127 fint < DPLL_FINT_BAND2_MIN) {
129 pr_debug("rejecting n=%d due to Fint failure\n", n);
130 ret = DPLL_FINT_INVALID;
132 } else if (fint > DPLL_FINT_BAND2_MAX) {
134 pr_debug("rejecting n=%d due to Fint failure, "
135 "boosting min_divider\n", n);
137 ret = DPLL_FINT_INVALID;
145 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
146 * @clk: OMAP clock struct ptr to use
148 * Convert a clockdomain name stored in a struct clk 'clk' into a
149 * clockdomain pointer, and save it into the struct clk. Intended to be
150 * called during clk_register(). No return value.
152 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
153 void omap2_init_clk_clkdm(struct clk *clk)
155 struct clockdomain *clkdm;
157 if (!clk->clkdm_name)
160 clkdm = clkdm_lookup(clk->clkdm_name);
162 pr_debug("clock: associated clk %s to clkdm %s\n",
163 clk->name, clk->clkdm_name);
166 pr_debug("clock: could not associate clk %s to "
167 "clkdm %s\n", clk->name, clk->clkdm_name);
173 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
174 * @clk: OMAP clock struct ptr to use
176 * Given a pointer to a source-selectable struct clk, read the hardware
177 * register and determine what its parent is currently set to. Update the
178 * clk->parent field with the appropriate clk ptr.
180 void omap2_init_clksel_parent(struct clk *clk)
182 const struct clksel *clks;
183 const struct clksel_rate *clkr;
189 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
190 r >>= __ffs(clk->clksel_mask);
192 for (clks = clk->clksel; clks->parent && !found; clks++) {
193 for (clkr = clks->rates; clkr->div && !found; clkr++) {
194 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
195 if (clk->parent != clks->parent) {
196 pr_debug("clock: inited %s parent "
198 clk->name, clks->parent->name,
200 clk->parent->name : "NULL"));
201 clk_reparent(clk, clks->parent);
209 printk(KERN_ERR "clock: init parent: could not find "
210 "regval %0x for clock %s\n", r, clk->name);
216 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
217 * @clk: struct clk * of a DPLL
219 * DPLLs can be locked or bypassed - basically, enabled or disabled.
220 * When locked, the DPLL output depends on the M and N values. When
221 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
222 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
223 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
224 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
225 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
226 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
227 * if the clock @clk is not a DPLL.
229 u32 omap2_get_dpll_rate(struct clk *clk)
232 u32 dpll_mult, dpll_div, v;
233 struct dpll_data *dd;
239 /* Return bypass rate if DPLL is bypassed */
240 v = __raw_readl(dd->control_reg);
241 v &= dd->enable_mask;
242 v >>= __ffs(dd->enable_mask);
244 if (cpu_is_omap24xx()) {
245 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
246 v == OMAP2XXX_EN_DPLL_FRBYPASS)
247 return dd->clk_bypass->rate;
248 } else if (cpu_is_omap34xx()) {
249 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
250 v == OMAP3XXX_EN_DPLL_FRBYPASS)
251 return dd->clk_bypass->rate;
252 } else if (cpu_is_omap44xx()) {
253 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
254 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
255 v == OMAP4XXX_EN_DPLL_MNBYPASS)
256 return dd->clk_bypass->rate;
259 v = __raw_readl(dd->mult_div1_reg);
260 dpll_mult = v & dd->mult_mask;
261 dpll_mult >>= __ffs(dd->mult_mask);
262 dpll_div = v & dd->div1_mask;
263 dpll_div >>= __ffs(dd->div1_mask);
265 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
266 do_div(dpll_clk, dpll_div + 1);
272 * Used for clocks that have the same value as the parent clock,
273 * divided by some factor
275 unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
277 WARN_ON(!clk->fixed_div);
279 return clk->parent->rate / clk->fixed_div;
283 * omap2_clk_dflt_find_companion - find companion clock to @clk
284 * @clk: struct clk * to find the companion clock of
285 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
286 * @other_bit: u8 ** to return the companion clock bit shift in
288 * Note: We don't need special code here for INVERT_ENABLE for the
289 * time being since INVERT_ENABLE only applies to clocks enabled by
292 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
293 * just a matter of XORing the bits.
295 * Some clocks don't have companion clocks. For example, modules with
296 * only an interface clock (such as MAILBOXES) don't have a companion
297 * clock. Right now, this code relies on the hardware exporting a bit
298 * in the correct companion register that indicates that the
299 * nonexistent 'companion clock' is active. Future patches will
300 * associate this type of code with per-module data structures to
301 * avoid this issue, and remove the casts. No return value.
303 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
309 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
310 * it's just a matter of XORing the bits.
312 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
314 *other_reg = (__force void __iomem *)r;
315 *other_bit = clk->enable_bit;
319 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
320 * @clk: struct clk * to find IDLEST info for
321 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
322 * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
324 * Return the CM_IDLEST register address and bit shift corresponding
325 * to the module that "owns" this clock. This default code assumes
326 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
327 * the IDLEST register address ID corresponds to the CM_*CLKEN
328 * register address ID (e.g., that CM_FCLKEN2 corresponds to
329 * CM_IDLEST2). This is not true for all modules. No return value.
331 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
336 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
337 *idlest_reg = (__force void __iomem *)r;
338 *idlest_bit = clk->enable_bit;
342 * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
343 * @clk: struct clk * belonging to the module
345 * If the necessary clocks for the OMAP hardware IP block that
346 * corresponds to clock @clk are enabled, then wait for the module to
347 * indicate readiness (i.e., to leave IDLE). This code does not
348 * belong in the clock code and will be moved in the medium term to
349 * module-dependent code. No return value.
351 static void omap2_module_wait_ready(struct clk *clk)
353 void __iomem *companion_reg, *idlest_reg;
354 u8 other_bit, idlest_bit;
356 /* Not all modules have multiple clocks that their IDLEST depends on */
357 if (clk->ops->find_companion) {
358 clk->ops->find_companion(clk, &companion_reg, &other_bit);
359 if (!(__raw_readl(companion_reg) & (1 << other_bit)))
363 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
365 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
368 int omap2_dflt_clk_enable(struct clk *clk)
372 if (unlikely(clk->enable_reg == NULL)) {
373 pr_err("clock.c: Enable for %s without enable code\n",
375 return 0; /* REVISIT: -EINVAL */
378 v = __raw_readl(clk->enable_reg);
379 if (clk->flags & INVERT_ENABLE)
380 v &= ~(1 << clk->enable_bit);
382 v |= (1 << clk->enable_bit);
383 __raw_writel(v, clk->enable_reg);
384 v = __raw_readl(clk->enable_reg); /* OCP barrier */
386 if (clk->ops->find_idlest)
387 omap2_module_wait_ready(clk);
392 void omap2_dflt_clk_disable(struct clk *clk)
396 if (!clk->enable_reg) {
398 * 'Independent' here refers to a clock which is not
399 * controlled by its parent.
401 printk(KERN_ERR "clock: clk_disable called on independent "
402 "clock %s which has no enable_reg\n", clk->name);
406 v = __raw_readl(clk->enable_reg);
407 if (clk->flags & INVERT_ENABLE)
408 v |= (1 << clk->enable_bit);
410 v &= ~(1 << clk->enable_bit);
411 __raw_writel(v, clk->enable_reg);
412 /* No OCP barrier needed here since it is a disable operation */
415 const struct clkops clkops_omap2_dflt_wait = {
416 .enable = omap2_dflt_clk_enable,
417 .disable = omap2_dflt_clk_disable,
418 .find_companion = omap2_clk_dflt_find_companion,
419 .find_idlest = omap2_clk_dflt_find_idlest,
422 const struct clkops clkops_omap2_dflt = {
423 .enable = omap2_dflt_clk_enable,
424 .disable = omap2_dflt_clk_disable,
427 /* Enables clock without considering parent dependencies or use count
428 * REVISIT: Maybe change this to use clk->enable like on omap1?
430 static int _omap2_clk_enable(struct clk *clk)
432 return clk->ops->enable(clk);
435 /* Disables clock without considering parent dependencies or use count */
436 static void _omap2_clk_disable(struct clk *clk)
438 clk->ops->disable(clk);
441 void omap2_clk_disable(struct clk *clk)
443 if (clk->usecount > 0 && !(--clk->usecount)) {
444 _omap2_clk_disable(clk);
446 omap2_clk_disable(clk->parent);
447 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
449 omap2_clkdm_clk_disable(clk->clkdm, clk);
455 int omap2_clk_enable(struct clk *clk)
459 if (clk->usecount++ == 0) {
460 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
462 omap2_clkdm_clk_enable(clk->clkdm, clk);
466 ret = omap2_clk_enable(clk->parent);
471 ret = _omap2_clk_enable(clk);
474 omap2_clk_disable(clk->parent);
482 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
484 omap2_clkdm_clk_disable(clk->clkdm, clk);
491 * Used for clocks that are part of CLKSEL_xyz governed clocks.
492 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
494 unsigned long omap2_clksel_recalc(struct clk *clk)
499 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
501 div = omap2_clksel_get_divisor(clk);
505 rate = clk->parent->rate / div;
507 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
513 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
514 * @clk: OMAP struct clk ptr to inspect
515 * @src_clk: OMAP struct clk ptr of the parent clk to search for
517 * Scan the struct clksel array associated with the clock to find
518 * the element associated with the supplied parent clock address.
519 * Returns a pointer to the struct clksel on success or NULL on error.
521 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
524 const struct clksel *clks;
529 for (clks = clk->clksel; clks->parent; clks++) {
530 if (clks->parent == src_clk)
531 break; /* Found the requested parent */
535 printk(KERN_ERR "clock: Could not find parent clock %s in "
536 "clksel array of clock %s\n", src_clk->name,
545 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
546 * @clk: OMAP struct clk to use
547 * @target_rate: desired clock rate
548 * @new_div: ptr to where we should store the divisor
550 * Finds 'best' divider value in an array based on the source and target
551 * rates. The divider array must be sorted with smallest divider first.
552 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
553 * they are only settable as part of virtual_prcm set.
555 * Returns the rounded clock rate or returns 0xffffffff on error.
557 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
560 unsigned long test_rate;
561 const struct clksel *clks;
562 const struct clksel_rate *clkr;
565 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
566 clk->name, target_rate);
570 clks = omap2_get_clksel_by_parent(clk, clk->parent);
574 for (clkr = clks->rates; clkr->div; clkr++) {
575 if (!(clkr->flags & cpu_mask))
579 if (clkr->div <= last_div)
580 pr_err("clock: clksel_rate table not sorted "
581 "for clock %s", clk->name);
583 last_div = clkr->div;
585 test_rate = clk->parent->rate / clkr->div;
587 if (test_rate <= target_rate)
588 break; /* found it */
592 pr_err("clock: Could not find divisor for target "
593 "rate %ld for clock %s parent %s\n", target_rate,
594 clk->name, clk->parent->name);
598 *new_div = clkr->div;
600 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
601 (clk->parent->rate / clkr->div));
603 return (clk->parent->rate / clkr->div);
607 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
608 * @clk: OMAP struct clk to use
609 * @target_rate: desired clock rate
611 * Compatibility wrapper for OMAP clock framework
612 * Finds best target rate based on the source clock and possible dividers.
613 * rates. The divider array must be sorted with smallest divider first.
614 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
615 * they are only settable as part of virtual_prcm set.
617 * Returns the rounded clock rate or returns 0xffffffff on error.
619 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
623 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
627 /* Given a clock and a rate apply a clock specific rounding function */
628 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
631 return clk->round_rate(clk, rate);
633 if (clk->flags & RATE_FIXED)
634 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
635 "on fixed-rate clock %s\n", clk->name);
641 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
642 * @clk: OMAP struct clk to use
643 * @field_val: register field value to find
645 * Given a struct clk of a rate-selectable clksel clock, and a register field
646 * value to search for, find the corresponding clock divisor. The register
647 * field value should be pre-masked and shifted down so the LSB is at bit 0
648 * before calling. Returns 0 on error
650 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
652 const struct clksel *clks;
653 const struct clksel_rate *clkr;
655 clks = omap2_get_clksel_by_parent(clk, clk->parent);
659 for (clkr = clks->rates; clkr->div; clkr++) {
660 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
665 printk(KERN_ERR "clock: Could not find fieldval %d for "
666 "clock %s parent %s\n", field_val, clk->name,
675 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
676 * @clk: OMAP struct clk to use
677 * @div: integer divisor to search for
679 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
680 * find the corresponding register field value. The return register value is
681 * the value before left-shifting. Returns ~0 on error
683 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
685 const struct clksel *clks;
686 const struct clksel_rate *clkr;
688 /* should never happen */
691 clks = omap2_get_clksel_by_parent(clk, clk->parent);
695 for (clkr = clks->rates; clkr->div; clkr++) {
696 if ((clkr->flags & cpu_mask) && (clkr->div == div))
701 printk(KERN_ERR "clock: Could not find divisor %d for "
702 "clock %s parent %s\n", div, clk->name,
711 * omap2_clksel_get_divisor - get current divider applied to parent clock.
712 * @clk: OMAP struct clk to use.
714 * Returns the integer divisor upon success or 0 on error.
716 u32 omap2_clksel_get_divisor(struct clk *clk)
720 if (!clk->clksel_mask)
723 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
724 v >>= __ffs(clk->clksel_mask);
726 return omap2_clksel_to_divisor(clk, v);
729 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
731 u32 v, field_val, validrate, new_div = 0;
733 if (!clk->clksel_mask)
736 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
737 if (validrate != rate)
740 field_val = omap2_divisor_to_clksel(clk, new_div);
744 v = __raw_readl(clk->clksel_reg);
745 v &= ~clk->clksel_mask;
746 v |= field_val << __ffs(clk->clksel_mask);
747 __raw_writel(v, clk->clksel_reg);
748 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
750 clk->rate = clk->parent->rate / new_div;
752 _omap2xxx_clk_commit(clk);
758 /* Set the clock rate for a clock source */
759 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
763 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
765 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
766 rate table mechanism, driven by mpu_speed */
767 if (clk->flags & CONFIG_PARTICIPANT)
770 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
772 ret = clk->set_rate(clk, rate);
778 * Converts encoded control register address into a full address
779 * On error, the return value (parent_div) will be 0.
781 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
784 const struct clksel *clks;
785 const struct clksel_rate *clkr;
787 clks = omap2_get_clksel_by_parent(clk, src_clk);
791 for (clkr = clks->rates; clkr->div; clkr++) {
792 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
793 break; /* Found the default rate for this platform */
797 printk(KERN_ERR "clock: Could not find default rate for "
798 "clock %s parent %s\n", clk->name,
799 src_clk->parent->name);
803 /* Should never happen. Add a clksel mask to the struct clk. */
804 WARN_ON(clk->clksel_mask == 0);
806 *field_val = clkr->val;
811 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
813 u32 field_val, v, parent_div;
815 if (clk->flags & CONFIG_PARTICIPANT)
821 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
825 /* Set new source value (previous dividers if any in effect) */
826 v = __raw_readl(clk->clksel_reg);
827 v &= ~clk->clksel_mask;
828 v |= field_val << __ffs(clk->clksel_mask);
829 __raw_writel(v, clk->clksel_reg);
830 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
832 _omap2xxx_clk_commit(clk);
834 clk_reparent(clk, new_parent);
836 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
837 clk->rate = new_parent->rate;
840 clk->rate /= parent_div;
842 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
843 clk->name, clk->parent->name, clk->rate);
848 /* DPLL rate rounding code */
851 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
852 * @clk: struct clk * of the DPLL
853 * @tolerance: maximum rate error tolerance
855 * Set the maximum DPLL rate error tolerance for the rate rounding
856 * algorithm. The rate tolerance is an attempt to balance DPLL power
857 * saving (the least divider value "n") vs. rate fidelity (the least
858 * difference between the desired DPLL target rate and the rounded
859 * rate out of the algorithm). So, increasing the tolerance is likely
860 * to decrease DPLL power consumption and increase DPLL rate error.
861 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
862 * DPLL; or 0 upon success.
864 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
866 if (!clk || !clk->dpll_data)
869 clk->dpll_data->rate_tolerance = tolerance;
874 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
875 unsigned int m, unsigned int n)
877 unsigned long long num;
879 num = (unsigned long long)parent_rate * m;
885 * _dpll_test_mult - test a DPLL multiplier value
886 * @m: pointer to the DPLL m (multiplier) value under test
887 * @n: current DPLL n (divider) value under test
888 * @new_rate: pointer to storage for the resulting rounded rate
889 * @target_rate: the desired DPLL rate
890 * @parent_rate: the DPLL's parent clock rate
892 * This code tests a DPLL multiplier value, ensuring that the
893 * resulting rate will not be higher than the target_rate, and that
894 * the multiplier value itself is valid for the DPLL. Initially, the
895 * integer pointed to by the m argument should be prescaled by
896 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
897 * a non-scaled m upon return. This non-scaled m will result in a
898 * new_rate as close as possible to target_rate (but not greater than
899 * target_rate) given the current (parent_rate, n, prescaled m)
900 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
901 * non-scaled m attempted to underflow, which can allow the calling
902 * function to bail out early; or 0 upon success.
904 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
905 unsigned long target_rate,
906 unsigned long parent_rate)
908 int r = 0, carry = 0;
910 /* Unscale m and round if necessary */
911 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
913 *m = (*m / DPLL_SCALE_FACTOR) + carry;
916 * The new rate must be <= the target rate to avoid programming
917 * a rate that is impossible for the hardware to handle
919 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
920 if (*new_rate > target_rate) {
925 /* Guard against m underflow */
926 if (*m < DPLL_MIN_MULTIPLIER) {
927 *m = DPLL_MIN_MULTIPLIER;
929 r = DPLL_MULT_UNDERFLOW;
933 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
939 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
940 * @clk: struct clk * for a DPLL
941 * @target_rate: desired DPLL clock rate
943 * Given a DPLL, a desired target rate, and a rate tolerance, round
944 * the target rate to a possible, programmable rate for this DPLL.
945 * Rate tolerance is assumed to be set by the caller before this
946 * function is called. Attempts to select the minimum possible n
947 * within the tolerance to reduce power consumption. Stores the
948 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
949 * will not need to call this (expensive) function again. Returns ~0
950 * if the target rate cannot be rounded, either because the rate is
951 * too low or because the rate tolerance is set too tightly; or the
952 * rounded rate upon success.
954 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
956 int m, n, r, e, scaled_max_m;
957 unsigned long scaled_rt_rp, new_rate;
958 int min_e = -1, min_e_m = -1, min_e_n = -1;
959 struct dpll_data *dd;
961 if (!clk || !clk->dpll_data)
966 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
967 "%ld\n", clk->name, target_rate);
969 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
970 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
972 dd->last_rounded_rate = 0;
974 for (n = dd->min_divider; n <= dd->max_divider; n++) {
976 /* Is the (input clk, divider) pair valid for the DPLL? */
977 r = _dpll_test_fint(clk, n);
978 if (r == DPLL_FINT_UNDERFLOW)
980 else if (r == DPLL_FINT_INVALID)
983 /* Compute the scaled DPLL multiplier, based on the divider */
984 m = scaled_rt_rp * n;
987 * Since we're counting n up, a m overflow means we
988 * can bail out completely (since as n increases in
989 * the next iteration, there's no way that m can
990 * increase beyond the current m)
992 if (m > scaled_max_m)
995 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
998 /* m can't be set low enough for this n - try with a larger n */
999 if (r == DPLL_MULT_UNDERFLOW)
1002 e = target_rate - new_rate;
1003 pr_debug("clock: n = %d: m = %d: rate error is %d "
1004 "(new_rate = %ld)\n", n, m, e, new_rate);
1007 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
1012 pr_debug("clock: found new least error %d\n", min_e);
1014 /* We found good settings -- bail out now */
1015 if (min_e <= dd->rate_tolerance)
1021 pr_debug("clock: error: target rate or tolerance too low\n");
1025 dd->last_rounded_m = min_e_m;
1026 dd->last_rounded_n = min_e_n;
1027 dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
1030 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1031 min_e, min_e_m, min_e_n);
1032 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1033 dd->last_rounded_rate, target_rate);
1035 return dd->last_rounded_rate;
1038 /*-------------------------------------------------------------------------
1039 * Omap2 clock reset and init functions
1040 *-------------------------------------------------------------------------*/
1042 #ifdef CONFIG_OMAP_RESET_CLOCKS
1043 void omap2_clk_disable_unused(struct clk *clk)
1047 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1049 regval32 = __raw_readl(clk->enable_reg);
1050 if ((regval32 & (1 << clk->enable_bit)) == v)
1053 printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
1054 if (cpu_is_omap34xx()) {
1055 omap2_clk_enable(clk);
1056 omap2_clk_disable(clk);
1058 _omap2_clk_disable(clk);
1059 if (clk->clkdm != NULL)
1060 pwrdm_clkdm_state_switch(clk->clkdm);