2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/clk-provider.h>
25 #include <linux/bitops.h>
26 #include <linux/clk-private.h>
29 #include <trace/events/power.h>
32 #include "clockdomain.h"
37 #include "cm-regbits-24xx.h"
38 #include "cm-regbits-34xx.h"
42 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
43 * for a module to indicate that it is no longer in idle
45 #define MAX_MODULE_ENABLE_WAIT 100000
50 * clkdm_control: if true, then when a clock is enabled in the
51 * hardware, its clockdomain will first be enabled; and when a clock
52 * is disabled in the hardware, its clockdomain will be disabled
55 static bool clkdm_control = true;
57 static LIST_HEAD(clk_hw_omap_clocks);
58 void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
60 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
62 if (clk->flags & MEMMAP_ADDRESSING) {
63 struct clk_omap_reg *r = (struct clk_omap_reg *)®
64 writel_relaxed(val, clk_memmaps[r->index] + r->offset);
66 writel_relaxed(val, reg);
70 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
74 if (clk->flags & MEMMAP_ADDRESSING) {
75 struct clk_omap_reg *r = (struct clk_omap_reg *)®
76 val = readl_relaxed(clk_memmaps[r->index] + r->offset);
78 val = readl_relaxed(reg);
85 * Used for clocks that have the same value as the parent clock,
86 * divided by some factor
88 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
89 unsigned long parent_rate)
91 struct clk_hw_omap *oclk;
94 pr_warn("%s: hw is NULL\n", __func__);
98 oclk = to_clk_hw_omap(hw);
100 WARN_ON(!oclk->fixed_div);
102 return parent_rate / oclk->fixed_div;
106 * OMAP2+ specific clock functions
109 /* Private functions */
113 * _wait_idlest_generic - wait for a module to leave the idle state
114 * @reg: virtual address of module IDLEST register
115 * @mask: value to mask against to determine if the module is active
116 * @idlest: idle state indicator (0 or 1) for the clock
117 * @name: name of the clock (for printk)
119 * Wait for a module to leave idle, where its idle-status register is
120 * not inside the CM module. Returns 1 if the module left idle
121 * promptly, or 0 if the module did not leave idle before the timeout
122 * elapsed. XXX Deprecated - should be moved into drivers for the
123 * individual IP block that the IDLEST register exists in.
125 static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
130 ena = (idlest) ? 0 : mask;
132 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
133 MAX_MODULE_ENABLE_WAIT, i);
135 if (i < MAX_MODULE_ENABLE_WAIT)
136 pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
139 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
140 name, MAX_MODULE_ENABLE_WAIT);
142 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
146 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
147 * @clk: struct clk * belonging to the module
149 * If the necessary clocks for the OMAP hardware IP block that
150 * corresponds to clock @clk are enabled, then wait for the module to
151 * indicate readiness (i.e., to leave IDLE). This code does not
152 * belong in the clock code and will be moved in the medium term to
153 * module-dependent code. No return value.
155 static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
157 void __iomem *companion_reg, *idlest_reg;
158 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
162 /* Not all modules have multiple clocks that their IDLEST depends on */
163 if (clk->ops->find_companion) {
164 clk->ops->find_companion(clk, &companion_reg, &other_bit);
165 if (!(__raw_readl(companion_reg) & (1 << other_bit)))
169 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
170 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
172 /* IDLEST register not in the CM module */
173 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
174 __clk_get_name(clk->hw.clk));
176 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
180 /* Public functions */
183 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
184 * @clk: OMAP clock struct ptr to use
186 * Convert a clockdomain name stored in a struct clk 'clk' into a
187 * clockdomain pointer, and save it into the struct clk. Intended to be
188 * called during clk_register(). No return value.
190 void omap2_init_clk_clkdm(struct clk_hw *hw)
192 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
193 struct clockdomain *clkdm;
194 const char *clk_name;
196 if (!clk->clkdm_name)
199 clk_name = __clk_get_name(hw->clk);
201 clkdm = clkdm_lookup(clk->clkdm_name);
203 pr_debug("clock: associated clk %s to clkdm %s\n",
204 clk_name, clk->clkdm_name);
207 pr_debug("clock: could not associate clk %s to clkdm %s\n",
208 clk_name, clk->clkdm_name);
213 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
215 * Prevent the OMAP clock code from calling into the clockdomain code
216 * when a hardware clock in that clockdomain is enabled or disabled.
217 * Intended to be called at init time from omap*_clk_init(). No
220 void __init omap2_clk_disable_clkdm_control(void)
222 clkdm_control = false;
226 * omap2_clk_dflt_find_companion - find companion clock to @clk
227 * @clk: struct clk * to find the companion clock of
228 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
229 * @other_bit: u8 ** to return the companion clock bit shift in
231 * Note: We don't need special code here for INVERT_ENABLE for the
232 * time being since INVERT_ENABLE only applies to clocks enabled by
235 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
236 * just a matter of XORing the bits.
238 * Some clocks don't have companion clocks. For example, modules with
239 * only an interface clock (such as MAILBOXES) don't have a companion
240 * clock. Right now, this code relies on the hardware exporting a bit
241 * in the correct companion register that indicates that the
242 * nonexistent 'companion clock' is active. Future patches will
243 * associate this type of code with per-module data structures to
244 * avoid this issue, and remove the casts. No return value.
246 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
247 void __iomem **other_reg, u8 *other_bit)
252 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
253 * it's just a matter of XORing the bits.
255 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
257 *other_reg = (__force void __iomem *)r;
258 *other_bit = clk->enable_bit;
262 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
263 * @clk: struct clk * to find IDLEST info for
264 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
265 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
266 * @idlest_val: u8 * to return the idle status indicator
268 * Return the CM_IDLEST register address and bit shift corresponding
269 * to the module that "owns" this clock. This default code assumes
270 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
271 * the IDLEST register address ID corresponds to the CM_*CLKEN
272 * register address ID (e.g., that CM_FCLKEN2 corresponds to
273 * CM_IDLEST2). This is not true for all modules. No return value.
275 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
276 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
280 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
281 *idlest_reg = (__force void __iomem *)r;
282 *idlest_bit = clk->enable_bit;
285 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
286 * 34xx reverses this, just to keep us on our toes
287 * AM35xx uses both, depending on the module.
289 if (cpu_is_omap24xx())
290 *idlest_val = OMAP24XX_CM_IDLEST_VAL;
291 else if (cpu_is_omap34xx())
292 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
299 * omap2_dflt_clk_enable - enable a clock in the hardware
300 * @hw: struct clk_hw * of the clock to enable
302 * Enable the clock @hw in the hardware. We first call into the OMAP
303 * clockdomain code to "enable" the corresponding clockdomain if this
304 * is the first enabled user of the clockdomain. Then program the
305 * hardware to enable the clock. Then wait for the IP block that uses
306 * this clock to leave idle (if applicable). Returns the error value
307 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
308 * if @hw has a null clock enable_reg, or zero upon success.
310 int omap2_dflt_clk_enable(struct clk_hw *hw)
312 struct clk_hw_omap *clk;
316 clk = to_clk_hw_omap(hw);
318 if (clkdm_control && clk->clkdm) {
319 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
321 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
322 __func__, __clk_get_name(hw->clk),
323 clk->clkdm->name, ret);
328 if (unlikely(clk->enable_reg == NULL)) {
329 pr_err("%s: %s missing enable_reg\n", __func__,
330 __clk_get_name(hw->clk));
335 /* FIXME should not have INVERT_ENABLE bit here */
336 v = __raw_readl(clk->enable_reg);
337 if (clk->flags & INVERT_ENABLE)
338 v &= ~(1 << clk->enable_bit);
340 v |= (1 << clk->enable_bit);
341 __raw_writel(v, clk->enable_reg);
342 v = __raw_readl(clk->enable_reg); /* OCP barrier */
344 if (clk->ops && clk->ops->find_idlest)
345 _omap2_module_wait_ready(clk);
350 if (clkdm_control && clk->clkdm)
351 clkdm_clk_disable(clk->clkdm, hw->clk);
356 * omap2_dflt_clk_disable - disable a clock in the hardware
357 * @hw: struct clk_hw * of the clock to disable
359 * Disable the clock @hw in the hardware, and call into the OMAP
360 * clockdomain code to "disable" the corresponding clockdomain if all
361 * clocks/hwmods in that clockdomain are now disabled. No return
364 void omap2_dflt_clk_disable(struct clk_hw *hw)
366 struct clk_hw_omap *clk;
369 clk = to_clk_hw_omap(hw);
370 if (!clk->enable_reg) {
372 * 'independent' here refers to a clock which is not
373 * controlled by its parent.
375 pr_err("%s: independent clock %s has no enable_reg\n",
376 __func__, __clk_get_name(hw->clk));
380 v = __raw_readl(clk->enable_reg);
381 if (clk->flags & INVERT_ENABLE)
382 v |= (1 << clk->enable_bit);
384 v &= ~(1 << clk->enable_bit);
385 __raw_writel(v, clk->enable_reg);
386 /* No OCP barrier needed here since it is a disable operation */
388 if (clkdm_control && clk->clkdm)
389 clkdm_clk_disable(clk->clkdm, hw->clk);
393 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
394 * @hw: struct clk_hw * of the clock being enabled
396 * Increment the usecount of the clockdomain of the clock pointed to
397 * by @hw; if the usecount is 1, the clockdomain will be "enabled."
398 * Only needed for clocks that don't use omap2_dflt_clk_enable() as
399 * their enable function pointer. Passes along the return value of
400 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a
401 * clockdomain, or 0 if clock framework-based clockdomain control is
404 int omap2_clkops_enable_clkdm(struct clk_hw *hw)
406 struct clk_hw_omap *clk;
409 clk = to_clk_hw_omap(hw);
411 if (unlikely(!clk->clkdm)) {
412 pr_err("%s: %s: no clkdm set ?!\n", __func__,
413 __clk_get_name(hw->clk));
417 if (unlikely(clk->enable_reg))
418 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
419 __clk_get_name(hw->clk));
421 if (!clkdm_control) {
422 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
423 __func__, __clk_get_name(hw->clk));
427 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
428 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
429 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
435 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
436 * @hw: struct clk_hw * of the clock being disabled
438 * Decrement the usecount of the clockdomain of the clock pointed to
439 * by @hw; if the usecount is 0, the clockdomain will be "disabled."
440 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their
441 * disable function pointer. No return value.
443 void omap2_clkops_disable_clkdm(struct clk_hw *hw)
445 struct clk_hw_omap *clk;
447 clk = to_clk_hw_omap(hw);
449 if (unlikely(!clk->clkdm)) {
450 pr_err("%s: %s: no clkdm set ?!\n", __func__,
451 __clk_get_name(hw->clk));
455 if (unlikely(clk->enable_reg))
456 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
457 __clk_get_name(hw->clk));
459 if (!clkdm_control) {
460 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
461 __func__, __clk_get_name(hw->clk));
465 clkdm_clk_disable(clk->clkdm, hw->clk);
469 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
470 * @hw: struct clk_hw * to check
472 * Return 1 if the clock represented by @hw is enabled in the
473 * hardware, or 0 otherwise. Intended for use in the struct
474 * clk_ops.is_enabled function pointer.
476 int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
478 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
481 v = __raw_readl(clk->enable_reg);
483 if (clk->flags & INVERT_ENABLE)
484 v ^= BIT(clk->enable_bit);
486 v &= BIT(clk->enable_bit);
491 static int __initdata mpurate;
494 * By default we use the rate set by the bootloader.
495 * You can override this with mpurate= cmdline option.
497 static int __init omap_clk_setup(char *str)
499 get_option(&str, &mpurate);
509 __setup("mpurate=", omap_clk_setup);
512 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock
513 * @clk: struct clk * to initialize
515 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used
516 * temporarily for autoidle handling, until this support can be
517 * integrated into the common clock framework code in some way. No
520 void omap2_init_clk_hw_omap_clocks(struct clk *clk)
522 struct clk_hw_omap *c;
524 if (__clk_get_flags(clk) & CLK_IS_BASIC)
527 c = to_clk_hw_omap(__clk_get_hw(clk));
528 list_add(&c->node, &clk_hw_omap_clocks);
532 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that
535 * Enable clock autoidle on all OMAP clocks that have allow_idle
536 * function pointers associated with them. This function is intended
537 * to be temporary until support for this is added to the common clock
540 int omap2_clk_enable_autoidle_all(void)
542 struct clk_hw_omap *c;
544 list_for_each_entry(c, &clk_hw_omap_clocks, node)
545 if (c->ops && c->ops->allow_idle)
546 c->ops->allow_idle(c);
548 of_ti_clk_allow_autoidle_all();
554 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that
557 * Disable clock autoidle on all OMAP clocks that have allow_idle
558 * function pointers associated with them. This function is intended
559 * to be temporary until support for this is added to the common clock
562 int omap2_clk_disable_autoidle_all(void)
564 struct clk_hw_omap *c;
566 list_for_each_entry(c, &clk_hw_omap_clocks, node)
567 if (c->ops && c->ops->deny_idle)
568 c->ops->deny_idle(c);
570 of_ti_clk_deny_autoidle_all();
576 * omap2_clk_deny_idle - disable autoidle on an OMAP clock
577 * @clk: struct clk * to disable autoidle for
579 * Disable autoidle on an OMAP clock.
581 int omap2_clk_deny_idle(struct clk *clk)
583 struct clk_hw_omap *c;
585 if (__clk_get_flags(clk) & CLK_IS_BASIC)
588 c = to_clk_hw_omap(__clk_get_hw(clk));
589 if (c->ops && c->ops->deny_idle)
590 c->ops->deny_idle(c);
595 * omap2_clk_allow_idle - enable autoidle on an OMAP clock
596 * @clk: struct clk * to enable autoidle for
598 * Enable autoidle on an OMAP clock.
600 int omap2_clk_allow_idle(struct clk *clk)
602 struct clk_hw_omap *c;
604 if (__clk_get_flags(clk) & CLK_IS_BASIC)
607 c = to_clk_hw_omap(__clk_get_hw(clk));
608 if (c->ops && c->ops->allow_idle)
609 c->ops->allow_idle(c);
614 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
615 * @clk_names: ptr to an array of strings of clock names to enable
616 * @num_clocks: number of clock names in @clk_names
618 * Prepare and enable a list of clocks, named by @clk_names. No
619 * return value. XXX Deprecated; only needed until these clocks are
620 * properly claimed and enabled by the drivers or core code that uses
621 * them. XXX What code disables & calls clk_put on these clocks?
623 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
625 struct clk *init_clk;
628 for (i = 0; i < num_clocks; i++) {
629 init_clk = clk_get(NULL, clk_names[i]);
630 clk_prepare_enable(init_clk);
634 const struct clk_hw_omap_ops clkhwops_wait = {
635 .find_idlest = omap2_clk_dflt_find_idlest,
636 .find_companion = omap2_clk_dflt_find_companion,
640 * omap_clocks_register - register an array of omap_clk
641 * @ocs: pointer to an array of omap_clk to register
643 void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
647 for (c = oclks; c < oclks + cnt; c++) {
649 if (!__clk_init(NULL, c->lk.clk))
650 omap2_init_clk_hw_omap_clocks(c->lk.clk);
655 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
656 * @mpurate_ck_name: clk name of the clock to change rate
658 * Change the ARM MPU clock rate to the rate specified on the command
659 * line, if one was specified. @mpurate_ck_name should be
660 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
661 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
662 * handled by the virt_prcm_set clock, but this should be handled by
663 * the OPP layer. XXX This is intended to be handled by the OPP layer
664 * code in the near future and should be removed from the clock code.
665 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
666 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
667 * cannot be found, or 0 upon success.
669 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
671 struct clk *mpurate_ck;
677 mpurate_ck = clk_get(NULL, mpurate_ck_name);
678 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
681 r = clk_set_rate(mpurate_ck, mpurate);
683 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
684 mpurate_ck_name, mpurate, r);
696 * omap2_clk_print_new_rates - print summary of current clock tree rates
697 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
698 * @core_ck_name: clk name for the on-chip CORE_CLK
699 * @mpu_ck_name: clk name for the ARM MPU clock
701 * Prints a short message to the console with the HFCLKIN oscillator
702 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
703 * Called by the boot-time MPU rate switching code. XXX This is intended
704 * to be handled by the OPP layer code in the near future and should be
705 * removed from the clock code. No return value.
707 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
708 const char *core_ck_name,
709 const char *mpu_ck_name)
711 struct clk *hfclkin_ck, *core_ck, *mpu_ck;
712 unsigned long hfclkin_rate;
714 mpu_ck = clk_get(NULL, mpu_ck_name);
715 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
718 core_ck = clk_get(NULL, core_ck_name);
719 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
722 hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
723 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
726 hfclkin_rate = clk_get_rate(hfclkin_ck);
728 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
729 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
730 (clk_get_rate(core_ck) / 1000000),
731 (clk_get_rate(mpu_ck) / 1000000));