2 * linux/arch/arm/mach-omap2/clock.h
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19 #include <plat/clock.h>
21 /* The maximum error between a target DPLL rate and the rounded rate in Hz */
22 #define DEFAULT_DPLL_RATE_TOLERANCE 50000
24 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25 #define CORE_CLK_SRC_32K 0x0
26 #define CORE_CLK_SRC_DPLL 0x1
27 #define CORE_CLK_SRC_DPLL_X2 0x2
29 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
30 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
31 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
32 #define OMAP2XXX_EN_DPLL_LOCKED 0x3
34 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
35 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
36 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
39 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
40 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
41 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
42 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
43 #define OMAP4XXX_EN_DPLL_LOCKED 0x7
45 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
46 #define DPLL_LOW_POWER_STOP 0x1
47 #define DPLL_LOW_POWER_BYPASS 0x5
48 #define DPLL_LOCKED 0x7
50 /* DPLL Type and DCO Selection Flags */
51 #define DPLL_J_TYPE 0x1
52 #define DPLL_NO_DCO_SEL 0x2
54 int omap2_clk_enable(struct clk *clk);
55 void omap2_clk_disable(struct clk *clk);
56 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
57 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
58 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
59 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
60 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
61 unsigned long omap3_dpll_recalc(struct clk *clk);
62 unsigned long omap3_clkoutx2_recalc(struct clk *clk);
63 void omap3_dpll_allow_idle(struct clk *clk);
64 void omap3_dpll_deny_idle(struct clk *clk);
65 u32 omap3_dpll_autoidle_read(struct clk *clk);
66 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
67 int omap3_noncore_dpll_enable(struct clk *clk);
68 void omap3_noncore_dpll_disable(struct clk *clk);
70 #ifdef CONFIG_OMAP_RESET_CLOCKS
71 void omap2_clk_disable_unused(struct clk *clk);
73 #define omap2_clk_disable_unused NULL
76 void omap2_init_clk_clkdm(struct clk *clk);
78 /* clkt_clksel.c public functions */
79 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
81 void omap2_init_clksel_parent(struct clk *clk);
82 unsigned long omap2_clksel_recalc(struct clk *clk);
83 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
84 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
85 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
87 u32 omap2_get_dpll_rate(struct clk *clk);
88 void omap2_init_dpll_parent(struct clk *clk);
90 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
93 #ifdef CONFIG_ARCH_OMAP2
94 void omap2xxx_clk_prepare_for_reboot(void);
96 static inline void omap2xxx_clk_prepare_for_reboot(void)
101 #ifdef CONFIG_ARCH_OMAP3
102 void omap3_clk_prepare_for_reboot(void);
104 static inline void omap3_clk_prepare_for_reboot(void)
109 #ifdef CONFIG_ARCH_OMAP4
110 void omap4_clk_prepare_for_reboot(void);
112 static inline void omap4_clk_prepare_for_reboot(void)
117 int omap2_dflt_clk_enable(struct clk *clk);
118 void omap2_dflt_clk_disable(struct clk *clk);
119 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
121 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
122 u8 *idlest_bit, u8 *idlest_val);
123 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
124 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
125 const char *core_ck_name,
126 const char *mpu_ck_name);
130 extern const struct clkops clkops_omap2_dflt_wait;
131 extern const struct clkops clkops_dummy;
132 extern const struct clkops clkops_omap2_dflt;
134 extern struct clk_functions omap2_clk_functions;
135 extern struct clk *vclk, *sclk;
137 extern const struct clksel_rate gpt_32k_rates[];
138 extern const struct clksel_rate gpt_sys_rates[];
139 extern const struct clksel_rate gfx_l3_rates[];
141 #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
142 extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
143 extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
145 #define omap2_clk_init_cpufreq_table 0
146 #define omap2_clk_exit_cpufreq_table 0
149 extern const struct clkops clkops_omap3_noncore_dpll_ops;