2 * linux/arch/arm/mach-omap2/clock24xx.h
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
23 #include "prm-regbits-24xx.h"
24 #include "cm-regbits-24xx.h"
27 static unsigned long omap2_table_mpu_recalc(struct clk *clk);
28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
31 static unsigned long omap2_osc_clk_recalc(struct clk *clk);
32 static unsigned long omap2_sys_clk_recalc(struct clk *clk);
33 static unsigned long omap2_dpllcore_recalc(struct clk *clk);
34 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
41 unsigned long xtal_speed; /* crystal rate */
42 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
43 unsigned long mpu_speed; /* speed of MPU */
44 unsigned long cm_clksel_mpu; /* mpu divider */
45 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
46 unsigned long cm_clksel_gfx; /* gfx dividers */
47 unsigned long cm_clksel1_core; /* major subsystem dividers */
48 unsigned long cm_clksel1_pll; /* m,n */
49 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
50 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
51 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
56 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
57 * These configurations are characterized by voltage and speed for clocks.
58 * The device is only validated for certain combinations. One way to express
59 * these combinations is via the 'ratio's' which the clocks operate with
60 * respect to each other. These ratio sets are for a given voltage/DPLL
61 * setting. All configurations can be described by a DPLL setting and a ratio
62 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
64 * 2430 differs from 2420 in that there are no more phase synchronizers used.
65 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
66 * 2430 (iva2.1, NOdsp, mdm)
69 /* Core fields for cm_clksel, not ratio governed */
70 #define RX_CLKSEL_DSS1 (0x10 << 8)
71 #define RX_CLKSEL_DSS2 (0x0 << 13)
72 #define RX_CLKSEL_SSI (0x5 << 20)
74 /*-------------------------------------------------------------------------
76 *-------------------------------------------------------------------------*/
78 /* 2430 Ratio's, 2430-Ratio Config 1 */
79 #define R1_CLKSEL_L3 (4 << 0)
80 #define R1_CLKSEL_L4 (2 << 5)
81 #define R1_CLKSEL_USB (4 << 25)
82 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
83 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
84 R1_CLKSEL_L4 | R1_CLKSEL_L3
85 #define R1_CLKSEL_MPU (2 << 0)
86 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
87 #define R1_CLKSEL_DSP (2 << 0)
88 #define R1_CLKSEL_DSP_IF (2 << 5)
89 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
90 #define R1_CLKSEL_GFX (2 << 0)
91 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
92 #define R1_CLKSEL_MDM (4 << 0)
93 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
95 /* 2430-Ratio Config 2 */
96 #define R2_CLKSEL_L3 (6 << 0)
97 #define R2_CLKSEL_L4 (2 << 5)
98 #define R2_CLKSEL_USB (2 << 25)
99 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
100 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
101 R2_CLKSEL_L4 | R2_CLKSEL_L3
102 #define R2_CLKSEL_MPU (2 << 0)
103 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
104 #define R2_CLKSEL_DSP (2 << 0)
105 #define R2_CLKSEL_DSP_IF (3 << 5)
106 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
107 #define R2_CLKSEL_GFX (2 << 0)
108 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
109 #define R2_CLKSEL_MDM (6 << 0)
110 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
112 /* 2430-Ratio Bootm (BYPASS) */
113 #define RB_CLKSEL_L3 (1 << 0)
114 #define RB_CLKSEL_L4 (1 << 5)
115 #define RB_CLKSEL_USB (1 << 25)
116 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
117 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
118 RB_CLKSEL_L4 | RB_CLKSEL_L3
119 #define RB_CLKSEL_MPU (1 << 0)
120 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
121 #define RB_CLKSEL_DSP (1 << 0)
122 #define RB_CLKSEL_DSP_IF (1 << 5)
123 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
124 #define RB_CLKSEL_GFX (1 << 0)
125 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
126 #define RB_CLKSEL_MDM (1 << 0)
127 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
129 /* 2420 Ratio Equivalents */
130 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
131 #define RXX_CLKSEL_SSI (0x8 << 20)
133 /* 2420-PRCM III 532MHz core */
134 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
135 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
136 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
137 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
138 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
139 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
141 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
142 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
143 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
144 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
145 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
146 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
147 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
148 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
149 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
151 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
152 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
154 /* 2420-PRCM II 600MHz core */
155 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
156 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
157 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
158 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
159 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
160 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
161 RII_CLKSEL_L4 | RII_CLKSEL_L3
162 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
163 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
164 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
165 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
166 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
167 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
168 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
169 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
170 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
172 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
173 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
175 /* 2420-PRCM I 660MHz core */
176 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
177 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
178 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
179 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
180 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
181 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
182 RI_CLKSEL_L4 | RI_CLKSEL_L3
183 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
184 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
185 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
186 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
187 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
188 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
189 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
190 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
191 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
193 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
194 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
196 /* 2420-PRCM VII (boot) */
197 #define RVII_CLKSEL_L3 (1 << 0)
198 #define RVII_CLKSEL_L4 (1 << 5)
199 #define RVII_CLKSEL_DSS1 (1 << 8)
200 #define RVII_CLKSEL_DSS2 (0 << 13)
201 #define RVII_CLKSEL_VLYNQ (1 << 15)
202 #define RVII_CLKSEL_SSI (1 << 20)
203 #define RVII_CLKSEL_USB (1 << 25)
205 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
206 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
207 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
209 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
210 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
212 #define RVII_CLKSEL_DSP (1 << 0)
213 #define RVII_CLKSEL_DSP_IF (1 << 5)
214 #define RVII_SYNC_DSP (0 << 7)
215 #define RVII_CLKSEL_IVA (1 << 8)
216 #define RVII_SYNC_IVA (0 << 13)
217 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
218 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
220 #define RVII_CLKSEL_GFX (1 << 0)
221 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
223 /*-------------------------------------------------------------------------
224 * 2430 Target modes: Along with each configuration the CPU has several
225 * modes which goes along with them. Modes mainly are the addition of
226 * describe DPLL combinations to go along with a ratio.
227 *-------------------------------------------------------------------------*/
229 /* Hardware governed */
230 #define MX_48M_SRC (0 << 3)
231 #define MX_54M_SRC (0 << 5)
232 #define MX_APLLS_CLIKIN_12 (3 << 23)
233 #define MX_APLLS_CLIKIN_13 (2 << 23)
234 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
237 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
238 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
240 #define M5A_DPLL_MULT_12 (133 << 12)
241 #define M5A_DPLL_DIV_12 (5 << 8)
242 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
243 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
245 #define M5A_DPLL_MULT_13 (61 << 12)
246 #define M5A_DPLL_DIV_13 (2 << 8)
247 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
248 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
250 #define M5A_DPLL_MULT_19 (55 << 12)
251 #define M5A_DPLL_DIV_19 (3 << 8)
252 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
253 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
255 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
256 #define M5B_DPLL_MULT_12 (50 << 12)
257 #define M5B_DPLL_DIV_12 (2 << 8)
258 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
259 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
261 #define M5B_DPLL_MULT_13 (200 << 12)
262 #define M5B_DPLL_DIV_13 (12 << 8)
264 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
265 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
267 #define M5B_DPLL_MULT_19 (125 << 12)
268 #define M5B_DPLL_DIV_19 (31 << 8)
269 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
270 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
273 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
275 #define M4_DPLL_MULT_12 (133 << 12)
276 #define M4_DPLL_DIV_12 (3 << 8)
277 #define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
278 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
281 #define M4_DPLL_MULT_13 (399 << 12)
282 #define M4_DPLL_DIV_13 (12 << 8)
283 #define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
284 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
287 #define M4_DPLL_MULT_19 (145 << 12)
288 #define M4_DPLL_DIV_19 (6 << 8)
289 #define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
290 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
294 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
296 #define M3_DPLL_MULT_12 (55 << 12)
297 #define M3_DPLL_DIV_12 (1 << 8)
298 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
299 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
301 #define M3_DPLL_MULT_13 (76 << 12)
302 #define M3_DPLL_DIV_13 (2 << 8)
303 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
304 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
306 #define M3_DPLL_MULT_19 (17 << 12)
307 #define M3_DPLL_DIV_19 (0 << 8)
308 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
309 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
313 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
315 #define M2_DPLL_MULT_12 (55 << 12)
316 #define M2_DPLL_DIV_12 (1 << 8)
317 #define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
318 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
321 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
322 * relock time issue */
323 /* Core frequency changed from 330/165 to 329/164 MHz*/
324 #define M2_DPLL_MULT_13 (76 << 12)
325 #define M2_DPLL_DIV_13 (2 << 8)
326 #define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
327 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
330 #define M2_DPLL_MULT_19 (17 << 12)
331 #define M2_DPLL_DIV_19 (0 << 8)
332 #define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
333 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
337 #define MB_DPLL_MULT (1 << 12)
338 #define MB_DPLL_DIV (0 << 8)
339 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
340 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
342 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
343 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
345 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
346 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
349 * 2430 - chassis (sedna)
350 * 165 (ratio1) same as above #2
352 * 133 (ratio2) same as above #4
353 * 110 (ratio2) same as above #3
358 /* PRCM I target DPLL = 2*330MHz = 660MHz */
359 #define MI_DPLL_MULT_12 (55 << 12)
360 #define MI_DPLL_DIV_12 (1 << 8)
361 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
362 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
366 * 2420 Equivalent - mode registers
367 * PRCM II , target DPLL = 2*300MHz = 600MHz
369 #define MII_DPLL_MULT_12 (50 << 12)
370 #define MII_DPLL_DIV_12 (1 << 8)
371 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
372 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
374 #define MII_DPLL_MULT_13 (300 << 12)
375 #define MII_DPLL_DIV_13 (12 << 8)
376 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
377 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
380 /* PRCM III target DPLL = 2*266 = 532MHz*/
381 #define MIII_DPLL_MULT_12 (133 << 12)
382 #define MIII_DPLL_DIV_12 (5 << 8)
383 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
384 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
386 #define MIII_DPLL_MULT_13 (266 << 12)
387 #define MIII_DPLL_DIV_13 (12 << 8)
388 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
389 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
392 /* PRCM VII (boot bypass) */
393 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
394 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
396 /* High and low operation value */
397 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
398 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
400 /* MPU speed defines */
401 #define S12M 12000000
402 #define S13M 13000000
403 #define S19M 19200000
404 #define S26M 26000000
405 #define S100M 100000000
406 #define S133M 133000000
407 #define S150M 150000000
408 #define S164M 164000000
409 #define S165M 165000000
410 #define S199M 199000000
411 #define S200M 200000000
412 #define S266M 266000000
413 #define S300M 300000000
414 #define S329M 329000000
415 #define S330M 330000000
416 #define S399M 399000000
417 #define S400M 400000000
418 #define S532M 532000000
419 #define S600M 600000000
420 #define S658M 658000000
421 #define S660M 660000000
422 #define S798M 798000000
424 /*-------------------------------------------------------------------------
425 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
426 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
427 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
428 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
430 * Filling in table based on H4 boards and 2430-SDPs variants available.
431 * There are quite a few more rates combinations which could be defined.
433 * When multiple values are defined the start up will try and choose the
434 * fastest one. If a 'fast' value is defined, then automatically, the /2
435 * one should be included as it can be used. Generally having more that
436 * one fast set does not make sense, as static timings need to be changed
437 * to change the set. The exception is the bypass setting which is
438 * availble for low power bypass.
440 * Note: This table needs to be sorted, fastest to slowest.
441 *-------------------------------------------------------------------------*/
442 static struct prcm_config rate_table[] = {
444 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
445 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
446 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
447 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
451 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
452 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
453 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
454 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
457 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
458 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
459 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
463 /* PRCM III - FAST */
464 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
465 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
466 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
470 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
471 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
472 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
473 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
477 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
478 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
479 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
480 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
483 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
484 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
485 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
486 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
489 /* PRCM III - SLOW */
490 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
491 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
492 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
493 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
496 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
497 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
498 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
499 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
502 /* PRCM-VII (boot-bypass) */
503 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
504 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
505 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
506 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
509 /* PRCM-VII (boot-bypass) */
510 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
511 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
512 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
513 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
516 /* PRCM #4 - ratio2 (ES2.1) - FAST */
517 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
518 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
519 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
520 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
521 SDRC_RFR_CTRL_133MHz,
524 /* PRCM #2 - ratio1 (ES2) - FAST */
525 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
526 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
527 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
528 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
529 SDRC_RFR_CTRL_165MHz,
532 /* PRCM #5a - ratio1 - FAST */
533 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
534 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
535 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
536 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
537 SDRC_RFR_CTRL_133MHz,
540 /* PRCM #5b - ratio1 - FAST */
541 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
542 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
543 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
544 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
545 SDRC_RFR_CTRL_100MHz,
548 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
549 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
550 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
551 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
552 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
553 SDRC_RFR_CTRL_133MHz,
556 /* PRCM #2 - ratio1 (ES2) - SLOW */
557 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
558 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
559 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
560 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
561 SDRC_RFR_CTRL_165MHz,
564 /* PRCM #5a - ratio1 - SLOW */
565 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
566 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
567 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
568 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
569 SDRC_RFR_CTRL_133MHz,
572 /* PRCM #5b - ratio1 - SLOW*/
573 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
574 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
575 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
576 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
577 SDRC_RFR_CTRL_100MHz,
580 /* PRCM-boot/bypass */
581 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
582 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
583 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
584 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
585 SDRC_RFR_CTRL_BYPASS,
588 /* PRCM-boot/bypass */
589 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
590 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
591 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
592 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
593 SDRC_RFR_CTRL_BYPASS,
596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
599 /*-------------------------------------------------------------------------
602 * NOTE:In many cases here we are assigning a 'default' parent. In many
603 * cases the parent is selectable. The get/set parent calls will also
606 * Many some clocks say always_enabled, but they can be auto idled for
607 * power savings. They will always be available upon clock request.
609 * Several sources are given initial rates which may be wrong, this will
610 * be fixed up in the init func.
612 * Things are broadly separated below by clock domains. It is
613 * noteworthy that most periferals have dependencies on multiple clock
614 * domains. Many get their interface clocks from the L4 domain, but get
615 * functional clocks from fixed sources or other core domain derived
617 *-------------------------------------------------------------------------*/
619 /* Base external input clocks */
620 static struct clk func_32k_ck = {
621 .name = "func_32k_ck",
625 .clkdm_name = "wkup_clkdm",
628 static struct clk secure_32k_ck = {
629 .name = "secure_32k_ck",
633 .clkdm_name = "wkup_clkdm",
636 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
637 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
639 .ops = &clkops_oscck,
640 .clkdm_name = "wkup_clkdm",
641 .recalc = &omap2_osc_clk_recalc,
644 /* Without modem likely 12MHz, with modem likely 13MHz */
645 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
646 .name = "sys_ck", /* ~ ref_clk also */
649 .clkdm_name = "wkup_clkdm",
650 .recalc = &omap2_sys_clk_recalc,
653 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
658 .clkdm_name = "wkup_clkdm",
662 * Analog domain root source clocks
665 /* dpll_ck, is broken out in to special cases through clksel */
666 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
670 static struct dpll_data dpll_dd = {
671 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
672 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
673 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
674 .clk_bypass = &sys_ck,
676 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
677 .enable_mask = OMAP24XX_EN_DPLL_MASK,
678 .max_multiplier = 1024,
681 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
685 * XXX Cannot add round_rate here yet, as this is still a composite clock,
688 static struct clk dpll_ck = {
691 .parent = &sys_ck, /* Can be func_32k also */
692 .dpll_data = &dpll_dd,
693 .clkdm_name = "wkup_clkdm",
694 .recalc = &omap2_dpllcore_recalc,
695 .set_rate = &omap2_reprogram_dpllcore,
698 static struct clk apll96_ck = {
700 .ops = &clkops_fixed,
703 .flags = RATE_FIXED | ENABLE_ON_INIT,
704 .clkdm_name = "wkup_clkdm",
705 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
706 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
709 static struct clk apll54_ck = {
711 .ops = &clkops_fixed,
714 .flags = RATE_FIXED | ENABLE_ON_INIT,
715 .clkdm_name = "wkup_clkdm",
716 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
717 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
721 * PRCM digital base sources
726 static const struct clksel_rate func_54m_apll54_rates[] = {
727 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
731 static const struct clksel_rate func_54m_alt_rates[] = {
732 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
736 static const struct clksel func_54m_clksel[] = {
737 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
738 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
742 static struct clk func_54m_ck = {
743 .name = "func_54m_ck",
745 .parent = &apll54_ck, /* can also be alt_clk */
746 .clkdm_name = "wkup_clkdm",
747 .init = &omap2_init_clksel_parent,
748 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
749 .clksel_mask = OMAP24XX_54M_SOURCE,
750 .clksel = func_54m_clksel,
751 .recalc = &omap2_clksel_recalc,
754 static struct clk core_ck = {
757 .parent = &dpll_ck, /* can also be 32k */
758 .clkdm_name = "wkup_clkdm",
759 .recalc = &followparent_recalc,
763 static const struct clksel_rate func_96m_apll96_rates[] = {
764 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
768 static const struct clksel_rate func_96m_alt_rates[] = {
769 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
773 static const struct clksel func_96m_clksel[] = {
774 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
775 { .parent = &alt_ck, .rates = func_96m_alt_rates },
779 /* The parent of this clock is not selectable on 2420. */
780 static struct clk func_96m_ck = {
781 .name = "func_96m_ck",
783 .parent = &apll96_ck,
784 .clkdm_name = "wkup_clkdm",
785 .init = &omap2_init_clksel_parent,
786 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
787 .clksel_mask = OMAP2430_96M_SOURCE,
788 .clksel = func_96m_clksel,
789 .recalc = &omap2_clksel_recalc,
790 .round_rate = &omap2_clksel_round_rate,
791 .set_rate = &omap2_clksel_set_rate
796 static const struct clksel_rate func_48m_apll96_rates[] = {
797 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
801 static const struct clksel_rate func_48m_alt_rates[] = {
802 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
806 static const struct clksel func_48m_clksel[] = {
807 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
808 { .parent = &alt_ck, .rates = func_48m_alt_rates },
812 static struct clk func_48m_ck = {
813 .name = "func_48m_ck",
815 .parent = &apll96_ck, /* 96M or Alt */
816 .clkdm_name = "wkup_clkdm",
817 .init = &omap2_init_clksel_parent,
818 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
819 .clksel_mask = OMAP24XX_48M_SOURCE,
820 .clksel = func_48m_clksel,
821 .recalc = &omap2_clksel_recalc,
822 .round_rate = &omap2_clksel_round_rate,
823 .set_rate = &omap2_clksel_set_rate
826 static struct clk func_12m_ck = {
827 .name = "func_12m_ck",
829 .parent = &func_48m_ck,
831 .clkdm_name = "wkup_clkdm",
832 .recalc = &omap2_fixed_divisor_recalc,
835 /* Secure timer, only available in secure mode */
836 static struct clk wdt1_osc_ck = {
837 .name = "ck_wdt1_osc",
838 .ops = &clkops_null, /* RMK: missing? */
840 .recalc = &followparent_recalc,
844 * The common_clkout* clksel_rate structs are common to
845 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
846 * sys_clkout2_* are 2420-only, so the
847 * clksel_rate flags fields are inaccurate for those clocks. This is
848 * harmless since access to those clocks are gated by the struct clk
849 * flags fields, which mark them as 2420-only.
851 static const struct clksel_rate common_clkout_src_core_rates[] = {
852 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
856 static const struct clksel_rate common_clkout_src_sys_rates[] = {
857 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
861 static const struct clksel_rate common_clkout_src_96m_rates[] = {
862 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
866 static const struct clksel_rate common_clkout_src_54m_rates[] = {
867 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
871 static const struct clksel common_clkout_src_clksel[] = {
872 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
873 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
874 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
875 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
879 static struct clk sys_clkout_src = {
880 .name = "sys_clkout_src",
881 .ops = &clkops_omap2_dflt,
882 .parent = &func_54m_ck,
883 .clkdm_name = "wkup_clkdm",
884 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
885 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
886 .init = &omap2_init_clksel_parent,
887 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
888 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
889 .clksel = common_clkout_src_clksel,
890 .recalc = &omap2_clksel_recalc,
891 .round_rate = &omap2_clksel_round_rate,
892 .set_rate = &omap2_clksel_set_rate
895 static const struct clksel_rate common_clkout_rates[] = {
896 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
897 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
898 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
899 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
900 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
904 static const struct clksel sys_clkout_clksel[] = {
905 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
909 static struct clk sys_clkout = {
910 .name = "sys_clkout",
912 .parent = &sys_clkout_src,
913 .clkdm_name = "wkup_clkdm",
914 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
915 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
916 .clksel = sys_clkout_clksel,
917 .recalc = &omap2_clksel_recalc,
918 .round_rate = &omap2_clksel_round_rate,
919 .set_rate = &omap2_clksel_set_rate
922 /* In 2430, new in 2420 ES2 */
923 static struct clk sys_clkout2_src = {
924 .name = "sys_clkout2_src",
925 .ops = &clkops_omap2_dflt,
926 .parent = &func_54m_ck,
927 .clkdm_name = "wkup_clkdm",
928 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
929 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
930 .init = &omap2_init_clksel_parent,
931 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
932 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
933 .clksel = common_clkout_src_clksel,
934 .recalc = &omap2_clksel_recalc,
935 .round_rate = &omap2_clksel_round_rate,
936 .set_rate = &omap2_clksel_set_rate
939 static const struct clksel sys_clkout2_clksel[] = {
940 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
944 /* In 2430, new in 2420 ES2 */
945 static struct clk sys_clkout2 = {
946 .name = "sys_clkout2",
948 .parent = &sys_clkout2_src,
949 .clkdm_name = "wkup_clkdm",
950 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
951 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
952 .clksel = sys_clkout2_clksel,
953 .recalc = &omap2_clksel_recalc,
954 .round_rate = &omap2_clksel_round_rate,
955 .set_rate = &omap2_clksel_set_rate
958 static struct clk emul_ck = {
960 .ops = &clkops_omap2_dflt,
961 .parent = &func_54m_ck,
962 .clkdm_name = "wkup_clkdm",
963 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
964 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
965 .recalc = &followparent_recalc,
973 * INT_M_FCLK, INT_M_I_CLK
975 * - Individual clocks are hardware managed.
976 * - Base divider comes from: CM_CLKSEL_MPU
979 static const struct clksel_rate mpu_core_rates[] = {
980 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
981 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
982 { .div = 4, .val = 4, .flags = RATE_IN_242X },
983 { .div = 6, .val = 6, .flags = RATE_IN_242X },
984 { .div = 8, .val = 8, .flags = RATE_IN_242X },
988 static const struct clksel mpu_clksel[] = {
989 { .parent = &core_ck, .rates = mpu_core_rates },
993 static struct clk mpu_ck = { /* Control cpu */
997 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
998 .clkdm_name = "mpu_clkdm",
999 .init = &omap2_init_clksel_parent,
1000 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1001 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
1002 .clksel = mpu_clksel,
1003 .recalc = &omap2_clksel_recalc,
1004 .round_rate = &omap2_clksel_round_rate,
1005 .set_rate = &omap2_clksel_set_rate
1009 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1011 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1012 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1014 * Won't be too specific here. The core clock comes into this block
1015 * it is divided then tee'ed. One branch goes directly to xyz enable
1016 * controls. The other branch gets further divided by 2 then possibly
1017 * routed into a synchronizer and out of clocks abc.
1019 static const struct clksel_rate dsp_fck_core_rates[] = {
1020 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1021 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1022 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1023 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1024 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1025 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1026 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1030 static const struct clksel dsp_fck_clksel[] = {
1031 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1035 static struct clk dsp_fck = {
1037 .ops = &clkops_omap2_dflt_wait,
1039 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1040 .clkdm_name = "dsp_clkdm",
1041 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1042 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1043 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1044 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1045 .clksel = dsp_fck_clksel,
1046 .recalc = &omap2_clksel_recalc,
1047 .round_rate = &omap2_clksel_round_rate,
1048 .set_rate = &omap2_clksel_set_rate
1051 /* DSP interface clock */
1052 static const struct clksel_rate dsp_irate_ick_rates[] = {
1053 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1054 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1055 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1059 static const struct clksel dsp_irate_ick_clksel[] = {
1060 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1064 /* This clock does not exist as such in the TRM. */
1065 static struct clk dsp_irate_ick = {
1066 .name = "dsp_irate_ick",
1067 .ops = &clkops_null,
1069 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1070 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1071 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1072 .clksel = dsp_irate_ick_clksel,
1073 .recalc = &omap2_clksel_recalc,
1074 .round_rate = &omap2_clksel_round_rate,
1075 .set_rate = &omap2_clksel_set_rate
1079 static struct clk dsp_ick = {
1080 .name = "dsp_ick", /* apparently ipi and isp */
1081 .ops = &clkops_omap2_dflt_wait,
1082 .parent = &dsp_irate_ick,
1083 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1084 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1085 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1088 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1089 static struct clk iva2_1_ick = {
1090 .name = "iva2_1_ick",
1091 .ops = &clkops_omap2_dflt_wait,
1092 .parent = &dsp_irate_ick,
1093 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1094 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1095 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1099 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1100 * the C54x, but which is contained in the DSP powerdomain. Does not
1101 * exist on later OMAPs.
1103 static struct clk iva1_ifck = {
1104 .name = "iva1_ifck",
1105 .ops = &clkops_omap2_dflt_wait,
1107 .flags = CONFIG_PARTICIPANT | DELAYED_APP,
1108 .clkdm_name = "iva1_clkdm",
1109 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1110 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1111 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1112 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1113 .clksel = dsp_fck_clksel,
1114 .recalc = &omap2_clksel_recalc,
1115 .round_rate = &omap2_clksel_round_rate,
1116 .set_rate = &omap2_clksel_set_rate
1119 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1120 static struct clk iva1_mpu_int_ifck = {
1121 .name = "iva1_mpu_int_ifck",
1122 .ops = &clkops_omap2_dflt_wait,
1123 .parent = &iva1_ifck,
1124 .clkdm_name = "iva1_clkdm",
1125 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1126 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1128 .recalc = &omap2_fixed_divisor_recalc,
1133 * L3 clocks are used for both interface and functional clocks to
1134 * multiple entities. Some of these clocks are completely managed
1135 * by hardware, and some others allow software control. Hardware
1136 * managed ones general are based on directly CLK_REQ signals and
1137 * various auto idle settings. The functional spec sets many of these
1138 * as 'tie-high' for their enables.
1141 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1146 * GPMC memories and SDRC have timing and clock sensitive registers which
1147 * may very well need notification when the clock changes. Currently for low
1148 * operating points, these are taken care of in sleep.S.
1150 static const struct clksel_rate core_l3_core_rates[] = {
1151 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1152 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1153 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1154 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1155 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1156 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1157 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1161 static const struct clksel core_l3_clksel[] = {
1162 { .parent = &core_ck, .rates = core_l3_core_rates },
1166 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1167 .name = "core_l3_ck",
1168 .ops = &clkops_null,
1170 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1171 .clkdm_name = "core_l3_clkdm",
1172 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1173 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1174 .clksel = core_l3_clksel,
1175 .recalc = &omap2_clksel_recalc,
1176 .round_rate = &omap2_clksel_round_rate,
1177 .set_rate = &omap2_clksel_set_rate
1181 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1182 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1183 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1184 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1188 static const struct clksel usb_l4_ick_clksel[] = {
1189 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1193 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1194 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1195 .name = "usb_l4_ick",
1196 .ops = &clkops_omap2_dflt_wait,
1197 .parent = &core_l3_ck,
1198 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1199 .clkdm_name = "core_l4_clkdm",
1200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1201 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1202 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1203 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1204 .clksel = usb_l4_ick_clksel,
1205 .recalc = &omap2_clksel_recalc,
1206 .round_rate = &omap2_clksel_round_rate,
1207 .set_rate = &omap2_clksel_set_rate
1211 * L4 clock management domain
1213 * This domain contains lots of interface clocks from the L4 interface, some
1214 * functional clocks. Fixed APLL functional source clocks are managed in
1217 static const struct clksel_rate l4_core_l3_rates[] = {
1218 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1219 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1223 static const struct clksel l4_clksel[] = {
1224 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1228 static struct clk l4_ck = { /* used both as an ick and fck */
1230 .ops = &clkops_null,
1231 .parent = &core_l3_ck,
1232 .flags = DELAYED_APP,
1233 .clkdm_name = "core_l4_clkdm",
1234 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1235 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1236 .clksel = l4_clksel,
1237 .recalc = &omap2_clksel_recalc,
1238 .round_rate = &omap2_clksel_round_rate,
1239 .set_rate = &omap2_clksel_set_rate
1243 * SSI is in L3 management domain, its direct parent is core not l3,
1244 * many core power domain entities are grouped into the L3 clock
1246 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1248 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1250 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1251 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1252 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1253 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1254 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1255 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1256 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1257 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1261 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1262 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1266 static struct clk ssi_ssr_sst_fck = {
1268 .ops = &clkops_omap2_dflt_wait,
1270 .flags = DELAYED_APP,
1271 .clkdm_name = "core_l3_clkdm",
1272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1273 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1274 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1275 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1276 .clksel = ssi_ssr_sst_fck_clksel,
1277 .recalc = &omap2_clksel_recalc,
1278 .round_rate = &omap2_clksel_round_rate,
1279 .set_rate = &omap2_clksel_set_rate
1283 * Presumably this is the same as SSI_ICLK.
1284 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1286 static struct clk ssi_l4_ick = {
1287 .name = "ssi_l4_ick",
1288 .ops = &clkops_omap2_dflt_wait,
1290 .clkdm_name = "core_l4_clkdm",
1291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1292 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1293 .recalc = &followparent_recalc,
1300 * GFX_FCLK, GFX_ICLK
1301 * GFX_CG1(2d), GFX_CG2(3d)
1303 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1304 * The 2d and 3d clocks run at a hardware determined
1305 * divided value of fclk.
1308 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1310 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1311 static const struct clksel gfx_fck_clksel[] = {
1312 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1316 static struct clk gfx_3d_fck = {
1317 .name = "gfx_3d_fck",
1318 .ops = &clkops_omap2_dflt_wait,
1319 .parent = &core_l3_ck,
1320 .clkdm_name = "gfx_clkdm",
1321 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1322 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1323 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1324 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1325 .clksel = gfx_fck_clksel,
1326 .recalc = &omap2_clksel_recalc,
1327 .round_rate = &omap2_clksel_round_rate,
1328 .set_rate = &omap2_clksel_set_rate
1331 static struct clk gfx_2d_fck = {
1332 .name = "gfx_2d_fck",
1333 .ops = &clkops_omap2_dflt_wait,
1334 .parent = &core_l3_ck,
1335 .clkdm_name = "gfx_clkdm",
1336 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1337 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1338 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1339 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1340 .clksel = gfx_fck_clksel,
1341 .recalc = &omap2_clksel_recalc,
1342 .round_rate = &omap2_clksel_round_rate,
1343 .set_rate = &omap2_clksel_set_rate
1346 static struct clk gfx_ick = {
1347 .name = "gfx_ick", /* From l3 */
1348 .ops = &clkops_omap2_dflt_wait,
1349 .parent = &core_l3_ck,
1350 .clkdm_name = "gfx_clkdm",
1351 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1352 .enable_bit = OMAP_EN_GFX_SHIFT,
1353 .recalc = &followparent_recalc,
1357 * Modem clock domain (2430)
1361 * These clocks are usable in chassis mode only.
1363 static const struct clksel_rate mdm_ick_core_rates[] = {
1364 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1365 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1366 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1367 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1371 static const struct clksel mdm_ick_clksel[] = {
1372 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1376 static struct clk mdm_ick = { /* used both as a ick and fck */
1378 .ops = &clkops_omap2_dflt_wait,
1380 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1381 .clkdm_name = "mdm_clkdm",
1382 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1383 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1384 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1385 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1386 .clksel = mdm_ick_clksel,
1387 .recalc = &omap2_clksel_recalc,
1388 .round_rate = &omap2_clksel_round_rate,
1389 .set_rate = &omap2_clksel_set_rate
1392 static struct clk mdm_osc_ck = {
1393 .name = "mdm_osc_ck",
1394 .ops = &clkops_omap2_dflt_wait,
1396 .clkdm_name = "mdm_clkdm",
1397 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1398 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1399 .recalc = &followparent_recalc,
1405 * DSS_L4_ICLK, DSS_L3_ICLK,
1406 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1408 * DSS is both initiator and target.
1410 /* XXX Add RATE_NOT_VALIDATED */
1412 static const struct clksel_rate dss1_fck_sys_rates[] = {
1413 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1417 static const struct clksel_rate dss1_fck_core_rates[] = {
1418 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1419 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1420 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1421 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1422 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1423 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1424 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1425 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1426 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1427 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1431 static const struct clksel dss1_fck_clksel[] = {
1432 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1433 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1437 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1439 .ops = &clkops_omap2_dflt,
1440 .parent = &l4_ck, /* really both l3 and l4 */
1441 .clkdm_name = "dss_clkdm",
1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1443 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1444 .recalc = &followparent_recalc,
1447 static struct clk dss1_fck = {
1449 .ops = &clkops_omap2_dflt,
1450 .parent = &core_ck, /* Core or sys */
1451 .flags = DELAYED_APP,
1452 .clkdm_name = "dss_clkdm",
1453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1455 .init = &omap2_init_clksel_parent,
1456 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1457 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1458 .clksel = dss1_fck_clksel,
1459 .recalc = &omap2_clksel_recalc,
1460 .round_rate = &omap2_clksel_round_rate,
1461 .set_rate = &omap2_clksel_set_rate
1464 static const struct clksel_rate dss2_fck_sys_rates[] = {
1465 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1469 static const struct clksel_rate dss2_fck_48m_rates[] = {
1470 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1474 static const struct clksel dss2_fck_clksel[] = {
1475 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1476 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1480 static struct clk dss2_fck = { /* Alt clk used in power management */
1482 .ops = &clkops_omap2_dflt,
1483 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1484 .flags = DELAYED_APP,
1485 .clkdm_name = "dss_clkdm",
1486 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1487 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1488 .init = &omap2_init_clksel_parent,
1489 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1490 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1491 .clksel = dss2_fck_clksel,
1492 .recalc = &followparent_recalc,
1495 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1496 .name = "dss_54m_fck", /* 54m tv clk */
1497 .ops = &clkops_omap2_dflt_wait,
1498 .parent = &func_54m_ck,
1499 .clkdm_name = "dss_clkdm",
1500 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1501 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1502 .recalc = &followparent_recalc,
1506 * CORE power domain ICLK & FCLK defines.
1507 * Many of the these can have more than one possible parent. Entries
1508 * here will likely have an L4 interface parent, and may have multiple
1509 * functional clock parents.
1511 static const struct clksel_rate gpt_alt_rates[] = {
1512 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1516 static const struct clksel omap24xx_gpt_clksel[] = {
1517 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1518 { .parent = &sys_ck, .rates = gpt_sys_rates },
1519 { .parent = &alt_ck, .rates = gpt_alt_rates },
1523 static struct clk gpt1_ick = {
1525 .ops = &clkops_omap2_dflt_wait,
1527 .clkdm_name = "core_l4_clkdm",
1528 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1529 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1530 .recalc = &followparent_recalc,
1533 static struct clk gpt1_fck = {
1535 .ops = &clkops_omap2_dflt_wait,
1536 .parent = &func_32k_ck,
1537 .clkdm_name = "core_l4_clkdm",
1538 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1539 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1540 .init = &omap2_init_clksel_parent,
1541 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1542 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1543 .clksel = omap24xx_gpt_clksel,
1544 .recalc = &omap2_clksel_recalc,
1545 .round_rate = &omap2_clksel_round_rate,
1546 .set_rate = &omap2_clksel_set_rate
1549 static struct clk gpt2_ick = {
1551 .ops = &clkops_omap2_dflt_wait,
1553 .clkdm_name = "core_l4_clkdm",
1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1555 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1556 .recalc = &followparent_recalc,
1559 static struct clk gpt2_fck = {
1561 .ops = &clkops_omap2_dflt_wait,
1562 .parent = &func_32k_ck,
1563 .clkdm_name = "core_l4_clkdm",
1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1566 .init = &omap2_init_clksel_parent,
1567 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1568 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1569 .clksel = omap24xx_gpt_clksel,
1570 .recalc = &omap2_clksel_recalc,
1573 static struct clk gpt3_ick = {
1575 .ops = &clkops_omap2_dflt_wait,
1577 .clkdm_name = "core_l4_clkdm",
1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1579 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1580 .recalc = &followparent_recalc,
1583 static struct clk gpt3_fck = {
1585 .ops = &clkops_omap2_dflt_wait,
1586 .parent = &func_32k_ck,
1587 .clkdm_name = "core_l4_clkdm",
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1589 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1590 .init = &omap2_init_clksel_parent,
1591 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1592 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1593 .clksel = omap24xx_gpt_clksel,
1594 .recalc = &omap2_clksel_recalc,
1597 static struct clk gpt4_ick = {
1599 .ops = &clkops_omap2_dflt_wait,
1601 .clkdm_name = "core_l4_clkdm",
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1604 .recalc = &followparent_recalc,
1607 static struct clk gpt4_fck = {
1609 .ops = &clkops_omap2_dflt_wait,
1610 .parent = &func_32k_ck,
1611 .clkdm_name = "core_l4_clkdm",
1612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1613 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1614 .init = &omap2_init_clksel_parent,
1615 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1616 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1617 .clksel = omap24xx_gpt_clksel,
1618 .recalc = &omap2_clksel_recalc,
1621 static struct clk gpt5_ick = {
1623 .ops = &clkops_omap2_dflt_wait,
1625 .clkdm_name = "core_l4_clkdm",
1626 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1627 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1628 .recalc = &followparent_recalc,
1631 static struct clk gpt5_fck = {
1633 .ops = &clkops_omap2_dflt_wait,
1634 .parent = &func_32k_ck,
1635 .clkdm_name = "core_l4_clkdm",
1636 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1637 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1638 .init = &omap2_init_clksel_parent,
1639 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1640 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1641 .clksel = omap24xx_gpt_clksel,
1642 .recalc = &omap2_clksel_recalc,
1645 static struct clk gpt6_ick = {
1647 .ops = &clkops_omap2_dflt_wait,
1649 .clkdm_name = "core_l4_clkdm",
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1652 .recalc = &followparent_recalc,
1655 static struct clk gpt6_fck = {
1657 .ops = &clkops_omap2_dflt_wait,
1658 .parent = &func_32k_ck,
1659 .clkdm_name = "core_l4_clkdm",
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1661 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1662 .init = &omap2_init_clksel_parent,
1663 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1664 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1665 .clksel = omap24xx_gpt_clksel,
1666 .recalc = &omap2_clksel_recalc,
1669 static struct clk gpt7_ick = {
1671 .ops = &clkops_omap2_dflt_wait,
1673 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1674 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1675 .recalc = &followparent_recalc,
1678 static struct clk gpt7_fck = {
1680 .ops = &clkops_omap2_dflt_wait,
1681 .parent = &func_32k_ck,
1682 .clkdm_name = "core_l4_clkdm",
1683 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1684 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1685 .init = &omap2_init_clksel_parent,
1686 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1687 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1688 .clksel = omap24xx_gpt_clksel,
1689 .recalc = &omap2_clksel_recalc,
1692 static struct clk gpt8_ick = {
1694 .ops = &clkops_omap2_dflt_wait,
1696 .clkdm_name = "core_l4_clkdm",
1697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1698 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1699 .recalc = &followparent_recalc,
1702 static struct clk gpt8_fck = {
1704 .ops = &clkops_omap2_dflt_wait,
1705 .parent = &func_32k_ck,
1706 .clkdm_name = "core_l4_clkdm",
1707 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1708 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1709 .init = &omap2_init_clksel_parent,
1710 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1711 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1712 .clksel = omap24xx_gpt_clksel,
1713 .recalc = &omap2_clksel_recalc,
1716 static struct clk gpt9_ick = {
1718 .ops = &clkops_omap2_dflt_wait,
1720 .clkdm_name = "core_l4_clkdm",
1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1722 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1723 .recalc = &followparent_recalc,
1726 static struct clk gpt9_fck = {
1728 .ops = &clkops_omap2_dflt_wait,
1729 .parent = &func_32k_ck,
1730 .clkdm_name = "core_l4_clkdm",
1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1732 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1733 .init = &omap2_init_clksel_parent,
1734 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1735 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1736 .clksel = omap24xx_gpt_clksel,
1737 .recalc = &omap2_clksel_recalc,
1740 static struct clk gpt10_ick = {
1741 .name = "gpt10_ick",
1742 .ops = &clkops_omap2_dflt_wait,
1744 .clkdm_name = "core_l4_clkdm",
1745 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1746 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1747 .recalc = &followparent_recalc,
1750 static struct clk gpt10_fck = {
1751 .name = "gpt10_fck",
1752 .ops = &clkops_omap2_dflt_wait,
1753 .parent = &func_32k_ck,
1754 .clkdm_name = "core_l4_clkdm",
1755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1756 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1757 .init = &omap2_init_clksel_parent,
1758 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1759 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1760 .clksel = omap24xx_gpt_clksel,
1761 .recalc = &omap2_clksel_recalc,
1764 static struct clk gpt11_ick = {
1765 .name = "gpt11_ick",
1766 .ops = &clkops_omap2_dflt_wait,
1768 .clkdm_name = "core_l4_clkdm",
1769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1770 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1771 .recalc = &followparent_recalc,
1774 static struct clk gpt11_fck = {
1775 .name = "gpt11_fck",
1776 .ops = &clkops_omap2_dflt_wait,
1777 .parent = &func_32k_ck,
1778 .clkdm_name = "core_l4_clkdm",
1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1780 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1781 .init = &omap2_init_clksel_parent,
1782 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1783 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1784 .clksel = omap24xx_gpt_clksel,
1785 .recalc = &omap2_clksel_recalc,
1788 static struct clk gpt12_ick = {
1789 .name = "gpt12_ick",
1790 .ops = &clkops_omap2_dflt_wait,
1792 .clkdm_name = "core_l4_clkdm",
1793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1794 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1795 .recalc = &followparent_recalc,
1798 static struct clk gpt12_fck = {
1799 .name = "gpt12_fck",
1800 .ops = &clkops_omap2_dflt_wait,
1801 .parent = &secure_32k_ck,
1802 .clkdm_name = "core_l4_clkdm",
1803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1804 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1805 .init = &omap2_init_clksel_parent,
1806 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1807 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1808 .clksel = omap24xx_gpt_clksel,
1809 .recalc = &omap2_clksel_recalc,
1812 static struct clk mcbsp1_ick = {
1813 .name = "mcbsp_ick",
1814 .ops = &clkops_omap2_dflt_wait,
1817 .clkdm_name = "core_l4_clkdm",
1818 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1819 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1820 .recalc = &followparent_recalc,
1823 static struct clk mcbsp1_fck = {
1824 .name = "mcbsp_fck",
1825 .ops = &clkops_omap2_dflt_wait,
1827 .parent = &func_96m_ck,
1828 .clkdm_name = "core_l4_clkdm",
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1830 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1831 .recalc = &followparent_recalc,
1834 static struct clk mcbsp2_ick = {
1835 .name = "mcbsp_ick",
1836 .ops = &clkops_omap2_dflt_wait,
1839 .clkdm_name = "core_l4_clkdm",
1840 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1841 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1842 .recalc = &followparent_recalc,
1845 static struct clk mcbsp2_fck = {
1846 .name = "mcbsp_fck",
1847 .ops = &clkops_omap2_dflt_wait,
1849 .parent = &func_96m_ck,
1850 .clkdm_name = "core_l4_clkdm",
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1852 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1853 .recalc = &followparent_recalc,
1856 static struct clk mcbsp3_ick = {
1857 .name = "mcbsp_ick",
1858 .ops = &clkops_omap2_dflt_wait,
1861 .clkdm_name = "core_l4_clkdm",
1862 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1863 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1864 .recalc = &followparent_recalc,
1867 static struct clk mcbsp3_fck = {
1868 .name = "mcbsp_fck",
1869 .ops = &clkops_omap2_dflt_wait,
1871 .parent = &func_96m_ck,
1872 .clkdm_name = "core_l4_clkdm",
1873 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1874 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1875 .recalc = &followparent_recalc,
1878 static struct clk mcbsp4_ick = {
1879 .name = "mcbsp_ick",
1880 .ops = &clkops_omap2_dflt_wait,
1883 .clkdm_name = "core_l4_clkdm",
1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1885 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1886 .recalc = &followparent_recalc,
1889 static struct clk mcbsp4_fck = {
1890 .name = "mcbsp_fck",
1891 .ops = &clkops_omap2_dflt_wait,
1893 .parent = &func_96m_ck,
1894 .clkdm_name = "core_l4_clkdm",
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1896 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1897 .recalc = &followparent_recalc,
1900 static struct clk mcbsp5_ick = {
1901 .name = "mcbsp_ick",
1902 .ops = &clkops_omap2_dflt_wait,
1905 .clkdm_name = "core_l4_clkdm",
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1907 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1908 .recalc = &followparent_recalc,
1911 static struct clk mcbsp5_fck = {
1912 .name = "mcbsp_fck",
1913 .ops = &clkops_omap2_dflt_wait,
1915 .parent = &func_96m_ck,
1916 .clkdm_name = "core_l4_clkdm",
1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1918 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1919 .recalc = &followparent_recalc,
1922 static struct clk mcspi1_ick = {
1923 .name = "mcspi_ick",
1924 .ops = &clkops_omap2_dflt_wait,
1927 .clkdm_name = "core_l4_clkdm",
1928 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1929 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1930 .recalc = &followparent_recalc,
1933 static struct clk mcspi1_fck = {
1934 .name = "mcspi_fck",
1935 .ops = &clkops_omap2_dflt_wait,
1937 .parent = &func_48m_ck,
1938 .clkdm_name = "core_l4_clkdm",
1939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1940 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1941 .recalc = &followparent_recalc,
1944 static struct clk mcspi2_ick = {
1945 .name = "mcspi_ick",
1946 .ops = &clkops_omap2_dflt_wait,
1949 .clkdm_name = "core_l4_clkdm",
1950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1951 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1952 .recalc = &followparent_recalc,
1955 static struct clk mcspi2_fck = {
1956 .name = "mcspi_fck",
1957 .ops = &clkops_omap2_dflt_wait,
1959 .parent = &func_48m_ck,
1960 .clkdm_name = "core_l4_clkdm",
1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1962 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1963 .recalc = &followparent_recalc,
1966 static struct clk mcspi3_ick = {
1967 .name = "mcspi_ick",
1968 .ops = &clkops_omap2_dflt_wait,
1971 .clkdm_name = "core_l4_clkdm",
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1973 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1974 .recalc = &followparent_recalc,
1977 static struct clk mcspi3_fck = {
1978 .name = "mcspi_fck",
1979 .ops = &clkops_omap2_dflt_wait,
1981 .parent = &func_48m_ck,
1982 .clkdm_name = "core_l4_clkdm",
1983 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1984 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1985 .recalc = &followparent_recalc,
1988 static struct clk uart1_ick = {
1989 .name = "uart1_ick",
1990 .ops = &clkops_omap2_dflt_wait,
1992 .clkdm_name = "core_l4_clkdm",
1993 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1994 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1995 .recalc = &followparent_recalc,
1998 static struct clk uart1_fck = {
1999 .name = "uart1_fck",
2000 .ops = &clkops_omap2_dflt_wait,
2001 .parent = &func_48m_ck,
2002 .clkdm_name = "core_l4_clkdm",
2003 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2004 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
2005 .recalc = &followparent_recalc,
2008 static struct clk uart2_ick = {
2009 .name = "uart2_ick",
2010 .ops = &clkops_omap2_dflt_wait,
2012 .clkdm_name = "core_l4_clkdm",
2013 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2014 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2015 .recalc = &followparent_recalc,
2018 static struct clk uart2_fck = {
2019 .name = "uart2_fck",
2020 .ops = &clkops_omap2_dflt_wait,
2021 .parent = &func_48m_ck,
2022 .clkdm_name = "core_l4_clkdm",
2023 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2024 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
2025 .recalc = &followparent_recalc,
2028 static struct clk uart3_ick = {
2029 .name = "uart3_ick",
2030 .ops = &clkops_omap2_dflt_wait,
2032 .clkdm_name = "core_l4_clkdm",
2033 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2034 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2035 .recalc = &followparent_recalc,
2038 static struct clk uart3_fck = {
2039 .name = "uart3_fck",
2040 .ops = &clkops_omap2_dflt_wait,
2041 .parent = &func_48m_ck,
2042 .clkdm_name = "core_l4_clkdm",
2043 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2044 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
2045 .recalc = &followparent_recalc,
2048 static struct clk gpios_ick = {
2049 .name = "gpios_ick",
2050 .ops = &clkops_omap2_dflt_wait,
2052 .clkdm_name = "core_l4_clkdm",
2053 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2054 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2055 .recalc = &followparent_recalc,
2058 static struct clk gpios_fck = {
2059 .name = "gpios_fck",
2060 .ops = &clkops_omap2_dflt_wait,
2061 .parent = &func_32k_ck,
2062 .clkdm_name = "wkup_clkdm",
2063 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2064 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
2065 .recalc = &followparent_recalc,
2068 static struct clk mpu_wdt_ick = {
2069 .name = "mpu_wdt_ick",
2070 .ops = &clkops_omap2_dflt_wait,
2072 .clkdm_name = "core_l4_clkdm",
2073 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2074 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2075 .recalc = &followparent_recalc,
2078 static struct clk mpu_wdt_fck = {
2079 .name = "mpu_wdt_fck",
2080 .ops = &clkops_omap2_dflt_wait,
2081 .parent = &func_32k_ck,
2082 .clkdm_name = "wkup_clkdm",
2083 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2084 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2085 .recalc = &followparent_recalc,
2088 static struct clk sync_32k_ick = {
2089 .name = "sync_32k_ick",
2090 .ops = &clkops_omap2_dflt_wait,
2092 .flags = ENABLE_ON_INIT,
2093 .clkdm_name = "core_l4_clkdm",
2094 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2095 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2096 .recalc = &followparent_recalc,
2099 static struct clk wdt1_ick = {
2101 .ops = &clkops_omap2_dflt_wait,
2103 .clkdm_name = "core_l4_clkdm",
2104 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2105 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2106 .recalc = &followparent_recalc,
2109 static struct clk omapctrl_ick = {
2110 .name = "omapctrl_ick",
2111 .ops = &clkops_omap2_dflt_wait,
2113 .flags = ENABLE_ON_INIT,
2114 .clkdm_name = "core_l4_clkdm",
2115 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2116 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2117 .recalc = &followparent_recalc,
2120 static struct clk icr_ick = {
2122 .ops = &clkops_omap2_dflt_wait,
2124 .clkdm_name = "core_l4_clkdm",
2125 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2126 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2127 .recalc = &followparent_recalc,
2130 static struct clk cam_ick = {
2132 .ops = &clkops_omap2_dflt,
2134 .clkdm_name = "core_l4_clkdm",
2135 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2136 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2137 .recalc = &followparent_recalc,
2141 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2142 * split into two separate clocks, since the parent clocks are different
2143 * and the clockdomains are also different.
2145 static struct clk cam_fck = {
2147 .ops = &clkops_omap2_dflt,
2148 .parent = &func_96m_ck,
2149 .clkdm_name = "core_l3_clkdm",
2150 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2151 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2152 .recalc = &followparent_recalc,
2155 static struct clk mailboxes_ick = {
2156 .name = "mailboxes_ick",
2157 .ops = &clkops_omap2_dflt_wait,
2159 .clkdm_name = "core_l4_clkdm",
2160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2161 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2162 .recalc = &followparent_recalc,
2165 static struct clk wdt4_ick = {
2167 .ops = &clkops_omap2_dflt_wait,
2169 .clkdm_name = "core_l4_clkdm",
2170 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2171 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2172 .recalc = &followparent_recalc,
2175 static struct clk wdt4_fck = {
2177 .ops = &clkops_omap2_dflt_wait,
2178 .parent = &func_32k_ck,
2179 .clkdm_name = "core_l4_clkdm",
2180 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2181 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2182 .recalc = &followparent_recalc,
2185 static struct clk wdt3_ick = {
2187 .ops = &clkops_omap2_dflt_wait,
2189 .clkdm_name = "core_l4_clkdm",
2190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2191 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2192 .recalc = &followparent_recalc,
2195 static struct clk wdt3_fck = {
2197 .ops = &clkops_omap2_dflt_wait,
2198 .parent = &func_32k_ck,
2199 .clkdm_name = "core_l4_clkdm",
2200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2201 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2202 .recalc = &followparent_recalc,
2205 static struct clk mspro_ick = {
2206 .name = "mspro_ick",
2207 .ops = &clkops_omap2_dflt_wait,
2209 .clkdm_name = "core_l4_clkdm",
2210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2211 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2212 .recalc = &followparent_recalc,
2215 static struct clk mspro_fck = {
2216 .name = "mspro_fck",
2217 .ops = &clkops_omap2_dflt_wait,
2218 .parent = &func_96m_ck,
2219 .clkdm_name = "core_l4_clkdm",
2220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2221 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2222 .recalc = &followparent_recalc,
2225 static struct clk mmc_ick = {
2227 .ops = &clkops_omap2_dflt_wait,
2229 .clkdm_name = "core_l4_clkdm",
2230 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2231 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2232 .recalc = &followparent_recalc,
2235 static struct clk mmc_fck = {
2237 .ops = &clkops_omap2_dflt_wait,
2238 .parent = &func_96m_ck,
2239 .clkdm_name = "core_l4_clkdm",
2240 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2241 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2242 .recalc = &followparent_recalc,
2245 static struct clk fac_ick = {
2247 .ops = &clkops_omap2_dflt_wait,
2249 .clkdm_name = "core_l4_clkdm",
2250 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2251 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2252 .recalc = &followparent_recalc,
2255 static struct clk fac_fck = {
2257 .ops = &clkops_omap2_dflt_wait,
2258 .parent = &func_12m_ck,
2259 .clkdm_name = "core_l4_clkdm",
2260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2261 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2262 .recalc = &followparent_recalc,
2265 static struct clk eac_ick = {
2267 .ops = &clkops_omap2_dflt_wait,
2269 .clkdm_name = "core_l4_clkdm",
2270 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2271 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2272 .recalc = &followparent_recalc,
2275 static struct clk eac_fck = {
2277 .ops = &clkops_omap2_dflt_wait,
2278 .parent = &func_96m_ck,
2279 .clkdm_name = "core_l4_clkdm",
2280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2281 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2282 .recalc = &followparent_recalc,
2285 static struct clk hdq_ick = {
2287 .ops = &clkops_omap2_dflt_wait,
2289 .clkdm_name = "core_l4_clkdm",
2290 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2291 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2292 .recalc = &followparent_recalc,
2295 static struct clk hdq_fck = {
2297 .ops = &clkops_omap2_dflt_wait,
2298 .parent = &func_12m_ck,
2299 .clkdm_name = "core_l4_clkdm",
2300 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2301 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2302 .recalc = &followparent_recalc,
2305 static struct clk i2c2_ick = {
2307 .ops = &clkops_omap2_dflt_wait,
2310 .clkdm_name = "core_l4_clkdm",
2311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2312 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2313 .recalc = &followparent_recalc,
2316 static struct clk i2c2_fck = {
2318 .ops = &clkops_omap2_dflt_wait,
2320 .parent = &func_12m_ck,
2321 .clkdm_name = "core_l4_clkdm",
2322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2323 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2324 .recalc = &followparent_recalc,
2327 static struct clk i2chs2_fck = {
2329 .ops = &clkops_omap2_dflt_wait,
2331 .parent = &func_96m_ck,
2332 .clkdm_name = "core_l4_clkdm",
2333 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2334 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2335 .recalc = &followparent_recalc,
2338 static struct clk i2c1_ick = {
2340 .ops = &clkops_omap2_dflt_wait,
2343 .clkdm_name = "core_l4_clkdm",
2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2345 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2346 .recalc = &followparent_recalc,
2349 static struct clk i2c1_fck = {
2351 .ops = &clkops_omap2_dflt_wait,
2353 .parent = &func_12m_ck,
2354 .clkdm_name = "core_l4_clkdm",
2355 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2356 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2357 .recalc = &followparent_recalc,
2360 static struct clk i2chs1_fck = {
2362 .ops = &clkops_omap2_dflt_wait,
2364 .parent = &func_96m_ck,
2365 .clkdm_name = "core_l4_clkdm",
2366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2367 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2368 .recalc = &followparent_recalc,
2371 static struct clk gpmc_fck = {
2373 .ops = &clkops_null, /* RMK: missing? */
2374 .parent = &core_l3_ck,
2375 .flags = ENABLE_ON_INIT,
2376 .clkdm_name = "core_l3_clkdm",
2377 .recalc = &followparent_recalc,
2380 static struct clk sdma_fck = {
2382 .ops = &clkops_null, /* RMK: missing? */
2383 .parent = &core_l3_ck,
2384 .clkdm_name = "core_l3_clkdm",
2385 .recalc = &followparent_recalc,
2388 static struct clk sdma_ick = {
2390 .ops = &clkops_null, /* RMK: missing? */
2392 .clkdm_name = "core_l3_clkdm",
2393 .recalc = &followparent_recalc,
2396 static struct clk vlynq_ick = {
2397 .name = "vlynq_ick",
2398 .ops = &clkops_omap2_dflt_wait,
2399 .parent = &core_l3_ck,
2400 .clkdm_name = "core_l3_clkdm",
2401 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2402 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2403 .recalc = &followparent_recalc,
2406 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2407 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2411 static const struct clksel_rate vlynq_fck_core_rates[] = {
2412 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2413 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2414 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2415 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2416 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2417 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2418 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2419 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2420 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2421 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2425 static const struct clksel vlynq_fck_clksel[] = {
2426 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2427 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2431 static struct clk vlynq_fck = {
2432 .name = "vlynq_fck",
2433 .ops = &clkops_omap2_dflt_wait,
2434 .parent = &func_96m_ck,
2435 .flags = DELAYED_APP,
2436 .clkdm_name = "core_l3_clkdm",
2437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2438 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2439 .init = &omap2_init_clksel_parent,
2440 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2441 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2442 .clksel = vlynq_fck_clksel,
2443 .recalc = &omap2_clksel_recalc,
2444 .round_rate = &omap2_clksel_round_rate,
2445 .set_rate = &omap2_clksel_set_rate
2448 static struct clk sdrc_ick = {
2450 .ops = &clkops_omap2_dflt_wait,
2452 .flags = ENABLE_ON_INIT,
2453 .clkdm_name = "core_l4_clkdm",
2454 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2455 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2456 .recalc = &followparent_recalc,
2459 static struct clk des_ick = {
2461 .ops = &clkops_omap2_dflt_wait,
2463 .clkdm_name = "core_l4_clkdm",
2464 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2465 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2466 .recalc = &followparent_recalc,
2469 static struct clk sha_ick = {
2471 .ops = &clkops_omap2_dflt_wait,
2473 .clkdm_name = "core_l4_clkdm",
2474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2475 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2476 .recalc = &followparent_recalc,
2479 static struct clk rng_ick = {
2481 .ops = &clkops_omap2_dflt_wait,
2483 .clkdm_name = "core_l4_clkdm",
2484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2485 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2486 .recalc = &followparent_recalc,
2489 static struct clk aes_ick = {
2491 .ops = &clkops_omap2_dflt_wait,
2493 .clkdm_name = "core_l4_clkdm",
2494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2495 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2496 .recalc = &followparent_recalc,
2499 static struct clk pka_ick = {
2501 .ops = &clkops_omap2_dflt_wait,
2503 .clkdm_name = "core_l4_clkdm",
2504 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2505 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2506 .recalc = &followparent_recalc,
2509 static struct clk usb_fck = {
2511 .ops = &clkops_omap2_dflt_wait,
2512 .parent = &func_48m_ck,
2513 .clkdm_name = "core_l3_clkdm",
2514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2515 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2516 .recalc = &followparent_recalc,
2519 static struct clk usbhs_ick = {
2520 .name = "usbhs_ick",
2521 .ops = &clkops_omap2_dflt_wait,
2522 .parent = &core_l3_ck,
2523 .clkdm_name = "core_l3_clkdm",
2524 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2525 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2526 .recalc = &followparent_recalc,
2529 static struct clk mmchs1_ick = {
2530 .name = "mmchs_ick",
2531 .ops = &clkops_omap2_dflt_wait,
2533 .clkdm_name = "core_l4_clkdm",
2534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2535 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2536 .recalc = &followparent_recalc,
2539 static struct clk mmchs1_fck = {
2540 .name = "mmchs_fck",
2541 .ops = &clkops_omap2_dflt_wait,
2542 .parent = &func_96m_ck,
2543 .clkdm_name = "core_l3_clkdm",
2544 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2545 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2546 .recalc = &followparent_recalc,
2549 static struct clk mmchs2_ick = {
2550 .name = "mmchs_ick",
2551 .ops = &clkops_omap2_dflt_wait,
2554 .clkdm_name = "core_l4_clkdm",
2555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2556 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2557 .recalc = &followparent_recalc,
2560 static struct clk mmchs2_fck = {
2561 .name = "mmchs_fck",
2562 .ops = &clkops_omap2_dflt_wait,
2564 .parent = &func_96m_ck,
2565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2566 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2567 .recalc = &followparent_recalc,
2570 static struct clk gpio5_ick = {
2571 .name = "gpio5_ick",
2572 .ops = &clkops_omap2_dflt_wait,
2574 .clkdm_name = "core_l4_clkdm",
2575 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2576 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2577 .recalc = &followparent_recalc,
2580 static struct clk gpio5_fck = {
2581 .name = "gpio5_fck",
2582 .ops = &clkops_omap2_dflt_wait,
2583 .parent = &func_32k_ck,
2584 .clkdm_name = "core_l4_clkdm",
2585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2586 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2587 .recalc = &followparent_recalc,
2590 static struct clk mdm_intc_ick = {
2591 .name = "mdm_intc_ick",
2592 .ops = &clkops_omap2_dflt_wait,
2594 .clkdm_name = "core_l4_clkdm",
2595 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2596 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2597 .recalc = &followparent_recalc,
2600 static struct clk mmchsdb1_fck = {
2601 .name = "mmchsdb_fck",
2602 .ops = &clkops_omap2_dflt_wait,
2603 .parent = &func_32k_ck,
2604 .clkdm_name = "core_l4_clkdm",
2605 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2606 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2607 .recalc = &followparent_recalc,
2610 static struct clk mmchsdb2_fck = {
2611 .name = "mmchsdb_fck",
2612 .ops = &clkops_omap2_dflt_wait,
2614 .parent = &func_32k_ck,
2615 .clkdm_name = "core_l4_clkdm",
2616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2617 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2618 .recalc = &followparent_recalc,
2622 * This clock is a composite clock which does entire set changes then
2623 * forces a rebalance. It keys on the MPU speed, but it really could
2624 * be any key speed part of a set in the rate table.
2626 * to really change a set, you need memory table sets which get changed
2627 * in sram, pre-notifiers & post notifiers, changing the top set, without
2628 * having low level display recalc's won't work... this is why dpm notifiers
2629 * work, isr's off, walk a list of clocks already _off_ and not messing with
2632 * This clock should have no parent. It embodies the entire upper level
2633 * active set. A parent will mess up some of the init also.
2635 static struct clk virt_prcm_set = {
2636 .name = "virt_prcm_set",
2637 .ops = &clkops_null,
2638 .flags = DELAYED_APP,
2639 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2640 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2641 .set_rate = &omap2_select_table_rate,
2642 .round_rate = &omap2_round_to_table_rate,