2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/cpufreq.h>
29 #include <linux/bitops.h>
31 #include <plat/clock.h>
32 #include <plat/sram.h>
33 #include <plat/prcm.h>
34 #include <plat/clkdev_omap.h>
35 #include <asm/div64.h>
36 #include <asm/clkdev.h>
38 #include <plat/sdrc.h>
40 #include "clock2xxx.h"
43 #include "prm-regbits-24xx.h"
45 #include "cm-regbits-24xx.h"
48 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
49 #define EN_APLL_STOPPED 0
50 #define EN_APLL_LOCKED 3
52 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
53 #define APLLS_CLKIN_19_2MHZ 0
54 #define APLLS_CLKIN_13MHZ 2
55 #define APLLS_CLKIN_12MHZ 3
57 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
59 const struct prcm_config *curr_prcm_set;
60 const struct prcm_config *rate_table;
62 struct clk *vclk, *sclk, *dclk;
64 void __iomem *prcm_clksrc_ctrl;
66 /*-------------------------------------------------------------------------
67 * Omap24xx specific clock functions
68 *-------------------------------------------------------------------------*/
71 * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
72 * @clk: struct clk * being enabled
73 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
74 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
76 * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
77 * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
78 * passes back the correct CM_IDLEST register address for I2CHS
79 * modules. No return value.
81 static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
82 void __iomem **idlest_reg,
85 *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
86 *idlest_bit = clk->enable_bit;
89 /* 2430 I2CHS has non-standard IDLEST register */
90 const struct clkops clkops_omap2430_i2chs_wait = {
91 .enable = omap2_dflt_clk_enable,
92 .disable = omap2_dflt_clk_disable,
93 .find_idlest = omap2430_clk_i2chs_find_idlest,
94 .find_companion = omap2_clk_dflt_find_companion,
98 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
99 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
101 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
102 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
103 * (the latter is unusual). This currently should be called with
104 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
107 unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
112 core_clk = omap2_get_dpll_rate(clk);
114 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
115 v &= OMAP24XX_CORE_CLK_SRC_MASK;
117 if (v == CORE_CLK_SRC_32K)
125 static int omap2_enable_osc_ck(struct clk *clk)
129 pcc = __raw_readl(prcm_clksrc_ctrl);
131 __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
136 static void omap2_disable_osc_ck(struct clk *clk)
140 pcc = __raw_readl(prcm_clksrc_ctrl);
142 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
145 const struct clkops clkops_oscck = {
146 .enable = omap2_enable_osc_ck,
147 .disable = omap2_disable_osc_ck,
151 /* Recalculate SYST_CLK */
152 static void omap2_sys_clk_recalc(struct clk *clk)
154 u32 div = PRCM_CLKSRC_CTRL;
155 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
156 div >>= clk->rate_offset;
157 clk->rate = (clk->parent->rate / div);
162 /* Enable an APLL if off */
163 static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
167 apll_mask = EN_APLL_LOCKED << clk->enable_bit;
169 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
171 if ((cval & apll_mask) == apll_mask)
172 return 0; /* apll already enabled */
176 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
178 omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
182 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
188 static int omap2_clk_apll96_enable(struct clk *clk)
190 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
193 static int omap2_clk_apll54_enable(struct clk *clk)
195 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
199 static void omap2_clk_apll_disable(struct clk *clk)
203 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
204 cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
205 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
208 const struct clkops clkops_apll96 = {
209 .enable = omap2_clk_apll96_enable,
210 .disable = omap2_clk_apll_disable,
213 const struct clkops clkops_apll54 = {
214 .enable = omap2_clk_apll54_enable,
215 .disable = omap2_clk_apll_disable,
219 * Uses the current prcm set to tell if a rate is valid.
220 * You can go slower, but not faster within a given rate set.
222 long omap2_dpllcore_round_rate(unsigned long target_rate)
224 u32 high, low, core_clk_src;
226 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
227 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
229 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
230 high = curr_prcm_set->dpll_speed * 2;
231 low = curr_prcm_set->dpll_speed;
232 } else { /* DPLL clockout x 2 */
233 high = curr_prcm_set->dpll_speed;
234 low = curr_prcm_set->dpll_speed / 2;
237 #ifdef DOWN_VARIABLE_DPLL
238 if (target_rate > high)
243 if (target_rate > low)
251 unsigned long omap2_dpllcore_recalc(struct clk *clk)
253 return omap2xxx_clk_get_core_rate(clk);
256 int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
258 u32 cur_rate, low, mult, div, valid_rate, done_rate;
260 struct prcm_config tmpset;
261 const struct dpll_data *dd;
263 cur_rate = omap2xxx_clk_get_core_rate(dclk);
264 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
265 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
267 if ((rate == (cur_rate / 2)) && (mult == 2)) {
268 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
269 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
270 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
271 } else if (rate != cur_rate) {
272 valid_rate = omap2_dpllcore_round_rate(rate);
273 if (valid_rate != rate)
277 low = curr_prcm_set->dpll_speed;
279 low = curr_prcm_set->dpll_speed / 2;
285 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
286 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
288 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
289 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
290 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
292 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
293 mult = ((rate / 2) / 1000000);
294 done_rate = CORE_CLK_SRC_DPLL_X2;
296 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
297 mult = (rate / 1000000);
298 done_rate = CORE_CLK_SRC_DPLL;
300 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
301 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
304 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
306 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
309 /* For omap2xxx_sdrc_init_params() */
310 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
312 /* Force dll lock mode */
313 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
316 /* Errata: ret dll entry state */
317 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
318 omap2xxx_sdrc_reprogram(done_rate, 0);
325 * omap2_table_mpu_recalc - just return the MPU speed
326 * @clk: virt_prcm_set struct clk
328 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
330 unsigned long omap2_table_mpu_recalc(struct clk *clk)
332 return curr_prcm_set->mpu_speed;
336 * Look for a rate equal or less than the target rate given a configuration set.
338 * What's not entirely clear is "which" field represents the key field.
339 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
340 * just uses the ARM rates.
342 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
344 const struct prcm_config *ptr;
348 sys_ck_rate = clk_get_rate(sclk);
350 highest_rate = -EINVAL;
352 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
353 if (!(ptr->flags & cpu_mask))
355 if (ptr->xtal_speed != sys_ck_rate)
358 highest_rate = ptr->mpu_speed;
360 /* Can check only after xtal frequency check */
361 if (ptr->mpu_speed <= rate)
367 /* Sets basic clocks based on the specified rate */
368 int omap2_select_table_rate(struct clk *clk, unsigned long rate)
370 u32 cur_rate, done_rate, bypass = 0, tmp;
371 const struct prcm_config *prcm;
372 unsigned long found_speed = 0;
376 sys_ck_rate = clk_get_rate(sclk);
378 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
379 if (!(prcm->flags & cpu_mask))
382 if (prcm->xtal_speed != sys_ck_rate)
385 if (prcm->mpu_speed <= rate) {
386 found_speed = prcm->mpu_speed;
392 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
397 curr_prcm_set = prcm;
398 cur_rate = omap2xxx_clk_get_core_rate(dclk);
400 if (prcm->dpll_speed == cur_rate / 2) {
401 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
402 } else if (prcm->dpll_speed == cur_rate * 2) {
403 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
404 } else if (prcm->dpll_speed != cur_rate) {
405 local_irq_save(flags);
407 if (prcm->dpll_speed == prcm->xtal_speed)
410 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
411 CORE_CLK_SRC_DPLL_X2)
412 done_rate = CORE_CLK_SRC_DPLL_X2;
414 done_rate = CORE_CLK_SRC_DPLL;
417 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
419 /* dsp + iva1 div(2420), iva2.1(2430) */
420 cm_write_mod_reg(prcm->cm_clksel_dsp,
421 OMAP24XX_DSP_MOD, CM_CLKSEL);
423 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
425 /* Major subsystem dividers */
426 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
427 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
430 if (cpu_is_omap2430())
431 cm_write_mod_reg(prcm->cm_clksel_mdm,
432 OMAP2430_MDM_MOD, CM_CLKSEL);
434 /* x2 to enter omap2xxx_sdrc_init_params() */
435 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
437 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
440 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
441 omap2xxx_sdrc_reprogram(done_rate, 0);
443 local_irq_restore(flags);
449 #ifdef CONFIG_CPU_FREQ
451 * Walk PRCM rate table and fillout cpufreq freq_table
452 * XXX This should be replaced by an OPP layer in the near future
454 static struct cpufreq_frequency_table *freq_table;
456 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
458 const struct prcm_config *prcm;
463 sys_ck_rate = clk_get_rate(sclk);
465 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
466 if (!(prcm->flags & cpu_mask))
468 if (prcm->xtal_speed != sys_ck_rate)
471 /* don't put bypass rates in table */
472 if (prcm->dpll_speed == prcm->xtal_speed)
479 * XXX Ensure that we're doing what CPUFreq expects for this error
480 * case and the following one
483 pr_warning("%s: no matching entries in rate_table\n",
488 /* Include the CPUFREQ_TABLE_END terminator entry */
491 freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
494 pr_err("%s: could not kzalloc frequency table\n", __func__);
498 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
499 if (!(prcm->flags & cpu_mask))
501 if (prcm->xtal_speed != sys_ck_rate)
504 /* don't put bypass rates in table */
505 if (prcm->dpll_speed == prcm->xtal_speed)
508 freq_table[i].index = i;
509 freq_table[i].frequency = prcm->mpu_speed / 1000;
513 freq_table[i].index = i;
514 freq_table[i].frequency = CPUFREQ_TABLE_END;
516 *table = &freq_table[0];
519 void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
526 struct clk_functions omap2_clk_functions = {
527 .clk_enable = omap2_clk_enable,
528 .clk_disable = omap2_clk_disable,
529 .clk_round_rate = omap2_clk_round_rate,
530 .clk_set_rate = omap2_clk_set_rate,
531 .clk_set_parent = omap2_clk_set_parent,
532 .clk_disable_unused = omap2_clk_disable_unused,
533 #ifdef CONFIG_CPU_FREQ
534 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
535 .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
539 static u32 omap2_get_apll_clkin(void)
541 u32 aplls, srate = 0;
543 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
544 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
545 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
547 if (aplls == APLLS_CLKIN_19_2MHZ)
549 else if (aplls == APLLS_CLKIN_13MHZ)
551 else if (aplls == APLLS_CLKIN_12MHZ)
557 static u32 omap2_get_sysclkdiv(void)
561 div = __raw_readl(prcm_clksrc_ctrl);
562 div &= OMAP_SYSCLKDIV_MASK;
563 div >>= OMAP_SYSCLKDIV_SHIFT;
568 unsigned long omap2_osc_clk_recalc(struct clk *clk)
570 return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
573 unsigned long omap2_sys_clk_recalc(struct clk *clk)
575 return clk->parent->rate / omap2_get_sysclkdiv();
579 * Set clocks for bypass mode for reboot to work.
581 void omap2_clk_prepare_for_reboot(void)
585 if (vclk == NULL || sclk == NULL)
588 rate = clk_get_rate(sclk);
589 clk_set_rate(vclk, rate);
593 * Switch the MPU rate if specified on cmdline.
594 * We cannot do this early until cmdline is parsed.
596 static int __init omap2_clk_arch_init(void)
598 struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
599 unsigned long sys_ck_rate;
604 virt_prcm_set = clk_get(NULL, "virt_prcm_set");
605 sys_ck = clk_get(NULL, "sys_ck");
606 dpll_ck = clk_get(NULL, "dpll_ck");
607 mpu_ck = clk_get(NULL, "mpu_ck");
609 if (clk_set_rate(virt_prcm_set, mpurate))
610 printk(KERN_ERR "Could not find matching MPU rate\n");
612 recalculate_root_clocks();
614 sys_ck_rate = clk_get_rate(sys_ck);
616 pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
617 "%ld.%01ld/%ld/%ld MHz\n",
618 (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
619 (clk_get_rate(dpll_ck) / 1000000),
620 (clk_get_rate(mpu_ck) / 1000000));
624 arch_initcall(omap2_clk_arch_init);