2 * OMAP3 clock framework
4 * Virtual clocks are introduced as a convenient tools.
5 * They are sources for other clocks and not supposed
6 * to be requested from drivers directly.
8 * Copyright (C) 2007-2008 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
11 * Written by Paul Walmsley
14 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
15 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
17 #include <asm/arch/control.h>
21 #include "cm-regbits-34xx.h"
23 #include "prm-regbits-34xx.h"
25 static void omap3_dpll_recalc(struct clk *clk);
26 static void omap3_clkoutx2_recalc(struct clk *clk);
29 * DPLL1 supplies clock to the MPU.
30 * DPLL2 supplies clock to the IVA2.
31 * DPLL3 supplies CORE domain clocks.
32 * DPLL4 supplies peripheral clocks.
33 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
38 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
39 static struct clk omap_32k_fck = {
40 .name = "omap_32k_fck",
42 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
44 .recalc = &propagate_rate,
47 static struct clk secure_32k_fck = {
48 .name = "secure_32k_fck",
50 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
52 .recalc = &propagate_rate,
55 /* Virtual source clocks for osc_sys_ck */
56 static struct clk virt_12m_ck = {
57 .name = "virt_12m_ck",
59 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
61 .recalc = &propagate_rate,
64 static struct clk virt_13m_ck = {
65 .name = "virt_13m_ck",
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
69 .recalc = &propagate_rate,
72 static struct clk virt_16_8m_ck = {
73 .name = "virt_16_8m_ck",
75 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
77 .recalc = &propagate_rate,
80 static struct clk virt_19_2m_ck = {
81 .name = "virt_19_2m_ck",
83 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
85 .recalc = &propagate_rate,
88 static struct clk virt_26m_ck = {
89 .name = "virt_26m_ck",
91 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
93 .recalc = &propagate_rate,
96 static struct clk virt_38_4m_ck = {
97 .name = "virt_38_4m_ck",
99 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
101 .recalc = &propagate_rate,
104 static const struct clksel_rate osc_sys_12m_rates[] = {
105 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
109 static const struct clksel_rate osc_sys_13m_rates[] = {
110 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
114 static const struct clksel_rate osc_sys_16_8m_rates[] = {
115 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
119 static const struct clksel_rate osc_sys_19_2m_rates[] = {
120 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
124 static const struct clksel_rate osc_sys_26m_rates[] = {
125 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
129 static const struct clksel_rate osc_sys_38_4m_rates[] = {
130 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
134 static const struct clksel osc_sys_clksel[] = {
135 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
136 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
137 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
138 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
139 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
140 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
144 /* Oscillator clock */
145 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
146 static struct clk osc_sys_ck = {
147 .name = "osc_sys_ck",
148 .init = &omap2_init_clksel_parent,
149 .clksel_reg = OMAP3430_PRM_CLKSEL,
150 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
151 .clksel = osc_sys_clksel,
152 /* REVISIT: deal with autoextclkmode? */
153 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
155 .recalc = &omap2_clksel_recalc,
158 static const struct clksel_rate div2_rates[] = {
159 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
160 { .div = 2, .val = 2, .flags = RATE_IN_343X },
164 static const struct clksel sys_clksel[] = {
165 { .parent = &osc_sys_ck, .rates = div2_rates },
169 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
170 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
171 static struct clk sys_ck = {
173 .parent = &osc_sys_ck,
174 .init = &omap2_init_clksel_parent,
175 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
176 .clksel_mask = OMAP_SYSCLKDIV_MASK,
177 .clksel = sys_clksel,
178 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
179 .recalc = &omap2_clksel_recalc,
182 static struct clk sys_altclk = {
183 .name = "sys_altclk",
184 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
185 .recalc = &propagate_rate,
188 /* Optional external clock input for some McBSPs */
189 static struct clk mcbsp_clks = {
190 .name = "mcbsp_clks",
191 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
192 .recalc = &propagate_rate,
195 /* PRM EXTERNAL CLOCK OUTPUT */
197 static struct clk sys_clkout1 = {
198 .name = "sys_clkout1",
199 .parent = &osc_sys_ck,
200 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
201 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
202 .flags = CLOCK_IN_OMAP343X,
203 .recalc = &followparent_recalc,
210 static const struct clksel_rate dpll_bypass_rates[] = {
211 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
215 static const struct clksel_rate dpll_locked_rates[] = {
216 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
220 static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
241 /* MPU clock source */
243 static const struct dpll_data dpll1_dd = {
244 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
245 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
247 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
248 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
249 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
250 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
251 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
254 static struct clk dpll1_ck = {
257 .dpll_data = &dpll1_dd,
258 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
259 .recalc = &omap3_dpll_recalc,
263 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
264 * DPLL isn't bypassed.
266 static struct clk dpll1_x2_ck = {
267 .name = "dpll1_x2_ck",
269 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
270 PARENT_CONTROLS_CLOCK,
271 .recalc = &omap3_clkoutx2_recalc,
274 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
275 static const struct clksel div16_dpll1_x2m2_clksel[] = {
276 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
281 * Does not exist in the TRM - needed to separate the M2 divider from
282 * bypass selection in mpu_ck
284 static struct clk dpll1_x2m2_ck = {
285 .name = "dpll1_x2m2_ck",
286 .parent = &dpll1_x2_ck,
287 .init = &omap2_init_clksel_parent,
288 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
289 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
290 .clksel = div16_dpll1_x2m2_clksel,
291 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
292 PARENT_CONTROLS_CLOCK,
293 .recalc = &omap2_clksel_recalc,
297 /* IVA2 clock source */
300 static const struct dpll_data dpll2_dd = {
301 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
302 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
303 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
304 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
305 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
306 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
307 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
308 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
311 static struct clk dpll2_ck = {
314 .dpll_data = &dpll2_dd,
315 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
316 .recalc = &omap3_dpll_recalc,
319 static const struct clksel div16_dpll2_m2x2_clksel[] = {
320 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
325 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
326 * or CLKOUTX2. CLKOUT seems most plausible.
328 static struct clk dpll2_m2_ck = {
329 .name = "dpll2_m2_ck",
331 .init = &omap2_init_clksel_parent,
332 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
333 OMAP3430_CM_CLKSEL2_PLL),
334 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
335 .clksel = div16_dpll2_m2x2_clksel,
336 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
337 PARENT_CONTROLS_CLOCK,
338 .recalc = &omap2_clksel_recalc,
342 /* Source clock for all interfaces and for some device fclks */
344 static const struct dpll_data dpll3_dd = {
345 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
346 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
347 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
348 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
349 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
350 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
355 static struct clk dpll3_ck = {
358 .dpll_data = &dpll3_dd,
359 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
360 .recalc = &omap3_dpll_recalc,
364 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
365 * DPLL isn't bypassed
367 static struct clk dpll3_x2_ck = {
368 .name = "dpll3_x2_ck",
370 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
371 PARENT_CONTROLS_CLOCK,
372 .recalc = &omap3_clkoutx2_recalc,
375 static const struct clksel_rate div31_dpll3_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
377 { .div = 2, .val = 2, .flags = RATE_IN_343X },
378 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
379 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
380 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
381 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
382 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
383 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
384 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
385 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
386 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
387 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
388 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
389 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
390 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
391 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
392 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
393 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
394 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
395 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
396 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
397 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
398 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
399 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
400 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
401 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
402 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
403 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
404 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
405 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
406 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
410 static const struct clksel div31_dpll3m2_clksel[] = {
411 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
417 * REVISIT: This DPLL output divider must be changed in SRAM, so until
418 * that code is ready, this should remain a 'read-only' clksel clock.
420 static struct clk dpll3_m2_ck = {
421 .name = "dpll3_m2_ck",
423 .init = &omap2_init_clksel_parent,
424 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
425 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
426 .clksel = div31_dpll3m2_clksel,
427 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
428 PARENT_CONTROLS_CLOCK,
429 .recalc = &omap2_clksel_recalc,
432 static const struct clksel core_ck_clksel[] = {
433 { .parent = &sys_ck, .rates = dpll_bypass_rates },
434 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
438 static struct clk core_ck = {
440 .init = &omap2_init_clksel_parent,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
442 .clksel_mask = OMAP3430_ST_CORE_CLK,
443 .clksel = core_ck_clksel,
444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
445 PARENT_CONTROLS_CLOCK,
446 .recalc = &omap2_clksel_recalc,
449 static const struct clksel dpll3_m2x2_ck_clksel[] = {
450 { .parent = &sys_ck, .rates = dpll_bypass_rates },
451 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
455 static struct clk dpll3_m2x2_ck = {
456 .name = "dpll3_m2x2_ck",
457 .init = &omap2_init_clksel_parent,
458 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
459 .clksel_mask = OMAP3430_ST_CORE_CLK,
460 .clksel = dpll3_m2x2_ck_clksel,
461 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
462 PARENT_CONTROLS_CLOCK,
463 .recalc = &omap2_clksel_recalc,
466 /* The PWRDN bit is apparently only available on 3430ES2 and above */
467 static const struct clksel div16_dpll3_clksel[] = {
468 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
472 /* This virtual clock is the source for dpll3_m3x2_ck */
473 static struct clk dpll3_m3_ck = {
474 .name = "dpll3_m3_ck",
476 .init = &omap2_init_clksel_parent,
477 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
478 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
479 .clksel = div16_dpll3_clksel,
480 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
481 PARENT_CONTROLS_CLOCK,
482 .recalc = &omap2_clksel_recalc,
485 /* The PWRDN bit is apparently only available on 3430ES2 and above */
486 static struct clk dpll3_m3x2_ck = {
487 .name = "dpll3_m3x2_ck",
488 .parent = &dpll3_m3_ck,
489 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
490 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
491 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
492 .recalc = &omap3_clkoutx2_recalc,
495 static const struct clksel emu_core_alwon_ck_clksel[] = {
496 { .parent = &sys_ck, .rates = dpll_bypass_rates },
497 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
501 static struct clk emu_core_alwon_ck = {
502 .name = "emu_core_alwon_ck",
503 .parent = &dpll3_m3x2_ck,
504 .init = &omap2_init_clksel_parent,
505 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
506 .clksel_mask = OMAP3430_ST_CORE_CLK,
507 .clksel = emu_core_alwon_ck_clksel,
508 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
509 PARENT_CONTROLS_CLOCK,
510 .recalc = &omap2_clksel_recalc,
514 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
516 static const struct dpll_data dpll4_dd = {
517 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
518 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
519 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
520 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
521 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
522 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
523 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
524 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
527 static struct clk dpll4_ck = {
530 .dpll_data = &dpll4_dd,
531 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
532 .recalc = &omap3_dpll_recalc,
536 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
537 * DPLL isn't bypassed --
538 * XXX does this serve any downstream clocks?
540 static struct clk dpll4_x2_ck = {
541 .name = "dpll4_x2_ck",
543 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
544 PARENT_CONTROLS_CLOCK,
545 .recalc = &omap3_clkoutx2_recalc,
548 static const struct clksel div16_dpll4_clksel[] = {
549 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
553 /* This virtual clock is the source for dpll4_m2x2_ck */
554 static struct clk dpll4_m2_ck = {
555 .name = "dpll4_m2_ck",
557 .init = &omap2_init_clksel_parent,
558 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
559 .clksel_mask = OMAP3430_DIV_96M_MASK,
560 .clksel = div16_dpll4_clksel,
561 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
562 PARENT_CONTROLS_CLOCK,
563 .recalc = &omap2_clksel_recalc,
566 /* The PWRDN bit is apparently only available on 3430ES2 and above */
567 static struct clk dpll4_m2x2_ck = {
568 .name = "dpll4_m2x2_ck",
569 .parent = &dpll4_m2_ck,
570 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
571 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
572 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
573 .recalc = &omap3_clkoutx2_recalc,
576 static const struct clksel omap_96m_alwon_fck_clksel[] = {
577 { .parent = &sys_ck, .rates = dpll_bypass_rates },
578 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
582 static struct clk omap_96m_alwon_fck = {
583 .name = "omap_96m_alwon_fck",
584 .parent = &dpll4_m2x2_ck,
585 .init = &omap2_init_clksel_parent,
586 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
587 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
588 .clksel = omap_96m_alwon_fck_clksel,
589 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
590 PARENT_CONTROLS_CLOCK,
591 .recalc = &omap2_clksel_recalc,
594 static struct clk omap_96m_fck = {
595 .name = "omap_96m_fck",
596 .parent = &omap_96m_alwon_fck,
597 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
598 PARENT_CONTROLS_CLOCK,
599 .recalc = &followparent_recalc,
602 static const struct clksel cm_96m_fck_clksel[] = {
603 { .parent = &sys_ck, .rates = dpll_bypass_rates },
604 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
608 static struct clk cm_96m_fck = {
609 .name = "cm_96m_fck",
610 .parent = &dpll4_m2x2_ck,
611 .init = &omap2_init_clksel_parent,
612 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
613 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
614 .clksel = cm_96m_fck_clksel,
615 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
616 PARENT_CONTROLS_CLOCK,
617 .recalc = &omap2_clksel_recalc,
620 /* This virtual clock is the source for dpll4_m3x2_ck */
621 static struct clk dpll4_m3_ck = {
622 .name = "dpll4_m3_ck",
624 .init = &omap2_init_clksel_parent,
625 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
626 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
627 .clksel = div16_dpll4_clksel,
628 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
629 PARENT_CONTROLS_CLOCK,
630 .recalc = &omap2_clksel_recalc,
633 /* The PWRDN bit is apparently only available on 3430ES2 and above */
634 static struct clk dpll4_m3x2_ck = {
635 .name = "dpll4_m3x2_ck",
636 .parent = &dpll4_m3_ck,
637 .init = &omap2_init_clksel_parent,
638 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
639 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
640 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
641 .recalc = &omap3_clkoutx2_recalc,
644 static const struct clksel virt_omap_54m_fck_clksel[] = {
645 { .parent = &sys_ck, .rates = dpll_bypass_rates },
646 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
650 static struct clk virt_omap_54m_fck = {
651 .name = "virt_omap_54m_fck",
652 .parent = &dpll4_m3x2_ck,
653 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
656 .clksel = virt_omap_54m_fck_clksel,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
658 PARENT_CONTROLS_CLOCK,
659 .recalc = &omap2_clksel_recalc,
662 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
663 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
667 static const struct clksel_rate omap_54m_alt_rates[] = {
668 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
672 static const struct clksel omap_54m_clksel[] = {
673 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
674 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
678 static struct clk omap_54m_fck = {
679 .name = "omap_54m_fck",
680 .init = &omap2_init_clksel_parent,
681 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
682 .clksel_mask = OMAP3430_SOURCE_54M,
683 .clksel = omap_54m_clksel,
684 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
685 PARENT_CONTROLS_CLOCK,
686 .recalc = &omap2_clksel_recalc,
689 static const struct clksel_rate omap_48m_96md2_rates[] = {
690 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
694 static const struct clksel_rate omap_48m_alt_rates[] = {
695 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
699 static const struct clksel omap_48m_clksel[] = {
700 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
701 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
705 static struct clk omap_48m_fck = {
706 .name = "omap_48m_fck",
707 .init = &omap2_init_clksel_parent,
708 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
709 .clksel_mask = OMAP3430_SOURCE_48M,
710 .clksel = omap_48m_clksel,
711 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
712 PARENT_CONTROLS_CLOCK,
713 .recalc = &omap2_clksel_recalc,
716 static struct clk omap_12m_fck = {
717 .name = "omap_12m_fck",
718 .parent = &omap_48m_fck,
720 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
721 PARENT_CONTROLS_CLOCK,
722 .recalc = &omap2_fixed_divisor_recalc,
725 /* This virstual clock is the source for dpll4_m4x2_ck */
726 static struct clk dpll4_m4_ck = {
727 .name = "dpll4_m4_ck",
729 .init = &omap2_init_clksel_parent,
730 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
731 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
732 .clksel = div16_dpll4_clksel,
733 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
734 PARENT_CONTROLS_CLOCK,
735 .recalc = &omap2_clksel_recalc,
738 /* The PWRDN bit is apparently only available on 3430ES2 and above */
739 static struct clk dpll4_m4x2_ck = {
740 .name = "dpll4_m4x2_ck",
741 .parent = &dpll4_m4_ck,
742 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
743 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
744 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
745 .recalc = &omap3_clkoutx2_recalc,
748 /* This virtual clock is the source for dpll4_m5x2_ck */
749 static struct clk dpll4_m5_ck = {
750 .name = "dpll4_m5_ck",
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
754 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
755 .clksel = div16_dpll4_clksel,
756 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
757 PARENT_CONTROLS_CLOCK,
758 .recalc = &omap2_clksel_recalc,
761 /* The PWRDN bit is apparently only available on 3430ES2 and above */
762 static struct clk dpll4_m5x2_ck = {
763 .name = "dpll4_m5x2_ck",
764 .parent = &dpll4_m5_ck,
765 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
766 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
768 .recalc = &omap3_clkoutx2_recalc,
771 /* This virtual clock is the source for dpll4_m6x2_ck */
772 static struct clk dpll4_m6_ck = {
773 .name = "dpll4_m6_ck",
775 .init = &omap2_init_clksel_parent,
776 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
777 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
778 .clksel = div16_dpll4_clksel,
779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
780 PARENT_CONTROLS_CLOCK,
781 .recalc = &omap2_clksel_recalc,
784 /* The PWRDN bit is apparently only available on 3430ES2 and above */
785 static struct clk dpll4_m6x2_ck = {
786 .name = "dpll4_m6x2_ck",
787 .parent = &dpll4_m6_ck,
788 .init = &omap2_init_clksel_parent,
789 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
790 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
791 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
792 .recalc = &omap3_clkoutx2_recalc,
795 static struct clk emu_per_alwon_ck = {
796 .name = "emu_per_alwon_ck",
797 .parent = &dpll4_m6x2_ck,
798 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
799 PARENT_CONTROLS_CLOCK,
800 .recalc = &followparent_recalc,
804 /* Supplies 120MHz clock, USIM source clock */
807 static const struct dpll_data dpll5_dd = {
808 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
809 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
810 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
811 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
812 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
813 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
814 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
815 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
818 static struct clk dpll5_ck = {
821 .dpll_data = &dpll5_dd,
822 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
824 .recalc = &omap3_dpll_recalc,
827 static const struct clksel div16_dpll5_clksel[] = {
828 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
832 static struct clk dpll5_m2_ck = {
833 .name = "dpll5_m2_ck",
835 .init = &omap2_init_clksel_parent,
836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
838 .clksel = div16_dpll5_clksel,
839 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
840 .recalc = &omap2_clksel_recalc,
843 static const struct clksel omap_120m_fck_clksel[] = {
844 { .parent = &sys_ck, .rates = dpll_bypass_rates },
845 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
849 static struct clk omap_120m_fck = {
850 .name = "omap_120m_fck",
851 .parent = &dpll5_m2_ck,
852 .init = &omap2_init_clksel_parent,
853 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
854 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
855 .clksel = omap_120m_fck_clksel,
856 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
857 PARENT_CONTROLS_CLOCK,
858 .recalc = &omap2_clksel_recalc,
861 /* CM EXTERNAL CLOCK OUTPUTS */
863 static const struct clksel_rate clkout2_src_core_rates[] = {
864 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
868 static const struct clksel_rate clkout2_src_sys_rates[] = {
869 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
873 static const struct clksel_rate clkout2_src_96m_rates[] = {
874 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
878 static const struct clksel_rate clkout2_src_54m_rates[] = {
879 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
883 static const struct clksel clkout2_src_clksel[] = {
884 { .parent = &core_ck, .rates = clkout2_src_core_rates },
885 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
886 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
887 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
891 static struct clk clkout2_src_ck = {
892 .name = "clkout2_src_ck",
893 .init = &omap2_init_clksel_parent,
894 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
895 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
896 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
897 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
898 .clksel = clkout2_src_clksel,
899 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
900 .recalc = &omap2_clksel_recalc,
903 static const struct clksel_rate sys_clkout2_rates[] = {
904 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
905 { .div = 2, .val = 1, .flags = RATE_IN_343X },
906 { .div = 4, .val = 2, .flags = RATE_IN_343X },
907 { .div = 8, .val = 3, .flags = RATE_IN_343X },
908 { .div = 16, .val = 4, .flags = RATE_IN_343X },
912 static const struct clksel sys_clkout2_clksel[] = {
913 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
917 static struct clk sys_clkout2 = {
918 .name = "sys_clkout2",
919 .init = &omap2_init_clksel_parent,
920 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
921 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
922 .clksel = sys_clkout2_clksel,
923 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
924 .recalc = &omap2_clksel_recalc,
927 /* CM OUTPUT CLOCKS */
929 static struct clk corex2_fck = {
930 .name = "corex2_fck",
931 .parent = &dpll3_m2x2_ck,
932 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
933 PARENT_CONTROLS_CLOCK,
934 .recalc = &followparent_recalc,
937 /* DPLL power domain clock controls */
939 static const struct clksel div2_core_clksel[] = {
940 { .parent = &core_ck, .rates = div2_rates },
945 * REVISIT: Are these in DPLL power domain or CM power domain? docs
946 * may be inconsistent here?
948 static struct clk dpll1_fck = {
951 .init = &omap2_init_clksel_parent,
952 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
953 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
954 .clksel = div2_core_clksel,
955 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
956 PARENT_CONTROLS_CLOCK,
957 .recalc = &omap2_clksel_recalc,
962 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
963 * derives from the high-frequency bypass clock originating from DPLL3,
966 static const struct clksel mpu_clksel[] = {
967 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
968 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
972 static struct clk mpu_ck = {
974 .parent = &dpll1_x2m2_ck,
975 .init = &omap2_init_clksel_parent,
976 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
977 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
978 .clksel = mpu_clksel,
979 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
980 PARENT_CONTROLS_CLOCK,
981 .recalc = &omap2_clksel_recalc,
984 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
985 static const struct clksel_rate arm_fck_rates[] = {
986 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
987 { .div = 2, .val = 1, .flags = RATE_IN_343X },
991 static const struct clksel arm_fck_clksel[] = {
992 { .parent = &mpu_ck, .rates = arm_fck_rates },
996 static struct clk arm_fck = {
999 .init = &omap2_init_clksel_parent,
1000 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1001 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1002 .clksel = arm_fck_clksel,
1003 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1004 PARENT_CONTROLS_CLOCK,
1005 .recalc = &omap2_clksel_recalc,
1009 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1010 * although it is referenced - so this is a guess
1012 static struct clk emu_mpu_alwon_ck = {
1013 .name = "emu_mpu_alwon_ck",
1015 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1016 PARENT_CONTROLS_CLOCK,
1017 .recalc = &followparent_recalc,
1020 static struct clk dpll2_fck = {
1021 .name = "dpll2_fck",
1023 .init = &omap2_init_clksel_parent,
1024 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1025 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1026 .clksel = div2_core_clksel,
1027 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1028 PARENT_CONTROLS_CLOCK,
1029 .recalc = &omap2_clksel_recalc,
1034 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1035 * derives from the high-frequency bypass clock originating from DPLL3,
1036 * called 'dpll2_fck'
1039 static const struct clksel iva2_clksel[] = {
1040 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1041 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1045 static struct clk iva2_ck = {
1047 .parent = &dpll2_m2_ck,
1048 .init = &omap2_init_clksel_parent,
1049 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1050 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1051 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1052 OMAP3430_CM_IDLEST_PLL),
1053 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1054 .clksel = iva2_clksel,
1055 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1056 .recalc = &omap2_clksel_recalc,
1059 /* Common interface clocks */
1061 static struct clk l3_ick = {
1064 .init = &omap2_init_clksel_parent,
1065 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1066 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1067 .clksel = div2_core_clksel,
1068 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1069 PARENT_CONTROLS_CLOCK,
1070 .recalc = &omap2_clksel_recalc,
1073 static const struct clksel div2_l3_clksel[] = {
1074 { .parent = &l3_ick, .rates = div2_rates },
1078 static struct clk l4_ick = {
1081 .init = &omap2_init_clksel_parent,
1082 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1083 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1084 .clksel = div2_l3_clksel,
1085 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1086 PARENT_CONTROLS_CLOCK,
1087 .recalc = &omap2_clksel_recalc,
1091 static const struct clksel div2_l4_clksel[] = {
1092 { .parent = &l4_ick, .rates = div2_rates },
1096 static struct clk rm_ick = {
1099 .init = &omap2_init_clksel_parent,
1100 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1101 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1102 .clksel = div2_l4_clksel,
1103 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1104 .recalc = &omap2_clksel_recalc,
1107 /* GFX power domain */
1109 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1111 static const struct clksel gfx_l3_clksel[] = {
1112 { .parent = &l3_ick, .rates = gfx_l3_rates },
1116 static struct clk gfx_l3_fck = {
1117 .name = "gfx_l3_fck",
1119 .init = &omap2_init_clksel_parent,
1120 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1121 .enable_bit = OMAP_EN_GFX_SHIFT,
1122 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1123 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1124 .clksel = gfx_l3_clksel,
1125 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1126 .recalc = &omap2_clksel_recalc,
1129 static struct clk gfx_l3_ick = {
1130 .name = "gfx_l3_ick",
1132 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1133 .enable_bit = OMAP_EN_GFX_SHIFT,
1134 .flags = CLOCK_IN_OMAP3430ES1,
1135 .recalc = &followparent_recalc,
1138 static struct clk gfx_cg1_ck = {
1139 .name = "gfx_cg1_ck",
1140 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1141 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1142 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1143 .flags = CLOCK_IN_OMAP3430ES1,
1144 .recalc = &followparent_recalc,
1147 static struct clk gfx_cg2_ck = {
1148 .name = "gfx_cg2_ck",
1149 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1150 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1151 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1152 .flags = CLOCK_IN_OMAP3430ES1,
1153 .recalc = &followparent_recalc,
1156 /* SGX power domain - 3430ES2 only */
1158 static const struct clksel_rate sgx_core_rates[] = {
1159 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1160 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1161 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1165 static const struct clksel_rate sgx_96m_rates[] = {
1166 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1170 static const struct clksel sgx_clksel[] = {
1171 { .parent = &core_ck, .rates = sgx_core_rates },
1172 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1176 static struct clk sgx_fck = {
1178 .init = &omap2_init_clksel_parent,
1179 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1180 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1181 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1182 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1183 .clksel = sgx_clksel,
1184 .flags = CLOCK_IN_OMAP3430ES2,
1185 .recalc = &omap2_clksel_recalc,
1188 static struct clk sgx_ick = {
1191 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1192 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1193 .flags = CLOCK_IN_OMAP3430ES2,
1194 .recalc = &followparent_recalc,
1197 /* CORE power domain */
1199 static struct clk d2d_26m_fck = {
1200 .name = "d2d_26m_fck",
1202 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1203 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1204 .flags = CLOCK_IN_OMAP3430ES1,
1205 .recalc = &followparent_recalc,
1208 static const struct clksel omap343x_gpt_clksel[] = {
1209 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1210 { .parent = &sys_ck, .rates = gpt_sys_rates },
1214 static struct clk gpt10_fck = {
1215 .name = "gpt10_fck",
1217 .init = &omap2_init_clksel_parent,
1218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1219 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1220 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1221 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1222 .clksel = omap343x_gpt_clksel,
1223 .flags = CLOCK_IN_OMAP343X,
1224 .recalc = &omap2_clksel_recalc,
1227 static struct clk gpt11_fck = {
1228 .name = "gpt11_fck",
1230 .init = &omap2_init_clksel_parent,
1231 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1232 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1233 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1234 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1235 .clksel = omap343x_gpt_clksel,
1236 .flags = CLOCK_IN_OMAP343X,
1237 .recalc = &omap2_clksel_recalc,
1240 static struct clk cpefuse_fck = {
1241 .name = "cpefuse_fck",
1243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1244 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1245 .flags = CLOCK_IN_OMAP3430ES2,
1246 .recalc = &followparent_recalc,
1249 static struct clk ts_fck = {
1251 .parent = &omap_32k_fck,
1252 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1253 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1254 .flags = CLOCK_IN_OMAP3430ES2,
1255 .recalc = &followparent_recalc,
1258 static struct clk usbtll_fck = {
1259 .name = "usbtll_fck",
1260 .parent = &omap_120m_fck,
1261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1262 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1263 .flags = CLOCK_IN_OMAP3430ES2,
1264 .recalc = &followparent_recalc,
1267 /* CORE 96M FCLK-derived clocks */
1269 static struct clk core_96m_fck = {
1270 .name = "core_96m_fck",
1271 .parent = &omap_96m_fck,
1272 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1273 PARENT_CONTROLS_CLOCK,
1274 .recalc = &followparent_recalc,
1277 static struct clk mmchs3_fck = {
1278 .name = "mmchs_fck",
1280 .parent = &core_96m_fck,
1281 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1282 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1283 .flags = CLOCK_IN_OMAP3430ES2,
1284 .recalc = &followparent_recalc,
1287 static struct clk mmchs2_fck = {
1288 .name = "mmchs_fck",
1290 .parent = &core_96m_fck,
1291 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1292 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1293 .flags = CLOCK_IN_OMAP343X,
1294 .recalc = &followparent_recalc,
1297 static struct clk mspro_fck = {
1298 .name = "mspro_fck",
1299 .parent = &core_96m_fck,
1300 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1301 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1302 .flags = CLOCK_IN_OMAP343X,
1303 .recalc = &followparent_recalc,
1306 static struct clk mmchs1_fck = {
1307 .name = "mmchs_fck",
1309 .parent = &core_96m_fck,
1310 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1311 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1312 .flags = CLOCK_IN_OMAP343X,
1313 .recalc = &followparent_recalc,
1316 static struct clk i2c3_fck = {
1319 .parent = &core_96m_fck,
1320 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1321 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1322 .flags = CLOCK_IN_OMAP343X,
1323 .recalc = &followparent_recalc,
1326 static struct clk i2c2_fck = {
1329 .parent = &core_96m_fck,
1330 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1331 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1332 .flags = CLOCK_IN_OMAP343X,
1333 .recalc = &followparent_recalc,
1336 static struct clk i2c1_fck = {
1339 .parent = &core_96m_fck,
1340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1341 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1342 .flags = CLOCK_IN_OMAP343X,
1343 .recalc = &followparent_recalc,
1347 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1348 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1350 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1351 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1355 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1356 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1360 static const struct clksel mcbsp_15_clksel[] = {
1361 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1362 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1366 static struct clk mcbsp5_fck = {
1367 .name = "mcbsp5_fck",
1368 .init = &omap2_init_clksel_parent,
1369 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1370 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1371 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1372 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1373 .clksel = mcbsp_15_clksel,
1374 .flags = CLOCK_IN_OMAP343X,
1375 .recalc = &omap2_clksel_recalc,
1378 static struct clk mcbsp1_fck = {
1379 .name = "mcbsp1_fck",
1380 .init = &omap2_init_clksel_parent,
1381 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1382 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1383 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1384 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1385 .clksel = mcbsp_15_clksel,
1386 .flags = CLOCK_IN_OMAP343X,
1387 .recalc = &omap2_clksel_recalc,
1390 /* CORE_48M_FCK-derived clocks */
1392 static struct clk core_48m_fck = {
1393 .name = "core_48m_fck",
1394 .parent = &omap_48m_fck,
1395 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1396 PARENT_CONTROLS_CLOCK,
1397 .recalc = &followparent_recalc,
1400 static struct clk mcspi4_fck = {
1401 .name = "mcspi_fck",
1403 .parent = &core_48m_fck,
1404 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1406 .flags = CLOCK_IN_OMAP343X,
1407 .recalc = &followparent_recalc,
1410 static struct clk mcspi3_fck = {
1411 .name = "mcspi_fck",
1413 .parent = &core_48m_fck,
1414 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1415 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1416 .flags = CLOCK_IN_OMAP343X,
1417 .recalc = &followparent_recalc,
1420 static struct clk mcspi2_fck = {
1421 .name = "mcspi_fck",
1423 .parent = &core_48m_fck,
1424 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1425 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1426 .flags = CLOCK_IN_OMAP343X,
1427 .recalc = &followparent_recalc,
1430 static struct clk mcspi1_fck = {
1431 .name = "mcspi_fck",
1433 .parent = &core_48m_fck,
1434 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1435 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1436 .flags = CLOCK_IN_OMAP343X,
1437 .recalc = &followparent_recalc,
1440 static struct clk uart2_fck = {
1441 .name = "uart2_fck",
1442 .parent = &core_48m_fck,
1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1444 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1445 .flags = CLOCK_IN_OMAP343X,
1446 .recalc = &followparent_recalc,
1449 static struct clk uart1_fck = {
1450 .name = "uart1_fck",
1451 .parent = &core_48m_fck,
1452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1454 .flags = CLOCK_IN_OMAP343X,
1455 .recalc = &followparent_recalc,
1458 static struct clk fshostusb_fck = {
1459 .name = "fshostusb_fck",
1460 .parent = &core_48m_fck,
1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1463 .flags = CLOCK_IN_OMAP3430ES1,
1464 .recalc = &followparent_recalc,
1467 /* CORE_12M_FCK based clocks */
1469 static struct clk core_12m_fck = {
1470 .name = "core_12m_fck",
1471 .parent = &omap_12m_fck,
1472 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1473 PARENT_CONTROLS_CLOCK,
1474 .recalc = &followparent_recalc,
1477 static struct clk hdq_fck = {
1479 .parent = &core_12m_fck,
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1481 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1482 .flags = CLOCK_IN_OMAP343X,
1483 .recalc = &followparent_recalc,
1486 /* DPLL3-derived clock */
1488 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1489 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1490 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1491 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1492 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1493 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1494 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1498 static const struct clksel ssi_ssr_clksel[] = {
1499 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1503 static struct clk ssi_ssr_fck = {
1504 .name = "ssi_ssr_fck",
1505 .init = &omap2_init_clksel_parent,
1506 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1507 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1508 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1509 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1510 .clksel = ssi_ssr_clksel,
1511 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1512 .recalc = &omap2_clksel_recalc,
1515 static struct clk ssi_sst_fck = {
1516 .name = "ssi_sst_fck",
1517 .parent = &ssi_ssr_fck,
1519 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1520 .recalc = &omap2_fixed_divisor_recalc,
1525 /* CORE_L3_ICK based clocks */
1527 static struct clk core_l3_ick = {
1528 .name = "core_l3_ick",
1530 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1531 PARENT_CONTROLS_CLOCK,
1532 .recalc = &followparent_recalc,
1535 static struct clk hsotgusb_ick = {
1536 .name = "hsotgusb_ick",
1537 .parent = &core_l3_ick,
1538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1539 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1540 .flags = CLOCK_IN_OMAP343X,
1541 .recalc = &followparent_recalc,
1544 static struct clk sdrc_ick = {
1546 .parent = &core_l3_ick,
1547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1548 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1549 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1550 .recalc = &followparent_recalc,
1553 static struct clk gpmc_fck = {
1555 .parent = &core_l3_ick,
1556 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1558 .recalc = &followparent_recalc,
1561 /* SECURITY_L3_ICK based clocks */
1563 static struct clk security_l3_ick = {
1564 .name = "security_l3_ick",
1566 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1567 PARENT_CONTROLS_CLOCK,
1568 .recalc = &followparent_recalc,
1571 static struct clk pka_ick = {
1573 .parent = &security_l3_ick,
1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1575 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1576 .flags = CLOCK_IN_OMAP343X,
1577 .recalc = &followparent_recalc,
1580 /* CORE_L4_ICK based clocks */
1582 static struct clk core_l4_ick = {
1583 .name = "core_l4_ick",
1585 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1586 PARENT_CONTROLS_CLOCK,
1587 .recalc = &followparent_recalc,
1590 static struct clk usbtll_ick = {
1591 .name = "usbtll_ick",
1592 .parent = &core_l4_ick,
1593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1594 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1595 .flags = CLOCK_IN_OMAP3430ES2,
1596 .recalc = &followparent_recalc,
1599 static struct clk mmchs3_ick = {
1600 .name = "mmchs_ick",
1602 .parent = &core_l4_ick,
1603 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1604 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1605 .flags = CLOCK_IN_OMAP3430ES2,
1606 .recalc = &followparent_recalc,
1609 /* Intersystem Communication Registers - chassis mode only */
1610 static struct clk icr_ick = {
1612 .parent = &core_l4_ick,
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1614 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1615 .flags = CLOCK_IN_OMAP343X,
1616 .recalc = &followparent_recalc,
1619 static struct clk aes2_ick = {
1621 .parent = &core_l4_ick,
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1624 .flags = CLOCK_IN_OMAP343X,
1625 .recalc = &followparent_recalc,
1628 static struct clk sha12_ick = {
1629 .name = "sha12_ick",
1630 .parent = &core_l4_ick,
1631 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1632 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1633 .flags = CLOCK_IN_OMAP343X,
1634 .recalc = &followparent_recalc,
1637 static struct clk des2_ick = {
1639 .parent = &core_l4_ick,
1640 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1641 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1642 .flags = CLOCK_IN_OMAP343X,
1643 .recalc = &followparent_recalc,
1646 static struct clk mmchs2_ick = {
1647 .name = "mmchs_ick",
1649 .parent = &core_l4_ick,
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1652 .flags = CLOCK_IN_OMAP343X,
1653 .recalc = &followparent_recalc,
1656 static struct clk mmchs1_ick = {
1657 .name = "mmchs_ick",
1659 .parent = &core_l4_ick,
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1661 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1662 .flags = CLOCK_IN_OMAP343X,
1663 .recalc = &followparent_recalc,
1666 static struct clk mspro_ick = {
1667 .name = "mspro_ick",
1668 .parent = &core_l4_ick,
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1671 .flags = CLOCK_IN_OMAP343X,
1672 .recalc = &followparent_recalc,
1675 static struct clk hdq_ick = {
1677 .parent = &core_l4_ick,
1678 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1679 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1680 .flags = CLOCK_IN_OMAP343X,
1681 .recalc = &followparent_recalc,
1684 static struct clk mcspi4_ick = {
1685 .name = "mcspi_ick",
1687 .parent = &core_l4_ick,
1688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1690 .flags = CLOCK_IN_OMAP343X,
1691 .recalc = &followparent_recalc,
1694 static struct clk mcspi3_ick = {
1695 .name = "mcspi_ick",
1697 .parent = &core_l4_ick,
1698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1699 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1700 .flags = CLOCK_IN_OMAP343X,
1701 .recalc = &followparent_recalc,
1704 static struct clk mcspi2_ick = {
1705 .name = "mcspi_ick",
1707 .parent = &core_l4_ick,
1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1709 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1710 .flags = CLOCK_IN_OMAP343X,
1711 .recalc = &followparent_recalc,
1714 static struct clk mcspi1_ick = {
1715 .name = "mcspi_ick",
1717 .parent = &core_l4_ick,
1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1719 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1720 .flags = CLOCK_IN_OMAP343X,
1721 .recalc = &followparent_recalc,
1724 static struct clk i2c3_ick = {
1727 .parent = &core_l4_ick,
1728 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1729 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1730 .flags = CLOCK_IN_OMAP343X,
1731 .recalc = &followparent_recalc,
1734 static struct clk i2c2_ick = {
1737 .parent = &core_l4_ick,
1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1740 .flags = CLOCK_IN_OMAP343X,
1741 .recalc = &followparent_recalc,
1744 static struct clk i2c1_ick = {
1747 .parent = &core_l4_ick,
1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1749 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1750 .flags = CLOCK_IN_OMAP343X,
1751 .recalc = &followparent_recalc,
1754 static struct clk uart2_ick = {
1755 .name = "uart2_ick",
1756 .parent = &core_l4_ick,
1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1759 .flags = CLOCK_IN_OMAP343X,
1760 .recalc = &followparent_recalc,
1763 static struct clk uart1_ick = {
1764 .name = "uart1_ick",
1765 .parent = &core_l4_ick,
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1767 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1768 .flags = CLOCK_IN_OMAP343X,
1769 .recalc = &followparent_recalc,
1772 static struct clk gpt11_ick = {
1773 .name = "gpt11_ick",
1774 .parent = &core_l4_ick,
1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1776 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1777 .flags = CLOCK_IN_OMAP343X,
1778 .recalc = &followparent_recalc,
1781 static struct clk gpt10_ick = {
1782 .name = "gpt10_ick",
1783 .parent = &core_l4_ick,
1784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1785 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1786 .flags = CLOCK_IN_OMAP343X,
1787 .recalc = &followparent_recalc,
1790 static struct clk mcbsp5_ick = {
1791 .name = "mcbsp5_ick",
1792 .parent = &core_l4_ick,
1793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1794 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1795 .flags = CLOCK_IN_OMAP343X,
1796 .recalc = &followparent_recalc,
1799 static struct clk mcbsp1_ick = {
1800 .name = "mcbsp1_ick",
1801 .parent = &core_l4_ick,
1802 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1804 .flags = CLOCK_IN_OMAP343X,
1805 .recalc = &followparent_recalc,
1808 static struct clk fac_ick = {
1810 .parent = &core_l4_ick,
1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1812 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1813 .flags = CLOCK_IN_OMAP3430ES1,
1814 .recalc = &followparent_recalc,
1817 static struct clk mailboxes_ick = {
1818 .name = "mailboxes_ick",
1819 .parent = &core_l4_ick,
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1822 .flags = CLOCK_IN_OMAP343X,
1823 .recalc = &followparent_recalc,
1826 static struct clk omapctrl_ick = {
1827 .name = "omapctrl_ick",
1828 .parent = &core_l4_ick,
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1831 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1832 .recalc = &followparent_recalc,
1835 /* SSI_L4_ICK based clocks */
1837 static struct clk ssi_l4_ick = {
1838 .name = "ssi_l4_ick",
1840 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1841 .recalc = &followparent_recalc,
1844 static struct clk ssi_ick = {
1846 .parent = &ssi_l4_ick,
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1849 .flags = CLOCK_IN_OMAP343X,
1850 .recalc = &followparent_recalc,
1853 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1854 * but l4_ick makes more sense to me */
1856 static const struct clksel usb_l4_clksel[] = {
1857 { .parent = &l4_ick, .rates = div2_rates },
1861 static struct clk usb_l4_ick = {
1862 .name = "usb_l4_ick",
1864 .init = &omap2_init_clksel_parent,
1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1867 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1868 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1869 .clksel = usb_l4_clksel,
1870 .flags = CLOCK_IN_OMAP3430ES1,
1871 .recalc = &omap2_clksel_recalc,
1874 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1876 /* SECURITY_L4_ICK2 based clocks */
1878 static struct clk security_l4_ick2 = {
1879 .name = "security_l4_ick2",
1881 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1882 PARENT_CONTROLS_CLOCK,
1883 .recalc = &followparent_recalc,
1886 static struct clk aes1_ick = {
1888 .parent = &security_l4_ick2,
1889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1890 .enable_bit = OMAP3430_EN_AES1_SHIFT,
1891 .flags = CLOCK_IN_OMAP343X,
1892 .recalc = &followparent_recalc,
1895 static struct clk rng_ick = {
1897 .parent = &security_l4_ick2,
1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1899 .enable_bit = OMAP3430_EN_RNG_SHIFT,
1900 .flags = CLOCK_IN_OMAP343X,
1901 .recalc = &followparent_recalc,
1904 static struct clk sha11_ick = {
1905 .name = "sha11_ick",
1906 .parent = &security_l4_ick2,
1907 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1908 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
1909 .flags = CLOCK_IN_OMAP343X,
1910 .recalc = &followparent_recalc,
1913 static struct clk des1_ick = {
1915 .parent = &security_l4_ick2,
1916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1917 .enable_bit = OMAP3430_EN_DES1_SHIFT,
1918 .flags = CLOCK_IN_OMAP343X,
1919 .recalc = &followparent_recalc,
1923 static const struct clksel dss1_alwon_fck_clksel[] = {
1924 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1925 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1929 static struct clk dss1_alwon_fck = {
1930 .name = "dss1_alwon_fck",
1931 .parent = &dpll4_m4x2_ck,
1932 .init = &omap2_init_clksel_parent,
1933 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1934 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1935 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1936 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1937 .clksel = dss1_alwon_fck_clksel,
1938 .flags = CLOCK_IN_OMAP343X,
1939 .recalc = &omap2_clksel_recalc,
1942 static struct clk dss_tv_fck = {
1943 .name = "dss_tv_fck",
1944 .parent = &omap_54m_fck,
1945 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1946 .enable_bit = OMAP3430_EN_TV_SHIFT,
1947 .flags = CLOCK_IN_OMAP343X,
1948 .recalc = &followparent_recalc,
1951 static struct clk dss_96m_fck = {
1952 .name = "dss_96m_fck",
1953 .parent = &omap_96m_fck,
1954 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1955 .enable_bit = OMAP3430_EN_TV_SHIFT,
1956 .flags = CLOCK_IN_OMAP343X,
1957 .recalc = &followparent_recalc,
1960 static struct clk dss2_alwon_fck = {
1961 .name = "dss2_alwon_fck",
1963 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1964 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1965 .flags = CLOCK_IN_OMAP343X,
1966 .recalc = &followparent_recalc,
1969 static struct clk dss_ick = {
1970 /* Handles both L3 and L4 clocks */
1973 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1974 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1975 .flags = CLOCK_IN_OMAP343X,
1976 .recalc = &followparent_recalc,
1981 static const struct clksel cam_mclk_clksel[] = {
1982 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1983 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
1987 static struct clk cam_mclk = {
1989 .parent = &dpll4_m5x2_ck,
1990 .init = &omap2_init_clksel_parent,
1991 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1992 .clksel_mask = OMAP3430_ST_PERIPH_CLK,
1993 .clksel = cam_mclk_clksel,
1994 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1995 .enable_bit = OMAP3430_EN_CAM_SHIFT,
1996 .flags = CLOCK_IN_OMAP343X,
1997 .recalc = &omap2_clksel_recalc,
2000 static struct clk cam_l3_ick = {
2001 .name = "cam_l3_ick",
2003 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2004 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2005 .flags = CLOCK_IN_OMAP343X,
2006 .recalc = &followparent_recalc,
2009 static struct clk cam_l4_ick = {
2010 .name = "cam_l4_ick",
2012 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2013 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2014 .flags = CLOCK_IN_OMAP343X,
2015 .recalc = &followparent_recalc,
2018 /* USBHOST - 3430ES2 only */
2020 static struct clk usbhost_120m_fck = {
2021 .name = "usbhost_120m_fck",
2022 .parent = &omap_120m_fck,
2023 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2024 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2025 .flags = CLOCK_IN_OMAP3430ES2,
2026 .recalc = &followparent_recalc,
2029 static struct clk usbhost_48m_fck = {
2030 .name = "usbhost_48m_fck",
2031 .parent = &omap_48m_fck,
2032 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2033 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2034 .flags = CLOCK_IN_OMAP3430ES2,
2035 .recalc = &followparent_recalc,
2038 static struct clk usbhost_l3_ick = {
2039 .name = "usbhost_l3_ick",
2041 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2042 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2043 .flags = CLOCK_IN_OMAP3430ES2,
2044 .recalc = &followparent_recalc,
2047 static struct clk usbhost_l4_ick = {
2048 .name = "usbhost_l4_ick",
2050 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2051 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2052 .flags = CLOCK_IN_OMAP3430ES2,
2053 .recalc = &followparent_recalc,
2056 static struct clk usbhost_sar_fck = {
2057 .name = "usbhost_sar_fck",
2058 .parent = &osc_sys_ck,
2059 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2060 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2061 .flags = CLOCK_IN_OMAP3430ES2,
2062 .recalc = &followparent_recalc,
2067 static const struct clksel_rate usim_96m_rates[] = {
2068 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2069 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2070 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2071 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2075 static const struct clksel_rate usim_120m_rates[] = {
2076 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2077 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2078 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2079 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2083 static const struct clksel usim_clksel[] = {
2084 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2085 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2086 { .parent = &sys_ck, .rates = div2_rates },
2091 static struct clk usim_fck = {
2093 .init = &omap2_init_clksel_parent,
2094 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2095 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2096 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2097 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2098 .clksel = usim_clksel,
2099 .flags = CLOCK_IN_OMAP3430ES2,
2100 .recalc = &omap2_clksel_recalc,
2103 static struct clk gpt1_fck = {
2105 .init = &omap2_init_clksel_parent,
2106 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2107 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2108 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2109 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2110 .clksel = omap343x_gpt_clksel,
2111 .flags = CLOCK_IN_OMAP343X,
2112 .recalc = &omap2_clksel_recalc,
2115 static struct clk wkup_32k_fck = {
2116 .name = "wkup_32k_fck",
2117 .parent = &omap_32k_fck,
2118 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2119 .recalc = &followparent_recalc,
2122 static struct clk gpio1_fck = {
2123 .name = "gpio1_fck",
2124 .parent = &wkup_32k_fck,
2125 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2126 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2127 .flags = CLOCK_IN_OMAP343X,
2128 .recalc = &followparent_recalc,
2131 static struct clk wdt2_fck = {
2133 .parent = &wkup_32k_fck,
2134 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2135 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2136 .flags = CLOCK_IN_OMAP343X,
2137 .recalc = &followparent_recalc,
2140 static struct clk wkup_l4_ick = {
2141 .name = "wkup_l4_ick",
2143 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2144 .recalc = &followparent_recalc,
2148 /* Never specifically named in the TRM, so we have to infer a likely name */
2149 static struct clk usim_ick = {
2151 .parent = &wkup_l4_ick,
2152 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2153 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2154 .flags = CLOCK_IN_OMAP3430ES2,
2155 .recalc = &followparent_recalc,
2158 static struct clk wdt2_ick = {
2160 .parent = &wkup_l4_ick,
2161 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2162 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2163 .flags = CLOCK_IN_OMAP343X,
2164 .recalc = &followparent_recalc,
2167 static struct clk wdt1_ick = {
2169 .parent = &wkup_l4_ick,
2170 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2171 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2172 .flags = CLOCK_IN_OMAP343X,
2173 .recalc = &followparent_recalc,
2176 static struct clk gpio1_ick = {
2177 .name = "gpio1_ick",
2178 .parent = &wkup_l4_ick,
2179 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2180 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2181 .flags = CLOCK_IN_OMAP343X,
2182 .recalc = &followparent_recalc,
2185 static struct clk omap_32ksync_ick = {
2186 .name = "omap_32ksync_ick",
2187 .parent = &wkup_l4_ick,
2188 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2189 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2190 .flags = CLOCK_IN_OMAP343X,
2191 .recalc = &followparent_recalc,
2194 static struct clk gpt12_ick = {
2195 .name = "gpt12_ick",
2196 .parent = &wkup_l4_ick,
2197 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2198 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2199 .flags = CLOCK_IN_OMAP343X,
2200 .recalc = &followparent_recalc,
2203 static struct clk gpt1_ick = {
2205 .parent = &wkup_l4_ick,
2206 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2207 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2208 .flags = CLOCK_IN_OMAP343X,
2209 .recalc = &followparent_recalc,
2214 /* PER clock domain */
2216 static struct clk per_96m_fck = {
2217 .name = "per_96m_fck",
2218 .parent = &omap_96m_alwon_fck,
2219 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2220 PARENT_CONTROLS_CLOCK,
2221 .recalc = &followparent_recalc,
2224 static struct clk per_48m_fck = {
2225 .name = "per_48m_fck",
2226 .parent = &omap_48m_fck,
2227 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2228 PARENT_CONTROLS_CLOCK,
2229 .recalc = &followparent_recalc,
2232 static struct clk uart3_fck = {
2233 .name = "uart3_fck",
2234 .parent = &per_48m_fck,
2235 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2236 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2237 .flags = CLOCK_IN_OMAP343X,
2238 .recalc = &followparent_recalc,
2241 static struct clk gpt2_fck = {
2243 .init = &omap2_init_clksel_parent,
2244 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2245 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2246 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2247 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2248 .clksel = omap343x_gpt_clksel,
2249 .flags = CLOCK_IN_OMAP343X,
2250 .recalc = &omap2_clksel_recalc,
2253 static struct clk gpt3_fck = {
2255 .init = &omap2_init_clksel_parent,
2256 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2257 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2258 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2259 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2260 .clksel = omap343x_gpt_clksel,
2261 .flags = CLOCK_IN_OMAP343X,
2262 .recalc = &omap2_clksel_recalc,
2265 static struct clk gpt4_fck = {
2267 .init = &omap2_init_clksel_parent,
2268 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2269 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2270 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2271 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2272 .clksel = omap343x_gpt_clksel,
2273 .flags = CLOCK_IN_OMAP343X,
2274 .recalc = &omap2_clksel_recalc,
2277 static struct clk gpt5_fck = {
2279 .init = &omap2_init_clksel_parent,
2280 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2281 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2282 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2283 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2284 .clksel = omap343x_gpt_clksel,
2285 .flags = CLOCK_IN_OMAP343X,
2286 .recalc = &omap2_clksel_recalc,
2289 static struct clk gpt6_fck = {
2291 .init = &omap2_init_clksel_parent,
2292 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2293 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2294 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2295 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2296 .clksel = omap343x_gpt_clksel,
2297 .flags = CLOCK_IN_OMAP343X,
2298 .recalc = &omap2_clksel_recalc,
2301 static struct clk gpt7_fck = {
2303 .init = &omap2_init_clksel_parent,
2304 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2305 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2306 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2307 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2308 .clksel = omap343x_gpt_clksel,
2309 .flags = CLOCK_IN_OMAP343X,
2310 .recalc = &omap2_clksel_recalc,
2313 static struct clk gpt8_fck = {
2315 .init = &omap2_init_clksel_parent,
2316 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2317 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2318 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2319 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2320 .clksel = omap343x_gpt_clksel,
2321 .flags = CLOCK_IN_OMAP343X,
2322 .recalc = &omap2_clksel_recalc,
2325 static struct clk gpt9_fck = {
2327 .init = &omap2_init_clksel_parent,
2328 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2329 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2330 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2331 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2332 .clksel = omap343x_gpt_clksel,
2333 .flags = CLOCK_IN_OMAP343X,
2334 .recalc = &omap2_clksel_recalc,
2337 static struct clk per_32k_alwon_fck = {
2338 .name = "per_32k_alwon_fck",
2339 .parent = &omap_32k_fck,
2340 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2341 .recalc = &followparent_recalc,
2344 static struct clk gpio6_fck = {
2345 .name = "gpio6_fck",
2346 .parent = &per_32k_alwon_fck,
2347 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2348 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2349 .flags = CLOCK_IN_OMAP343X,
2350 .recalc = &followparent_recalc,
2353 static struct clk gpio5_fck = {
2354 .name = "gpio5_fck",
2355 .parent = &per_32k_alwon_fck,
2356 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2357 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2358 .flags = CLOCK_IN_OMAP343X,
2359 .recalc = &followparent_recalc,
2362 static struct clk gpio4_fck = {
2363 .name = "gpio4_fck",
2364 .parent = &per_32k_alwon_fck,
2365 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2366 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2367 .flags = CLOCK_IN_OMAP343X,
2368 .recalc = &followparent_recalc,
2371 static struct clk gpio3_fck = {
2372 .name = "gpio3_fck",
2373 .parent = &per_32k_alwon_fck,
2374 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2375 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2376 .flags = CLOCK_IN_OMAP343X,
2377 .recalc = &followparent_recalc,
2380 static struct clk gpio2_fck = {
2381 .name = "gpio2_fck",
2382 .parent = &per_32k_alwon_fck,
2383 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2384 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2385 .flags = CLOCK_IN_OMAP343X,
2386 .recalc = &followparent_recalc,
2389 static struct clk wdt3_fck = {
2391 .parent = &per_32k_alwon_fck,
2392 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2393 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2394 .flags = CLOCK_IN_OMAP343X,
2395 .recalc = &followparent_recalc,
2398 static struct clk per_l4_ick = {
2399 .name = "per_l4_ick",
2401 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2402 PARENT_CONTROLS_CLOCK,
2403 .recalc = &followparent_recalc,
2406 static struct clk gpio6_ick = {
2407 .name = "gpio6_ick",
2408 .parent = &per_l4_ick,
2409 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2410 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2411 .flags = CLOCK_IN_OMAP343X,
2412 .recalc = &followparent_recalc,
2415 static struct clk gpio5_ick = {
2416 .name = "gpio5_ick",
2417 .parent = &per_l4_ick,
2418 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2419 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2420 .flags = CLOCK_IN_OMAP343X,
2421 .recalc = &followparent_recalc,
2424 static struct clk gpio4_ick = {
2425 .name = "gpio4_ick",
2426 .parent = &per_l4_ick,
2427 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2428 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2429 .flags = CLOCK_IN_OMAP343X,
2430 .recalc = &followparent_recalc,
2433 static struct clk gpio3_ick = {
2434 .name = "gpio3_ick",
2435 .parent = &per_l4_ick,
2436 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2437 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2438 .flags = CLOCK_IN_OMAP343X,
2439 .recalc = &followparent_recalc,
2442 static struct clk gpio2_ick = {
2443 .name = "gpio2_ick",
2444 .parent = &per_l4_ick,
2445 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2446 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2447 .flags = CLOCK_IN_OMAP343X,
2448 .recalc = &followparent_recalc,
2451 static struct clk wdt3_ick = {
2453 .parent = &per_l4_ick,
2454 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2455 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2456 .flags = CLOCK_IN_OMAP343X,
2457 .recalc = &followparent_recalc,
2460 static struct clk uart3_ick = {
2461 .name = "uart3_ick",
2462 .parent = &per_l4_ick,
2463 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2464 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2465 .flags = CLOCK_IN_OMAP343X,
2466 .recalc = &followparent_recalc,
2469 static struct clk gpt9_ick = {
2471 .parent = &per_l4_ick,
2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2473 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2474 .flags = CLOCK_IN_OMAP343X,
2475 .recalc = &followparent_recalc,
2478 static struct clk gpt8_ick = {
2480 .parent = &per_l4_ick,
2481 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2482 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2483 .flags = CLOCK_IN_OMAP343X,
2484 .recalc = &followparent_recalc,
2487 static struct clk gpt7_ick = {
2489 .parent = &per_l4_ick,
2490 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2491 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2492 .flags = CLOCK_IN_OMAP343X,
2493 .recalc = &followparent_recalc,
2496 static struct clk gpt6_ick = {
2498 .parent = &per_l4_ick,
2499 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2500 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2501 .flags = CLOCK_IN_OMAP343X,
2502 .recalc = &followparent_recalc,
2505 static struct clk gpt5_ick = {
2507 .parent = &per_l4_ick,
2508 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2509 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2510 .flags = CLOCK_IN_OMAP343X,
2511 .recalc = &followparent_recalc,
2514 static struct clk gpt4_ick = {
2516 .parent = &per_l4_ick,
2517 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2518 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2519 .flags = CLOCK_IN_OMAP343X,
2520 .recalc = &followparent_recalc,
2523 static struct clk gpt3_ick = {
2525 .parent = &per_l4_ick,
2526 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2527 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2528 .flags = CLOCK_IN_OMAP343X,
2529 .recalc = &followparent_recalc,
2532 static struct clk gpt2_ick = {
2534 .parent = &per_l4_ick,
2535 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2536 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2537 .flags = CLOCK_IN_OMAP343X,
2538 .recalc = &followparent_recalc,
2541 static struct clk mcbsp2_ick = {
2542 .name = "mcbsp2_ick",
2543 .parent = &per_l4_ick,
2544 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2545 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2546 .flags = CLOCK_IN_OMAP343X,
2547 .recalc = &followparent_recalc,
2550 static struct clk mcbsp3_ick = {
2551 .name = "mcbsp3_ick",
2552 .parent = &per_l4_ick,
2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2554 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2555 .flags = CLOCK_IN_OMAP343X,
2556 .recalc = &followparent_recalc,
2559 static struct clk mcbsp4_ick = {
2560 .name = "mcbsp4_ick",
2561 .parent = &per_l4_ick,
2562 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2563 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2564 .flags = CLOCK_IN_OMAP343X,
2565 .recalc = &followparent_recalc,
2568 static const struct clksel mcbsp_234_clksel[] = {
2569 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2570 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2574 static struct clk mcbsp2_fck = {
2575 .name = "mcbsp2_fck",
2576 .init = &omap2_init_clksel_parent,
2577 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2578 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2579 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2580 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2581 .clksel = mcbsp_234_clksel,
2582 .flags = CLOCK_IN_OMAP343X,
2583 .recalc = &omap2_clksel_recalc,
2586 static struct clk mcbsp3_fck = {
2587 .name = "mcbsp3_fck",
2588 .init = &omap2_init_clksel_parent,
2589 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2591 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2592 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2593 .clksel = mcbsp_234_clksel,
2594 .flags = CLOCK_IN_OMAP343X,
2595 .recalc = &omap2_clksel_recalc,
2598 static struct clk mcbsp4_fck = {
2599 .name = "mcbsp4_fck",
2600 .init = &omap2_init_clksel_parent,
2601 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2602 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2603 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2604 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2605 .clksel = mcbsp_234_clksel,
2606 .flags = CLOCK_IN_OMAP343X,
2607 .recalc = &omap2_clksel_recalc,
2612 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2614 static const struct clksel_rate emu_src_sys_rates[] = {
2615 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2619 static const struct clksel_rate emu_src_core_rates[] = {
2620 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2624 static const struct clksel_rate emu_src_per_rates[] = {
2625 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2629 static const struct clksel_rate emu_src_mpu_rates[] = {
2630 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2634 static const struct clksel emu_src_clksel[] = {
2635 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2636 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2637 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2638 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2643 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2644 * to switch the source of some of the EMU clocks.
2645 * XXX Are there CLKEN bits for these EMU clks?
2647 static struct clk emu_src_ck = {
2648 .name = "emu_src_ck",
2649 .init = &omap2_init_clksel_parent,
2650 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2651 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2652 .clksel = emu_src_clksel,
2653 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2654 .recalc = &omap2_clksel_recalc,
2657 static const struct clksel_rate pclk_emu_rates[] = {
2658 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2659 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2660 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2661 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2665 static const struct clksel pclk_emu_clksel[] = {
2666 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2670 static struct clk pclk_fck = {
2672 .init = &omap2_init_clksel_parent,
2673 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2674 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2675 .clksel = pclk_emu_clksel,
2676 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2677 .recalc = &omap2_clksel_recalc,
2680 static const struct clksel_rate pclkx2_emu_rates[] = {
2681 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2682 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2683 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2687 static const struct clksel pclkx2_emu_clksel[] = {
2688 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2692 static struct clk pclkx2_fck = {
2693 .name = "pclkx2_fck",
2694 .init = &omap2_init_clksel_parent,
2695 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2696 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2697 .clksel = pclkx2_emu_clksel,
2698 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2699 .recalc = &omap2_clksel_recalc,
2702 static const struct clksel atclk_emu_clksel[] = {
2703 { .parent = &emu_src_ck, .rates = div2_rates },
2707 static struct clk atclk_fck = {
2708 .name = "atclk_fck",
2709 .init = &omap2_init_clksel_parent,
2710 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2711 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2712 .clksel = atclk_emu_clksel,
2713 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2714 .recalc = &omap2_clksel_recalc,
2717 static struct clk traceclk_src_fck = {
2718 .name = "traceclk_src_fck",
2719 .init = &omap2_init_clksel_parent,
2720 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2721 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2722 .clksel = emu_src_clksel,
2723 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2724 .recalc = &omap2_clksel_recalc,
2727 static const struct clksel_rate traceclk_rates[] = {
2728 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2729 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2730 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2734 static const struct clksel traceclk_clksel[] = {
2735 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2739 static struct clk traceclk_fck = {
2740 .name = "traceclk_fck",
2741 .init = &omap2_init_clksel_parent,
2742 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2743 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2744 .clksel = traceclk_clksel,
2745 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2746 .recalc = &omap2_clksel_recalc,
2751 /* SmartReflex fclk (VDD1) */
2752 static struct clk sr1_fck = {
2755 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2756 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2757 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2758 .recalc = &followparent_recalc,
2761 /* SmartReflex fclk (VDD2) */
2762 static struct clk sr2_fck = {
2765 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2766 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2767 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2768 .recalc = &followparent_recalc,
2771 static struct clk sr_l4_ick = {
2772 .name = "sr_l4_ick",
2774 .flags = CLOCK_IN_OMAP343X,
2775 .recalc = &followparent_recalc,
2778 /* SECURE_32K_FCK clocks */
2780 static struct clk gpt12_fck = {
2781 .name = "gpt12_fck",
2782 .parent = &secure_32k_fck,
2783 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2784 .recalc = &followparent_recalc,
2787 static struct clk wdt1_fck = {
2789 .parent = &secure_32k_fck,
2790 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2791 .recalc = &followparent_recalc,
2794 static struct clk *onchip_34xx_clks[] __initdata = {
2822 &omap_96m_alwon_fck,