arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 static void omap3_dpll_recalc(struct clk *clk);
  31 static void omap3_clkoutx2_recalc(struct clk *clk);
  32 static void omap3_dpll_allow_idle(struct clk *clk);
  33 static void omap3_dpll_deny_idle(struct clk *clk);
  34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  35
  36 /* Maximum DPLL multiplier, divider values for OMAP3 */
  37 #define OMAP3_MAX_DPLL_MULT             2048
  38 #define OMAP3_MAX_DPLL_DIV              128
  39
  40 /*
  41  * DPLL1 supplies clock to the MPU.
  42  * DPLL2 supplies clock to the IVA2.
  43  * DPLL3 supplies CORE domain clocks.
  44  * DPLL4 supplies peripheral clocks.
  45  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  46  */
  47
  48 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  49 #define DPLL_LOW_POWER_STOP             0x1
  50 #define DPLL_LOW_POWER_BYPASS           0x5
  51 #define DPLL_LOCKED                     0x7
  52
  53 /* PRM CLOCKS */
  54
  55 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  56 static struct clk omap_32k_fck = {
  57         .name           = "omap_32k_fck",
  58         .ops            = &clkops_null,
  59         .rate           = 32768,
  60         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  61 };
  62
  63 static struct clk secure_32k_fck = {
  64         .name           = "secure_32k_fck",
  65         .ops            = &clkops_null,
  66         .rate           = 32768,
  67         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  68 };
  69
  70 /* Virtual source clocks for osc_sys_ck */
  71 static struct clk virt_12m_ck = {
  72         .name           = "virt_12m_ck",
  73         .ops            = &clkops_null,
  74         .rate           = 12000000,
  75         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  76 };
  77
  78 static struct clk virt_13m_ck = {
  79         .name           = "virt_13m_ck",
  80         .ops            = &clkops_null,
  81         .rate           = 13000000,
  82         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  83 };
  84
  85 static struct clk virt_16_8m_ck = {
  86         .name           = "virt_16_8m_ck",
  87         .ops            = &clkops_null,
  88         .rate           = 16800000,
  89         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES,
  90 };
  91
  92 static struct clk virt_19_2m_ck = {
  93         .name           = "virt_19_2m_ck",
  94         .ops            = &clkops_null,
  95         .rate           = 19200000,
  96         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
  97 };
  98
  99 static struct clk virt_26m_ck = {
 100         .name           = "virt_26m_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 26000000,
 103         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 104 };
 105
 106 static struct clk virt_38_4m_ck = {
 107         .name           = "virt_38_4m_ck",
 108         .ops            = &clkops_null,
 109         .rate           = 38400000,
 110         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 111 };
 112
 113 static const struct clksel_rate osc_sys_12m_rates[] = {
 114         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 115         { .div = 0 }
 116 };
 117
 118 static const struct clksel_rate osc_sys_13m_rates[] = {
 119         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 120         { .div = 0 }
 121 };
 122
 123 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 124         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 125         { .div = 0 }
 126 };
 127
 128 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 129         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 130         { .div = 0 }
 131 };
 132
 133 static const struct clksel_rate osc_sys_26m_rates[] = {
 134         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 135         { .div = 0 }
 136 };
 137
 138 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 139         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 140         { .div = 0 }
 141 };
 142
 143 static const struct clksel osc_sys_clksel[] = {
 144         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 145         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 146         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 147         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 148         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 149         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 150         { .parent = NULL },
 151 };
 152
 153 /* Oscillator clock */
 154 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 155 static struct clk osc_sys_ck = {
 156         .name           = "osc_sys_ck",
 157         .ops            = &clkops_null,
 158         .init           = &omap2_init_clksel_parent,
 159         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 160         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 161         .clksel         = osc_sys_clksel,
 162         /* REVISIT: deal with autoextclkmode? */
 163         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
 164         .recalc         = &omap2_clksel_recalc,
 165 };
 166
 167 static const struct clksel_rate div2_rates[] = {
 168         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 169         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 170         { .div = 0 }
 171 };
 172
 173 static const struct clksel sys_clksel[] = {
 174         { .parent = &osc_sys_ck, .rates = div2_rates },
 175         { .parent = NULL }
 176 };
 177
 178 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 179 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 180 static struct clk sys_ck = {
 181         .name           = "sys_ck",
 182         .ops            = &clkops_null,
 183         .parent         = &osc_sys_ck,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 186         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 187         .clksel         = sys_clksel,
 188         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 189         .recalc         = &omap2_clksel_recalc,
 190 };
 191
 192 static struct clk sys_altclk = {
 193         .name           = "sys_altclk",
 194         .ops            = &clkops_null,
 195         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 196 };
 197
 198 /* Optional external clock input for some McBSPs */
 199 static struct clk mcbsp_clks = {
 200         .name           = "mcbsp_clks",
 201         .ops            = &clkops_null,
 202         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 203 };
 204
 205 /* PRM EXTERNAL CLOCK OUTPUT */
 206
 207 static struct clk sys_clkout1 = {
 208         .name           = "sys_clkout1",
 209         .ops            = &clkops_omap2_dflt,
 210         .parent         = &osc_sys_ck,
 211         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 212         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 213         .flags          = CLOCK_IN_OMAP343X,
 214         .recalc         = &followparent_recalc,
 215 };
 216
 217 /* DPLLS */
 218
 219 /* CM CLOCKS */
 220
 221 static const struct clksel_rate dpll_bypass_rates[] = {
 222         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 223         { .div = 0 }
 224 };
 225
 226 static const struct clksel_rate dpll_locked_rates[] = {
 227         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 228         { .div = 0 }
 229 };
 230
 231 static const struct clksel_rate div16_dpll_rates[] = {
 232         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 233         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 234         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 235         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 236         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 237         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 238         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 239         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 240         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 241         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 242         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 243         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 244         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 245         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 246         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 247         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 248         { .div = 0 }
 249 };
 250
 251 /* DPLL1 */
 252 /* MPU clock source */
 253 /* Type: DPLL */
 254 static struct dpll_data dpll1_dd = {
 255         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 256         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 257         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 258         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 259         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 260         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 261         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 262         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 263         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 264         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 265         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 266         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 267         .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 268         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 269         .max_divider    = OMAP3_MAX_DPLL_DIV,
 270         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 271 };
 272
 273 static struct clk dpll1_ck = {
 274         .name           = "dpll1_ck",
 275         .ops            = &clkops_null,
 276         .parent         = &sys_ck,
 277         .dpll_data      = &dpll1_dd,
 278         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 279         .round_rate     = &omap2_dpll_round_rate,
 280         .recalc         = &omap3_dpll_recalc,
 281 };
 282
 283 /*
 284  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 285  * DPLL isn't bypassed.
 286  */
 287 static struct clk dpll1_x2_ck = {
 288         .name           = "dpll1_x2_ck",
 289         .ops            = &clkops_null,
 290         .parent         = &dpll1_ck,
 291         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 292         .recalc         = &omap3_clkoutx2_recalc,
 293 };
 294
 295 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 296 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 297         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 298         { .parent = NULL }
 299 };
 300
 301 /*
 302  * Does not exist in the TRM - needed to separate the M2 divider from
 303  * bypass selection in mpu_ck
 304  */
 305 static struct clk dpll1_x2m2_ck = {
 306         .name           = "dpll1_x2m2_ck",
 307         .ops            = &clkops_null,
 308         .parent         = &dpll1_x2_ck,
 309         .init           = &omap2_init_clksel_parent,
 310         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 311         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 312         .clksel         = div16_dpll1_x2m2_clksel,
 313         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 314         .recalc         = &omap2_clksel_recalc,
 315 };
 316
 317 /* DPLL2 */
 318 /* IVA2 clock source */
 319 /* Type: DPLL */
 320
 321 static struct dpll_data dpll2_dd = {
 322         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 323         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 324         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 325         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 326         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 327         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 328                                 (1 << DPLL_LOW_POWER_BYPASS),
 329         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 330         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 331         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 332         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 333         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 334         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 335         .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT,
 336         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 337         .max_divider    = OMAP3_MAX_DPLL_DIV,
 338         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 339 };
 340
 341 static struct clk dpll2_ck = {
 342         .name           = "dpll2_ck",
 343         .ops            = &clkops_noncore_dpll_ops,
 344         .parent         = &sys_ck,
 345         .dpll_data      = &dpll2_dd,
 346         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 347         .round_rate     = &omap2_dpll_round_rate,
 348         .recalc         = &omap3_dpll_recalc,
 349 };
 350
 351 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 352         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 353         { .parent = NULL }
 354 };
 355
 356 /*
 357  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 358  * or CLKOUTX2. CLKOUT seems most plausible.
 359  */
 360 static struct clk dpll2_m2_ck = {
 361         .name           = "dpll2_m2_ck",
 362         .ops            = &clkops_null,
 363         .parent         = &dpll2_ck,
 364         .init           = &omap2_init_clksel_parent,
 365         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 366                                           OMAP3430_CM_CLKSEL2_PLL),
 367         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 368         .clksel         = div16_dpll2_m2x2_clksel,
 369         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 370         .recalc         = &omap2_clksel_recalc,
 371 };
 372
 373 /*
 374  * DPLL3
 375  * Source clock for all interfaces and for some device fclks
 376  * REVISIT: Also supports fast relock bypass - not included below
 377  */
 378 static struct dpll_data dpll3_dd = {
 379         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 380         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 381         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 382         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 383         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 384         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 385         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 386         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 387         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 388         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 389         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 390         .max_divider    = OMAP3_MAX_DPLL_DIV,
 391         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 392 };
 393
 394 static struct clk dpll3_ck = {
 395         .name           = "dpll3_ck",
 396         .ops            = &clkops_null,
 397         .parent         = &sys_ck,
 398         .dpll_data      = &dpll3_dd,
 399         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 400         .round_rate     = &omap2_dpll_round_rate,
 401         .recalc         = &omap3_dpll_recalc,
 402 };
 403
 404 /*
 405  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 406  * DPLL isn't bypassed
 407  */
 408 static struct clk dpll3_x2_ck = {
 409         .name           = "dpll3_x2_ck",
 410         .ops            = &clkops_null,
 411         .parent         = &dpll3_ck,
 412         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 413         .recalc         = &omap3_clkoutx2_recalc,
 414 };
 415
 416 static const struct clksel_rate div31_dpll3_rates[] = {
 417         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 418         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 419         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 420         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 421         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 422         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 423         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 424         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 425         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 426         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 427         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 428         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 429         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 430         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 431         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 432         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 433         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 434         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 435         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 436         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 437         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 438         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 439         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 440         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 441         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 442         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 443         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 444         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 445         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 446         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 447         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 448         { .div = 0 },
 449 };
 450
 451 static const struct clksel div31_dpll3m2_clksel[] = {
 452         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 453         { .parent = NULL }
 454 };
 455
 456 /*
 457  * DPLL3 output M2
 458  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 459  * that code is ready, this should remain a 'read-only' clksel clock.
 460  */
 461 static struct clk dpll3_m2_ck = {
 462         .name           = "dpll3_m2_ck",
 463         .ops            = &clkops_null,
 464         .parent         = &dpll3_ck,
 465         .init           = &omap2_init_clksel_parent,
 466         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 467         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 468         .clksel         = div31_dpll3m2_clksel,
 469         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 470         .recalc         = &omap2_clksel_recalc,
 471 };
 472
 473 static const struct clksel core_ck_clksel[] = {
 474         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 475         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 476         { .parent = NULL }
 477 };
 478
 479 static struct clk core_ck = {
 480         .name           = "core_ck",
 481         .ops            = &clkops_null,
 482         .init           = &omap2_init_clksel_parent,
 483         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 484         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 485         .clksel         = core_ck_clksel,
 486         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 487         .recalc         = &omap2_clksel_recalc,
 488 };
 489
 490 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 491         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 492         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 493         { .parent = NULL }
 494 };
 495
 496 static struct clk dpll3_m2x2_ck = {
 497         .name           = "dpll3_m2x2_ck",
 498         .ops            = &clkops_null,
 499         .init           = &omap2_init_clksel_parent,
 500         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 501         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 502         .clksel         = dpll3_m2x2_ck_clksel,
 503         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 504         .recalc         = &omap2_clksel_recalc,
 505 };
 506
 507 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 508 static const struct clksel div16_dpll3_clksel[] = {
 509         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 510         { .parent = NULL }
 511 };
 512
 513 /* This virtual clock is the source for dpll3_m3x2_ck */
 514 static struct clk dpll3_m3_ck = {
 515         .name           = "dpll3_m3_ck",
 516         .ops            = &clkops_null,
 517         .parent         = &dpll3_ck,
 518         .init           = &omap2_init_clksel_parent,
 519         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 520         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 521         .clksel         = div16_dpll3_clksel,
 522         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 523         .recalc         = &omap2_clksel_recalc,
 524 };
 525
 526 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 527 static struct clk dpll3_m3x2_ck = {
 528         .name           = "dpll3_m3x2_ck",
 529         .ops            = &clkops_omap2_dflt_wait,
 530         .parent         = &dpll3_m3_ck,
 531         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 532         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 533         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 534         .recalc         = &omap3_clkoutx2_recalc,
 535 };
 536
 537 static const struct clksel emu_core_alwon_ck_clksel[] = {
 538         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 539         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 540         { .parent = NULL }
 541 };
 542
 543 static struct clk emu_core_alwon_ck = {
 544         .name           = "emu_core_alwon_ck",
 545         .ops            = &clkops_null,
 546         .parent         = &dpll3_m3x2_ck,
 547         .init           = &omap2_init_clksel_parent,
 548         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 549         .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
 550         .clksel         = emu_core_alwon_ck_clksel,
 551         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 552         .recalc         = &omap2_clksel_recalc,
 553 };
 554
 555 /* DPLL4 */
 556 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 557 /* Type: DPLL */
 558 static struct dpll_data dpll4_dd = {
 559         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 560         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 561         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 562         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 563         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 564         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 565         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 566         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 567         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 568         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 569         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 570         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 571         .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 572         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 573         .max_divider    = OMAP3_MAX_DPLL_DIV,
 574         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 575 };
 576
 577 static struct clk dpll4_ck = {
 578         .name           = "dpll4_ck",
 579         .ops            = &clkops_noncore_dpll_ops,
 580         .parent         = &sys_ck,
 581         .dpll_data      = &dpll4_dd,
 582         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 583         .round_rate     = &omap2_dpll_round_rate,
 584         .recalc         = &omap3_dpll_recalc,
 585 };
 586
 587 /*
 588  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 589  * DPLL isn't bypassed --
 590  * XXX does this serve any downstream clocks?
 591  */
 592 static struct clk dpll4_x2_ck = {
 593         .name           = "dpll4_x2_ck",
 594         .ops            = &clkops_null,
 595         .parent         = &dpll4_ck,
 596         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 597         .recalc         = &omap3_clkoutx2_recalc,
 598 };
 599
 600 static const struct clksel div16_dpll4_clksel[] = {
 601         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 602         { .parent = NULL }
 603 };
 604
 605 /* This virtual clock is the source for dpll4_m2x2_ck */
 606 static struct clk dpll4_m2_ck = {
 607         .name           = "dpll4_m2_ck",
 608         .ops            = &clkops_null,
 609         .parent         = &dpll4_ck,
 610         .init           = &omap2_init_clksel_parent,
 611         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 612         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 613         .clksel         = div16_dpll4_clksel,
 614         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 615         .recalc         = &omap2_clksel_recalc,
 616 };
 617
 618 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 619 static struct clk dpll4_m2x2_ck = {
 620         .name           = "dpll4_m2x2_ck",
 621         .ops            = &clkops_omap2_dflt_wait,
 622         .parent         = &dpll4_m2_ck,
 623         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 624         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 625         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 626         .recalc         = &omap3_clkoutx2_recalc,
 627 };
 628
 629 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 630         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 631         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 632         { .parent = NULL }
 633 };
 634
 635 static struct clk omap_96m_alwon_fck = {
 636         .name           = "omap_96m_alwon_fck",
 637         .ops            = &clkops_null,
 638         .parent         = &dpll4_m2x2_ck,
 639         .init           = &omap2_init_clksel_parent,
 640         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 641         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 642         .clksel         = omap_96m_alwon_fck_clksel,
 643         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 644         .recalc         = &omap2_clksel_recalc,
 645 };
 646
 647 static struct clk omap_96m_fck = {
 648         .name           = "omap_96m_fck",
 649         .ops            = &clkops_null,
 650         .parent         = &omap_96m_alwon_fck,
 651         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 652         .recalc         = &followparent_recalc,
 653 };
 654
 655 static const struct clksel cm_96m_fck_clksel[] = {
 656         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 657         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 658         { .parent = NULL }
 659 };
 660
 661 static struct clk cm_96m_fck = {
 662         .name           = "cm_96m_fck",
 663         .ops            = &clkops_null,
 664         .parent         = &dpll4_m2x2_ck,
 665         .init           = &omap2_init_clksel_parent,
 666         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 667         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 668         .clksel         = cm_96m_fck_clksel,
 669         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 670         .recalc         = &omap2_clksel_recalc,
 671 };
 672
 673 /* This virtual clock is the source for dpll4_m3x2_ck */
 674 static struct clk dpll4_m3_ck = {
 675         .name           = "dpll4_m3_ck",
 676         .ops            = &clkops_null,
 677         .parent         = &dpll4_ck,
 678         .init           = &omap2_init_clksel_parent,
 679         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 680         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 681         .clksel         = div16_dpll4_clksel,
 682         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 683         .recalc         = &omap2_clksel_recalc,
 684 };
 685
 686 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 687 static struct clk dpll4_m3x2_ck = {
 688         .name           = "dpll4_m3x2_ck",
 689         .ops            = &clkops_omap2_dflt_wait,
 690         .parent         = &dpll4_m3_ck,
 691         .init           = &omap2_init_clksel_parent,
 692         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 693         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 694         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 695         .recalc         = &omap3_clkoutx2_recalc,
 696 };
 697
 698 static const struct clksel virt_omap_54m_fck_clksel[] = {
 699         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 700         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 701         { .parent = NULL }
 702 };
 703
 704 static struct clk virt_omap_54m_fck = {
 705         .name           = "virt_omap_54m_fck",
 706         .ops            = &clkops_null,
 707         .parent         = &dpll4_m3x2_ck,
 708         .init           = &omap2_init_clksel_parent,
 709         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 710         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 711         .clksel         = virt_omap_54m_fck_clksel,
 712         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 713         .recalc         = &omap2_clksel_recalc,
 714 };
 715
 716 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 717         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 718         { .div = 0 }
 719 };
 720
 721 static const struct clksel_rate omap_54m_alt_rates[] = {
 722         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 723         { .div = 0 }
 724 };
 725
 726 static const struct clksel omap_54m_clksel[] = {
 727         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 728         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 729         { .parent = NULL }
 730 };
 731
 732 static struct clk omap_54m_fck = {
 733         .name           = "omap_54m_fck",
 734         .ops            = &clkops_null,
 735         .init           = &omap2_init_clksel_parent,
 736         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 737         .clksel_mask    = OMAP3430_SOURCE_54M,
 738         .clksel         = omap_54m_clksel,
 739         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 740         .recalc         = &omap2_clksel_recalc,
 741 };
 742
 743 static const struct clksel_rate omap_48m_96md2_rates[] = {
 744         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 745         { .div = 0 }
 746 };
 747
 748 static const struct clksel_rate omap_48m_alt_rates[] = {
 749         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 750         { .div = 0 }
 751 };
 752
 753 static const struct clksel omap_48m_clksel[] = {
 754         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 755         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 756         { .parent = NULL }
 757 };
 758
 759 static struct clk omap_48m_fck = {
 760         .name           = "omap_48m_fck",
 761         .ops            = &clkops_null,
 762         .init           = &omap2_init_clksel_parent,
 763         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 764         .clksel_mask    = OMAP3430_SOURCE_48M,
 765         .clksel         = omap_48m_clksel,
 766         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 767         .recalc         = &omap2_clksel_recalc,
 768 };
 769
 770 static struct clk omap_12m_fck = {
 771         .name           = "omap_12m_fck",
 772         .ops            = &clkops_null,
 773         .parent         = &omap_48m_fck,
 774         .fixed_div      = 4,
 775         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 776         .recalc         = &omap2_fixed_divisor_recalc,
 777 };
 778
 779 /* This virstual clock is the source for dpll4_m4x2_ck */
 780 static struct clk dpll4_m4_ck = {
 781         .name           = "dpll4_m4_ck",
 782         .ops            = &clkops_null,
 783         .parent         = &dpll4_ck,
 784         .init           = &omap2_init_clksel_parent,
 785         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 786         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 787         .clksel         = div16_dpll4_clksel,
 788         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 789         .recalc         = &omap2_clksel_recalc,
 790 };
 791
 792 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 793 static struct clk dpll4_m4x2_ck = {
 794         .name           = "dpll4_m4x2_ck",
 795         .ops            = &clkops_omap2_dflt_wait,
 796         .parent         = &dpll4_m4_ck,
 797         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 798         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 799         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 800         .recalc         = &omap3_clkoutx2_recalc,
 801 };
 802
 803 /* This virtual clock is the source for dpll4_m5x2_ck */
 804 static struct clk dpll4_m5_ck = {
 805         .name           = "dpll4_m5_ck",
 806         .ops            = &clkops_null,
 807         .parent         = &dpll4_ck,
 808         .init           = &omap2_init_clksel_parent,
 809         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 810         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 811         .clksel         = div16_dpll4_clksel,
 812         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 813         .recalc         = &omap2_clksel_recalc,
 814 };
 815
 816 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 817 static struct clk dpll4_m5x2_ck = {
 818         .name           = "dpll4_m5x2_ck",
 819         .ops            = &clkops_omap2_dflt_wait,
 820         .parent         = &dpll4_m5_ck,
 821         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 822         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 823         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 824         .recalc         = &omap3_clkoutx2_recalc,
 825 };
 826
 827 /* This virtual clock is the source for dpll4_m6x2_ck */
 828 static struct clk dpll4_m6_ck = {
 829         .name           = "dpll4_m6_ck",
 830         .ops            = &clkops_null,
 831         .parent         = &dpll4_ck,
 832         .init           = &omap2_init_clksel_parent,
 833         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 834         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 835         .clksel         = div16_dpll4_clksel,
 836         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 837         .recalc         = &omap2_clksel_recalc,
 838 };
 839
 840 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 841 static struct clk dpll4_m6x2_ck = {
 842         .name           = "dpll4_m6x2_ck",
 843         .ops            = &clkops_omap2_dflt_wait,
 844         .parent         = &dpll4_m6_ck,
 845         .init           = &omap2_init_clksel_parent,
 846         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 847         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 848         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 849         .recalc         = &omap3_clkoutx2_recalc,
 850 };
 851
 852 static struct clk emu_per_alwon_ck = {
 853         .name           = "emu_per_alwon_ck",
 854         .ops            = &clkops_null,
 855         .parent         = &dpll4_m6x2_ck,
 856         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 857         .recalc         = &followparent_recalc,
 858 };
 859
 860 /* DPLL5 */
 861 /* Supplies 120MHz clock, USIM source clock */
 862 /* Type: DPLL */
 863 /* 3430ES2 only */
 864 static struct dpll_data dpll5_dd = {
 865         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 866         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 867         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 868         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 869         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 870         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 871         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 872         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 873         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 874         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 875         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 876         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 877         .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 878         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 879         .max_divider    = OMAP3_MAX_DPLL_DIV,
 880         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 881 };
 882
 883 static struct clk dpll5_ck = {
 884         .name           = "dpll5_ck",
 885         .ops            = &clkops_noncore_dpll_ops,
 886         .parent         = &sys_ck,
 887         .dpll_data      = &dpll5_dd,
 888         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 889         .round_rate     = &omap2_dpll_round_rate,
 890         .recalc         = &omap3_dpll_recalc,
 891 };
 892
 893 static const struct clksel div16_dpll5_clksel[] = {
 894         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 895         { .parent = NULL }
 896 };
 897
 898 static struct clk dpll5_m2_ck = {
 899         .name           = "dpll5_m2_ck",
 900         .ops            = &clkops_null,
 901         .parent         = &dpll5_ck,
 902         .init           = &omap2_init_clksel_parent,
 903         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 904         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 905         .clksel         = div16_dpll5_clksel,
 906         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 907         .recalc         = &omap2_clksel_recalc,
 908 };
 909
 910 static const struct clksel omap_120m_fck_clksel[] = {
 911         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 912         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 913         { .parent = NULL }
 914 };
 915
 916 static struct clk omap_120m_fck = {
 917         .name           = "omap_120m_fck",
 918         .ops            = &clkops_null,
 919         .parent         = &dpll5_m2_ck,
 920         .init           = &omap2_init_clksel_parent,
 921         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 922         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 923         .clksel         = omap_120m_fck_clksel,
 924         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 925         .recalc         = &omap2_clksel_recalc,
 926 };
 927
 928 /* CM EXTERNAL CLOCK OUTPUTS */
 929
 930 static const struct clksel_rate clkout2_src_core_rates[] = {
 931         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 932         { .div = 0 }
 933 };
 934
 935 static const struct clksel_rate clkout2_src_sys_rates[] = {
 936         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 937         { .div = 0 }
 938 };
 939
 940 static const struct clksel_rate clkout2_src_96m_rates[] = {
 941         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 942         { .div = 0 }
 943 };
 944
 945 static const struct clksel_rate clkout2_src_54m_rates[] = {
 946         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 947         { .div = 0 }
 948 };
 949
 950 static const struct clksel clkout2_src_clksel[] = {
 951         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 952         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 953         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 954         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 955         { .parent = NULL }
 956 };
 957
 958 static struct clk clkout2_src_ck = {
 959         .name           = "clkout2_src_ck",
 960         .ops            = &clkops_omap2_dflt,
 961         .init           = &omap2_init_clksel_parent,
 962         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 963         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 964         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 965         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 966         .clksel         = clkout2_src_clksel,
 967         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 968         .recalc         = &omap2_clksel_recalc,
 969 };
 970
 971 static const struct clksel_rate sys_clkout2_rates[] = {
 972         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 973         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 974         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 975         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 976         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 977         { .div = 0 },
 978 };
 979
 980 static const struct clksel sys_clkout2_clksel[] = {
 981         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 982         { .parent = NULL },
 983 };
 984
 985 static struct clk sys_clkout2 = {
 986         .name           = "sys_clkout2",
 987         .ops            = &clkops_null,
 988         .init           = &omap2_init_clksel_parent,
 989         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 990         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 991         .clksel         = sys_clkout2_clksel,
 992         .flags          = CLOCK_IN_OMAP343X,
 993         .recalc         = &omap2_clksel_recalc,
 994 };
 995
 996 /* CM OUTPUT CLOCKS */
 997
 998 static struct clk corex2_fck = {
 999         .name           = "corex2_fck",
1000         .ops            = &clkops_null,
1001         .parent         = &dpll3_m2x2_ck,
1002         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1003         .recalc         = &followparent_recalc,
1004 };
1005
1006 /* DPLL power domain clock controls */
1007
1008 static const struct clksel div2_core_clksel[] = {
1009         { .parent = &core_ck, .rates = div2_rates },
1010         { .parent = NULL }
1011 };
1012
1013 /*
1014  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1015  * may be inconsistent here?
1016  */
1017 static struct clk dpll1_fck = {
1018         .name           = "dpll1_fck",
1019         .ops            = &clkops_null,
1020         .parent         = &core_ck,
1021         .init           = &omap2_init_clksel_parent,
1022         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1024         .clksel         = div2_core_clksel,
1025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1026         .recalc         = &omap2_clksel_recalc,
1027 };
1028
1029 /*
1030  * MPU clksel:
1031  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1032  * derives from the high-frequency bypass clock originating from DPLL3,
1033  * called 'dpll1_fck'
1034  */
1035 static const struct clksel mpu_clksel[] = {
1036         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
1037         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1038         { .parent = NULL }
1039 };
1040
1041 static struct clk mpu_ck = {
1042         .name           = "mpu_ck",
1043         .ops            = &clkops_null,
1044         .parent         = &dpll1_x2m2_ck,
1045         .init           = &omap2_init_clksel_parent,
1046         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1048         .clksel         = mpu_clksel,
1049         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1050         .clkdm_name     = "mpu_clkdm",
1051         .recalc         = &omap2_clksel_recalc,
1052 };
1053
1054 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1055 static const struct clksel_rate arm_fck_rates[] = {
1056         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1057         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1058         { .div = 0 },
1059 };
1060
1061 static const struct clksel arm_fck_clksel[] = {
1062         { .parent = &mpu_ck, .rates = arm_fck_rates },
1063         { .parent = NULL }
1064 };
1065
1066 static struct clk arm_fck = {
1067         .name           = "arm_fck",
1068         .ops            = &clkops_null,
1069         .parent         = &mpu_ck,
1070         .init           = &omap2_init_clksel_parent,
1071         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1073         .clksel         = arm_fck_clksel,
1074         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1075         .recalc         = &omap2_clksel_recalc,
1076 };
1077
1078 /* XXX What about neon_clkdm ? */
1079
1080 /*
1081  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1082  * although it is referenced - so this is a guess
1083  */
1084 static struct clk emu_mpu_alwon_ck = {
1085         .name           = "emu_mpu_alwon_ck",
1086         .ops            = &clkops_null,
1087         .parent         = &mpu_ck,
1088         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1089         .recalc         = &followparent_recalc,
1090 };
1091
1092 static struct clk dpll2_fck = {
1093         .name           = "dpll2_fck",
1094         .ops            = &clkops_null,
1095         .parent         = &core_ck,
1096         .init           = &omap2_init_clksel_parent,
1097         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1099         .clksel         = div2_core_clksel,
1100         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1101         .recalc         = &omap2_clksel_recalc,
1102 };
1103
1104 /*
1105  * IVA2 clksel:
1106  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1107  * derives from the high-frequency bypass clock originating from DPLL3,
1108  * called 'dpll2_fck'
1109  */
1110
1111 static const struct clksel iva2_clksel[] = {
1112         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1113         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1114         { .parent = NULL }
1115 };
1116
1117 static struct clk iva2_ck = {
1118         .name           = "iva2_ck",
1119         .ops            = &clkops_omap2_dflt_wait,
1120         .parent         = &dpll2_m2_ck,
1121         .init           = &omap2_init_clksel_parent,
1122         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1123         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1124         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1125                                           OMAP3430_CM_IDLEST_PLL),
1126         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1127         .clksel         = iva2_clksel,
1128         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1129         .clkdm_name     = "iva2_clkdm",
1130         .recalc         = &omap2_clksel_recalc,
1131 };
1132
1133 /* Common interface clocks */
1134
1135 static struct clk l3_ick = {
1136         .name           = "l3_ick",
1137         .ops            = &clkops_null,
1138         .parent         = &core_ck,
1139         .init           = &omap2_init_clksel_parent,
1140         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1141         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1142         .clksel         = div2_core_clksel,
1143         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1144         .clkdm_name     = "core_l3_clkdm",
1145         .recalc         = &omap2_clksel_recalc,
1146 };
1147
1148 static const struct clksel div2_l3_clksel[] = {
1149         { .parent = &l3_ick, .rates = div2_rates },
1150         { .parent = NULL }
1151 };
1152
1153 static struct clk l4_ick = {
1154         .name           = "l4_ick",
1155         .ops            = &clkops_null,
1156         .parent         = &l3_ick,
1157         .init           = &omap2_init_clksel_parent,
1158         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1159         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1160         .clksel         = div2_l3_clksel,
1161         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1162         .clkdm_name     = "core_l4_clkdm",
1163         .recalc         = &omap2_clksel_recalc,
1164
1165 };
1166
1167 static const struct clksel div2_l4_clksel[] = {
1168         { .parent = &l4_ick, .rates = div2_rates },
1169         { .parent = NULL }
1170 };
1171
1172 static struct clk rm_ick = {
1173         .name           = "rm_ick",
1174         .ops            = &clkops_null,
1175         .parent         = &l4_ick,
1176         .init           = &omap2_init_clksel_parent,
1177         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1178         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1179         .clksel         = div2_l4_clksel,
1180         .flags          = CLOCK_IN_OMAP343X,
1181         .recalc         = &omap2_clksel_recalc,
1182 };
1183
1184 /* GFX power domain */
1185
1186 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1187
1188 static const struct clksel gfx_l3_clksel[] = {
1189         { .parent = &l3_ick, .rates = gfx_l3_rates },
1190         { .parent = NULL }
1191 };
1192
1193 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1194 static struct clk gfx_l3_ck = {
1195         .name           = "gfx_l3_ck",
1196         .ops            = &clkops_omap2_dflt_wait,
1197         .parent         = &l3_ick,
1198         .init           = &omap2_init_clksel_parent,
1199         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1200         .enable_bit     = OMAP_EN_GFX_SHIFT,
1201         .flags          = CLOCK_IN_OMAP3430ES1,
1202         .recalc         = &followparent_recalc,
1203 };
1204
1205 static struct clk gfx_l3_fck = {
1206         .name           = "gfx_l3_fck",
1207         .ops            = &clkops_null,
1208         .parent         = &gfx_l3_ck,
1209         .init           = &omap2_init_clksel_parent,
1210         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1211         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1212         .clksel         = gfx_l3_clksel,
1213         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1214         .clkdm_name     = "gfx_3430es1_clkdm",
1215         .recalc         = &omap2_clksel_recalc,
1216 };
1217
1218 static struct clk gfx_l3_ick = {
1219         .name           = "gfx_l3_ick",
1220         .ops            = &clkops_null,
1221         .parent         = &gfx_l3_ck,
1222         .flags          = CLOCK_IN_OMAP3430ES1,
1223         .clkdm_name     = "gfx_3430es1_clkdm",
1224         .recalc         = &followparent_recalc,
1225 };
1226
1227 static struct clk gfx_cg1_ck = {
1228         .name           = "gfx_cg1_ck",
1229         .ops            = &clkops_omap2_dflt_wait,
1230         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1231         .init           = &omap2_init_clk_clkdm,
1232         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1233         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1234         .flags          = CLOCK_IN_OMAP3430ES1,
1235         .clkdm_name     = "gfx_3430es1_clkdm",
1236         .recalc         = &followparent_recalc,
1237 };
1238
1239 static struct clk gfx_cg2_ck = {
1240         .name           = "gfx_cg2_ck",
1241         .ops            = &clkops_omap2_dflt_wait,
1242         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1243         .init           = &omap2_init_clk_clkdm,
1244         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1245         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1246         .flags          = CLOCK_IN_OMAP3430ES1,
1247         .clkdm_name     = "gfx_3430es1_clkdm",
1248         .recalc         = &followparent_recalc,
1249 };
1250
1251 /* SGX power domain - 3430ES2 only */
1252
1253 static const struct clksel_rate sgx_core_rates[] = {
1254         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1255         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1256         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1257         { .div = 0 },
1258 };
1259
1260 static const struct clksel_rate sgx_96m_rates[] = {
1261         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1262         { .div = 0 },
1263 };
1264
1265 static const struct clksel sgx_clksel[] = {
1266         { .parent = &core_ck,    .rates = sgx_core_rates },
1267         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1268         { .parent = NULL },
1269 };
1270
1271 static struct clk sgx_fck = {
1272         .name           = "sgx_fck",
1273         .ops            = &clkops_omap2_dflt_wait,
1274         .init           = &omap2_init_clksel_parent,
1275         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1276         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1277         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1278         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1279         .clksel         = sgx_clksel,
1280         .flags          = CLOCK_IN_OMAP3430ES2,
1281         .clkdm_name     = "sgx_clkdm",
1282         .recalc         = &omap2_clksel_recalc,
1283 };
1284
1285 static struct clk sgx_ick = {
1286         .name           = "sgx_ick",
1287         .ops            = &clkops_omap2_dflt_wait,
1288         .parent         = &l3_ick,
1289         .init           = &omap2_init_clk_clkdm,
1290         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1291         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1292         .flags          = CLOCK_IN_OMAP3430ES2,
1293         .clkdm_name     = "sgx_clkdm",
1294         .recalc         = &followparent_recalc,
1295 };
1296
1297 /* CORE power domain */
1298
1299 static struct clk d2d_26m_fck = {
1300         .name           = "d2d_26m_fck",
1301         .ops            = &clkops_omap2_dflt_wait,
1302         .parent         = &sys_ck,
1303         .init           = &omap2_init_clk_clkdm,
1304         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1305         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1306         .flags          = CLOCK_IN_OMAP3430ES1,
1307         .clkdm_name     = "d2d_clkdm",
1308         .recalc         = &followparent_recalc,
1309 };
1310
1311 static const struct clksel omap343x_gpt_clksel[] = {
1312         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1313         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1314         { .parent = NULL}
1315 };
1316
1317 static struct clk gpt10_fck = {
1318         .name           = "gpt10_fck",
1319         .ops            = &clkops_omap2_dflt_wait,
1320         .parent         = &sys_ck,
1321         .init           = &omap2_init_clksel_parent,
1322         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1323         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1324         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1325         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1326         .clksel         = omap343x_gpt_clksel,
1327         .flags          = CLOCK_IN_OMAP343X,
1328         .clkdm_name     = "core_l4_clkdm",
1329         .recalc         = &omap2_clksel_recalc,
1330 };
1331
1332 static struct clk gpt11_fck = {
1333         .name           = "gpt11_fck",
1334         .ops            = &clkops_omap2_dflt_wait,
1335         .parent         = &sys_ck,
1336         .init           = &omap2_init_clksel_parent,
1337         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1338         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1339         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1340         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1341         .clksel         = omap343x_gpt_clksel,
1342         .flags          = CLOCK_IN_OMAP343X,
1343         .clkdm_name     = "core_l4_clkdm",
1344         .recalc         = &omap2_clksel_recalc,
1345 };
1346
1347 static struct clk cpefuse_fck = {
1348         .name           = "cpefuse_fck",
1349         .ops            = &clkops_omap2_dflt,
1350         .parent         = &sys_ck,
1351         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1352         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1353         .flags          = CLOCK_IN_OMAP3430ES2,
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk ts_fck = {
1358         .name           = "ts_fck",
1359         .ops            = &clkops_omap2_dflt,
1360         .parent         = &omap_32k_fck,
1361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1362         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1363         .flags          = CLOCK_IN_OMAP3430ES2,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 static struct clk usbtll_fck = {
1368         .name           = "usbtll_fck",
1369         .ops            = &clkops_omap2_dflt,
1370         .parent         = &omap_120m_fck,
1371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1372         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1373         .flags          = CLOCK_IN_OMAP3430ES2,
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 /* CORE 96M FCLK-derived clocks */
1378
1379 static struct clk core_96m_fck = {
1380         .name           = "core_96m_fck",
1381         .ops            = &clkops_null,
1382         .parent         = &omap_96m_fck,
1383         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1384         .clkdm_name     = "core_l4_clkdm",
1385         .recalc         = &followparent_recalc,
1386 };
1387
1388 static struct clk mmchs3_fck = {
1389         .name           = "mmchs_fck",
1390         .ops            = &clkops_omap2_dflt_wait,
1391         .id             = 2,
1392         .parent         = &core_96m_fck,
1393         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1394         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1395         .flags          = CLOCK_IN_OMAP3430ES2,
1396         .clkdm_name     = "core_l4_clkdm",
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static struct clk mmchs2_fck = {
1401         .name           = "mmchs_fck",
1402         .ops            = &clkops_omap2_dflt_wait,
1403         .id             = 1,
1404         .parent         = &core_96m_fck,
1405         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1407         .flags          = CLOCK_IN_OMAP343X,
1408         .clkdm_name     = "core_l4_clkdm",
1409         .recalc         = &followparent_recalc,
1410 };
1411
1412 static struct clk mspro_fck = {
1413         .name           = "mspro_fck",
1414         .ops            = &clkops_omap2_dflt_wait,
1415         .parent         = &core_96m_fck,
1416         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1418         .flags          = CLOCK_IN_OMAP343X,
1419         .clkdm_name     = "core_l4_clkdm",
1420         .recalc         = &followparent_recalc,
1421 };
1422
1423 static struct clk mmchs1_fck = {
1424         .name           = "mmchs_fck",
1425         .ops            = &clkops_omap2_dflt_wait,
1426         .parent         = &core_96m_fck,
1427         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1428         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1429         .flags          = CLOCK_IN_OMAP343X,
1430         .clkdm_name     = "core_l4_clkdm",
1431         .recalc         = &followparent_recalc,
1432 };
1433
1434 static struct clk i2c3_fck = {
1435         .name           = "i2c_fck",
1436         .ops            = &clkops_omap2_dflt_wait,
1437         .id             = 3,
1438         .parent         = &core_96m_fck,
1439         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1440         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1441         .flags          = CLOCK_IN_OMAP343X,
1442         .clkdm_name     = "core_l4_clkdm",
1443         .recalc         = &followparent_recalc,
1444 };
1445
1446 static struct clk i2c2_fck = {
1447         .name           = "i2c_fck",
1448         .ops            = &clkops_omap2_dflt_wait,
1449         .id             = 2,
1450         .parent         = &core_96m_fck,
1451         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1452         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1453         .flags          = CLOCK_IN_OMAP343X,
1454         .clkdm_name     = "core_l4_clkdm",
1455         .recalc         = &followparent_recalc,
1456 };
1457
1458 static struct clk i2c1_fck = {
1459         .name           = "i2c_fck",
1460         .ops            = &clkops_omap2_dflt_wait,
1461         .id             = 1,
1462         .parent         = &core_96m_fck,
1463         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1464         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1465         .flags          = CLOCK_IN_OMAP343X,
1466         .clkdm_name     = "core_l4_clkdm",
1467         .recalc         = &followparent_recalc,
1468 };
1469
1470 /*
1471  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1472  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1473  */
1474 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1475         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1476         { .div = 0 }
1477 };
1478
1479 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1480         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1481         { .div = 0 }
1482 };
1483
1484 static const struct clksel mcbsp_15_clksel[] = {
1485         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1486         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1487         { .parent = NULL }
1488 };
1489
1490 static struct clk mcbsp5_fck = {
1491         .name           = "mcbsp_fck",
1492         .ops            = &clkops_omap2_dflt_wait,
1493         .id             = 5,
1494         .init           = &omap2_init_clksel_parent,
1495         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1496         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1497         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1498         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1499         .clksel         = mcbsp_15_clksel,
1500         .flags          = CLOCK_IN_OMAP343X,
1501         .clkdm_name     = "core_l4_clkdm",
1502         .recalc         = &omap2_clksel_recalc,
1503 };
1504
1505 static struct clk mcbsp1_fck = {
1506         .name           = "mcbsp_fck",
1507         .ops            = &clkops_omap2_dflt_wait,
1508         .id             = 1,
1509         .init           = &omap2_init_clksel_parent,
1510         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1511         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1512         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1513         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1514         .clksel         = mcbsp_15_clksel,
1515         .flags          = CLOCK_IN_OMAP343X,
1516         .clkdm_name     = "core_l4_clkdm",
1517         .recalc         = &omap2_clksel_recalc,
1518 };
1519
1520 /* CORE_48M_FCK-derived clocks */
1521
1522 static struct clk core_48m_fck = {
1523         .name           = "core_48m_fck",
1524         .ops            = &clkops_null,
1525         .parent         = &omap_48m_fck,
1526         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1527         .clkdm_name     = "core_l4_clkdm",
1528         .recalc         = &followparent_recalc,
1529 };
1530
1531 static struct clk mcspi4_fck = {
1532         .name           = "mcspi_fck",
1533         .ops            = &clkops_omap2_dflt_wait,
1534         .id             = 4,
1535         .parent         = &core_48m_fck,
1536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1538         .flags          = CLOCK_IN_OMAP343X,
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk mcspi3_fck = {
1543         .name           = "mcspi_fck",
1544         .ops            = &clkops_omap2_dflt_wait,
1545         .id             = 3,
1546         .parent         = &core_48m_fck,
1547         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1548         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1549         .flags          = CLOCK_IN_OMAP343X,
1550         .recalc         = &followparent_recalc,
1551 };
1552
1553 static struct clk mcspi2_fck = {
1554         .name           = "mcspi_fck",
1555         .ops            = &clkops_omap2_dflt_wait,
1556         .id             = 2,
1557         .parent         = &core_48m_fck,
1558         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1560         .flags          = CLOCK_IN_OMAP343X,
1561         .recalc         = &followparent_recalc,
1562 };
1563
1564 static struct clk mcspi1_fck = {
1565         .name           = "mcspi_fck",
1566         .ops            = &clkops_omap2_dflt_wait,
1567         .id             = 1,
1568         .parent         = &core_48m_fck,
1569         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1571         .flags          = CLOCK_IN_OMAP343X,
1572         .recalc         = &followparent_recalc,
1573 };
1574
1575 static struct clk uart2_fck = {
1576         .name           = "uart2_fck",
1577         .ops            = &clkops_omap2_dflt_wait,
1578         .parent         = &core_48m_fck,
1579         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1580         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1581         .flags          = CLOCK_IN_OMAP343X,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk uart1_fck = {
1586         .name           = "uart1_fck",
1587         .ops            = &clkops_omap2_dflt_wait,
1588         .parent         = &core_48m_fck,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1591         .flags          = CLOCK_IN_OMAP343X,
1592         .recalc         = &followparent_recalc,
1593 };
1594
1595 static struct clk fshostusb_fck = {
1596         .name           = "fshostusb_fck",
1597         .ops            = &clkops_omap2_dflt_wait,
1598         .parent         = &core_48m_fck,
1599         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1601         .flags          = CLOCK_IN_OMAP3430ES1,
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 /* CORE_12M_FCK based clocks */
1606
1607 static struct clk core_12m_fck = {
1608         .name           = "core_12m_fck",
1609         .ops            = &clkops_null,
1610         .parent         = &omap_12m_fck,
1611         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1612         .clkdm_name     = "core_l4_clkdm",
1613         .recalc         = &followparent_recalc,
1614 };
1615
1616 static struct clk hdq_fck = {
1617         .name           = "hdq_fck",
1618         .ops            = &clkops_omap2_dflt_wait,
1619         .parent         = &core_12m_fck,
1620         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1621         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1622         .flags          = CLOCK_IN_OMAP343X,
1623         .recalc         = &followparent_recalc,
1624 };
1625
1626 /* DPLL3-derived clock */
1627
1628 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1629         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1630         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1631         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1632         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1633         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1634         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1635         { .div = 0 }
1636 };
1637
1638 static const struct clksel ssi_ssr_clksel[] = {
1639         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1640         { .parent = NULL }
1641 };
1642
1643 static struct clk ssi_ssr_fck = {
1644         .name           = "ssi_ssr_fck",
1645         .ops            = &clkops_omap2_dflt,
1646         .init           = &omap2_init_clksel_parent,
1647         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1648         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1649         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1650         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1651         .clksel         = ssi_ssr_clksel,
1652         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1653         .clkdm_name     = "core_l4_clkdm",
1654         .recalc         = &omap2_clksel_recalc,
1655 };
1656
1657 static struct clk ssi_sst_fck = {
1658         .name           = "ssi_sst_fck",
1659         .ops            = &clkops_null,
1660         .parent         = &ssi_ssr_fck,
1661         .fixed_div      = 2,
1662         .flags          = CLOCK_IN_OMAP343X,
1663         .recalc         = &omap2_fixed_divisor_recalc,
1664 };
1665
1666
1667
1668 /* CORE_L3_ICK based clocks */
1669
1670 /*
1671  * XXX must add clk_enable/clk_disable for these if standard code won't
1672  * handle it
1673  */
1674 static struct clk core_l3_ick = {
1675         .name           = "core_l3_ick",
1676         .ops            = &clkops_null,
1677         .parent         = &l3_ick,
1678         .init           = &omap2_init_clk_clkdm,
1679         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1680         .clkdm_name     = "core_l3_clkdm",
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 static struct clk hsotgusb_ick = {
1685         .name           = "hsotgusb_ick",
1686         .ops            = &clkops_omap2_dflt_wait,
1687         .parent         = &core_l3_ick,
1688         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1690         .flags          = CLOCK_IN_OMAP343X,
1691         .clkdm_name     = "core_l3_clkdm",
1692         .recalc         = &followparent_recalc,
1693 };
1694
1695 static struct clk sdrc_ick = {
1696         .name           = "sdrc_ick",
1697         .ops            = &clkops_omap2_dflt_wait,
1698         .parent         = &core_l3_ick,
1699         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1700         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1701         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1702         .clkdm_name     = "core_l3_clkdm",
1703         .recalc         = &followparent_recalc,
1704 };
1705
1706 static struct clk gpmc_fck = {
1707         .name           = "gpmc_fck",
1708         .ops            = &clkops_null,
1709         .parent         = &core_l3_ick,
1710         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, /* huh? */
1711         .clkdm_name     = "core_l3_clkdm",
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 /* SECURITY_L3_ICK based clocks */
1716
1717 static struct clk security_l3_ick = {
1718         .name           = "security_l3_ick",
1719         .ops            = &clkops_null,
1720         .parent         = &l3_ick,
1721         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1722         .recalc         = &followparent_recalc,
1723 };
1724
1725 static struct clk pka_ick = {
1726         .name           = "pka_ick",
1727         .ops            = &clkops_omap2_dflt_wait,
1728         .parent         = &security_l3_ick,
1729         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1730         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1731         .flags          = CLOCK_IN_OMAP343X,
1732         .recalc         = &followparent_recalc,
1733 };
1734
1735 /* CORE_L4_ICK based clocks */
1736
1737 static struct clk core_l4_ick = {
1738         .name           = "core_l4_ick",
1739         .ops            = &clkops_null,
1740         .parent         = &l4_ick,
1741         .init           = &omap2_init_clk_clkdm,
1742         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1743         .clkdm_name     = "core_l4_clkdm",
1744         .recalc         = &followparent_recalc,
1745 };
1746
1747 static struct clk usbtll_ick = {
1748         .name           = "usbtll_ick",
1749         .ops            = &clkops_omap2_dflt_wait,
1750         .parent         = &core_l4_ick,
1751         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1752         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1753         .flags          = CLOCK_IN_OMAP3430ES2,
1754         .clkdm_name     = "core_l4_clkdm",
1755         .recalc         = &followparent_recalc,
1756 };
1757
1758 static struct clk mmchs3_ick = {
1759         .name           = "mmchs_ick",
1760         .ops            = &clkops_omap2_dflt_wait,
1761         .id             = 2,
1762         .parent         = &core_l4_ick,
1763         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1764         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1765         .flags          = CLOCK_IN_OMAP3430ES2,
1766         .clkdm_name     = "core_l4_clkdm",
1767         .recalc         = &followparent_recalc,
1768 };
1769
1770 /* Intersystem Communication Registers - chassis mode only */
1771 static struct clk icr_ick = {
1772         .name           = "icr_ick",
1773         .ops            = &clkops_omap2_dflt_wait,
1774         .parent         = &core_l4_ick,
1775         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1776         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1777         .flags          = CLOCK_IN_OMAP343X,
1778         .clkdm_name     = "core_l4_clkdm",
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 static struct clk aes2_ick = {
1783         .name           = "aes2_ick",
1784         .ops            = &clkops_omap2_dflt_wait,
1785         .parent         = &core_l4_ick,
1786         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1787         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1788         .flags          = CLOCK_IN_OMAP343X,
1789         .clkdm_name     = "core_l4_clkdm",
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk sha12_ick = {
1794         .name           = "sha12_ick",
1795         .ops            = &clkops_omap2_dflt_wait,
1796         .parent         = &core_l4_ick,
1797         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1798         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1799         .flags          = CLOCK_IN_OMAP343X,
1800         .clkdm_name     = "core_l4_clkdm",
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk des2_ick = {
1805         .name           = "des2_ick",
1806         .ops            = &clkops_omap2_dflt_wait,
1807         .parent         = &core_l4_ick,
1808         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1810         .flags          = CLOCK_IN_OMAP343X,
1811         .clkdm_name     = "core_l4_clkdm",
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk mmchs2_ick = {
1816         .name           = "mmchs_ick",
1817         .ops            = &clkops_omap2_dflt_wait,
1818         .id             = 1,
1819         .parent         = &core_l4_ick,
1820         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1822         .flags          = CLOCK_IN_OMAP343X,
1823         .clkdm_name     = "core_l4_clkdm",
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 static struct clk mmchs1_ick = {
1828         .name           = "mmchs_ick",
1829         .ops            = &clkops_omap2_dflt_wait,
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1833         .flags          = CLOCK_IN_OMAP343X,
1834         .clkdm_name     = "core_l4_clkdm",
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk mspro_ick = {
1839         .name           = "mspro_ick",
1840         .ops            = &clkops_omap2_dflt_wait,
1841         .parent         = &core_l4_ick,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1844         .flags          = CLOCK_IN_OMAP343X,
1845         .clkdm_name     = "core_l4_clkdm",
1846         .recalc         = &followparent_recalc,
1847 };
1848
1849 static struct clk hdq_ick = {
1850         .name           = "hdq_ick",
1851         .ops            = &clkops_omap2_dflt_wait,
1852         .parent         = &core_l4_ick,
1853         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1854         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1855         .flags          = CLOCK_IN_OMAP343X,
1856         .clkdm_name     = "core_l4_clkdm",
1857         .recalc         = &followparent_recalc,
1858 };
1859
1860 static struct clk mcspi4_ick = {
1861         .name           = "mcspi_ick",
1862         .ops            = &clkops_omap2_dflt_wait,
1863         .id             = 4,
1864         .parent         = &core_l4_ick,
1865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1867         .flags          = CLOCK_IN_OMAP343X,
1868         .clkdm_name     = "core_l4_clkdm",
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mcspi3_ick = {
1873         .name           = "mcspi_ick",
1874         .ops            = &clkops_omap2_dflt_wait,
1875         .id             = 3,
1876         .parent         = &core_l4_ick,
1877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1878         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1879         .flags          = CLOCK_IN_OMAP343X,
1880         .clkdm_name     = "core_l4_clkdm",
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 static struct clk mcspi2_ick = {
1885         .name           = "mcspi_ick",
1886         .ops            = &clkops_omap2_dflt_wait,
1887         .id             = 2,
1888         .parent         = &core_l4_ick,
1889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1891         .flags          = CLOCK_IN_OMAP343X,
1892         .clkdm_name     = "core_l4_clkdm",
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mcspi1_ick = {
1897         .name           = "mcspi_ick",
1898         .ops            = &clkops_omap2_dflt_wait,
1899         .id             = 1,
1900         .parent         = &core_l4_ick,
1901         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1903         .flags          = CLOCK_IN_OMAP343X,
1904         .clkdm_name     = "core_l4_clkdm",
1905         .recalc         = &followparent_recalc,
1906 };
1907
1908 static struct clk i2c3_ick = {
1909         .name           = "i2c_ick",
1910         .ops            = &clkops_omap2_dflt_wait,
1911         .id             = 3,
1912         .parent         = &core_l4_ick,
1913         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1914         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1915         .flags          = CLOCK_IN_OMAP343X,
1916         .clkdm_name     = "core_l4_clkdm",
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk i2c2_ick = {
1921         .name           = "i2c_ick",
1922         .ops            = &clkops_omap2_dflt_wait,
1923         .id             = 2,
1924         .parent         = &core_l4_ick,
1925         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1927         .flags          = CLOCK_IN_OMAP343X,
1928         .clkdm_name     = "core_l4_clkdm",
1929         .recalc         = &followparent_recalc,
1930 };
1931
1932 static struct clk i2c1_ick = {
1933         .name           = "i2c_ick",
1934         .ops            = &clkops_omap2_dflt_wait,
1935         .id             = 1,
1936         .parent         = &core_l4_ick,
1937         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1938         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1939         .flags          = CLOCK_IN_OMAP343X,
1940         .clkdm_name     = "core_l4_clkdm",
1941         .recalc         = &followparent_recalc,
1942 };
1943
1944 static struct clk uart2_ick = {
1945         .name           = "uart2_ick",
1946         .ops            = &clkops_omap2_dflt_wait,
1947         .parent         = &core_l4_ick,
1948         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1950         .flags          = CLOCK_IN_OMAP343X,
1951         .clkdm_name     = "core_l4_clkdm",
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk uart1_ick = {
1956         .name           = "uart1_ick",
1957         .ops            = &clkops_omap2_dflt_wait,
1958         .parent         = &core_l4_ick,
1959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1961         .flags          = CLOCK_IN_OMAP343X,
1962         .clkdm_name     = "core_l4_clkdm",
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk gpt11_ick = {
1967         .name           = "gpt11_ick",
1968         .ops            = &clkops_omap2_dflt_wait,
1969         .parent         = &core_l4_ick,
1970         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1971         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1972         .flags          = CLOCK_IN_OMAP343X,
1973         .clkdm_name     = "core_l4_clkdm",
1974         .recalc         = &followparent_recalc,
1975 };
1976
1977 static struct clk gpt10_ick = {
1978         .name           = "gpt10_ick",
1979         .ops            = &clkops_omap2_dflt_wait,
1980         .parent         = &core_l4_ick,
1981         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1983         .flags          = CLOCK_IN_OMAP343X,
1984         .clkdm_name     = "core_l4_clkdm",
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk mcbsp5_ick = {
1989         .name           = "mcbsp_ick",
1990         .ops            = &clkops_omap2_dflt_wait,
1991         .id             = 5,
1992         .parent         = &core_l4_ick,
1993         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1994         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1995         .flags          = CLOCK_IN_OMAP343X,
1996         .clkdm_name     = "core_l4_clkdm",
1997         .recalc         = &followparent_recalc,
1998 };
1999
2000 static struct clk mcbsp1_ick = {
2001         .name           = "mcbsp_ick",
2002         .ops            = &clkops_omap2_dflt_wait,
2003         .id             = 1,
2004         .parent         = &core_l4_ick,
2005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2007         .flags          = CLOCK_IN_OMAP343X,
2008         .clkdm_name     = "core_l4_clkdm",
2009         .recalc         = &followparent_recalc,
2010 };
2011
2012 static struct clk fac_ick = {
2013         .name           = "fac_ick",
2014         .ops            = &clkops_omap2_dflt_wait,
2015         .parent         = &core_l4_ick,
2016         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2017         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2018         .flags          = CLOCK_IN_OMAP3430ES1,
2019         .clkdm_name     = "core_l4_clkdm",
2020         .recalc         = &followparent_recalc,
2021 };
2022
2023 static struct clk mailboxes_ick = {
2024         .name           = "mailboxes_ick",
2025         .ops            = &clkops_omap2_dflt_wait,
2026         .parent         = &core_l4_ick,
2027         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2028         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2029         .flags          = CLOCK_IN_OMAP343X,
2030         .clkdm_name     = "core_l4_clkdm",
2031         .recalc         = &followparent_recalc,
2032 };
2033
2034 static struct clk omapctrl_ick = {
2035         .name           = "omapctrl_ick",
2036         .ops            = &clkops_omap2_dflt_wait,
2037         .parent         = &core_l4_ick,
2038         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2040         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
2041         .recalc         = &followparent_recalc,
2042 };
2043
2044 /* SSI_L4_ICK based clocks */
2045
2046 static struct clk ssi_l4_ick = {
2047         .name           = "ssi_l4_ick",
2048         .ops            = &clkops_null,
2049         .parent         = &l4_ick,
2050         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2051         .clkdm_name     = "core_l4_clkdm",
2052         .recalc         = &followparent_recalc,
2053 };
2054
2055 static struct clk ssi_ick = {
2056         .name           = "ssi_ick",
2057         .ops            = &clkops_omap2_dflt,
2058         .parent         = &ssi_l4_ick,
2059         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2060         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2061         .flags          = CLOCK_IN_OMAP343X,
2062         .clkdm_name     = "core_l4_clkdm",
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2067  * but l4_ick makes more sense to me */
2068
2069 static const struct clksel usb_l4_clksel[] = {
2070         { .parent = &l4_ick, .rates = div2_rates },
2071         { .parent = NULL },
2072 };
2073
2074 static struct clk usb_l4_ick = {
2075         .name           = "usb_l4_ick",
2076         .ops            = &clkops_omap2_dflt_wait,
2077         .parent         = &l4_ick,
2078         .init           = &omap2_init_clksel_parent,
2079         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2080         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2081         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2082         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2083         .clksel         = usb_l4_clksel,
2084         .flags          = CLOCK_IN_OMAP3430ES1,
2085         .recalc         = &omap2_clksel_recalc,
2086 };
2087
2088 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
2089
2090 /* SECURITY_L4_ICK2 based clocks */
2091
2092 static struct clk security_l4_ick2 = {
2093         .name           = "security_l4_ick2",
2094         .ops            = &clkops_null,
2095         .parent         = &l4_ick,
2096         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2097         .recalc         = &followparent_recalc,
2098 };
2099
2100 static struct clk aes1_ick = {
2101         .name           = "aes1_ick",
2102         .ops            = &clkops_omap2_dflt_wait,
2103         .parent         = &security_l4_ick2,
2104         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2105         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2106         .flags          = CLOCK_IN_OMAP343X,
2107         .recalc         = &followparent_recalc,
2108 };
2109
2110 static struct clk rng_ick = {
2111         .name           = "rng_ick",
2112         .ops            = &clkops_omap2_dflt_wait,
2113         .parent         = &security_l4_ick2,
2114         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2115         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2116         .flags          = CLOCK_IN_OMAP343X,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk sha11_ick = {
2121         .name           = "sha11_ick",
2122         .ops            = &clkops_omap2_dflt_wait,
2123         .parent         = &security_l4_ick2,
2124         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2125         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2126         .flags          = CLOCK_IN_OMAP343X,
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk des1_ick = {
2131         .name           = "des1_ick",
2132         .ops            = &clkops_omap2_dflt_wait,
2133         .parent         = &security_l4_ick2,
2134         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2135         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2136         .flags          = CLOCK_IN_OMAP343X,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 /* DSS */
2141 static const struct clksel dss1_alwon_fck_clksel[] = {
2142         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2143         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2144         { .parent = NULL }
2145 };
2146
2147 static struct clk dss1_alwon_fck = {
2148         .name           = "dss1_alwon_fck",
2149         .ops            = &clkops_omap2_dflt,
2150         .parent         = &dpll4_m4x2_ck,
2151         .init           = &omap2_init_clksel_parent,
2152         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2153         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2154         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2155         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2156         .clksel         = dss1_alwon_fck_clksel,
2157         .flags          = CLOCK_IN_OMAP343X,
2158         .clkdm_name     = "dss_clkdm",
2159         .recalc         = &omap2_clksel_recalc,
2160 };
2161
2162 static struct clk dss_tv_fck = {
2163         .name           = "dss_tv_fck",
2164         .ops            = &clkops_omap2_dflt,
2165         .parent         = &omap_54m_fck,
2166         .init           = &omap2_init_clk_clkdm,
2167         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2168         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2169         .flags          = CLOCK_IN_OMAP343X,
2170         .clkdm_name     = "dss_clkdm",
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk dss_96m_fck = {
2175         .name           = "dss_96m_fck",
2176         .ops            = &clkops_omap2_dflt,
2177         .parent         = &omap_96m_fck,
2178         .init           = &omap2_init_clk_clkdm,
2179         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2180         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2181         .flags          = CLOCK_IN_OMAP343X,
2182         .clkdm_name     = "dss_clkdm",
2183         .recalc         = &followparent_recalc,
2184 };
2185
2186 static struct clk dss2_alwon_fck = {
2187         .name           = "dss2_alwon_fck",
2188         .ops            = &clkops_omap2_dflt,
2189         .parent         = &sys_ck,
2190         .init           = &omap2_init_clk_clkdm,
2191         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2192         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2193         .flags          = CLOCK_IN_OMAP343X,
2194         .clkdm_name     = "dss_clkdm",
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk dss_ick = {
2199         /* Handles both L3 and L4 clocks */
2200         .name           = "dss_ick",
2201         .ops            = &clkops_omap2_dflt,
2202         .parent         = &l4_ick,
2203         .init           = &omap2_init_clk_clkdm,
2204         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2205         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2206         .flags          = CLOCK_IN_OMAP343X,
2207         .clkdm_name     = "dss_clkdm",
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 /* CAM */
2212
2213 static const struct clksel cam_mclk_clksel[] = {
2214         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
2215         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2216         { .parent = NULL }
2217 };
2218
2219 static struct clk cam_mclk = {
2220         .name           = "cam_mclk",
2221         .ops            = &clkops_omap2_dflt_wait,
2222         .parent         = &dpll4_m5x2_ck,
2223         .init           = &omap2_init_clksel_parent,
2224         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2225         .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
2226         .clksel         = cam_mclk_clksel,
2227         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2228         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2229         .flags          = CLOCK_IN_OMAP343X,
2230         .clkdm_name     = "cam_clkdm",
2231         .recalc         = &omap2_clksel_recalc,
2232 };
2233
2234 static struct clk cam_ick = {
2235         /* Handles both L3 and L4 clocks */
2236         .name           = "cam_ick",
2237         .ops            = &clkops_omap2_dflt_wait,
2238         .parent         = &l4_ick,
2239         .init           = &omap2_init_clk_clkdm,
2240         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2241         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2242         .flags          = CLOCK_IN_OMAP343X,
2243         .clkdm_name     = "cam_clkdm",
2244         .recalc         = &followparent_recalc,
2245 };
2246
2247 /* USBHOST - 3430ES2 only */
2248
2249 static struct clk usbhost_120m_fck = {
2250         .name           = "usbhost_120m_fck",
2251         .ops            = &clkops_omap2_dflt_wait,
2252         .parent         = &omap_120m_fck,
2253         .init           = &omap2_init_clk_clkdm,
2254         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2255         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2256         .flags          = CLOCK_IN_OMAP3430ES2,
2257         .clkdm_name     = "usbhost_clkdm",
2258         .recalc         = &followparent_recalc,
2259 };
2260
2261 static struct clk usbhost_48m_fck = {
2262         .name           = "usbhost_48m_fck",
2263         .ops            = &clkops_omap2_dflt_wait,
2264         .parent         = &omap_48m_fck,
2265         .init           = &omap2_init_clk_clkdm,
2266         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2267         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2268         .flags          = CLOCK_IN_OMAP3430ES2,
2269         .clkdm_name     = "usbhost_clkdm",
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk usbhost_ick = {
2274         /* Handles both L3 and L4 clocks */
2275         .name           = "usbhost_ick",
2276         .ops            = &clkops_omap2_dflt_wait,
2277         .parent         = &l4_ick,
2278         .init           = &omap2_init_clk_clkdm,
2279         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2280         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2281         .flags          = CLOCK_IN_OMAP3430ES2,
2282         .clkdm_name     = "usbhost_clkdm",
2283         .recalc         = &followparent_recalc,
2284 };
2285
2286 static struct clk usbhost_sar_fck = {
2287         .name           = "usbhost_sar_fck",
2288         .ops            = &clkops_omap2_dflt,
2289         .parent         = &osc_sys_ck,
2290         .init           = &omap2_init_clk_clkdm,
2291         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2292         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2293         .flags          = CLOCK_IN_OMAP3430ES2,
2294         .clkdm_name     = "usbhost_clkdm",
2295         .recalc         = &followparent_recalc,
2296 };
2297
2298 /* WKUP */
2299
2300 static const struct clksel_rate usim_96m_rates[] = {
2301         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2302         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2303         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2304         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2305         { .div = 0 },
2306 };
2307
2308 static const struct clksel_rate usim_120m_rates[] = {
2309         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2310         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2311         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2312         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2313         { .div = 0 },
2314 };
2315
2316 static const struct clksel usim_clksel[] = {
2317         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2318         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2319         { .parent = &sys_ck,            .rates = div2_rates },
2320         { .parent = NULL },
2321 };
2322
2323 /* 3430ES2 only */
2324 static struct clk usim_fck = {
2325         .name           = "usim_fck",
2326         .ops            = &clkops_omap2_dflt_wait,
2327         .init           = &omap2_init_clksel_parent,
2328         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2329         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2330         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2331         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2332         .clksel         = usim_clksel,
2333         .flags          = CLOCK_IN_OMAP3430ES2,
2334         .recalc         = &omap2_clksel_recalc,
2335 };
2336
2337 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2338 static struct clk gpt1_fck = {
2339         .name           = "gpt1_fck",
2340         .ops            = &clkops_omap2_dflt_wait,
2341         .init           = &omap2_init_clksel_parent,
2342         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2343         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2344         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2345         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2346         .clksel         = omap343x_gpt_clksel,
2347         .flags          = CLOCK_IN_OMAP343X,
2348         .clkdm_name     = "wkup_clkdm",
2349         .recalc         = &omap2_clksel_recalc,
2350 };
2351
2352 static struct clk wkup_32k_fck = {
2353         .name           = "wkup_32k_fck",
2354         .ops            = &clkops_null,
2355         .init           = &omap2_init_clk_clkdm,
2356         .parent         = &omap_32k_fck,
2357         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2358         .clkdm_name     = "wkup_clkdm",
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk gpio1_dbck = {
2363         .name           = "gpio1_dbck",
2364         .ops            = &clkops_omap2_dflt_wait,
2365         .parent         = &wkup_32k_fck,
2366         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2367         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2368         .flags          = CLOCK_IN_OMAP343X,
2369         .clkdm_name     = "wkup_clkdm",
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk wdt2_fck = {
2374         .name           = "wdt2_fck",
2375         .ops            = &clkops_omap2_dflt_wait,
2376         .parent         = &wkup_32k_fck,
2377         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2378         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2379         .flags          = CLOCK_IN_OMAP343X,
2380         .clkdm_name     = "wkup_clkdm",
2381         .recalc         = &followparent_recalc,
2382 };
2383
2384 static struct clk wkup_l4_ick = {
2385         .name           = "wkup_l4_ick",
2386         .ops            = &clkops_null,
2387         .parent         = &sys_ck,
2388         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2389         .clkdm_name     = "wkup_clkdm",
2390         .recalc         = &followparent_recalc,
2391 };
2392
2393 /* 3430ES2 only */
2394 /* Never specifically named in the TRM, so we have to infer a likely name */
2395 static struct clk usim_ick = {
2396         .name           = "usim_ick",
2397         .ops            = &clkops_omap2_dflt_wait,
2398         .parent         = &wkup_l4_ick,
2399         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2400         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2401         .flags          = CLOCK_IN_OMAP3430ES2,
2402         .clkdm_name     = "wkup_clkdm",
2403         .recalc         = &followparent_recalc,
2404 };
2405
2406 static struct clk wdt2_ick = {
2407         .name           = "wdt2_ick",
2408         .ops            = &clkops_omap2_dflt_wait,
2409         .parent         = &wkup_l4_ick,
2410         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2411         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2412         .flags          = CLOCK_IN_OMAP343X,
2413         .clkdm_name     = "wkup_clkdm",
2414         .recalc         = &followparent_recalc,
2415 };
2416
2417 static struct clk wdt1_ick = {
2418         .name           = "wdt1_ick",
2419         .ops            = &clkops_omap2_dflt_wait,
2420         .parent         = &wkup_l4_ick,
2421         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2422         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2423         .flags          = CLOCK_IN_OMAP343X,
2424         .clkdm_name     = "wkup_clkdm",
2425         .recalc         = &followparent_recalc,
2426 };
2427
2428 static struct clk gpio1_ick = {
2429         .name           = "gpio1_ick",
2430         .ops            = &clkops_omap2_dflt_wait,
2431         .parent         = &wkup_l4_ick,
2432         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2433         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2434         .flags          = CLOCK_IN_OMAP343X,
2435         .clkdm_name     = "wkup_clkdm",
2436         .recalc         = &followparent_recalc,
2437 };
2438
2439 static struct clk omap_32ksync_ick = {
2440         .name           = "omap_32ksync_ick",
2441         .ops            = &clkops_omap2_dflt_wait,
2442         .parent         = &wkup_l4_ick,
2443         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2444         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2445         .flags          = CLOCK_IN_OMAP343X,
2446         .clkdm_name     = "wkup_clkdm",
2447         .recalc         = &followparent_recalc,
2448 };
2449
2450 /* XXX This clock no longer exists in 3430 TRM rev F */
2451 static struct clk gpt12_ick = {
2452         .name           = "gpt12_ick",
2453         .ops            = &clkops_omap2_dflt_wait,
2454         .parent         = &wkup_l4_ick,
2455         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2456         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2457         .flags          = CLOCK_IN_OMAP343X,
2458         .clkdm_name     = "wkup_clkdm",
2459         .recalc         = &followparent_recalc,
2460 };
2461
2462 static struct clk gpt1_ick = {
2463         .name           = "gpt1_ick",
2464         .ops            = &clkops_omap2_dflt_wait,
2465         .parent         = &wkup_l4_ick,
2466         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2467         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2468         .flags          = CLOCK_IN_OMAP343X,
2469         .clkdm_name     = "wkup_clkdm",
2470         .recalc         = &followparent_recalc,
2471 };
2472
2473
2474
2475 /* PER clock domain */
2476
2477 static struct clk per_96m_fck = {
2478         .name           = "per_96m_fck",
2479         .ops            = &clkops_null,
2480         .parent         = &omap_96m_alwon_fck,
2481         .init           = &omap2_init_clk_clkdm,
2482         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2483         .clkdm_name     = "per_clkdm",
2484         .recalc         = &followparent_recalc,
2485 };
2486
2487 static struct clk per_48m_fck = {
2488         .name           = "per_48m_fck",
2489         .ops            = &clkops_null,
2490         .parent         = &omap_48m_fck,
2491         .init           = &omap2_init_clk_clkdm,
2492         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2493         .clkdm_name     = "per_clkdm",
2494         .recalc         = &followparent_recalc,
2495 };
2496
2497 static struct clk uart3_fck = {
2498         .name           = "uart3_fck",
2499         .ops            = &clkops_omap2_dflt_wait,
2500         .parent         = &per_48m_fck,
2501         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2502         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2503         .flags          = CLOCK_IN_OMAP343X,
2504         .clkdm_name     = "per_clkdm",
2505         .recalc         = &followparent_recalc,
2506 };
2507
2508 static struct clk gpt2_fck = {
2509         .name           = "gpt2_fck",
2510         .ops            = &clkops_omap2_dflt_wait,
2511         .init           = &omap2_init_clksel_parent,
2512         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2513         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2514         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2515         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2516         .clksel         = omap343x_gpt_clksel,
2517         .flags          = CLOCK_IN_OMAP343X,
2518         .clkdm_name     = "per_clkdm",
2519         .recalc         = &omap2_clksel_recalc,
2520 };
2521
2522 static struct clk gpt3_fck = {
2523         .name           = "gpt3_fck",
2524         .ops            = &clkops_omap2_dflt_wait,
2525         .init           = &omap2_init_clksel_parent,
2526         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2527         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2528         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2529         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2530         .clksel         = omap343x_gpt_clksel,
2531         .flags          = CLOCK_IN_OMAP343X,
2532         .clkdm_name     = "per_clkdm",
2533         .recalc         = &omap2_clksel_recalc,
2534 };
2535
2536 static struct clk gpt4_fck = {
2537         .name           = "gpt4_fck",
2538         .ops            = &clkops_omap2_dflt_wait,
2539         .init           = &omap2_init_clksel_parent,
2540         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2541         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2542         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2543         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2544         .clksel         = omap343x_gpt_clksel,
2545         .flags          = CLOCK_IN_OMAP343X,
2546         .clkdm_name     = "per_clkdm",
2547         .recalc         = &omap2_clksel_recalc,
2548 };
2549
2550 static struct clk gpt5_fck = {
2551         .name           = "gpt5_fck",
2552         .ops            = &clkops_omap2_dflt_wait,
2553         .init           = &omap2_init_clksel_parent,
2554         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2555         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2556         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2557         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2558         .clksel         = omap343x_gpt_clksel,
2559         .flags          = CLOCK_IN_OMAP343X,
2560         .clkdm_name     = "per_clkdm",
2561         .recalc         = &omap2_clksel_recalc,
2562 };
2563
2564 static struct clk gpt6_fck = {
2565         .name           = "gpt6_fck",
2566         .ops            = &clkops_omap2_dflt_wait,
2567         .init           = &omap2_init_clksel_parent,
2568         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2569         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2570         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2571         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2572         .clksel         = omap343x_gpt_clksel,
2573         .flags          = CLOCK_IN_OMAP343X,
2574         .clkdm_name     = "per_clkdm",
2575         .recalc         = &omap2_clksel_recalc,
2576 };
2577
2578 static struct clk gpt7_fck = {
2579         .name           = "gpt7_fck",
2580         .ops            = &clkops_omap2_dflt_wait,
2581         .init           = &omap2_init_clksel_parent,
2582         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2583         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2584         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2585         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2586         .clksel         = omap343x_gpt_clksel,
2587         .flags          = CLOCK_IN_OMAP343X,
2588         .clkdm_name     = "per_clkdm",
2589         .recalc         = &omap2_clksel_recalc,
2590 };
2591
2592 static struct clk gpt8_fck = {
2593         .name           = "gpt8_fck",
2594         .ops            = &clkops_omap2_dflt_wait,
2595         .init           = &omap2_init_clksel_parent,
2596         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2597         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2598         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2599         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2600         .clksel         = omap343x_gpt_clksel,
2601         .flags          = CLOCK_IN_OMAP343X,
2602         .clkdm_name     = "per_clkdm",
2603         .recalc         = &omap2_clksel_recalc,
2604 };
2605
2606 static struct clk gpt9_fck = {
2607         .name           = "gpt9_fck",
2608         .ops            = &clkops_omap2_dflt_wait,
2609         .init           = &omap2_init_clksel_parent,
2610         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2611         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2612         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2613         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2614         .clksel         = omap343x_gpt_clksel,
2615         .flags          = CLOCK_IN_OMAP343X,
2616         .clkdm_name     = "per_clkdm",
2617         .recalc         = &omap2_clksel_recalc,
2618 };
2619
2620 static struct clk per_32k_alwon_fck = {
2621         .name           = "per_32k_alwon_fck",
2622         .ops            = &clkops_null,
2623         .parent         = &omap_32k_fck,
2624         .clkdm_name     = "per_clkdm",
2625         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2626         .recalc         = &followparent_recalc,
2627 };
2628
2629 static struct clk gpio6_dbck = {
2630         .name           = "gpio6_dbck",
2631         .ops            = &clkops_omap2_dflt_wait,
2632         .parent         = &per_32k_alwon_fck,
2633         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2634         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2635         .flags          = CLOCK_IN_OMAP343X,
2636         .clkdm_name     = "per_clkdm",
2637         .recalc         = &followparent_recalc,
2638 };
2639
2640 static struct clk gpio5_dbck = {
2641         .name           = "gpio5_dbck",
2642         .ops            = &clkops_omap2_dflt_wait,
2643         .parent         = &per_32k_alwon_fck,
2644         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2645         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2646         .flags          = CLOCK_IN_OMAP343X,
2647         .clkdm_name     = "per_clkdm",
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 static struct clk gpio4_dbck = {
2652         .name           = "gpio4_dbck",
2653         .ops            = &clkops_omap2_dflt_wait,
2654         .parent         = &per_32k_alwon_fck,
2655         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2656         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2657         .flags          = CLOCK_IN_OMAP343X,
2658         .clkdm_name     = "per_clkdm",
2659         .recalc         = &followparent_recalc,
2660 };
2661
2662 static struct clk gpio3_dbck = {
2663         .name           = "gpio3_dbck",
2664         .ops            = &clkops_omap2_dflt_wait,
2665         .parent         = &per_32k_alwon_fck,
2666         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2667         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2668         .flags          = CLOCK_IN_OMAP343X,
2669         .clkdm_name     = "per_clkdm",
2670         .recalc         = &followparent_recalc,
2671 };
2672
2673 static struct clk gpio2_dbck = {
2674         .name           = "gpio2_dbck",
2675         .ops            = &clkops_omap2_dflt_wait,
2676         .parent         = &per_32k_alwon_fck,
2677         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2678         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2679         .flags          = CLOCK_IN_OMAP343X,
2680         .clkdm_name     = "per_clkdm",
2681         .recalc         = &followparent_recalc,
2682 };
2683
2684 static struct clk wdt3_fck = {
2685         .name           = "wdt3_fck",
2686         .ops            = &clkops_omap2_dflt_wait,
2687         .parent         = &per_32k_alwon_fck,
2688         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2689         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2690         .flags          = CLOCK_IN_OMAP343X,
2691         .clkdm_name     = "per_clkdm",
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk per_l4_ick = {
2696         .name           = "per_l4_ick",
2697         .ops            = &clkops_null,
2698         .parent         = &l4_ick,
2699         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2700         .clkdm_name     = "per_clkdm",
2701         .recalc         = &followparent_recalc,
2702 };
2703
2704 static struct clk gpio6_ick = {
2705         .name           = "gpio6_ick",
2706         .ops            = &clkops_omap2_dflt_wait,
2707         .parent         = &per_l4_ick,
2708         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2710         .flags          = CLOCK_IN_OMAP343X,
2711         .clkdm_name     = "per_clkdm",
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk gpio5_ick = {
2716         .name           = "gpio5_ick",
2717         .ops            = &clkops_omap2_dflt_wait,
2718         .parent         = &per_l4_ick,
2719         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2720         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2721         .flags          = CLOCK_IN_OMAP343X,
2722         .clkdm_name     = "per_clkdm",
2723         .recalc         = &followparent_recalc,
2724 };
2725
2726 static struct clk gpio4_ick = {
2727         .name           = "gpio4_ick",
2728         .ops            = &clkops_omap2_dflt_wait,
2729         .parent         = &per_l4_ick,
2730         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2732         .flags          = CLOCK_IN_OMAP343X,
2733         .clkdm_name     = "per_clkdm",
2734         .recalc         = &followparent_recalc,
2735 };
2736
2737 static struct clk gpio3_ick = {
2738         .name           = "gpio3_ick",
2739         .ops            = &clkops_omap2_dflt_wait,
2740         .parent         = &per_l4_ick,
2741         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2742         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2743         .flags          = CLOCK_IN_OMAP343X,
2744         .clkdm_name     = "per_clkdm",
2745         .recalc         = &followparent_recalc,
2746 };
2747
2748 static struct clk gpio2_ick = {
2749         .name           = "gpio2_ick",
2750         .ops            = &clkops_omap2_dflt_wait,
2751         .parent         = &per_l4_ick,
2752         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2753         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2754         .flags          = CLOCK_IN_OMAP343X,
2755         .clkdm_name     = "per_clkdm",
2756         .recalc         = &followparent_recalc,
2757 };
2758
2759 static struct clk wdt3_ick = {
2760         .name           = "wdt3_ick",
2761         .ops            = &clkops_omap2_dflt_wait,
2762         .parent         = &per_l4_ick,
2763         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2764         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2765         .flags          = CLOCK_IN_OMAP343X,
2766         .clkdm_name     = "per_clkdm",
2767         .recalc         = &followparent_recalc,
2768 };
2769
2770 static struct clk uart3_ick = {
2771         .name           = "uart3_ick",
2772         .ops            = &clkops_omap2_dflt_wait,
2773         .parent         = &per_l4_ick,
2774         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2775         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2776         .flags          = CLOCK_IN_OMAP343X,
2777         .clkdm_name     = "per_clkdm",
2778         .recalc         = &followparent_recalc,
2779 };
2780
2781 static struct clk gpt9_ick = {
2782         .name           = "gpt9_ick",
2783         .ops            = &clkops_omap2_dflt_wait,
2784         .parent         = &per_l4_ick,
2785         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2786         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2787         .flags          = CLOCK_IN_OMAP343X,
2788         .clkdm_name     = "per_clkdm",
2789         .recalc         = &followparent_recalc,
2790 };
2791
2792 static struct clk gpt8_ick = {
2793         .name           = "gpt8_ick",
2794         .ops            = &clkops_omap2_dflt_wait,
2795         .parent         = &per_l4_ick,
2796         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2797         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2798         .flags          = CLOCK_IN_OMAP343X,
2799         .clkdm_name     = "per_clkdm",
2800         .recalc         = &followparent_recalc,
2801 };
2802
2803 static struct clk gpt7_ick = {
2804         .name           = "gpt7_ick",
2805         .ops            = &clkops_omap2_dflt_wait,
2806         .parent         = &per_l4_ick,
2807         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2808         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2809         .flags          = CLOCK_IN_OMAP343X,
2810         .clkdm_name     = "per_clkdm",
2811         .recalc         = &followparent_recalc,
2812 };
2813
2814 static struct clk gpt6_ick = {
2815         .name           = "gpt6_ick",
2816         .ops            = &clkops_omap2_dflt_wait,
2817         .parent         = &per_l4_ick,
2818         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2820         .flags          = CLOCK_IN_OMAP343X,
2821         .clkdm_name     = "per_clkdm",
2822         .recalc         = &followparent_recalc,
2823 };
2824
2825 static struct clk gpt5_ick = {
2826         .name           = "gpt5_ick",
2827         .ops            = &clkops_omap2_dflt_wait,
2828         .parent         = &per_l4_ick,
2829         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2830         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2831         .flags          = CLOCK_IN_OMAP343X,
2832         .clkdm_name     = "per_clkdm",
2833         .recalc         = &followparent_recalc,
2834 };
2835
2836 static struct clk gpt4_ick = {
2837         .name           = "gpt4_ick",
2838         .ops            = &clkops_omap2_dflt_wait,
2839         .parent         = &per_l4_ick,
2840         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2841         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2842         .flags          = CLOCK_IN_OMAP343X,
2843         .clkdm_name     = "per_clkdm",
2844         .recalc         = &followparent_recalc,
2845 };
2846
2847 static struct clk gpt3_ick = {
2848         .name           = "gpt3_ick",
2849         .ops            = &clkops_omap2_dflt_wait,
2850         .parent         = &per_l4_ick,
2851         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2852         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2853         .flags          = CLOCK_IN_OMAP343X,
2854         .clkdm_name     = "per_clkdm",
2855         .recalc         = &followparent_recalc,
2856 };
2857
2858 static struct clk gpt2_ick = {
2859         .name           = "gpt2_ick",
2860         .ops            = &clkops_omap2_dflt_wait,
2861         .parent         = &per_l4_ick,
2862         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2863         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2864         .flags          = CLOCK_IN_OMAP343X,
2865         .clkdm_name     = "per_clkdm",
2866         .recalc         = &followparent_recalc,
2867 };
2868
2869 static struct clk mcbsp2_ick = {
2870         .name           = "mcbsp_ick",
2871         .ops            = &clkops_omap2_dflt_wait,
2872         .id             = 2,
2873         .parent         = &per_l4_ick,
2874         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2875         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2876         .flags          = CLOCK_IN_OMAP343X,
2877         .clkdm_name     = "per_clkdm",
2878         .recalc         = &followparent_recalc,
2879 };
2880
2881 static struct clk mcbsp3_ick = {
2882         .name           = "mcbsp_ick",
2883         .ops            = &clkops_omap2_dflt_wait,
2884         .id             = 3,
2885         .parent         = &per_l4_ick,
2886         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2887         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2888         .flags          = CLOCK_IN_OMAP343X,
2889         .clkdm_name     = "per_clkdm",
2890         .recalc         = &followparent_recalc,
2891 };
2892
2893 static struct clk mcbsp4_ick = {
2894         .name           = "mcbsp_ick",
2895         .ops            = &clkops_omap2_dflt_wait,
2896         .id             = 4,
2897         .parent         = &per_l4_ick,
2898         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2899         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2900         .flags          = CLOCK_IN_OMAP343X,
2901         .clkdm_name     = "per_clkdm",
2902         .recalc         = &followparent_recalc,
2903 };
2904
2905 static const struct clksel mcbsp_234_clksel[] = {
2906         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2907         { .parent = &mcbsp_clks,  .rates = common_mcbsp_mcbsp_rates },
2908         { .parent = NULL }
2909 };
2910
2911 static struct clk mcbsp2_fck = {
2912         .name           = "mcbsp_fck",
2913         .ops            = &clkops_omap2_dflt_wait,
2914         .id             = 2,
2915         .init           = &omap2_init_clksel_parent,
2916         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2917         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2918         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2919         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2920         .clksel         = mcbsp_234_clksel,
2921         .flags          = CLOCK_IN_OMAP343X,
2922         .clkdm_name     = "per_clkdm",
2923         .recalc         = &omap2_clksel_recalc,
2924 };
2925
2926 static struct clk mcbsp3_fck = {
2927         .name           = "mcbsp_fck",
2928         .ops            = &clkops_omap2_dflt_wait,
2929         .id             = 3,
2930         .init           = &omap2_init_clksel_parent,
2931         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2932         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2933         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2934         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2935         .clksel         = mcbsp_234_clksel,
2936         .flags          = CLOCK_IN_OMAP343X,
2937         .clkdm_name     = "per_clkdm",
2938         .recalc         = &omap2_clksel_recalc,
2939 };
2940
2941 static struct clk mcbsp4_fck = {
2942         .name           = "mcbsp_fck",
2943         .ops            = &clkops_omap2_dflt_wait,
2944         .id             = 4,
2945         .init           = &omap2_init_clksel_parent,
2946         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2947         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2948         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2949         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2950         .clksel         = mcbsp_234_clksel,
2951         .flags          = CLOCK_IN_OMAP343X,
2952         .clkdm_name     = "per_clkdm",
2953         .recalc         = &omap2_clksel_recalc,
2954 };
2955
2956 /* EMU clocks */
2957
2958 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2959
2960 static const struct clksel_rate emu_src_sys_rates[] = {
2961         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2962         { .div = 0 },
2963 };
2964
2965 static const struct clksel_rate emu_src_core_rates[] = {
2966         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2967         { .div = 0 },
2968 };
2969
2970 static const struct clksel_rate emu_src_per_rates[] = {
2971         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2972         { .div = 0 },
2973 };
2974
2975 static const struct clksel_rate emu_src_mpu_rates[] = {
2976         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2977         { .div = 0 },
2978 };
2979
2980 static const struct clksel emu_src_clksel[] = {
2981         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2982         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2983         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2984         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2985         { .parent = NULL },
2986 };
2987
2988 /*
2989  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2990  * to switch the source of some of the EMU clocks.
2991  * XXX Are there CLKEN bits for these EMU clks?
2992  */
2993 static struct clk emu_src_ck = {
2994         .name           = "emu_src_ck",
2995         .ops            = &clkops_null,
2996         .init           = &omap2_init_clksel_parent,
2997         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2998         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2999         .clksel         = emu_src_clksel,
3000         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3001         .clkdm_name     = "emu_clkdm",
3002         .recalc         = &omap2_clksel_recalc,
3003 };
3004
3005 static const struct clksel_rate pclk_emu_rates[] = {
3006         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3007         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3008         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3009         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3010         { .div = 0 },
3011 };
3012
3013 static const struct clksel pclk_emu_clksel[] = {
3014         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3015         { .parent = NULL },
3016 };
3017
3018 static struct clk pclk_fck = {
3019         .name           = "pclk_fck",
3020         .ops            = &clkops_null,
3021         .init           = &omap2_init_clksel_parent,
3022         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3023         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3024         .clksel         = pclk_emu_clksel,
3025         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3026         .clkdm_name     = "emu_clkdm",
3027         .recalc         = &omap2_clksel_recalc,
3028 };
3029
3030 static const struct clksel_rate pclkx2_emu_rates[] = {
3031         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3032         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3033         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3034         { .div = 0 },
3035 };
3036
3037 static const struct clksel pclkx2_emu_clksel[] = {
3038         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3039         { .parent = NULL },
3040 };
3041
3042 static struct clk pclkx2_fck = {
3043         .name           = "pclkx2_fck",
3044         .ops            = &clkops_null,
3045         .init           = &omap2_init_clksel_parent,
3046         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3047         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3048         .clksel         = pclkx2_emu_clksel,
3049         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3050         .clkdm_name     = "emu_clkdm",
3051         .recalc         = &omap2_clksel_recalc,
3052 };
3053
3054 static const struct clksel atclk_emu_clksel[] = {
3055         { .parent = &emu_src_ck, .rates = div2_rates },
3056         { .parent = NULL },
3057 };
3058
3059 static struct clk atclk_fck = {
3060         .name           = "atclk_fck",
3061         .ops            = &clkops_null,
3062         .init           = &omap2_init_clksel_parent,
3063         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3064         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3065         .clksel         = atclk_emu_clksel,
3066         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3067         .clkdm_name     = "emu_clkdm",
3068         .recalc         = &omap2_clksel_recalc,
3069 };
3070
3071 static struct clk traceclk_src_fck = {
3072         .name           = "traceclk_src_fck",
3073         .ops            = &clkops_null,
3074         .init           = &omap2_init_clksel_parent,
3075         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3076         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3077         .clksel         = emu_src_clksel,
3078         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3079         .clkdm_name     = "emu_clkdm",
3080         .recalc         = &omap2_clksel_recalc,
3081 };
3082
3083 static const struct clksel_rate traceclk_rates[] = {
3084         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3085         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3086         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3087         { .div = 0 },
3088 };
3089
3090 static const struct clksel traceclk_clksel[] = {
3091         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3092         { .parent = NULL },
3093 };
3094
3095 static struct clk traceclk_fck = {
3096         .name           = "traceclk_fck",
3097         .ops            = &clkops_null,
3098         .init           = &omap2_init_clksel_parent,
3099         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3100         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3101         .clksel         = traceclk_clksel,
3102         .flags          = CLOCK_IN_OMAP343X,
3103         .clkdm_name     = "emu_clkdm",
3104         .recalc         = &omap2_clksel_recalc,
3105 };
3106
3107 /* SR clocks */
3108
3109 /* SmartReflex fclk (VDD1) */
3110 static struct clk sr1_fck = {
3111         .name           = "sr1_fck",
3112         .ops            = &clkops_omap2_dflt_wait,
3113         .parent         = &sys_ck,
3114         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3115         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3116         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3117         .recalc         = &followparent_recalc,
3118 };
3119
3120 /* SmartReflex fclk (VDD2) */
3121 static struct clk sr2_fck = {
3122         .name           = "sr2_fck",
3123         .ops            = &clkops_omap2_dflt_wait,
3124         .parent         = &sys_ck,
3125         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3126         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3127         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
3128         .recalc         = &followparent_recalc,
3129 };
3130
3131 static struct clk sr_l4_ick = {
3132         .name           = "sr_l4_ick",
3133         .ops            = &clkops_null, /* RMK: missing? */
3134         .parent         = &l4_ick,
3135         .flags          = CLOCK_IN_OMAP343X,
3136         .clkdm_name     = "core_l4_clkdm",
3137         .recalc         = &followparent_recalc,
3138 };
3139
3140 /* SECURE_32K_FCK clocks */
3141
3142 /* XXX This clock no longer exists in 3430 TRM rev F */
3143 static struct clk gpt12_fck = {
3144         .name           = "gpt12_fck",
3145         .ops            = &clkops_null,
3146         .parent         = &secure_32k_fck,
3147         .flags          = CLOCK_IN_OMAP343X,
3148         .recalc         = &followparent_recalc,
3149 };
3150
3151 static struct clk wdt1_fck = {
3152         .name           = "wdt1_fck",
3153         .ops            = &clkops_null,
3154         .parent         = &secure_32k_fck,
3155         .flags          = CLOCK_IN_OMAP343X,
3156         .recalc         = &followparent_recalc,
3157 };
3158
3159 static struct clk *onchip_34xx_clks[] __initdata = {
3160         &omap_32k_fck,
3161         &virt_12m_ck,
3162         &virt_13m_ck,
3163         &virt_16_8m_ck,
3164         &virt_19_2m_ck,
3165         &virt_26m_ck,
3166         &virt_38_4m_ck,
3167         &osc_sys_ck,
3168         &sys_ck,
3169         &sys_altclk,
3170         &mcbsp_clks,
3171         &sys_clkout1,
3172         &dpll1_ck,
3173         &dpll1_x2_ck,
3174         &dpll1_x2m2_ck,
3175         &dpll2_ck,
3176         &dpll2_m2_ck,
3177         &dpll3_ck,
3178         &core_ck,
3179         &dpll3_x2_ck,
3180         &dpll3_m2_ck,
3181         &dpll3_m2x2_ck,
3182         &dpll3_m3_ck,
3183         &dpll3_m3x2_ck,
3184         &emu_core_alwon_ck,
3185         &dpll4_ck,
3186         &dpll4_x2_ck,
3187         &omap_96m_alwon_fck,
3188         &omap_96m_fck,
3189         &cm_96m_fck,
3190         &virt_omap_54m_fck,
3191         &omap_54m_fck,
3192         &omap_48m_fck,
3193         &omap_12m_fck,
3194         &dpll4_m2_ck,
3195         &dpll4_m2x2_ck,
3196         &dpll4_m3_ck,
3197         &dpll4_m3x2_ck,
3198         &dpll4_m4_ck,
3199         &dpll4_m4x2_ck,
3200         &dpll4_m5_ck,
3201         &dpll4_m5x2_ck,
3202         &dpll4_m6_ck,
3203         &dpll4_m6x2_ck,
3204         &emu_per_alwon_ck,
3205         &dpll5_ck,
3206         &dpll5_m2_ck,
3207         &omap_120m_fck,
3208         &clkout2_src_ck,
3209         &sys_clkout2,
3210         &corex2_fck,
3211         &dpll1_fck,
3212         &mpu_ck,
3213         &arm_fck,
3214         &emu_mpu_alwon_ck,
3215         &dpll2_fck,
3216         &iva2_ck,
3217         &l3_ick,
3218         &l4_ick,
3219         &rm_ick,
3220         &gfx_l3_ck,
3221         &gfx_l3_fck,
3222         &gfx_l3_ick,
3223         &gfx_cg1_ck,
3224         &gfx_cg2_ck,
3225         &sgx_fck,
3226         &sgx_ick,
3227         &d2d_26m_fck,
3228         &gpt10_fck,
3229         &gpt11_fck,
3230         &cpefuse_fck,
3231         &ts_fck,
3232         &usbtll_fck,
3233         &core_96m_fck,
3234         &mmchs3_fck,
3235         &mmchs2_fck,
3236         &mspro_fck,
3237         &mmchs1_fck,
3238         &i2c3_fck,
3239         &i2c2_fck,
3240         &i2c1_fck,
3241         &mcbsp5_fck,
3242         &mcbsp1_fck,
3243         &core_48m_fck,
3244         &mcspi4_fck,
3245         &mcspi3_fck,
3246         &mcspi2_fck,
3247         &mcspi1_fck,
3248         &uart2_fck,
3249         &uart1_fck,
3250         &fshostusb_fck,
3251         &core_12m_fck,
3252         &hdq_fck,
3253         &ssi_ssr_fck,
3254         &ssi_sst_fck,
3255         &core_l3_ick,
3256         &hsotgusb_ick,
3257         &sdrc_ick,
3258         &gpmc_fck,
3259         &security_l3_ick,
3260         &pka_ick,
3261         &core_l4_ick,
3262         &usbtll_ick,
3263         &mmchs3_ick,
3264         &icr_ick,
3265         &aes2_ick,
3266         &sha12_ick,
3267         &des2_ick,
3268         &mmchs2_ick,
3269         &mmchs1_ick,
3270         &mspro_ick,
3271         &hdq_ick,
3272         &mcspi4_ick,
3273         &mcspi3_ick,
3274         &mcspi2_ick,
3275         &mcspi1_ick,
3276         &i2c3_ick,
3277         &i2c2_ick,
3278         &i2c1_ick,
3279         &uart2_ick,
3280         &uart1_ick,
3281         &gpt11_ick,
3282         &gpt10_ick,
3283         &mcbsp5_ick,
3284         &mcbsp1_ick,
3285         &fac_ick,
3286         &mailboxes_ick,
3287         &omapctrl_ick,
3288         &ssi_l4_ick,
3289         &ssi_ick,
3290         &usb_l4_ick,
3291         &security_l4_ick2,
3292         &aes1_ick,
3293         &rng_ick,
3294         &sha11_ick,
3295         &des1_ick,
3296         &dss1_alwon_fck,
3297         &dss_tv_fck,
3298         &dss_96m_fck,
3299         &dss2_alwon_fck,
3300         &dss_ick,
3301         &cam_mclk,
3302         &cam_ick,
3303         &usbhost_120m_fck,
3304         &usbhost_48m_fck,
3305         &usbhost_ick,
3306         &usbhost_sar_fck,
3307         &usim_fck,
3308         &gpt1_fck,
3309         &wkup_32k_fck,
3310         &gpio1_dbck,
3311         &wdt2_fck,
3312         &wkup_l4_ick,
3313         &usim_ick,
3314         &wdt2_ick,
3315         &wdt1_ick,
3316         &gpio1_ick,
3317         &omap_32ksync_ick,
3318         &gpt12_ick,
3319         &gpt1_ick,
3320         &per_96m_fck,
3321         &per_48m_fck,
3322         &uart3_fck,
3323         &gpt2_fck,
3324         &gpt3_fck,
3325         &gpt4_fck,
3326         &gpt5_fck,
3327         &gpt6_fck,
3328         &gpt7_fck,
3329         &gpt8_fck,
3330         &gpt9_fck,
3331         &per_32k_alwon_fck,
3332         &gpio6_dbck,
3333         &gpio5_dbck,
3334         &gpio4_dbck,
3335         &gpio3_dbck,
3336         &gpio2_dbck,
3337         &wdt3_fck,
3338         &per_l4_ick,
3339         &gpio6_ick,
3340         &gpio5_ick,
3341         &gpio4_ick,
3342         &gpio3_ick,
3343         &gpio2_ick,
3344         &wdt3_ick,
3345         &uart3_ick,
3346         &gpt9_ick,
3347         &gpt8_ick,
3348         &gpt7_ick,
3349         &gpt6_ick,
3350         &gpt5_ick,
3351         &gpt4_ick,
3352         &gpt3_ick,
3353         &gpt2_ick,
3354         &mcbsp2_ick,
3355         &mcbsp3_ick,
3356         &mcbsp4_ick,
3357         &mcbsp2_fck,
3358         &mcbsp3_fck,
3359         &mcbsp4_fck,
3360         &emu_src_ck,
3361         &pclk_fck,
3362         &pclkx2_fck,
3363         &atclk_fck,
3364         &traceclk_src_fck,
3365         &traceclk_fck,
3366         &sr1_fck,
3367         &sr2_fck,
3368         &sr_l4_ick,
3369         &secure_32k_fck,
3370         &gpt12_fck,
3371         &wdt1_fck,
3372 };
3373
3374 #endif