arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  31
  32 static unsigned long omap3_dpll_recalc(struct clk *clk);
  33 static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
  34 static void omap3_dpll_allow_idle(struct clk *clk);
  35 static void omap3_dpll_deny_idle(struct clk *clk);
  36 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  39 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  40
  41 /* Maximum DPLL multiplier, divider values for OMAP3 */
  42 #define OMAP3_MAX_DPLL_MULT             2048
  43 #define OMAP3_MAX_DPLL_DIV              128
  44
  45 /*
  46  * DPLL1 supplies clock to the MPU.
  47  * DPLL2 supplies clock to the IVA2.
  48  * DPLL3 supplies CORE domain clocks.
  49  * DPLL4 supplies peripheral clocks.
  50  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  51  */
  52
  53 /* Forward declarations for DPLL bypass clocks */
  54 static struct clk dpll1_fck;
  55 static struct clk dpll2_fck;
  56
  57 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  58 #define DPLL_LOW_POWER_STOP             0x1
  59 #define DPLL_LOW_POWER_BYPASS           0x5
  60 #define DPLL_LOCKED                     0x7
  61
  62 /* PRM CLOCKS */
  63
  64 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  65 static struct clk omap_32k_fck = {
  66         .name           = "omap_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69         .flags          = RATE_FIXED,
  70 };
  71
  72 static struct clk secure_32k_fck = {
  73         .name           = "secure_32k_fck",
  74         .ops            = &clkops_null,
  75         .rate           = 32768,
  76         .flags          = RATE_FIXED,
  77 };
  78
  79 /* Virtual source clocks for osc_sys_ck */
  80 static struct clk virt_12m_ck = {
  81         .name           = "virt_12m_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 12000000,
  84         .flags          = RATE_FIXED,
  85 };
  86
  87 static struct clk virt_13m_ck = {
  88         .name           = "virt_13m_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 13000000,
  91         .flags          = RATE_FIXED,
  92 };
  93
  94 static struct clk virt_16_8m_ck = {
  95         .name           = "virt_16_8m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 16800000,
  98         .flags          = RATE_FIXED,
  99 };
 100
 101 static struct clk virt_19_2m_ck = {
 102         .name           = "virt_19_2m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 19200000,
 105         .flags          = RATE_FIXED,
 106 };
 107
 108 static struct clk virt_26m_ck = {
 109         .name           = "virt_26m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 26000000,
 112         .flags          = RATE_FIXED,
 113 };
 114
 115 static struct clk virt_38_4m_ck = {
 116         .name           = "virt_38_4m_ck",
 117         .ops            = &clkops_null,
 118         .rate           = 38400000,
 119         .flags          = RATE_FIXED,
 120 };
 121
 122 static const struct clksel_rate osc_sys_12m_rates[] = {
 123         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 124         { .div = 0 }
 125 };
 126
 127 static const struct clksel_rate osc_sys_13m_rates[] = {
 128         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 129         { .div = 0 }
 130 };
 131
 132 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 133         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 134         { .div = 0 }
 135 };
 136
 137 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 138         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 139         { .div = 0 }
 140 };
 141
 142 static const struct clksel_rate osc_sys_26m_rates[] = {
 143         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 144         { .div = 0 }
 145 };
 146
 147 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 148         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 149         { .div = 0 }
 150 };
 151
 152 static const struct clksel osc_sys_clksel[] = {
 153         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 154         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 155         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 156         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 157         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 158         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 159         { .parent = NULL },
 160 };
 161
 162 /* Oscillator clock */
 163 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 164 static struct clk osc_sys_ck = {
 165         .name           = "osc_sys_ck",
 166         .ops            = &clkops_null,
 167         .init           = &omap2_init_clksel_parent,
 168         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 169         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 170         .clksel         = osc_sys_clksel,
 171         /* REVISIT: deal with autoextclkmode? */
 172         .flags          = RATE_FIXED,
 173         .recalc         = &omap2_clksel_recalc,
 174 };
 175
 176 static const struct clksel_rate div2_rates[] = {
 177         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 178         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 179         { .div = 0 }
 180 };
 181
 182 static const struct clksel sys_clksel[] = {
 183         { .parent = &osc_sys_ck, .rates = div2_rates },
 184         { .parent = NULL }
 185 };
 186
 187 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 188 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 189 static struct clk sys_ck = {
 190         .name           = "sys_ck",
 191         .ops            = &clkops_null,
 192         .parent         = &osc_sys_ck,
 193         .init           = &omap2_init_clksel_parent,
 194         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 195         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 196         .clksel         = sys_clksel,
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static struct clk sys_altclk = {
 201         .name           = "sys_altclk",
 202         .ops            = &clkops_null,
 203 };
 204
 205 /* Optional external clock input for some McBSPs */
 206 static struct clk mcbsp_clks = {
 207         .name           = "mcbsp_clks",
 208         .ops            = &clkops_null,
 209 };
 210
 211 /* PRM EXTERNAL CLOCK OUTPUT */
 212
 213 static struct clk sys_clkout1 = {
 214         .name           = "sys_clkout1",
 215         .ops            = &clkops_omap2_dflt,
 216         .parent         = &osc_sys_ck,
 217         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 218         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 219         .recalc         = &followparent_recalc,
 220 };
 221
 222 /* DPLLS */
 223
 224 /* CM CLOCKS */
 225
 226 static const struct clksel_rate div16_dpll_rates[] = {
 227         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 228         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 229         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 230         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 231         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 232         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 233         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 234         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 235         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 236         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 237         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 238         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 239         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 240         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 241         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 242         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 243         { .div = 0 }
 244 };
 245
 246 /* DPLL1 */
 247 /* MPU clock source */
 248 /* Type: DPLL */
 249 static struct dpll_data dpll1_dd = {
 250         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 251         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 252         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 253         .clk_bypass     = &dpll1_fck,
 254         .clk_ref        = &sys_ck,
 255         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 256         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 257         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 258         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 259         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 260         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 261         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 262         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 263         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 264         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 265         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 266         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 267         .min_divider    = 1,
 268         .max_divider    = OMAP3_MAX_DPLL_DIV,
 269         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 270 };
 271
 272 static struct clk dpll1_ck = {
 273         .name           = "dpll1_ck",
 274         .ops            = &clkops_null,
 275         .parent         = &sys_ck,
 276         .dpll_data      = &dpll1_dd,
 277         .round_rate     = &omap2_dpll_round_rate,
 278         .set_rate       = &omap3_noncore_dpll_set_rate,
 279         .clkdm_name     = "dpll1_clkdm",
 280         .recalc         = &omap3_dpll_recalc,
 281 };
 282
 283 /*
 284  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 285  * DPLL isn't bypassed.
 286  */
 287 static struct clk dpll1_x2_ck = {
 288         .name           = "dpll1_x2_ck",
 289         .ops            = &clkops_null,
 290         .parent         = &dpll1_ck,
 291         .clkdm_name     = "dpll1_clkdm",
 292         .recalc         = &omap3_clkoutx2_recalc,
 293 };
 294
 295 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 296 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 297         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 298         { .parent = NULL }
 299 };
 300
 301 /*
 302  * Does not exist in the TRM - needed to separate the M2 divider from
 303  * bypass selection in mpu_ck
 304  */
 305 static struct clk dpll1_x2m2_ck = {
 306         .name           = "dpll1_x2m2_ck",
 307         .ops            = &clkops_null,
 308         .parent         = &dpll1_x2_ck,
 309         .init           = &omap2_init_clksel_parent,
 310         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 311         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 312         .clksel         = div16_dpll1_x2m2_clksel,
 313         .clkdm_name     = "dpll1_clkdm",
 314         .recalc         = &omap2_clksel_recalc,
 315 };
 316
 317 /* DPLL2 */
 318 /* IVA2 clock source */
 319 /* Type: DPLL */
 320
 321 static struct dpll_data dpll2_dd = {
 322         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 323         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 324         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 325         .clk_bypass     = &dpll2_fck,
 326         .clk_ref        = &sys_ck,
 327         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 328         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 329         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 330         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 331                                 (1 << DPLL_LOW_POWER_BYPASS),
 332         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 333         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 334         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 335         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 336         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 337         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 338         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 339         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 340         .min_divider    = 1,
 341         .max_divider    = OMAP3_MAX_DPLL_DIV,
 342         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 343 };
 344
 345 static struct clk dpll2_ck = {
 346         .name           = "dpll2_ck",
 347         .ops            = &clkops_noncore_dpll_ops,
 348         .parent         = &sys_ck,
 349         .dpll_data      = &dpll2_dd,
 350         .round_rate     = &omap2_dpll_round_rate,
 351         .set_rate       = &omap3_noncore_dpll_set_rate,
 352         .clkdm_name     = "dpll2_clkdm",
 353         .recalc         = &omap3_dpll_recalc,
 354 };
 355
 356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 357         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 358         { .parent = NULL }
 359 };
 360
 361 /*
 362  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 363  * or CLKOUTX2. CLKOUT seems most plausible.
 364  */
 365 static struct clk dpll2_m2_ck = {
 366         .name           = "dpll2_m2_ck",
 367         .ops            = &clkops_null,
 368         .parent         = &dpll2_ck,
 369         .init           = &omap2_init_clksel_parent,
 370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 371                                           OMAP3430_CM_CLKSEL2_PLL),
 372         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 373         .clksel         = div16_dpll2_m2x2_clksel,
 374         .clkdm_name     = "dpll2_clkdm",
 375         .recalc         = &omap2_clksel_recalc,
 376 };
 377
 378 /*
 379  * DPLL3
 380  * Source clock for all interfaces and for some device fclks
 381  * REVISIT: Also supports fast relock bypass - not included below
 382  */
 383 static struct dpll_data dpll3_dd = {
 384         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 385         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 386         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 387         .clk_bypass     = &sys_ck,
 388         .clk_ref        = &sys_ck,
 389         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 390         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 391         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 392         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 393         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 394         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 395         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 396         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 397         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 398         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 399         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 400         .min_divider    = 1,
 401         .max_divider    = OMAP3_MAX_DPLL_DIV,
 402         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 403 };
 404
 405 static struct clk dpll3_ck = {
 406         .name           = "dpll3_ck",
 407         .ops            = &clkops_null,
 408         .parent         = &sys_ck,
 409         .dpll_data      = &dpll3_dd,
 410         .round_rate     = &omap2_dpll_round_rate,
 411         .clkdm_name     = "dpll3_clkdm",
 412         .recalc         = &omap3_dpll_recalc,
 413 };
 414
 415 /*
 416  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 417  * DPLL isn't bypassed
 418  */
 419 static struct clk dpll3_x2_ck = {
 420         .name           = "dpll3_x2_ck",
 421         .ops            = &clkops_null,
 422         .parent         = &dpll3_ck,
 423         .clkdm_name     = "dpll3_clkdm",
 424         .recalc         = &omap3_clkoutx2_recalc,
 425 };
 426
 427 static const struct clksel_rate div31_dpll3_rates[] = {
 428         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 429         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 430         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 431         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 432         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 433         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 434         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 435         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 436         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 437         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 438         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 439         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 440         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 441         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 442         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 443         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 444         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 445         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 446         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 447         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 448         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 449         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 450         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 451         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 452         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 453         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 454         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 455         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 456         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 457         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 458         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 459         { .div = 0 },
 460 };
 461
 462 static const struct clksel div31_dpll3m2_clksel[] = {
 463         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 464         { .parent = NULL }
 465 };
 466
 467 /* DPLL3 output M2 - primary control point for CORE speed */
 468 static struct clk dpll3_m2_ck = {
 469         .name           = "dpll3_m2_ck",
 470         .ops            = &clkops_null,
 471         .parent         = &dpll3_ck,
 472         .init           = &omap2_init_clksel_parent,
 473         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 474         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 475         .clksel         = div31_dpll3m2_clksel,
 476         .clkdm_name     = "dpll3_clkdm",
 477         .round_rate     = &omap2_clksel_round_rate,
 478         .set_rate       = &omap3_core_dpll_m2_set_rate,
 479         .recalc         = &omap2_clksel_recalc,
 480 };
 481
 482 static struct clk core_ck = {
 483         .name           = "core_ck",
 484         .ops            = &clkops_null,
 485         .parent         = &dpll3_m2_ck,
 486         .recalc         = &followparent_recalc,
 487 };
 488
 489 static struct clk dpll3_m2x2_ck = {
 490         .name           = "dpll3_m2x2_ck",
 491         .ops            = &clkops_null,
 492         .parent         = &dpll3_x2_ck,
 493         .clkdm_name     = "dpll3_clkdm",
 494         .recalc         = &followparent_recalc,
 495 };
 496
 497 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 498 static const struct clksel div16_dpll3_clksel[] = {
 499         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 500         { .parent = NULL }
 501 };
 502
 503 /* This virtual clock is the source for dpll3_m3x2_ck */
 504 static struct clk dpll3_m3_ck = {
 505         .name           = "dpll3_m3_ck",
 506         .ops            = &clkops_null,
 507         .parent         = &dpll3_ck,
 508         .init           = &omap2_init_clksel_parent,
 509         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 510         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 511         .clksel         = div16_dpll3_clksel,
 512         .clkdm_name     = "dpll3_clkdm",
 513         .recalc         = &omap2_clksel_recalc,
 514 };
 515
 516 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 517 static struct clk dpll3_m3x2_ck = {
 518         .name           = "dpll3_m3x2_ck",
 519         .ops            = &clkops_omap2_dflt_wait,
 520         .parent         = &dpll3_m3_ck,
 521         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 522         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 523         .flags          = INVERT_ENABLE,
 524         .clkdm_name     = "dpll3_clkdm",
 525         .recalc         = &omap3_clkoutx2_recalc,
 526 };
 527
 528 static struct clk emu_core_alwon_ck = {
 529         .name           = "emu_core_alwon_ck",
 530         .ops            = &clkops_null,
 531         .parent         = &dpll3_m3x2_ck,
 532         .clkdm_name     = "dpll3_clkdm",
 533         .recalc         = &followparent_recalc,
 534 };
 535
 536 /* DPLL4 */
 537 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 538 /* Type: DPLL */
 539 static struct dpll_data dpll4_dd = {
 540         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 541         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 542         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 543         .clk_bypass     = &sys_ck,
 544         .clk_ref        = &sys_ck,
 545         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 546         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 547         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 548         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 549         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 550         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 551         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 552         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 553         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 554         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 555         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 556         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 557         .min_divider    = 1,
 558         .max_divider    = OMAP3_MAX_DPLL_DIV,
 559         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 560 };
 561
 562 static struct clk dpll4_ck = {
 563         .name           = "dpll4_ck",
 564         .ops            = &clkops_noncore_dpll_ops,
 565         .parent         = &sys_ck,
 566         .dpll_data      = &dpll4_dd,
 567         .round_rate     = &omap2_dpll_round_rate,
 568         .set_rate       = &omap3_dpll4_set_rate,
 569         .clkdm_name     = "dpll4_clkdm",
 570         .recalc         = &omap3_dpll_recalc,
 571 };
 572
 573 /*
 574  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 575  * DPLL isn't bypassed --
 576  * XXX does this serve any downstream clocks?
 577  */
 578 static struct clk dpll4_x2_ck = {
 579         .name           = "dpll4_x2_ck",
 580         .ops            = &clkops_null,
 581         .parent         = &dpll4_ck,
 582         .clkdm_name     = "dpll4_clkdm",
 583         .recalc         = &omap3_clkoutx2_recalc,
 584 };
 585
 586 static const struct clksel div16_dpll4_clksel[] = {
 587         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 588         { .parent = NULL }
 589 };
 590
 591 /* This virtual clock is the source for dpll4_m2x2_ck */
 592 static struct clk dpll4_m2_ck = {
 593         .name           = "dpll4_m2_ck",
 594         .ops            = &clkops_null,
 595         .parent         = &dpll4_ck,
 596         .init           = &omap2_init_clksel_parent,
 597         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 598         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 599         .clksel         = div16_dpll4_clksel,
 600         .clkdm_name     = "dpll4_clkdm",
 601         .recalc         = &omap2_clksel_recalc,
 602 };
 603
 604 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 605 static struct clk dpll4_m2x2_ck = {
 606         .name           = "dpll4_m2x2_ck",
 607         .ops            = &clkops_omap2_dflt_wait,
 608         .parent         = &dpll4_m2_ck,
 609         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 610         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 611         .flags          = INVERT_ENABLE,
 612         .clkdm_name     = "dpll4_clkdm",
 613         .recalc         = &omap3_clkoutx2_recalc,
 614 };
 615
 616 /*
 617  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 618  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 619  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 620  * CM_96K_(F)CLK.
 621  */
 622 static struct clk omap_96m_alwon_fck = {
 623         .name           = "omap_96m_alwon_fck",
 624         .ops            = &clkops_null,
 625         .parent         = &dpll4_m2x2_ck,
 626         .recalc         = &followparent_recalc,
 627 };
 628
 629 static struct clk cm_96m_fck = {
 630         .name           = "cm_96m_fck",
 631         .ops            = &clkops_null,
 632         .parent         = &omap_96m_alwon_fck,
 633         .recalc         = &followparent_recalc,
 634 };
 635
 636 static const struct clksel_rate omap_96m_dpll_rates[] = {
 637         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 638         { .div = 0 }
 639 };
 640
 641 static const struct clksel_rate omap_96m_sys_rates[] = {
 642         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 643         { .div = 0 }
 644 };
 645
 646 static const struct clksel omap_96m_fck_clksel[] = {
 647         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 648         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 649         { .parent = NULL }
 650 };
 651
 652 static struct clk omap_96m_fck = {
 653         .name           = "omap_96m_fck",
 654         .ops            = &clkops_null,
 655         .parent         = &sys_ck,
 656         .init           = &omap2_init_clksel_parent,
 657         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 658         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 659         .clksel         = omap_96m_fck_clksel,
 660         .recalc         = &omap2_clksel_recalc,
 661 };
 662
 663 /* This virtual clock is the source for dpll4_m3x2_ck */
 664 static struct clk dpll4_m3_ck = {
 665         .name           = "dpll4_m3_ck",
 666         .ops            = &clkops_null,
 667         .parent         = &dpll4_ck,
 668         .init           = &omap2_init_clksel_parent,
 669         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 670         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 671         .clksel         = div16_dpll4_clksel,
 672         .clkdm_name     = "dpll4_clkdm",
 673         .recalc         = &omap2_clksel_recalc,
 674 };
 675
 676 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 677 static struct clk dpll4_m3x2_ck = {
 678         .name           = "dpll4_m3x2_ck",
 679         .ops            = &clkops_omap2_dflt_wait,
 680         .parent         = &dpll4_m3_ck,
 681         .init           = &omap2_init_clksel_parent,
 682         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 683         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 684         .flags          = INVERT_ENABLE,
 685         .clkdm_name     = "dpll4_clkdm",
 686         .recalc         = &omap3_clkoutx2_recalc,
 687 };
 688
 689 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 690         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 691         { .div = 0 }
 692 };
 693
 694 static const struct clksel_rate omap_54m_alt_rates[] = {
 695         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 696         { .div = 0 }
 697 };
 698
 699 static const struct clksel omap_54m_clksel[] = {
 700         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 701         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 702         { .parent = NULL }
 703 };
 704
 705 static struct clk omap_54m_fck = {
 706         .name           = "omap_54m_fck",
 707         .ops            = &clkops_null,
 708         .init           = &omap2_init_clksel_parent,
 709         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 710         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 711         .clksel         = omap_54m_clksel,
 712         .recalc         = &omap2_clksel_recalc,
 713 };
 714
 715 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 716         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 717         { .div = 0 }
 718 };
 719
 720 static const struct clksel_rate omap_48m_alt_rates[] = {
 721         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 722         { .div = 0 }
 723 };
 724
 725 static const struct clksel omap_48m_clksel[] = {
 726         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 727         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 728         { .parent = NULL }
 729 };
 730
 731 static struct clk omap_48m_fck = {
 732         .name           = "omap_48m_fck",
 733         .ops            = &clkops_null,
 734         .init           = &omap2_init_clksel_parent,
 735         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 736         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 737         .clksel         = omap_48m_clksel,
 738         .recalc         = &omap2_clksel_recalc,
 739 };
 740
 741 static struct clk omap_12m_fck = {
 742         .name           = "omap_12m_fck",
 743         .ops            = &clkops_null,
 744         .parent         = &omap_48m_fck,
 745         .fixed_div      = 4,
 746         .recalc         = &omap2_fixed_divisor_recalc,
 747 };
 748
 749 /* This virstual clock is the source for dpll4_m4x2_ck */
 750 static struct clk dpll4_m4_ck = {
 751         .name           = "dpll4_m4_ck",
 752         .ops            = &clkops_null,
 753         .parent         = &dpll4_ck,
 754         .init           = &omap2_init_clksel_parent,
 755         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 756         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 757         .clksel         = div16_dpll4_clksel,
 758         .clkdm_name     = "dpll4_clkdm",
 759         .recalc         = &omap2_clksel_recalc,
 760         .set_rate       = &omap2_clksel_set_rate,
 761         .round_rate     = &omap2_clksel_round_rate,
 762 };
 763
 764 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 765 static struct clk dpll4_m4x2_ck = {
 766         .name           = "dpll4_m4x2_ck",
 767         .ops            = &clkops_omap2_dflt_wait,
 768         .parent         = &dpll4_m4_ck,
 769         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 770         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 771         .flags          = INVERT_ENABLE,
 772         .clkdm_name     = "dpll4_clkdm",
 773         .recalc         = &omap3_clkoutx2_recalc,
 774 };
 775
 776 /* This virtual clock is the source for dpll4_m5x2_ck */
 777 static struct clk dpll4_m5_ck = {
 778         .name           = "dpll4_m5_ck",
 779         .ops            = &clkops_null,
 780         .parent         = &dpll4_ck,
 781         .init           = &omap2_init_clksel_parent,
 782         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 783         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 784         .clksel         = div16_dpll4_clksel,
 785         .clkdm_name     = "dpll4_clkdm",
 786         .recalc         = &omap2_clksel_recalc,
 787 };
 788
 789 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 790 static struct clk dpll4_m5x2_ck = {
 791         .name           = "dpll4_m5x2_ck",
 792         .ops            = &clkops_omap2_dflt_wait,
 793         .parent         = &dpll4_m5_ck,
 794         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 795         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 796         .flags          = INVERT_ENABLE,
 797         .clkdm_name     = "dpll4_clkdm",
 798         .recalc         = &omap3_clkoutx2_recalc,
 799 };
 800
 801 /* This virtual clock is the source for dpll4_m6x2_ck */
 802 static struct clk dpll4_m6_ck = {
 803         .name           = "dpll4_m6_ck",
 804         .ops            = &clkops_null,
 805         .parent         = &dpll4_ck,
 806         .init           = &omap2_init_clksel_parent,
 807         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 808         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 809         .clksel         = div16_dpll4_clksel,
 810         .clkdm_name     = "dpll4_clkdm",
 811         .recalc         = &omap2_clksel_recalc,
 812 };
 813
 814 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 815 static struct clk dpll4_m6x2_ck = {
 816         .name           = "dpll4_m6x2_ck",
 817         .ops            = &clkops_omap2_dflt_wait,
 818         .parent         = &dpll4_m6_ck,
 819         .init           = &omap2_init_clksel_parent,
 820         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 821         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 822         .flags          = INVERT_ENABLE,
 823         .clkdm_name     = "dpll4_clkdm",
 824         .recalc         = &omap3_clkoutx2_recalc,
 825 };
 826
 827 static struct clk emu_per_alwon_ck = {
 828         .name           = "emu_per_alwon_ck",
 829         .ops            = &clkops_null,
 830         .parent         = &dpll4_m6x2_ck,
 831         .clkdm_name     = "dpll4_clkdm",
 832         .recalc         = &followparent_recalc,
 833 };
 834
 835 /* DPLL5 */
 836 /* Supplies 120MHz clock, USIM source clock */
 837 /* Type: DPLL */
 838 /* 3430ES2 only */
 839 static struct dpll_data dpll5_dd = {
 840         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 841         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 842         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 843         .clk_bypass     = &sys_ck,
 844         .clk_ref        = &sys_ck,
 845         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 846         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 847         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 848         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 849         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 850         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 851         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 852         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 853         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 854         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 855         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 856         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 857         .min_divider    = 1,
 858         .max_divider    = OMAP3_MAX_DPLL_DIV,
 859         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 860 };
 861
 862 static struct clk dpll5_ck = {
 863         .name           = "dpll5_ck",
 864         .ops            = &clkops_noncore_dpll_ops,
 865         .parent         = &sys_ck,
 866         .dpll_data      = &dpll5_dd,
 867         .round_rate     = &omap2_dpll_round_rate,
 868         .set_rate       = &omap3_noncore_dpll_set_rate,
 869         .clkdm_name     = "dpll5_clkdm",
 870         .recalc         = &omap3_dpll_recalc,
 871 };
 872
 873 static const struct clksel div16_dpll5_clksel[] = {
 874         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 875         { .parent = NULL }
 876 };
 877
 878 static struct clk dpll5_m2_ck = {
 879         .name           = "dpll5_m2_ck",
 880         .ops            = &clkops_null,
 881         .parent         = &dpll5_ck,
 882         .init           = &omap2_init_clksel_parent,
 883         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 884         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 885         .clksel         = div16_dpll5_clksel,
 886         .clkdm_name     = "dpll5_clkdm",
 887         .recalc         = &omap2_clksel_recalc,
 888 };
 889
 890 /* CM EXTERNAL CLOCK OUTPUTS */
 891
 892 static const struct clksel_rate clkout2_src_core_rates[] = {
 893         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 894         { .div = 0 }
 895 };
 896
 897 static const struct clksel_rate clkout2_src_sys_rates[] = {
 898         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 899         { .div = 0 }
 900 };
 901
 902 static const struct clksel_rate clkout2_src_96m_rates[] = {
 903         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 904         { .div = 0 }
 905 };
 906
 907 static const struct clksel_rate clkout2_src_54m_rates[] = {
 908         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 909         { .div = 0 }
 910 };
 911
 912 static const struct clksel clkout2_src_clksel[] = {
 913         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 914         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 915         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 916         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 917         { .parent = NULL }
 918 };
 919
 920 static struct clk clkout2_src_ck = {
 921         .name           = "clkout2_src_ck",
 922         .ops            = &clkops_omap2_dflt,
 923         .init           = &omap2_init_clksel_parent,
 924         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 925         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 926         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 927         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 928         .clksel         = clkout2_src_clksel,
 929         .clkdm_name     = "core_clkdm",
 930         .recalc         = &omap2_clksel_recalc,
 931 };
 932
 933 static const struct clksel_rate sys_clkout2_rates[] = {
 934         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 935         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 936         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 937         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 938         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 939         { .div = 0 },
 940 };
 941
 942 static const struct clksel sys_clkout2_clksel[] = {
 943         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 944         { .parent = NULL },
 945 };
 946
 947 static struct clk sys_clkout2 = {
 948         .name           = "sys_clkout2",
 949         .ops            = &clkops_null,
 950         .init           = &omap2_init_clksel_parent,
 951         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 952         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 953         .clksel         = sys_clkout2_clksel,
 954         .recalc         = &omap2_clksel_recalc,
 955 };
 956
 957 /* CM OUTPUT CLOCKS */
 958
 959 static struct clk corex2_fck = {
 960         .name           = "corex2_fck",
 961         .ops            = &clkops_null,
 962         .parent         = &dpll3_m2x2_ck,
 963         .recalc         = &followparent_recalc,
 964 };
 965
 966 /* DPLL power domain clock controls */
 967
 968 static const struct clksel_rate div4_rates[] = {
 969         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 970         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 971         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 972         { .div = 0 }
 973 };
 974
 975 static const struct clksel div4_core_clksel[] = {
 976         { .parent = &core_ck, .rates = div4_rates },
 977         { .parent = NULL }
 978 };
 979
 980 /*
 981  * REVISIT: Are these in DPLL power domain or CM power domain? docs
 982  * may be inconsistent here?
 983  */
 984 static struct clk dpll1_fck = {
 985         .name           = "dpll1_fck",
 986         .ops            = &clkops_null,
 987         .parent         = &core_ck,
 988         .init           = &omap2_init_clksel_parent,
 989         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 990         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 991         .clksel         = div4_core_clksel,
 992         .recalc         = &omap2_clksel_recalc,
 993 };
 994
 995 static struct clk mpu_ck = {
 996         .name           = "mpu_ck",
 997         .ops            = &clkops_null,
 998         .parent         = &dpll1_x2m2_ck,
 999         .clkdm_name     = "mpu_clkdm",
1000         .recalc         = &followparent_recalc,
1001 };
1002
1003 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1004 static const struct clksel_rate arm_fck_rates[] = {
1005         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1006         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1007         { .div = 0 },
1008 };
1009
1010 static const struct clksel arm_fck_clksel[] = {
1011         { .parent = &mpu_ck, .rates = arm_fck_rates },
1012         { .parent = NULL }
1013 };
1014
1015 static struct clk arm_fck = {
1016         .name           = "arm_fck",
1017         .ops            = &clkops_null,
1018         .parent         = &mpu_ck,
1019         .init           = &omap2_init_clksel_parent,
1020         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1021         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1022         .clksel         = arm_fck_clksel,
1023         .recalc         = &omap2_clksel_recalc,
1024 };
1025
1026 /* XXX What about neon_clkdm ? */
1027
1028 /*
1029  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1030  * although it is referenced - so this is a guess
1031  */
1032 static struct clk emu_mpu_alwon_ck = {
1033         .name           = "emu_mpu_alwon_ck",
1034         .ops            = &clkops_null,
1035         .parent         = &mpu_ck,
1036         .recalc         = &followparent_recalc,
1037 };
1038
1039 static struct clk dpll2_fck = {
1040         .name           = "dpll2_fck",
1041         .ops            = &clkops_null,
1042         .parent         = &core_ck,
1043         .init           = &omap2_init_clksel_parent,
1044         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1045         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1046         .clksel         = div4_core_clksel,
1047         .recalc         = &omap2_clksel_recalc,
1048 };
1049
1050 static struct clk iva2_ck = {
1051         .name           = "iva2_ck",
1052         .ops            = &clkops_omap2_dflt_wait,
1053         .parent         = &dpll2_m2_ck,
1054         .init           = &omap2_init_clksel_parent,
1055         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1056         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1057         .clkdm_name     = "iva2_clkdm",
1058         .recalc         = &followparent_recalc,
1059 };
1060
1061 /* Common interface clocks */
1062
1063 static const struct clksel div2_core_clksel[] = {
1064         { .parent = &core_ck, .rates = div2_rates },
1065         { .parent = NULL }
1066 };
1067
1068 static struct clk l3_ick = {
1069         .name           = "l3_ick",
1070         .ops            = &clkops_null,
1071         .parent         = &core_ck,
1072         .init           = &omap2_init_clksel_parent,
1073         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1074         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1075         .clksel         = div2_core_clksel,
1076         .clkdm_name     = "core_l3_clkdm",
1077         .recalc         = &omap2_clksel_recalc,
1078 };
1079
1080 static const struct clksel div2_l3_clksel[] = {
1081         { .parent = &l3_ick, .rates = div2_rates },
1082         { .parent = NULL }
1083 };
1084
1085 static struct clk l4_ick = {
1086         .name           = "l4_ick",
1087         .ops            = &clkops_null,
1088         .parent         = &l3_ick,
1089         .init           = &omap2_init_clksel_parent,
1090         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1091         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1092         .clksel         = div2_l3_clksel,
1093         .clkdm_name     = "core_l4_clkdm",
1094         .recalc         = &omap2_clksel_recalc,
1095
1096 };
1097
1098 static const struct clksel div2_l4_clksel[] = {
1099         { .parent = &l4_ick, .rates = div2_rates },
1100         { .parent = NULL }
1101 };
1102
1103 static struct clk rm_ick = {
1104         .name           = "rm_ick",
1105         .ops            = &clkops_null,
1106         .parent         = &l4_ick,
1107         .init           = &omap2_init_clksel_parent,
1108         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1109         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1110         .clksel         = div2_l4_clksel,
1111         .recalc         = &omap2_clksel_recalc,
1112 };
1113
1114 /* GFX power domain */
1115
1116 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1117
1118 static const struct clksel gfx_l3_clksel[] = {
1119         { .parent = &l3_ick, .rates = gfx_l3_rates },
1120         { .parent = NULL }
1121 };
1122
1123 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1124 static struct clk gfx_l3_ck = {
1125         .name           = "gfx_l3_ck",
1126         .ops            = &clkops_omap2_dflt_wait,
1127         .parent         = &l3_ick,
1128         .init           = &omap2_init_clksel_parent,
1129         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1130         .enable_bit     = OMAP_EN_GFX_SHIFT,
1131         .recalc         = &followparent_recalc,
1132 };
1133
1134 static struct clk gfx_l3_fck = {
1135         .name           = "gfx_l3_fck",
1136         .ops            = &clkops_null,
1137         .parent         = &gfx_l3_ck,
1138         .init           = &omap2_init_clksel_parent,
1139         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1140         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1141         .clksel         = gfx_l3_clksel,
1142         .clkdm_name     = "gfx_3430es1_clkdm",
1143         .recalc         = &omap2_clksel_recalc,
1144 };
1145
1146 static struct clk gfx_l3_ick = {
1147         .name           = "gfx_l3_ick",
1148         .ops            = &clkops_null,
1149         .parent         = &gfx_l3_ck,
1150         .clkdm_name     = "gfx_3430es1_clkdm",
1151         .recalc         = &followparent_recalc,
1152 };
1153
1154 static struct clk gfx_cg1_ck = {
1155         .name           = "gfx_cg1_ck",
1156         .ops            = &clkops_omap2_dflt_wait,
1157         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1158         .init           = &omap2_init_clk_clkdm,
1159         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1160         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1161         .clkdm_name     = "gfx_3430es1_clkdm",
1162         .recalc         = &followparent_recalc,
1163 };
1164
1165 static struct clk gfx_cg2_ck = {
1166         .name           = "gfx_cg2_ck",
1167         .ops            = &clkops_omap2_dflt_wait,
1168         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1169         .init           = &omap2_init_clk_clkdm,
1170         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1171         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1172         .clkdm_name     = "gfx_3430es1_clkdm",
1173         .recalc         = &followparent_recalc,
1174 };
1175
1176 /* SGX power domain - 3430ES2 only */
1177
1178 static const struct clksel_rate sgx_core_rates[] = {
1179         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1180         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1181         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1182         { .div = 0 },
1183 };
1184
1185 static const struct clksel_rate sgx_96m_rates[] = {
1186         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1187         { .div = 0 },
1188 };
1189
1190 static const struct clksel sgx_clksel[] = {
1191         { .parent = &core_ck,    .rates = sgx_core_rates },
1192         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1193         { .parent = NULL },
1194 };
1195
1196 static struct clk sgx_fck = {
1197         .name           = "sgx_fck",
1198         .ops            = &clkops_omap2_dflt_wait,
1199         .init           = &omap2_init_clksel_parent,
1200         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1201         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1202         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1203         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1204         .clksel         = sgx_clksel,
1205         .clkdm_name     = "sgx_clkdm",
1206         .recalc         = &omap2_clksel_recalc,
1207 };
1208
1209 static struct clk sgx_ick = {
1210         .name           = "sgx_ick",
1211         .ops            = &clkops_omap2_dflt_wait,
1212         .parent         = &l3_ick,
1213         .init           = &omap2_init_clk_clkdm,
1214         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1215         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1216         .clkdm_name     = "sgx_clkdm",
1217         .recalc         = &followparent_recalc,
1218 };
1219
1220 /* CORE power domain */
1221
1222 static struct clk d2d_26m_fck = {
1223         .name           = "d2d_26m_fck",
1224         .ops            = &clkops_omap2_dflt_wait,
1225         .parent         = &sys_ck,
1226         .init           = &omap2_init_clk_clkdm,
1227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1228         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1229         .clkdm_name     = "d2d_clkdm",
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static const struct clksel omap343x_gpt_clksel[] = {
1234         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1235         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1236         { .parent = NULL}
1237 };
1238
1239 static struct clk gpt10_fck = {
1240         .name           = "gpt10_fck",
1241         .ops            = &clkops_omap2_dflt_wait,
1242         .parent         = &sys_ck,
1243         .init           = &omap2_init_clksel_parent,
1244         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1245         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1246         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1247         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1248         .clksel         = omap343x_gpt_clksel,
1249         .clkdm_name     = "core_l4_clkdm",
1250         .recalc         = &omap2_clksel_recalc,
1251 };
1252
1253 static struct clk gpt11_fck = {
1254         .name           = "gpt11_fck",
1255         .ops            = &clkops_omap2_dflt_wait,
1256         .parent         = &sys_ck,
1257         .init           = &omap2_init_clksel_parent,
1258         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1259         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1260         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1261         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1262         .clksel         = omap343x_gpt_clksel,
1263         .clkdm_name     = "core_l4_clkdm",
1264         .recalc         = &omap2_clksel_recalc,
1265 };
1266
1267 static struct clk cpefuse_fck = {
1268         .name           = "cpefuse_fck",
1269         .ops            = &clkops_omap2_dflt,
1270         .parent         = &sys_ck,
1271         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1272         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1273         .recalc         = &followparent_recalc,
1274 };
1275
1276 static struct clk ts_fck = {
1277         .name           = "ts_fck",
1278         .ops            = &clkops_omap2_dflt,
1279         .parent         = &omap_32k_fck,
1280         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1281         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1282         .recalc         = &followparent_recalc,
1283 };
1284
1285 static struct clk usbtll_fck = {
1286         .name           = "usbtll_fck",
1287         .ops            = &clkops_omap2_dflt,
1288         .parent         = &dpll5_m2_ck,
1289         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1290         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1291         .recalc         = &followparent_recalc,
1292 };
1293
1294 /* CORE 96M FCLK-derived clocks */
1295
1296 static struct clk core_96m_fck = {
1297         .name           = "core_96m_fck",
1298         .ops            = &clkops_null,
1299         .parent         = &omap_96m_fck,
1300         .clkdm_name     = "core_l4_clkdm",
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static struct clk mmchs3_fck = {
1305         .name           = "mmchs_fck",
1306         .ops            = &clkops_omap2_dflt_wait,
1307         .id             = 2,
1308         .parent         = &core_96m_fck,
1309         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1310         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1311         .clkdm_name     = "core_l4_clkdm",
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 static struct clk mmchs2_fck = {
1316         .name           = "mmchs_fck",
1317         .ops            = &clkops_omap2_dflt_wait,
1318         .id             = 1,
1319         .parent         = &core_96m_fck,
1320         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1321         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1322         .clkdm_name     = "core_l4_clkdm",
1323         .recalc         = &followparent_recalc,
1324 };
1325
1326 static struct clk mspro_fck = {
1327         .name           = "mspro_fck",
1328         .ops            = &clkops_omap2_dflt_wait,
1329         .parent         = &core_96m_fck,
1330         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1331         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1332         .clkdm_name     = "core_l4_clkdm",
1333         .recalc         = &followparent_recalc,
1334 };
1335
1336 static struct clk mmchs1_fck = {
1337         .name           = "mmchs_fck",
1338         .ops            = &clkops_omap2_dflt_wait,
1339         .parent         = &core_96m_fck,
1340         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1341         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1342         .clkdm_name     = "core_l4_clkdm",
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 static struct clk i2c3_fck = {
1347         .name           = "i2c_fck",
1348         .ops            = &clkops_omap2_dflt_wait,
1349         .id             = 3,
1350         .parent         = &core_96m_fck,
1351         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1352         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1353         .clkdm_name     = "core_l4_clkdm",
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk i2c2_fck = {
1358         .name           = "i2c_fck",
1359         .ops            = &clkops_omap2_dflt_wait,
1360         .id             = 2,
1361         .parent         = &core_96m_fck,
1362         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1363         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1364         .clkdm_name     = "core_l4_clkdm",
1365         .recalc         = &followparent_recalc,
1366 };
1367
1368 static struct clk i2c1_fck = {
1369         .name           = "i2c_fck",
1370         .ops            = &clkops_omap2_dflt_wait,
1371         .id             = 1,
1372         .parent         = &core_96m_fck,
1373         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1374         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1375         .clkdm_name     = "core_l4_clkdm",
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 /*
1380  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1381  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1382  */
1383 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1384         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1385         { .div = 0 }
1386 };
1387
1388 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1389         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1390         { .div = 0 }
1391 };
1392
1393 static const struct clksel mcbsp_15_clksel[] = {
1394         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1395         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1396         { .parent = NULL }
1397 };
1398
1399 static struct clk mcbsp5_fck = {
1400         .name           = "mcbsp_fck",
1401         .ops            = &clkops_omap2_dflt_wait,
1402         .id             = 5,
1403         .init           = &omap2_init_clksel_parent,
1404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1406         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1407         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1408         .clksel         = mcbsp_15_clksel,
1409         .clkdm_name     = "core_l4_clkdm",
1410         .recalc         = &omap2_clksel_recalc,
1411 };
1412
1413 static struct clk mcbsp1_fck = {
1414         .name           = "mcbsp_fck",
1415         .ops            = &clkops_omap2_dflt_wait,
1416         .id             = 1,
1417         .init           = &omap2_init_clksel_parent,
1418         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1419         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1420         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1421         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1422         .clksel         = mcbsp_15_clksel,
1423         .clkdm_name     = "core_l4_clkdm",
1424         .recalc         = &omap2_clksel_recalc,
1425 };
1426
1427 /* CORE_48M_FCK-derived clocks */
1428
1429 static struct clk core_48m_fck = {
1430         .name           = "core_48m_fck",
1431         .ops            = &clkops_null,
1432         .parent         = &omap_48m_fck,
1433         .clkdm_name     = "core_l4_clkdm",
1434         .recalc         = &followparent_recalc,
1435 };
1436
1437 static struct clk mcspi4_fck = {
1438         .name           = "mcspi_fck",
1439         .ops            = &clkops_omap2_dflt_wait,
1440         .id             = 4,
1441         .parent         = &core_48m_fck,
1442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1444         .recalc         = &followparent_recalc,
1445 };
1446
1447 static struct clk mcspi3_fck = {
1448         .name           = "mcspi_fck",
1449         .ops            = &clkops_omap2_dflt_wait,
1450         .id             = 3,
1451         .parent         = &core_48m_fck,
1452         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1454         .recalc         = &followparent_recalc,
1455 };
1456
1457 static struct clk mcspi2_fck = {
1458         .name           = "mcspi_fck",
1459         .ops            = &clkops_omap2_dflt_wait,
1460         .id             = 2,
1461         .parent         = &core_48m_fck,
1462         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk mcspi1_fck = {
1468         .name           = "mcspi_fck",
1469         .ops            = &clkops_omap2_dflt_wait,
1470         .id             = 1,
1471         .parent         = &core_48m_fck,
1472         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1474         .recalc         = &followparent_recalc,
1475 };
1476
1477 static struct clk uart2_fck = {
1478         .name           = "uart2_fck",
1479         .ops            = &clkops_omap2_dflt_wait,
1480         .parent         = &core_48m_fck,
1481         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1482         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1483         .recalc         = &followparent_recalc,
1484 };
1485
1486 static struct clk uart1_fck = {
1487         .name           = "uart1_fck",
1488         .ops            = &clkops_omap2_dflt_wait,
1489         .parent         = &core_48m_fck,
1490         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1491         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1492         .recalc         = &followparent_recalc,
1493 };
1494
1495 static struct clk fshostusb_fck = {
1496         .name           = "fshostusb_fck",
1497         .ops            = &clkops_omap2_dflt_wait,
1498         .parent         = &core_48m_fck,
1499         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1500         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1501         .recalc         = &followparent_recalc,
1502 };
1503
1504 /* CORE_12M_FCK based clocks */
1505
1506 static struct clk core_12m_fck = {
1507         .name           = "core_12m_fck",
1508         .ops            = &clkops_null,
1509         .parent         = &omap_12m_fck,
1510         .clkdm_name     = "core_l4_clkdm",
1511         .recalc         = &followparent_recalc,
1512 };
1513
1514 static struct clk hdq_fck = {
1515         .name           = "hdq_fck",
1516         .ops            = &clkops_omap2_dflt_wait,
1517         .parent         = &core_12m_fck,
1518         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1519         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 /* DPLL3-derived clock */
1524
1525 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1526         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1527         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1528         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1529         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1530         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1531         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1532         { .div = 0 }
1533 };
1534
1535 static const struct clksel ssi_ssr_clksel[] = {
1536         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1537         { .parent = NULL }
1538 };
1539
1540 static struct clk ssi_ssr_fck = {
1541         .name           = "ssi_ssr_fck",
1542         .ops            = &clkops_omap2_dflt,
1543         .init           = &omap2_init_clksel_parent,
1544         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1545         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1546         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1547         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1548         .clksel         = ssi_ssr_clksel,
1549         .clkdm_name     = "core_l4_clkdm",
1550         .recalc         = &omap2_clksel_recalc,
1551 };
1552
1553 static struct clk ssi_sst_fck = {
1554         .name           = "ssi_sst_fck",
1555         .ops            = &clkops_null,
1556         .parent         = &ssi_ssr_fck,
1557         .fixed_div      = 2,
1558         .recalc         = &omap2_fixed_divisor_recalc,
1559 };
1560
1561
1562
1563 /* CORE_L3_ICK based clocks */
1564
1565 /*
1566  * XXX must add clk_enable/clk_disable for these if standard code won't
1567  * handle it
1568  */
1569 static struct clk core_l3_ick = {
1570         .name           = "core_l3_ick",
1571         .ops            = &clkops_null,
1572         .parent         = &l3_ick,
1573         .init           = &omap2_init_clk_clkdm,
1574         .clkdm_name     = "core_l3_clkdm",
1575         .recalc         = &followparent_recalc,
1576 };
1577
1578 static struct clk hsotgusb_ick = {
1579         .name           = "hsotgusb_ick",
1580         .ops            = &clkops_omap2_dflt_wait,
1581         .parent         = &core_l3_ick,
1582         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1583         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1584         .clkdm_name     = "core_l3_clkdm",
1585         .recalc         = &followparent_recalc,
1586 };
1587
1588 static struct clk sdrc_ick = {
1589         .name           = "sdrc_ick",
1590         .ops            = &clkops_omap2_dflt_wait,
1591         .parent         = &core_l3_ick,
1592         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1593         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1594         .flags          = ENABLE_ON_INIT,
1595         .clkdm_name     = "core_l3_clkdm",
1596         .recalc         = &followparent_recalc,
1597 };
1598
1599 static struct clk gpmc_fck = {
1600         .name           = "gpmc_fck",
1601         .ops            = &clkops_null,
1602         .parent         = &core_l3_ick,
1603         .flags          = ENABLE_ON_INIT, /* huh? */
1604         .clkdm_name     = "core_l3_clkdm",
1605         .recalc         = &followparent_recalc,
1606 };
1607
1608 /* SECURITY_L3_ICK based clocks */
1609
1610 static struct clk security_l3_ick = {
1611         .name           = "security_l3_ick",
1612         .ops            = &clkops_null,
1613         .parent         = &l3_ick,
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 static struct clk pka_ick = {
1618         .name           = "pka_ick",
1619         .ops            = &clkops_omap2_dflt_wait,
1620         .parent         = &security_l3_ick,
1621         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1622         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1623         .recalc         = &followparent_recalc,
1624 };
1625
1626 /* CORE_L4_ICK based clocks */
1627
1628 static struct clk core_l4_ick = {
1629         .name           = "core_l4_ick",
1630         .ops            = &clkops_null,
1631         .parent         = &l4_ick,
1632         .init           = &omap2_init_clk_clkdm,
1633         .clkdm_name     = "core_l4_clkdm",
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk usbtll_ick = {
1638         .name           = "usbtll_ick",
1639         .ops            = &clkops_omap2_dflt_wait,
1640         .parent         = &core_l4_ick,
1641         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1642         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1643         .clkdm_name     = "core_l4_clkdm",
1644         .recalc         = &followparent_recalc,
1645 };
1646
1647 static struct clk mmchs3_ick = {
1648         .name           = "mmchs_ick",
1649         .ops            = &clkops_omap2_dflt_wait,
1650         .id             = 2,
1651         .parent         = &core_l4_ick,
1652         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1653         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1654         .clkdm_name     = "core_l4_clkdm",
1655         .recalc         = &followparent_recalc,
1656 };
1657
1658 /* Intersystem Communication Registers - chassis mode only */
1659 static struct clk icr_ick = {
1660         .name           = "icr_ick",
1661         .ops            = &clkops_omap2_dflt_wait,
1662         .parent         = &core_l4_ick,
1663         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1664         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1665         .clkdm_name     = "core_l4_clkdm",
1666         .recalc         = &followparent_recalc,
1667 };
1668
1669 static struct clk aes2_ick = {
1670         .name           = "aes2_ick",
1671         .ops            = &clkops_omap2_dflt_wait,
1672         .parent         = &core_l4_ick,
1673         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1674         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1675         .clkdm_name     = "core_l4_clkdm",
1676         .recalc         = &followparent_recalc,
1677 };
1678
1679 static struct clk sha12_ick = {
1680         .name           = "sha12_ick",
1681         .ops            = &clkops_omap2_dflt_wait,
1682         .parent         = &core_l4_ick,
1683         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1684         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1685         .clkdm_name     = "core_l4_clkdm",
1686         .recalc         = &followparent_recalc,
1687 };
1688
1689 static struct clk des2_ick = {
1690         .name           = "des2_ick",
1691         .ops            = &clkops_omap2_dflt_wait,
1692         .parent         = &core_l4_ick,
1693         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1694         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1695         .clkdm_name     = "core_l4_clkdm",
1696         .recalc         = &followparent_recalc,
1697 };
1698
1699 static struct clk mmchs2_ick = {
1700         .name           = "mmchs_ick",
1701         .ops            = &clkops_omap2_dflt_wait,
1702         .id             = 1,
1703         .parent         = &core_l4_ick,
1704         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1705         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1706         .clkdm_name     = "core_l4_clkdm",
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 static struct clk mmchs1_ick = {
1711         .name           = "mmchs_ick",
1712         .ops            = &clkops_omap2_dflt_wait,
1713         .parent         = &core_l4_ick,
1714         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1715         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1716         .clkdm_name     = "core_l4_clkdm",
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 static struct clk mspro_ick = {
1721         .name           = "mspro_ick",
1722         .ops            = &clkops_omap2_dflt_wait,
1723         .parent         = &core_l4_ick,
1724         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1725         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1726         .clkdm_name     = "core_l4_clkdm",
1727         .recalc         = &followparent_recalc,
1728 };
1729
1730 static struct clk hdq_ick = {
1731         .name           = "hdq_ick",
1732         .ops            = &clkops_omap2_dflt_wait,
1733         .parent         = &core_l4_ick,
1734         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1735         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1736         .clkdm_name     = "core_l4_clkdm",
1737         .recalc         = &followparent_recalc,
1738 };
1739
1740 static struct clk mcspi4_ick = {
1741         .name           = "mcspi_ick",
1742         .ops            = &clkops_omap2_dflt_wait,
1743         .id             = 4,
1744         .parent         = &core_l4_ick,
1745         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1746         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1747         .clkdm_name     = "core_l4_clkdm",
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk mcspi3_ick = {
1752         .name           = "mcspi_ick",
1753         .ops            = &clkops_omap2_dflt_wait,
1754         .id             = 3,
1755         .parent         = &core_l4_ick,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1758         .clkdm_name     = "core_l4_clkdm",
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 static struct clk mcspi2_ick = {
1763         .name           = "mcspi_ick",
1764         .ops            = &clkops_omap2_dflt_wait,
1765         .id             = 2,
1766         .parent         = &core_l4_ick,
1767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1769         .clkdm_name     = "core_l4_clkdm",
1770         .recalc         = &followparent_recalc,
1771 };
1772
1773 static struct clk mcspi1_ick = {
1774         .name           = "mcspi_ick",
1775         .ops            = &clkops_omap2_dflt_wait,
1776         .id             = 1,
1777         .parent         = &core_l4_ick,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1780         .clkdm_name     = "core_l4_clkdm",
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk i2c3_ick = {
1785         .name           = "i2c_ick",
1786         .ops            = &clkops_omap2_dflt_wait,
1787         .id             = 3,
1788         .parent         = &core_l4_ick,
1789         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1791         .clkdm_name     = "core_l4_clkdm",
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk i2c2_ick = {
1796         .name           = "i2c_ick",
1797         .ops            = &clkops_omap2_dflt_wait,
1798         .id             = 2,
1799         .parent         = &core_l4_ick,
1800         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1802         .clkdm_name     = "core_l4_clkdm",
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk i2c1_ick = {
1807         .name           = "i2c_ick",
1808         .ops            = &clkops_omap2_dflt_wait,
1809         .id             = 1,
1810         .parent         = &core_l4_ick,
1811         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1812         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1813         .clkdm_name     = "core_l4_clkdm",
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk uart2_ick = {
1818         .name           = "uart2_ick",
1819         .ops            = &clkops_omap2_dflt_wait,
1820         .parent         = &core_l4_ick,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1822         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1823         .clkdm_name     = "core_l4_clkdm",
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 static struct clk uart1_ick = {
1828         .name           = "uart1_ick",
1829         .ops            = &clkops_omap2_dflt_wait,
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk gpt11_ick = {
1838         .name           = "gpt11_ick",
1839         .ops            = &clkops_omap2_dflt_wait,
1840         .parent         = &core_l4_ick,
1841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1843         .clkdm_name     = "core_l4_clkdm",
1844         .recalc         = &followparent_recalc,
1845 };
1846
1847 static struct clk gpt10_ick = {
1848         .name           = "gpt10_ick",
1849         .ops            = &clkops_omap2_dflt_wait,
1850         .parent         = &core_l4_ick,
1851         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1852         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1853         .clkdm_name     = "core_l4_clkdm",
1854         .recalc         = &followparent_recalc,
1855 };
1856
1857 static struct clk mcbsp5_ick = {
1858         .name           = "mcbsp_ick",
1859         .ops            = &clkops_omap2_dflt_wait,
1860         .id             = 5,
1861         .parent         = &core_l4_ick,
1862         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1864         .clkdm_name     = "core_l4_clkdm",
1865         .recalc         = &followparent_recalc,
1866 };
1867
1868 static struct clk mcbsp1_ick = {
1869         .name           = "mcbsp_ick",
1870         .ops            = &clkops_omap2_dflt_wait,
1871         .id             = 1,
1872         .parent         = &core_l4_ick,
1873         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1874         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1875         .clkdm_name     = "core_l4_clkdm",
1876         .recalc         = &followparent_recalc,
1877 };
1878
1879 static struct clk fac_ick = {
1880         .name           = "fac_ick",
1881         .ops            = &clkops_omap2_dflt_wait,
1882         .parent         = &core_l4_ick,
1883         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1884         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1885         .clkdm_name     = "core_l4_clkdm",
1886         .recalc         = &followparent_recalc,
1887 };
1888
1889 static struct clk mailboxes_ick = {
1890         .name           = "mailboxes_ick",
1891         .ops            = &clkops_omap2_dflt_wait,
1892         .parent         = &core_l4_ick,
1893         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1894         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1895         .clkdm_name     = "core_l4_clkdm",
1896         .recalc         = &followparent_recalc,
1897 };
1898
1899 static struct clk omapctrl_ick = {
1900         .name           = "omapctrl_ick",
1901         .ops            = &clkops_omap2_dflt_wait,
1902         .parent         = &core_l4_ick,
1903         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1904         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1905         .flags          = ENABLE_ON_INIT,
1906         .recalc         = &followparent_recalc,
1907 };
1908
1909 /* SSI_L4_ICK based clocks */
1910
1911 static struct clk ssi_l4_ick = {
1912         .name           = "ssi_l4_ick",
1913         .ops            = &clkops_null,
1914         .parent         = &l4_ick,
1915         .clkdm_name     = "core_l4_clkdm",
1916         .recalc         = &followparent_recalc,
1917 };
1918
1919 static struct clk ssi_ick = {
1920         .name           = "ssi_ick",
1921         .ops            = &clkops_omap2_dflt,
1922         .parent         = &ssi_l4_ick,
1923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1924         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1925         .clkdm_name     = "core_l4_clkdm",
1926         .recalc         = &followparent_recalc,
1927 };
1928
1929 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1930  * but l4_ick makes more sense to me */
1931
1932 static const struct clksel usb_l4_clksel[] = {
1933         { .parent = &l4_ick, .rates = div2_rates },
1934         { .parent = NULL },
1935 };
1936
1937 static struct clk usb_l4_ick = {
1938         .name           = "usb_l4_ick",
1939         .ops            = &clkops_omap2_dflt_wait,
1940         .parent         = &l4_ick,
1941         .init           = &omap2_init_clksel_parent,
1942         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1944         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1945         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1946         .clksel         = usb_l4_clksel,
1947         .recalc         = &omap2_clksel_recalc,
1948 };
1949
1950 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1951
1952 /* SECURITY_L4_ICK2 based clocks */
1953
1954 static struct clk security_l4_ick2 = {
1955         .name           = "security_l4_ick2",
1956         .ops            = &clkops_null,
1957         .parent         = &l4_ick,
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk aes1_ick = {
1962         .name           = "aes1_ick",
1963         .ops            = &clkops_omap2_dflt_wait,
1964         .parent         = &security_l4_ick2,
1965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1966         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk rng_ick = {
1971         .name           = "rng_ick",
1972         .ops            = &clkops_omap2_dflt_wait,
1973         .parent         = &security_l4_ick2,
1974         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1975         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk sha11_ick = {
1980         .name           = "sha11_ick",
1981         .ops            = &clkops_omap2_dflt_wait,
1982         .parent         = &security_l4_ick2,
1983         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1984         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk des1_ick = {
1989         .name           = "des1_ick",
1990         .ops            = &clkops_omap2_dflt_wait,
1991         .parent         = &security_l4_ick2,
1992         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1993         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 /* DSS */
1998 static struct clk dss1_alwon_fck = {
1999         .name           = "dss1_alwon_fck",
2000         .ops            = &clkops_omap2_dflt,
2001         .parent         = &dpll4_m4x2_ck,
2002         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2003         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2004         .clkdm_name     = "dss_clkdm",
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 static struct clk dss_tv_fck = {
2009         .name           = "dss_tv_fck",
2010         .ops            = &clkops_omap2_dflt,
2011         .parent         = &omap_54m_fck,
2012         .init           = &omap2_init_clk_clkdm,
2013         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2014         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2015         .clkdm_name     = "dss_clkdm",
2016         .recalc         = &followparent_recalc,
2017 };
2018
2019 static struct clk dss_96m_fck = {
2020         .name           = "dss_96m_fck",
2021         .ops            = &clkops_omap2_dflt,
2022         .parent         = &omap_96m_fck,
2023         .init           = &omap2_init_clk_clkdm,
2024         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2025         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2026         .clkdm_name     = "dss_clkdm",
2027         .recalc         = &followparent_recalc,
2028 };
2029
2030 static struct clk dss2_alwon_fck = {
2031         .name           = "dss2_alwon_fck",
2032         .ops            = &clkops_omap2_dflt,
2033         .parent         = &sys_ck,
2034         .init           = &omap2_init_clk_clkdm,
2035         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2036         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2037         .clkdm_name     = "dss_clkdm",
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 static struct clk dss_ick = {
2042         /* Handles both L3 and L4 clocks */
2043         .name           = "dss_ick",
2044         .ops            = &clkops_omap2_dflt,
2045         .parent         = &l4_ick,
2046         .init           = &omap2_init_clk_clkdm,
2047         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2048         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2049         .clkdm_name     = "dss_clkdm",
2050         .recalc         = &followparent_recalc,
2051 };
2052
2053 /* CAM */
2054
2055 static struct clk cam_mclk = {
2056         .name           = "cam_mclk",
2057         .ops            = &clkops_omap2_dflt,
2058         .parent         = &dpll4_m5x2_ck,
2059         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2060         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2061         .clkdm_name     = "cam_clkdm",
2062         .recalc         = &followparent_recalc,
2063 };
2064
2065 static struct clk cam_ick = {
2066         /* Handles both L3 and L4 clocks */
2067         .name           = "cam_ick",
2068         .ops            = &clkops_omap2_dflt,
2069         .parent         = &l4_ick,
2070         .init           = &omap2_init_clk_clkdm,
2071         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2072         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2073         .clkdm_name     = "cam_clkdm",
2074         .recalc         = &followparent_recalc,
2075 };
2076
2077 static struct clk csi2_96m_fck = {
2078         .name           = "csi2_96m_fck",
2079         .ops            = &clkops_omap2_dflt,
2080         .parent         = &core_96m_fck,
2081         .init           = &omap2_init_clk_clkdm,
2082         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2083         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2084         .clkdm_name     = "cam_clkdm",
2085         .recalc         = &followparent_recalc,
2086 };
2087
2088 /* USBHOST - 3430ES2 only */
2089
2090 static struct clk usbhost_120m_fck = {
2091         .name           = "usbhost_120m_fck",
2092         .ops            = &clkops_omap2_dflt_wait,
2093         .parent         = &dpll5_m2_ck,
2094         .init           = &omap2_init_clk_clkdm,
2095         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2096         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2097         .clkdm_name     = "usbhost_clkdm",
2098         .recalc         = &followparent_recalc,
2099 };
2100
2101 static struct clk usbhost_48m_fck = {
2102         .name           = "usbhost_48m_fck",
2103         .ops            = &clkops_omap2_dflt_wait,
2104         .parent         = &omap_48m_fck,
2105         .init           = &omap2_init_clk_clkdm,
2106         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2107         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2108         .clkdm_name     = "usbhost_clkdm",
2109         .recalc         = &followparent_recalc,
2110 };
2111
2112 static struct clk usbhost_ick = {
2113         /* Handles both L3 and L4 clocks */
2114         .name           = "usbhost_ick",
2115         .ops            = &clkops_omap2_dflt_wait,
2116         .parent         = &l4_ick,
2117         .init           = &omap2_init_clk_clkdm,
2118         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2119         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2120         .clkdm_name     = "usbhost_clkdm",
2121         .recalc         = &followparent_recalc,
2122 };
2123
2124 /* WKUP */
2125
2126 static const struct clksel_rate usim_96m_rates[] = {
2127         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2128         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2129         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2130         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2131         { .div = 0 },
2132 };
2133
2134 static const struct clksel_rate usim_120m_rates[] = {
2135         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2136         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2137         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2138         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2139         { .div = 0 },
2140 };
2141
2142 static const struct clksel usim_clksel[] = {
2143         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2144         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2145         { .parent = &sys_ck,            .rates = div2_rates },
2146         { .parent = NULL },
2147 };
2148
2149 /* 3430ES2 only */
2150 static struct clk usim_fck = {
2151         .name           = "usim_fck",
2152         .ops            = &clkops_omap2_dflt_wait,
2153         .init           = &omap2_init_clksel_parent,
2154         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2155         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2156         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2157         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2158         .clksel         = usim_clksel,
2159         .recalc         = &omap2_clksel_recalc,
2160 };
2161
2162 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2163 static struct clk gpt1_fck = {
2164         .name           = "gpt1_fck",
2165         .ops            = &clkops_omap2_dflt_wait,
2166         .init           = &omap2_init_clksel_parent,
2167         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2168         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2169         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2170         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2171         .clksel         = omap343x_gpt_clksel,
2172         .clkdm_name     = "wkup_clkdm",
2173         .recalc         = &omap2_clksel_recalc,
2174 };
2175
2176 static struct clk wkup_32k_fck = {
2177         .name           = "wkup_32k_fck",
2178         .ops            = &clkops_null,
2179         .init           = &omap2_init_clk_clkdm,
2180         .parent         = &omap_32k_fck,
2181         .clkdm_name     = "wkup_clkdm",
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk gpio1_dbck = {
2186         .name           = "gpio1_dbck",
2187         .ops            = &clkops_omap2_dflt,
2188         .parent         = &wkup_32k_fck,
2189         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2190         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2191         .clkdm_name     = "wkup_clkdm",
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk wdt2_fck = {
2196         .name           = "wdt2_fck",
2197         .ops            = &clkops_omap2_dflt_wait,
2198         .parent         = &wkup_32k_fck,
2199         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2200         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2201         .clkdm_name     = "wkup_clkdm",
2202         .recalc         = &followparent_recalc,
2203 };
2204
2205 static struct clk wkup_l4_ick = {
2206         .name           = "wkup_l4_ick",
2207         .ops            = &clkops_null,
2208         .parent         = &sys_ck,
2209         .clkdm_name     = "wkup_clkdm",
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 /* 3430ES2 only */
2214 /* Never specifically named in the TRM, so we have to infer a likely name */
2215 static struct clk usim_ick = {
2216         .name           = "usim_ick",
2217         .ops            = &clkops_omap2_dflt_wait,
2218         .parent         = &wkup_l4_ick,
2219         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2220         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2221         .clkdm_name     = "wkup_clkdm",
2222         .recalc         = &followparent_recalc,
2223 };
2224
2225 static struct clk wdt2_ick = {
2226         .name           = "wdt2_ick",
2227         .ops            = &clkops_omap2_dflt_wait,
2228         .parent         = &wkup_l4_ick,
2229         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2230         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2231         .clkdm_name     = "wkup_clkdm",
2232         .recalc         = &followparent_recalc,
2233 };
2234
2235 static struct clk wdt1_ick = {
2236         .name           = "wdt1_ick",
2237         .ops            = &clkops_omap2_dflt_wait,
2238         .parent         = &wkup_l4_ick,
2239         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2240         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2241         .clkdm_name     = "wkup_clkdm",
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk gpio1_ick = {
2246         .name           = "gpio1_ick",
2247         .ops            = &clkops_omap2_dflt_wait,
2248         .parent         = &wkup_l4_ick,
2249         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2250         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2251         .clkdm_name     = "wkup_clkdm",
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 static struct clk omap_32ksync_ick = {
2256         .name           = "omap_32ksync_ick",
2257         .ops            = &clkops_omap2_dflt_wait,
2258         .parent         = &wkup_l4_ick,
2259         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2260         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2261         .clkdm_name     = "wkup_clkdm",
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 /* XXX This clock no longer exists in 3430 TRM rev F */
2266 static struct clk gpt12_ick = {
2267         .name           = "gpt12_ick",
2268         .ops            = &clkops_omap2_dflt_wait,
2269         .parent         = &wkup_l4_ick,
2270         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2271         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2272         .clkdm_name     = "wkup_clkdm",
2273         .recalc         = &followparent_recalc,
2274 };
2275
2276 static struct clk gpt1_ick = {
2277         .name           = "gpt1_ick",
2278         .ops            = &clkops_omap2_dflt_wait,
2279         .parent         = &wkup_l4_ick,
2280         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2281         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2282         .clkdm_name     = "wkup_clkdm",
2283         .recalc         = &followparent_recalc,
2284 };
2285
2286
2287
2288 /* PER clock domain */
2289
2290 static struct clk per_96m_fck = {
2291         .name           = "per_96m_fck",
2292         .ops            = &clkops_null,
2293         .parent         = &omap_96m_alwon_fck,
2294         .init           = &omap2_init_clk_clkdm,
2295         .clkdm_name     = "per_clkdm",
2296         .recalc         = &followparent_recalc,
2297 };
2298
2299 static struct clk per_48m_fck = {
2300         .name           = "per_48m_fck",
2301         .ops            = &clkops_null,
2302         .parent         = &omap_48m_fck,
2303         .init           = &omap2_init_clk_clkdm,
2304         .clkdm_name     = "per_clkdm",
2305         .recalc         = &followparent_recalc,
2306 };
2307
2308 static struct clk uart3_fck = {
2309         .name           = "uart3_fck",
2310         .ops            = &clkops_omap2_dflt_wait,
2311         .parent         = &per_48m_fck,
2312         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2313         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2314         .clkdm_name     = "per_clkdm",
2315         .recalc         = &followparent_recalc,
2316 };
2317
2318 static struct clk gpt2_fck = {
2319         .name           = "gpt2_fck",
2320         .ops            = &clkops_omap2_dflt_wait,
2321         .init           = &omap2_init_clksel_parent,
2322         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2323         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2324         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2325         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2326         .clksel         = omap343x_gpt_clksel,
2327         .clkdm_name     = "per_clkdm",
2328         .recalc         = &omap2_clksel_recalc,
2329 };
2330
2331 static struct clk gpt3_fck = {
2332         .name           = "gpt3_fck",
2333         .ops            = &clkops_omap2_dflt_wait,
2334         .init           = &omap2_init_clksel_parent,
2335         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2336         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2337         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2338         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2339         .clksel         = omap343x_gpt_clksel,
2340         .clkdm_name     = "per_clkdm",
2341         .recalc         = &omap2_clksel_recalc,
2342 };
2343
2344 static struct clk gpt4_fck = {
2345         .name           = "gpt4_fck",
2346         .ops            = &clkops_omap2_dflt_wait,
2347         .init           = &omap2_init_clksel_parent,
2348         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2349         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2350         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2351         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2352         .clksel         = omap343x_gpt_clksel,
2353         .clkdm_name     = "per_clkdm",
2354         .recalc         = &omap2_clksel_recalc,
2355 };
2356
2357 static struct clk gpt5_fck = {
2358         .name           = "gpt5_fck",
2359         .ops            = &clkops_omap2_dflt_wait,
2360         .init           = &omap2_init_clksel_parent,
2361         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2362         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2363         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2364         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2365         .clksel         = omap343x_gpt_clksel,
2366         .clkdm_name     = "per_clkdm",
2367         .recalc         = &omap2_clksel_recalc,
2368 };
2369
2370 static struct clk gpt6_fck = {
2371         .name           = "gpt6_fck",
2372         .ops            = &clkops_omap2_dflt_wait,
2373         .init           = &omap2_init_clksel_parent,
2374         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2375         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2376         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2377         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2378         .clksel         = omap343x_gpt_clksel,
2379         .clkdm_name     = "per_clkdm",
2380         .recalc         = &omap2_clksel_recalc,
2381 };
2382
2383 static struct clk gpt7_fck = {
2384         .name           = "gpt7_fck",
2385         .ops            = &clkops_omap2_dflt_wait,
2386         .init           = &omap2_init_clksel_parent,
2387         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2388         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2389         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2390         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2391         .clksel         = omap343x_gpt_clksel,
2392         .clkdm_name     = "per_clkdm",
2393         .recalc         = &omap2_clksel_recalc,
2394 };
2395
2396 static struct clk gpt8_fck = {
2397         .name           = "gpt8_fck",
2398         .ops            = &clkops_omap2_dflt_wait,
2399         .init           = &omap2_init_clksel_parent,
2400         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2401         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2402         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2403         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2404         .clksel         = omap343x_gpt_clksel,
2405         .clkdm_name     = "per_clkdm",
2406         .recalc         = &omap2_clksel_recalc,
2407 };
2408
2409 static struct clk gpt9_fck = {
2410         .name           = "gpt9_fck",
2411         .ops            = &clkops_omap2_dflt_wait,
2412         .init           = &omap2_init_clksel_parent,
2413         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2414         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2415         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2416         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2417         .clksel         = omap343x_gpt_clksel,
2418         .clkdm_name     = "per_clkdm",
2419         .recalc         = &omap2_clksel_recalc,
2420 };
2421
2422 static struct clk per_32k_alwon_fck = {
2423         .name           = "per_32k_alwon_fck",
2424         .ops            = &clkops_null,
2425         .parent         = &omap_32k_fck,
2426         .clkdm_name     = "per_clkdm",
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk gpio6_dbck = {
2431         .name           = "gpio6_dbck",
2432         .ops            = &clkops_omap2_dflt,
2433         .parent         = &per_32k_alwon_fck,
2434         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2435         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2436         .clkdm_name     = "per_clkdm",
2437         .recalc         = &followparent_recalc,
2438 };
2439
2440 static struct clk gpio5_dbck = {
2441         .name           = "gpio5_dbck",
2442         .ops            = &clkops_omap2_dflt,
2443         .parent         = &per_32k_alwon_fck,
2444         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2445         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2446         .clkdm_name     = "per_clkdm",
2447         .recalc         = &followparent_recalc,
2448 };
2449
2450 static struct clk gpio4_dbck = {
2451         .name           = "gpio4_dbck",
2452         .ops            = &clkops_omap2_dflt,
2453         .parent         = &per_32k_alwon_fck,
2454         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2455         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2456         .clkdm_name     = "per_clkdm",
2457         .recalc         = &followparent_recalc,
2458 };
2459
2460 static struct clk gpio3_dbck = {
2461         .name           = "gpio3_dbck",
2462         .ops            = &clkops_omap2_dflt,
2463         .parent         = &per_32k_alwon_fck,
2464         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2465         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2466         .clkdm_name     = "per_clkdm",
2467         .recalc         = &followparent_recalc,
2468 };
2469
2470 static struct clk gpio2_dbck = {
2471         .name           = "gpio2_dbck",
2472         .ops            = &clkops_omap2_dflt,
2473         .parent         = &per_32k_alwon_fck,
2474         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2475         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2476         .clkdm_name     = "per_clkdm",
2477         .recalc         = &followparent_recalc,
2478 };
2479
2480 static struct clk wdt3_fck = {
2481         .name           = "wdt3_fck",
2482         .ops            = &clkops_omap2_dflt_wait,
2483         .parent         = &per_32k_alwon_fck,
2484         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2485         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2486         .clkdm_name     = "per_clkdm",
2487         .recalc         = &followparent_recalc,
2488 };
2489
2490 static struct clk per_l4_ick = {
2491         .name           = "per_l4_ick",
2492         .ops            = &clkops_null,
2493         .parent         = &l4_ick,
2494         .clkdm_name     = "per_clkdm",
2495         .recalc         = &followparent_recalc,
2496 };
2497
2498 static struct clk gpio6_ick = {
2499         .name           = "gpio6_ick",
2500         .ops            = &clkops_omap2_dflt_wait,
2501         .parent         = &per_l4_ick,
2502         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2503         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2504         .clkdm_name     = "per_clkdm",
2505         .recalc         = &followparent_recalc,
2506 };
2507
2508 static struct clk gpio5_ick = {
2509         .name           = "gpio5_ick",
2510         .ops            = &clkops_omap2_dflt_wait,
2511         .parent         = &per_l4_ick,
2512         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2513         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2514         .clkdm_name     = "per_clkdm",
2515         .recalc         = &followparent_recalc,
2516 };
2517
2518 static struct clk gpio4_ick = {
2519         .name           = "gpio4_ick",
2520         .ops            = &clkops_omap2_dflt_wait,
2521         .parent         = &per_l4_ick,
2522         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2523         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2524         .clkdm_name     = "per_clkdm",
2525         .recalc         = &followparent_recalc,
2526 };
2527
2528 static struct clk gpio3_ick = {
2529         .name           = "gpio3_ick",
2530         .ops            = &clkops_omap2_dflt_wait,
2531         .parent         = &per_l4_ick,
2532         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2533         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2534         .clkdm_name     = "per_clkdm",
2535         .recalc         = &followparent_recalc,
2536 };
2537
2538 static struct clk gpio2_ick = {
2539         .name           = "gpio2_ick",
2540         .ops            = &clkops_omap2_dflt_wait,
2541         .parent         = &per_l4_ick,
2542         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2543         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2544         .clkdm_name     = "per_clkdm",
2545         .recalc         = &followparent_recalc,
2546 };
2547
2548 static struct clk wdt3_ick = {
2549         .name           = "wdt3_ick",
2550         .ops            = &clkops_omap2_dflt_wait,
2551         .parent         = &per_l4_ick,
2552         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2553         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2554         .clkdm_name     = "per_clkdm",
2555         .recalc         = &followparent_recalc,
2556 };
2557
2558 static struct clk uart3_ick = {
2559         .name           = "uart3_ick",
2560         .ops            = &clkops_omap2_dflt_wait,
2561         .parent         = &per_l4_ick,
2562         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2563         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2564         .clkdm_name     = "per_clkdm",
2565         .recalc         = &followparent_recalc,
2566 };
2567
2568 static struct clk gpt9_ick = {
2569         .name           = "gpt9_ick",
2570         .ops            = &clkops_omap2_dflt_wait,
2571         .parent         = &per_l4_ick,
2572         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2573         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2574         .clkdm_name     = "per_clkdm",
2575         .recalc         = &followparent_recalc,
2576 };
2577
2578 static struct clk gpt8_ick = {
2579         .name           = "gpt8_ick",
2580         .ops            = &clkops_omap2_dflt_wait,
2581         .parent         = &per_l4_ick,
2582         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2583         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2584         .clkdm_name     = "per_clkdm",
2585         .recalc         = &followparent_recalc,
2586 };
2587
2588 static struct clk gpt7_ick = {
2589         .name           = "gpt7_ick",
2590         .ops            = &clkops_omap2_dflt_wait,
2591         .parent         = &per_l4_ick,
2592         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2593         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2594         .clkdm_name     = "per_clkdm",
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk gpt6_ick = {
2599         .name           = "gpt6_ick",
2600         .ops            = &clkops_omap2_dflt_wait,
2601         .parent         = &per_l4_ick,
2602         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2603         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2604         .clkdm_name     = "per_clkdm",
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk gpt5_ick = {
2609         .name           = "gpt5_ick",
2610         .ops            = &clkops_omap2_dflt_wait,
2611         .parent         = &per_l4_ick,
2612         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2613         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2614         .clkdm_name     = "per_clkdm",
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk gpt4_ick = {
2619         .name           = "gpt4_ick",
2620         .ops            = &clkops_omap2_dflt_wait,
2621         .parent         = &per_l4_ick,
2622         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2623         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2624         .clkdm_name     = "per_clkdm",
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk gpt3_ick = {
2629         .name           = "gpt3_ick",
2630         .ops            = &clkops_omap2_dflt_wait,
2631         .parent         = &per_l4_ick,
2632         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2633         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2634         .clkdm_name     = "per_clkdm",
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk gpt2_ick = {
2639         .name           = "gpt2_ick",
2640         .ops            = &clkops_omap2_dflt_wait,
2641         .parent         = &per_l4_ick,
2642         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2643         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2644         .clkdm_name     = "per_clkdm",
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static struct clk mcbsp2_ick = {
2649         .name           = "mcbsp_ick",
2650         .ops            = &clkops_omap2_dflt_wait,
2651         .id             = 2,
2652         .parent         = &per_l4_ick,
2653         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2654         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2655         .clkdm_name     = "per_clkdm",
2656         .recalc         = &followparent_recalc,
2657 };
2658
2659 static struct clk mcbsp3_ick = {
2660         .name           = "mcbsp_ick",
2661         .ops            = &clkops_omap2_dflt_wait,
2662         .id             = 3,
2663         .parent         = &per_l4_ick,
2664         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2665         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2666         .clkdm_name     = "per_clkdm",
2667         .recalc         = &followparent_recalc,
2668 };
2669
2670 static struct clk mcbsp4_ick = {
2671         .name           = "mcbsp_ick",
2672         .ops            = &clkops_omap2_dflt_wait,
2673         .id             = 4,
2674         .parent         = &per_l4_ick,
2675         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2676         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2677         .clkdm_name     = "per_clkdm",
2678         .recalc         = &followparent_recalc,
2679 };
2680
2681 static const struct clksel mcbsp_234_clksel[] = {
2682         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2683         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2684         { .parent = NULL }
2685 };
2686
2687 static struct clk mcbsp2_fck = {
2688         .name           = "mcbsp_fck",
2689         .ops            = &clkops_omap2_dflt_wait,
2690         .id             = 2,
2691         .init           = &omap2_init_clksel_parent,
2692         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2693         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2694         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2695         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2696         .clksel         = mcbsp_234_clksel,
2697         .clkdm_name     = "per_clkdm",
2698         .recalc         = &omap2_clksel_recalc,
2699 };
2700
2701 static struct clk mcbsp3_fck = {
2702         .name           = "mcbsp_fck",
2703         .ops            = &clkops_omap2_dflt_wait,
2704         .id             = 3,
2705         .init           = &omap2_init_clksel_parent,
2706         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2707         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2708         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2709         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2710         .clksel         = mcbsp_234_clksel,
2711         .clkdm_name     = "per_clkdm",
2712         .recalc         = &omap2_clksel_recalc,
2713 };
2714
2715 static struct clk mcbsp4_fck = {
2716         .name           = "mcbsp_fck",
2717         .ops            = &clkops_omap2_dflt_wait,
2718         .id             = 4,
2719         .init           = &omap2_init_clksel_parent,
2720         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2721         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2722         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2723         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2724         .clksel         = mcbsp_234_clksel,
2725         .clkdm_name     = "per_clkdm",
2726         .recalc         = &omap2_clksel_recalc,
2727 };
2728
2729 /* EMU clocks */
2730
2731 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2732
2733 static const struct clksel_rate emu_src_sys_rates[] = {
2734         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2735         { .div = 0 },
2736 };
2737
2738 static const struct clksel_rate emu_src_core_rates[] = {
2739         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2740         { .div = 0 },
2741 };
2742
2743 static const struct clksel_rate emu_src_per_rates[] = {
2744         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2745         { .div = 0 },
2746 };
2747
2748 static const struct clksel_rate emu_src_mpu_rates[] = {
2749         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2750         { .div = 0 },
2751 };
2752
2753 static const struct clksel emu_src_clksel[] = {
2754         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2755         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2756         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2757         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2758         { .parent = NULL },
2759 };
2760
2761 /*
2762  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2763  * to switch the source of some of the EMU clocks.
2764  * XXX Are there CLKEN bits for these EMU clks?
2765  */
2766 static struct clk emu_src_ck = {
2767         .name           = "emu_src_ck",
2768         .ops            = &clkops_null,
2769         .init           = &omap2_init_clksel_parent,
2770         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2771         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2772         .clksel         = emu_src_clksel,
2773         .clkdm_name     = "emu_clkdm",
2774         .recalc         = &omap2_clksel_recalc,
2775 };
2776
2777 static const struct clksel_rate pclk_emu_rates[] = {
2778         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2779         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2780         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2781         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2782         { .div = 0 },
2783 };
2784
2785 static const struct clksel pclk_emu_clksel[] = {
2786         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2787         { .parent = NULL },
2788 };
2789
2790 static struct clk pclk_fck = {
2791         .name           = "pclk_fck",
2792         .ops            = &clkops_null,
2793         .init           = &omap2_init_clksel_parent,
2794         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2795         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2796         .clksel         = pclk_emu_clksel,
2797         .clkdm_name     = "emu_clkdm",
2798         .recalc         = &omap2_clksel_recalc,
2799 };
2800
2801 static const struct clksel_rate pclkx2_emu_rates[] = {
2802         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2803         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2804         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2805         { .div = 0 },
2806 };
2807
2808 static const struct clksel pclkx2_emu_clksel[] = {
2809         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2810         { .parent = NULL },
2811 };
2812
2813 static struct clk pclkx2_fck = {
2814         .name           = "pclkx2_fck",
2815         .ops            = &clkops_null,
2816         .init           = &omap2_init_clksel_parent,
2817         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2818         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2819         .clksel         = pclkx2_emu_clksel,
2820         .clkdm_name     = "emu_clkdm",
2821         .recalc         = &omap2_clksel_recalc,
2822 };
2823
2824 static const struct clksel atclk_emu_clksel[] = {
2825         { .parent = &emu_src_ck, .rates = div2_rates },
2826         { .parent = NULL },
2827 };
2828
2829 static struct clk atclk_fck = {
2830         .name           = "atclk_fck",
2831         .ops            = &clkops_null,
2832         .init           = &omap2_init_clksel_parent,
2833         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2834         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2835         .clksel         = atclk_emu_clksel,
2836         .clkdm_name     = "emu_clkdm",
2837         .recalc         = &omap2_clksel_recalc,
2838 };
2839
2840 static struct clk traceclk_src_fck = {
2841         .name           = "traceclk_src_fck",
2842         .ops            = &clkops_null,
2843         .init           = &omap2_init_clksel_parent,
2844         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2845         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2846         .clksel         = emu_src_clksel,
2847         .clkdm_name     = "emu_clkdm",
2848         .recalc         = &omap2_clksel_recalc,
2849 };
2850
2851 static const struct clksel_rate traceclk_rates[] = {
2852         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2853         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2854         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2855         { .div = 0 },
2856 };
2857
2858 static const struct clksel traceclk_clksel[] = {
2859         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2860         { .parent = NULL },
2861 };
2862
2863 static struct clk traceclk_fck = {
2864         .name           = "traceclk_fck",
2865         .ops            = &clkops_null,
2866         .init           = &omap2_init_clksel_parent,
2867         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2868         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2869         .clksel         = traceclk_clksel,
2870         .clkdm_name     = "emu_clkdm",
2871         .recalc         = &omap2_clksel_recalc,
2872 };
2873
2874 /* SR clocks */
2875
2876 /* SmartReflex fclk (VDD1) */
2877 static struct clk sr1_fck = {
2878         .name           = "sr1_fck",
2879         .ops            = &clkops_omap2_dflt_wait,
2880         .parent         = &sys_ck,
2881         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2882         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2883         .recalc         = &followparent_recalc,
2884 };
2885
2886 /* SmartReflex fclk (VDD2) */
2887 static struct clk sr2_fck = {
2888         .name           = "sr2_fck",
2889         .ops            = &clkops_omap2_dflt_wait,
2890         .parent         = &sys_ck,
2891         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2892         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2893         .recalc         = &followparent_recalc,
2894 };
2895
2896 static struct clk sr_l4_ick = {
2897         .name           = "sr_l4_ick",
2898         .ops            = &clkops_null, /* RMK: missing? */
2899         .parent         = &l4_ick,
2900         .clkdm_name     = "core_l4_clkdm",
2901         .recalc         = &followparent_recalc,
2902 };
2903
2904 /* SECURE_32K_FCK clocks */
2905
2906 static struct clk gpt12_fck = {
2907         .name           = "gpt12_fck",
2908         .ops            = &clkops_null,
2909         .parent         = &secure_32k_fck,
2910         .recalc         = &followparent_recalc,
2911 };
2912
2913 static struct clk wdt1_fck = {
2914         .name           = "wdt1_fck",
2915         .ops            = &clkops_null,
2916         .parent         = &secure_32k_fck,
2917         .recalc         = &followparent_recalc,
2918 };
2919
2920 #endif