arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009 Texas Instruments, Inc.
   5  * Copyright (C) 2009 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/clk.h>
  25
  26 #include <plat/control.h>
  27 #include <plat/clkdev_omap.h>
  28
  29 #include "clock.h"
  30 #include "clock44xx.h"
  31 #include "cm.h"
  32 #include "cm-regbits-44xx.h"
  33 #include "prm.h"
  34 #include "prm-regbits-44xx.h"
  35
  36 /* Root clocks */
  37
  38 static struct clk extalt_clkin_ck = {
  39         .name           = "extalt_clkin_ck",
  40         .rate           = 59000000,
  41         .ops            = &clkops_null,
  42         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
  43 };
  44
  45 static struct clk pad_clks_ck = {
  46         .name           = "pad_clks_ck",
  47         .rate           = 12000000,
  48         .ops            = &clkops_null,
  49         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
  50 };
  51
  52 static struct clk pad_slimbus_core_clks_ck = {
  53         .name           = "pad_slimbus_core_clks_ck",
  54         .rate           = 12000000,
  55         .ops            = &clkops_null,
  56         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
  57 };
  58
  59 static struct clk secure_32k_clk_src_ck = {
  60         .name           = "secure_32k_clk_src_ck",
  61         .rate           = 32768,
  62         .ops            = &clkops_null,
  63         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
  64 };
  65
  66 static struct clk slimbus_clk = {
  67         .name           = "slimbus_clk",
  68         .rate           = 12000000,
  69         .ops            = &clkops_null,
  70         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
  71 };
  72
  73 static struct clk sys_32k_ck = {
  74         .name           = "sys_32k_ck",
  75         .rate           = 32768,
  76         .ops            = &clkops_null,
  77         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
  78 };
  79
  80 static struct clk virt_12000000_ck = {
  81         .name           = "virt_12000000_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 12000000,
  84 };
  85
  86 static struct clk virt_13000000_ck = {
  87         .name           = "virt_13000000_ck",
  88         .ops            = &clkops_null,
  89         .rate           = 13000000,
  90 };
  91
  92 static struct clk virt_16800000_ck = {
  93         .name           = "virt_16800000_ck",
  94         .ops            = &clkops_null,
  95         .rate           = 16800000,
  96 };
  97
  98 static struct clk virt_19200000_ck = {
  99         .name           = "virt_19200000_ck",
 100         .ops            = &clkops_null,
 101         .rate           = 19200000,
 102 };
 103
 104 static struct clk virt_26000000_ck = {
 105         .name           = "virt_26000000_ck",
 106         .ops            = &clkops_null,
 107         .rate           = 26000000,
 108 };
 109
 110 static struct clk virt_27000000_ck = {
 111         .name           = "virt_27000000_ck",
 112         .ops            = &clkops_null,
 113         .rate           = 27000000,
 114 };
 115
 116 static struct clk virt_38400000_ck = {
 117         .name           = "virt_38400000_ck",
 118         .ops            = &clkops_null,
 119         .rate           = 38400000,
 120 };
 121
 122 static const struct clksel_rate div_1_0_rates[] = {
 123         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 124         { .div = 0 },
 125 };
 126
 127 static const struct clksel_rate div_1_1_rates[] = {
 128         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 129         { .div = 0 },
 130 };
 131
 132 static const struct clksel_rate div_1_2_rates[] = {
 133         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 134         { .div = 0 },
 135 };
 136
 137 static const struct clksel_rate div_1_3_rates[] = {
 138         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 139         { .div = 0 },
 140 };
 141
 142 static const struct clksel_rate div_1_4_rates[] = {
 143         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 144         { .div = 0 },
 145 };
 146
 147 static const struct clksel_rate div_1_5_rates[] = {
 148         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 149         { .div = 0 },
 150 };
 151
 152 static const struct clksel_rate div_1_6_rates[] = {
 153         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 154         { .div = 0 },
 155 };
 156
 157 static const struct clksel_rate div_1_7_rates[] = {
 158         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 159         { .div = 0 },
 160 };
 161
 162 static const struct clksel sys_clkin_sel[] = {
 163         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 164         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 165         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 166         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 167         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 168         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 169         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 170         { .parent = NULL },
 171 };
 172
 173 static struct clk sys_clkin_ck = {
 174         .name           = "sys_clkin_ck",
 175         .rate           = 38400000,
 176         .clksel         = sys_clkin_sel,
 177         .init           = &omap2_init_clksel_parent,
 178         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 179         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 180         .ops            = &clkops_null,
 181         .recalc         = &omap2_clksel_recalc,
 182         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
 183 };
 184
 185 static struct clk utmi_phy_clkout_ck = {
 186         .name           = "utmi_phy_clkout_ck",
 187         .rate           = 12000000,
 188         .ops            = &clkops_null,
 189         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
 190 };
 191
 192 static struct clk xclk60mhsp1_ck = {
 193         .name           = "xclk60mhsp1_ck",
 194         .rate           = 12000000,
 195         .ops            = &clkops_null,
 196         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
 197 };
 198
 199 static struct clk xclk60mhsp2_ck = {
 200         .name           = "xclk60mhsp2_ck",
 201         .rate           = 12000000,
 202         .ops            = &clkops_null,
 203         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
 204 };
 205
 206 static struct clk xclk60motg_ck = {
 207         .name           = "xclk60motg_ck",
 208         .rate           = 60000000,
 209         .ops            = &clkops_null,
 210         .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
 211 };
 212
 213 /* Module clocks and DPLL outputs */
 214
 215 static const struct clksel_rate div2_1to2_rates[] = {
 216         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 217         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 218         { .div = 0 },
 219 };
 220
 221 static const struct clksel dpll_sys_ref_clk_div[] = {
 222         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
 223         { .parent = NULL },
 224 };
 225
 226 static struct clk dpll_sys_ref_clk = {
 227         .name           = "dpll_sys_ref_clk",
 228         .parent         = &sys_clkin_ck,
 229         .clksel         = dpll_sys_ref_clk_div,
 230         .clksel_reg     = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
 231         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 232         .ops            = &clkops_null,
 233         .recalc         = &omap2_clksel_recalc,
 234         .round_rate     = &omap2_clksel_round_rate,
 235         .set_rate       = &omap2_clksel_set_rate,
 236         .flags          = CLOCK_IN_OMAP4430,
 237 };
 238
 239 static const struct clksel abe_dpll_refclk_mux_sel[] = {
 240         { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
 241         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 242         { .parent = NULL },
 243 };
 244
 245 static struct clk abe_dpll_refclk_mux_ck = {
 246         .name           = "abe_dpll_refclk_mux_ck",
 247         .parent         = &dpll_sys_ref_clk,
 248         .clksel         = abe_dpll_refclk_mux_sel,
 249         .init           = &omap2_init_clksel_parent,
 250         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 251         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 252         .ops            = &clkops_null,
 253         .recalc         = &omap2_clksel_recalc,
 254         .flags          = CLOCK_IN_OMAP4430,
 255 };
 256
 257 /* DPLL_ABE */
 258 static struct dpll_data dpll_abe_dd = {
 259         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 260         .clk_bypass     = &sys_clkin_ck,
 261         .clk_ref        = &abe_dpll_refclk_mux_ck,
 262         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 263         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 264         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 265         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 266         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 267         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 268         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 269         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 270         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 271         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 272         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 273         .min_divider    = 1,
 274 };
 275
 276
 277 static struct clk dpll_abe_ck = {
 278         .name           = "dpll_abe_ck",
 279         .parent         = &abe_dpll_refclk_mux_ck,
 280         .dpll_data      = &dpll_abe_dd,
 281         .ops            = &clkops_noncore_dpll_ops,
 282         .recalc         = &omap3_dpll_recalc,
 283         .round_rate     = &omap2_dpll_round_rate,
 284         .set_rate       = &omap3_noncore_dpll_set_rate,
 285         .flags          = CLOCK_IN_OMAP4430,
 286 };
 287
 288 static struct clk dpll_abe_m2x2_ck = {
 289         .name           = "dpll_abe_m2x2_ck",
 290         .parent         = &dpll_abe_ck,
 291         .ops            = &clkops_null,
 292         .recalc         = &followparent_recalc,
 293         .flags          = CLOCK_IN_OMAP4430,
 294 };
 295
 296 static struct clk abe_24m_fclk = {
 297         .name           = "abe_24m_fclk",
 298         .parent         = &dpll_abe_m2x2_ck,
 299         .ops            = &clkops_null,
 300         .recalc         = &followparent_recalc,
 301         .flags          = CLOCK_IN_OMAP4430,
 302 };
 303
 304 static const struct clksel_rate div3_1to4_rates[] = {
 305         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 306         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 307         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 308         { .div = 0 },
 309 };
 310
 311 static const struct clksel abe_clk_div[] = {
 312         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 313         { .parent = NULL },
 314 };
 315
 316 static struct clk abe_clk = {
 317         .name           = "abe_clk",
 318         .parent         = &dpll_abe_m2x2_ck,
 319         .clksel         = abe_clk_div,
 320         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 321         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 322         .ops            = &clkops_null,
 323         .recalc         = &omap2_clksel_recalc,
 324         .round_rate     = &omap2_clksel_round_rate,
 325         .set_rate       = &omap2_clksel_set_rate,
 326         .flags          = CLOCK_IN_OMAP4430,
 327 };
 328
 329 static const struct clksel aess_fclk_div[] = {
 330         { .parent = &abe_clk, .rates = div2_1to2_rates },
 331         { .parent = NULL },
 332 };
 333
 334 static struct clk aess_fclk = {
 335         .name           = "aess_fclk",
 336         .parent         = &abe_clk,
 337         .clksel         = aess_fclk_div,
 338         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 339         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 340         .ops            = &clkops_null,
 341         .recalc         = &omap2_clksel_recalc,
 342         .round_rate     = &omap2_clksel_round_rate,
 343         .set_rate       = &omap2_clksel_set_rate,
 344         .flags          = CLOCK_IN_OMAP4430,
 345 };
 346
 347 static const struct clksel_rate div31_1to31_rates[] = {
 348         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 349         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 350         { .div = 3, .val = 2, .flags = RATE_IN_4430 },
 351         { .div = 4, .val = 3, .flags = RATE_IN_4430 },
 352         { .div = 5, .val = 4, .flags = RATE_IN_4430 },
 353         { .div = 6, .val = 5, .flags = RATE_IN_4430 },
 354         { .div = 7, .val = 6, .flags = RATE_IN_4430 },
 355         { .div = 8, .val = 7, .flags = RATE_IN_4430 },
 356         { .div = 9, .val = 8, .flags = RATE_IN_4430 },
 357         { .div = 10, .val = 9, .flags = RATE_IN_4430 },
 358         { .div = 11, .val = 10, .flags = RATE_IN_4430 },
 359         { .div = 12, .val = 11, .flags = RATE_IN_4430 },
 360         { .div = 13, .val = 12, .flags = RATE_IN_4430 },
 361         { .div = 14, .val = 13, .flags = RATE_IN_4430 },
 362         { .div = 15, .val = 14, .flags = RATE_IN_4430 },
 363         { .div = 16, .val = 15, .flags = RATE_IN_4430 },
 364         { .div = 17, .val = 16, .flags = RATE_IN_4430 },
 365         { .div = 18, .val = 17, .flags = RATE_IN_4430 },
 366         { .div = 19, .val = 18, .flags = RATE_IN_4430 },
 367         { .div = 20, .val = 19, .flags = RATE_IN_4430 },
 368         { .div = 21, .val = 20, .flags = RATE_IN_4430 },
 369         { .div = 22, .val = 21, .flags = RATE_IN_4430 },
 370         { .div = 23, .val = 22, .flags = RATE_IN_4430 },
 371         { .div = 24, .val = 23, .flags = RATE_IN_4430 },
 372         { .div = 25, .val = 24, .flags = RATE_IN_4430 },
 373         { .div = 26, .val = 25, .flags = RATE_IN_4430 },
 374         { .div = 27, .val = 26, .flags = RATE_IN_4430 },
 375         { .div = 28, .val = 27, .flags = RATE_IN_4430 },
 376         { .div = 29, .val = 28, .flags = RATE_IN_4430 },
 377         { .div = 30, .val = 29, .flags = RATE_IN_4430 },
 378         { .div = 31, .val = 30, .flags = RATE_IN_4430 },
 379         { .div = 0 },
 380 };
 381
 382 static const struct clksel dpll_abe_m3_div[] = {
 383         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 384         { .parent = NULL },
 385 };
 386
 387 static struct clk dpll_abe_m3_ck = {
 388         .name           = "dpll_abe_m3_ck",
 389         .parent         = &dpll_abe_ck,
 390         .clksel         = dpll_abe_m3_div,
 391         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 392         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 393         .ops            = &clkops_null,
 394         .recalc         = &omap2_clksel_recalc,
 395         .round_rate     = &omap2_clksel_round_rate,
 396         .set_rate       = &omap2_clksel_set_rate,
 397         .flags          = CLOCK_IN_OMAP4430,
 398 };
 399
 400 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 401         { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
 402         { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
 403         { .parent = NULL },
 404 };
 405
 406 static struct clk core_hsd_byp_clk_mux_ck = {
 407         .name           = "core_hsd_byp_clk_mux_ck",
 408         .parent         = &dpll_sys_ref_clk,
 409         .clksel         = core_hsd_byp_clk_mux_sel,
 410         .init           = &omap2_init_clksel_parent,
 411         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 412         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 413         .ops            = &clkops_null,
 414         .recalc         = &omap2_clksel_recalc,
 415         .flags          = CLOCK_IN_OMAP4430,
 416 };
 417
 418 /* DPLL_CORE */
 419 static struct dpll_data dpll_core_dd = {
 420         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 421         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 422         .clk_ref        = &dpll_sys_ref_clk,
 423         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 424         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 425         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 426         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 427         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 428         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 429         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 430         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 431         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 432         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 433         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 434         .min_divider    = 1,
 435 };
 436
 437
 438 static struct clk dpll_core_ck = {
 439         .name           = "dpll_core_ck",
 440         .parent         = &dpll_sys_ref_clk,
 441         .dpll_data      = &dpll_core_dd,
 442         .ops            = &clkops_null,
 443         .recalc         = &omap3_dpll_recalc,
 444         .flags          = CLOCK_IN_OMAP4430,
 445 };
 446
 447 static const struct clksel dpll_core_m6_div[] = {
 448         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 449         { .parent = NULL },
 450 };
 451
 452 static struct clk dpll_core_m6_ck = {
 453         .name           = "dpll_core_m6_ck",
 454         .parent         = &dpll_core_ck,
 455         .clksel         = dpll_core_m6_div,
 456         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 457         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 458         .ops            = &clkops_null,
 459         .recalc         = &omap2_clksel_recalc,
 460         .round_rate     = &omap2_clksel_round_rate,
 461         .set_rate       = &omap2_clksel_set_rate,
 462         .flags          = CLOCK_IN_OMAP4430,
 463 };
 464
 465 static const struct clksel dbgclk_mux_sel[] = {
 466         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 467         { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
 468         { .parent = NULL },
 469 };
 470
 471 static struct clk dbgclk_mux_ck = {
 472         .name           = "dbgclk_mux_ck",
 473         .parent         = &sys_clkin_ck,
 474         .ops            = &clkops_null,
 475         .recalc         = &followparent_recalc,
 476         .flags          = CLOCK_IN_OMAP4430,
 477 };
 478
 479 static struct clk dpll_core_m2_ck = {
 480         .name           = "dpll_core_m2_ck",
 481         .parent         = &dpll_core_ck,
 482         .clksel         = dpll_core_m6_div,
 483         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 484         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 485         .ops            = &clkops_null,
 486         .recalc         = &omap2_clksel_recalc,
 487         .round_rate     = &omap2_clksel_round_rate,
 488         .set_rate       = &omap2_clksel_set_rate,
 489         .flags          = CLOCK_IN_OMAP4430,
 490 };
 491
 492 static struct clk ddrphy_ck = {
 493         .name           = "ddrphy_ck",
 494         .parent         = &dpll_core_m2_ck,
 495         .ops            = &clkops_null,
 496         .recalc         = &followparent_recalc,
 497         .flags          = CLOCK_IN_OMAP4430,
 498 };
 499
 500 static struct clk dpll_core_m5_ck = {
 501         .name           = "dpll_core_m5_ck",
 502         .parent         = &dpll_core_ck,
 503         .clksel         = dpll_core_m6_div,
 504         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 505         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 506         .ops            = &clkops_null,
 507         .recalc         = &omap2_clksel_recalc,
 508         .round_rate     = &omap2_clksel_round_rate,
 509         .set_rate       = &omap2_clksel_set_rate,
 510         .flags          = CLOCK_IN_OMAP4430,
 511 };
 512
 513 static const struct clksel div_core_div[] = {
 514         { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
 515         { .parent = NULL },
 516 };
 517
 518 static struct clk div_core_ck = {
 519         .name           = "div_core_ck",
 520         .parent         = &dpll_core_m5_ck,
 521         .clksel         = div_core_div,
 522         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 523         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 524         .ops            = &clkops_null,
 525         .recalc         = &omap2_clksel_recalc,
 526         .round_rate     = &omap2_clksel_round_rate,
 527         .set_rate       = &omap2_clksel_set_rate,
 528         .flags          = CLOCK_IN_OMAP4430,
 529 };
 530
 531 static const struct clksel_rate div4_1to8_rates[] = {
 532         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 533         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 534         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 535         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 536         { .div = 0 },
 537 };
 538
 539 static const struct clksel div_iva_hs_clk_div[] = {
 540         { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
 541         { .parent = NULL },
 542 };
 543
 544 static struct clk div_iva_hs_clk = {
 545         .name           = "div_iva_hs_clk",
 546         .parent         = &dpll_core_m5_ck,
 547         .clksel         = div_iva_hs_clk_div,
 548         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 549         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 550         .ops            = &clkops_null,
 551         .recalc         = &omap2_clksel_recalc,
 552         .round_rate     = &omap2_clksel_round_rate,
 553         .set_rate       = &omap2_clksel_set_rate,
 554         .flags          = CLOCK_IN_OMAP4430,
 555 };
 556
 557 static struct clk div_mpu_hs_clk = {
 558         .name           = "div_mpu_hs_clk",
 559         .parent         = &dpll_core_m5_ck,
 560         .clksel         = div_iva_hs_clk_div,
 561         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 562         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 563         .ops            = &clkops_null,
 564         .recalc         = &omap2_clksel_recalc,
 565         .round_rate     = &omap2_clksel_round_rate,
 566         .set_rate       = &omap2_clksel_set_rate,
 567         .flags          = CLOCK_IN_OMAP4430,
 568 };
 569
 570 static struct clk dpll_core_m4_ck = {
 571         .name           = "dpll_core_m4_ck",
 572         .parent         = &dpll_core_ck,
 573         .clksel         = dpll_core_m6_div,
 574         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 575         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 576         .ops            = &clkops_null,
 577         .recalc         = &omap2_clksel_recalc,
 578         .round_rate     = &omap2_clksel_round_rate,
 579         .set_rate       = &omap2_clksel_set_rate,
 580         .flags          = CLOCK_IN_OMAP4430,
 581 };
 582
 583 static struct clk dll_clk_div_ck = {
 584         .name           = "dll_clk_div_ck",
 585         .parent         = &dpll_core_m4_ck,
 586         .ops            = &clkops_null,
 587         .recalc         = &followparent_recalc,
 588         .flags          = CLOCK_IN_OMAP4430,
 589 };
 590
 591 static struct clk dpll_abe_m2_ck = {
 592         .name           = "dpll_abe_m2_ck",
 593         .parent         = &dpll_abe_ck,
 594         .clksel         = dpll_abe_m3_div,
 595         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 596         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 597         .ops            = &clkops_null,
 598         .recalc         = &omap2_clksel_recalc,
 599         .round_rate     = &omap2_clksel_round_rate,
 600         .set_rate       = &omap2_clksel_set_rate,
 601         .flags          = CLOCK_IN_OMAP4430,
 602 };
 603
 604 static struct clk dpll_core_m3_ck = {
 605         .name           = "dpll_core_m3_ck",
 606         .parent         = &dpll_core_ck,
 607         .clksel         = dpll_core_m6_div,
 608         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 609         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 610         .ops            = &clkops_null,
 611         .recalc         = &omap2_clksel_recalc,
 612         .round_rate     = &omap2_clksel_round_rate,
 613         .set_rate       = &omap2_clksel_set_rate,
 614         .flags          = CLOCK_IN_OMAP4430,
 615 };
 616
 617 static struct clk dpll_core_m7_ck = {
 618         .name           = "dpll_core_m7_ck",
 619         .parent         = &dpll_core_ck,
 620         .clksel         = dpll_core_m6_div,
 621         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 622         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 623         .ops            = &clkops_null,
 624         .recalc         = &omap2_clksel_recalc,
 625         .round_rate     = &omap2_clksel_round_rate,
 626         .set_rate       = &omap2_clksel_set_rate,
 627         .flags          = CLOCK_IN_OMAP4430,
 628 };
 629
 630 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 631         { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
 632         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 633         { .parent = NULL },
 634 };
 635
 636 static struct clk iva_hsd_byp_clk_mux_ck = {
 637         .name           = "iva_hsd_byp_clk_mux_ck",
 638         .parent         = &dpll_sys_ref_clk,
 639         .ops            = &clkops_null,
 640         .recalc         = &followparent_recalc,
 641         .flags          = CLOCK_IN_OMAP4430,
 642 };
 643
 644 /* DPLL_IVA */
 645 static struct dpll_data dpll_iva_dd = {
 646         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 647         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 648         .clk_ref        = &dpll_sys_ref_clk,
 649         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 650         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 651         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 652         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 653         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 654         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 655         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 656         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 657         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 658         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 659         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 660         .min_divider    = 1,
 661 };
 662
 663
 664 static struct clk dpll_iva_ck = {
 665         .name           = "dpll_iva_ck",
 666         .parent         = &dpll_sys_ref_clk,
 667         .dpll_data      = &dpll_iva_dd,
 668         .ops            = &clkops_noncore_dpll_ops,
 669         .recalc         = &omap3_dpll_recalc,
 670         .round_rate     = &omap2_dpll_round_rate,
 671         .set_rate       = &omap3_noncore_dpll_set_rate,
 672         .flags          = CLOCK_IN_OMAP4430,
 673 };
 674
 675 static const struct clksel dpll_iva_m4_div[] = {
 676         { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
 677         { .parent = NULL },
 678 };
 679
 680 static struct clk dpll_iva_m4_ck = {
 681         .name           = "dpll_iva_m4_ck",
 682         .parent         = &dpll_iva_ck,
 683         .clksel         = dpll_iva_m4_div,
 684         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 685         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 686         .ops            = &clkops_null,
 687         .recalc         = &omap2_clksel_recalc,
 688         .round_rate     = &omap2_clksel_round_rate,
 689         .set_rate       = &omap2_clksel_set_rate,
 690         .flags          = CLOCK_IN_OMAP4430,
 691 };
 692
 693 static struct clk dpll_iva_m5_ck = {
 694         .name           = "dpll_iva_m5_ck",
 695         .parent         = &dpll_iva_ck,
 696         .clksel         = dpll_iva_m4_div,
 697         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 698         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 699         .ops            = &clkops_null,
 700         .recalc         = &omap2_clksel_recalc,
 701         .round_rate     = &omap2_clksel_round_rate,
 702         .set_rate       = &omap2_clksel_set_rate,
 703         .flags          = CLOCK_IN_OMAP4430,
 704 };
 705
 706 /* DPLL_MPU */
 707 static struct dpll_data dpll_mpu_dd = {
 708         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 709         .clk_bypass     = &div_mpu_hs_clk,
 710         .clk_ref        = &dpll_sys_ref_clk,
 711         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 712         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 713         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 714         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 715         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 716         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 717         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 718         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 719         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 720         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 721         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 722         .min_divider    = 1,
 723 };
 724
 725
 726 static struct clk dpll_mpu_ck = {
 727         .name           = "dpll_mpu_ck",
 728         .parent         = &dpll_sys_ref_clk,
 729         .dpll_data      = &dpll_mpu_dd,
 730         .ops            = &clkops_noncore_dpll_ops,
 731         .recalc         = &omap3_dpll_recalc,
 732         .round_rate     = &omap2_dpll_round_rate,
 733         .set_rate       = &omap3_noncore_dpll_set_rate,
 734         .flags          = CLOCK_IN_OMAP4430,
 735 };
 736
 737 static const struct clksel dpll_mpu_m2_div[] = {
 738         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 739         { .parent = NULL },
 740 };
 741
 742 static struct clk dpll_mpu_m2_ck = {
 743         .name           = "dpll_mpu_m2_ck",
 744         .parent         = &dpll_mpu_ck,
 745         .clksel         = dpll_mpu_m2_div,
 746         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 747         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 748         .ops            = &clkops_null,
 749         .recalc         = &omap2_clksel_recalc,
 750         .round_rate     = &omap2_clksel_round_rate,
 751         .set_rate       = &omap2_clksel_set_rate,
 752         .flags          = CLOCK_IN_OMAP4430,
 753 };
 754
 755 static struct clk per_hs_clk_div_ck = {
 756         .name           = "per_hs_clk_div_ck",
 757         .parent         = &dpll_abe_m3_ck,
 758         .ops            = &clkops_null,
 759         .recalc         = &followparent_recalc,
 760         .flags          = CLOCK_IN_OMAP4430,
 761 };
 762
 763 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 764         { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
 765         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 766         { .parent = NULL },
 767 };
 768
 769 static struct clk per_hsd_byp_clk_mux_ck = {
 770         .name           = "per_hsd_byp_clk_mux_ck",
 771         .parent         = &dpll_sys_ref_clk,
 772         .clksel         = per_hsd_byp_clk_mux_sel,
 773         .init           = &omap2_init_clksel_parent,
 774         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 775         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 776         .ops            = &clkops_null,
 777         .recalc         = &omap2_clksel_recalc,
 778         .flags          = CLOCK_IN_OMAP4430,
 779 };
 780
 781 /* DPLL_PER */
 782 static struct dpll_data dpll_per_dd = {
 783         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 784         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 785         .clk_ref        = &dpll_sys_ref_clk,
 786         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 787         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 788         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 789         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 790         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 791         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 792         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 793         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 794         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 795         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 796         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 797         .min_divider    = 1,
 798 };
 799
 800
 801 static struct clk dpll_per_ck = {
 802         .name           = "dpll_per_ck",
 803         .parent         = &dpll_sys_ref_clk,
 804         .dpll_data      = &dpll_per_dd,
 805         .ops            = &clkops_noncore_dpll_ops,
 806         .recalc         = &omap3_dpll_recalc,
 807         .round_rate     = &omap2_dpll_round_rate,
 808         .set_rate       = &omap3_noncore_dpll_set_rate,
 809         .flags          = CLOCK_IN_OMAP4430,
 810 };
 811
 812 static const struct clksel dpll_per_m2_div[] = {
 813         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 814         { .parent = NULL },
 815 };
 816
 817 static struct clk dpll_per_m2_ck = {
 818         .name           = "dpll_per_m2_ck",
 819         .parent         = &dpll_per_ck,
 820         .clksel         = dpll_per_m2_div,
 821         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 822         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 823         .ops            = &clkops_null,
 824         .recalc         = &omap2_clksel_recalc,
 825         .round_rate     = &omap2_clksel_round_rate,
 826         .set_rate       = &omap2_clksel_set_rate,
 827         .flags          = CLOCK_IN_OMAP4430,
 828 };
 829
 830 static struct clk dpll_per_m2x2_ck = {
 831         .name           = "dpll_per_m2x2_ck",
 832         .parent         = &dpll_per_ck,
 833         .ops            = &clkops_null,
 834         .recalc         = &followparent_recalc,
 835         .flags          = CLOCK_IN_OMAP4430,
 836 };
 837
 838 static struct clk dpll_per_m3_ck = {
 839         .name           = "dpll_per_m3_ck",
 840         .parent         = &dpll_per_ck,
 841         .clksel         = dpll_per_m2_div,
 842         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 843         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 844         .ops            = &clkops_null,
 845         .recalc         = &omap2_clksel_recalc,
 846         .round_rate     = &omap2_clksel_round_rate,
 847         .set_rate       = &omap2_clksel_set_rate,
 848         .flags          = CLOCK_IN_OMAP4430,
 849 };
 850
 851 static struct clk dpll_per_m4_ck = {
 852         .name           = "dpll_per_m4_ck",
 853         .parent         = &dpll_per_ck,
 854         .clksel         = dpll_per_m2_div,
 855         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 856         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 857         .ops            = &clkops_null,
 858         .recalc         = &omap2_clksel_recalc,
 859         .round_rate     = &omap2_clksel_round_rate,
 860         .set_rate       = &omap2_clksel_set_rate,
 861         .flags          = CLOCK_IN_OMAP4430,
 862 };
 863
 864 static struct clk dpll_per_m5_ck = {
 865         .name           = "dpll_per_m5_ck",
 866         .parent         = &dpll_per_ck,
 867         .clksel         = dpll_per_m2_div,
 868         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 869         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 870         .ops            = &clkops_null,
 871         .recalc         = &omap2_clksel_recalc,
 872         .round_rate     = &omap2_clksel_round_rate,
 873         .set_rate       = &omap2_clksel_set_rate,
 874         .flags          = CLOCK_IN_OMAP4430,
 875 };
 876
 877 static struct clk dpll_per_m6_ck = {
 878         .name           = "dpll_per_m6_ck",
 879         .parent         = &dpll_per_ck,
 880         .clksel         = dpll_per_m2_div,
 881         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 882         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 883         .ops            = &clkops_null,
 884         .recalc         = &omap2_clksel_recalc,
 885         .round_rate     = &omap2_clksel_round_rate,
 886         .set_rate       = &omap2_clksel_set_rate,
 887         .flags          = CLOCK_IN_OMAP4430,
 888 };
 889
 890 static struct clk dpll_per_m7_ck = {
 891         .name           = "dpll_per_m7_ck",
 892         .parent         = &dpll_per_ck,
 893         .clksel         = dpll_per_m2_div,
 894         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 895         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 896         .ops            = &clkops_null,
 897         .recalc         = &omap2_clksel_recalc,
 898         .round_rate     = &omap2_clksel_round_rate,
 899         .set_rate       = &omap2_clksel_set_rate,
 900         .flags          = CLOCK_IN_OMAP4430,
 901 };
 902
 903 /* DPLL_UNIPRO */
 904 static struct dpll_data dpll_unipro_dd = {
 905         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 906         .clk_bypass     = &dpll_sys_ref_clk,
 907         .clk_ref        = &dpll_sys_ref_clk,
 908         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 909         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 910         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 911         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 912         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 913         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 914         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 915         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 916         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 917         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 918         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 919         .min_divider    = 1,
 920 };
 921
 922
 923 static struct clk dpll_unipro_ck = {
 924         .name           = "dpll_unipro_ck",
 925         .parent         = &dpll_sys_ref_clk,
 926         .dpll_data      = &dpll_unipro_dd,
 927         .ops            = &clkops_noncore_dpll_ops,
 928         .recalc         = &omap3_dpll_recalc,
 929         .round_rate     = &omap2_dpll_round_rate,
 930         .set_rate       = &omap3_noncore_dpll_set_rate,
 931         .flags          = CLOCK_IN_OMAP4430,
 932 };
 933
 934 static const struct clksel dpll_unipro_m2x2_div[] = {
 935         { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
 936         { .parent = NULL },
 937 };
 938
 939 static struct clk dpll_unipro_m2x2_ck = {
 940         .name           = "dpll_unipro_m2x2_ck",
 941         .parent         = &dpll_unipro_ck,
 942         .clksel         = dpll_unipro_m2x2_div,
 943         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 944         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 945         .ops            = &clkops_null,
 946         .recalc         = &omap2_clksel_recalc,
 947         .round_rate     = &omap2_clksel_round_rate,
 948         .set_rate       = &omap2_clksel_set_rate,
 949         .flags          = CLOCK_IN_OMAP4430,
 950 };
 951
 952 static struct clk usb_hs_clk_div_ck = {
 953         .name           = "usb_hs_clk_div_ck",
 954         .parent         = &dpll_abe_m3_ck,
 955         .ops            = &clkops_null,
 956         .recalc         = &followparent_recalc,
 957         .flags          = CLOCK_IN_OMAP4430,
 958 };
 959
 960 /* DPLL_USB */
 961 static struct dpll_data dpll_usb_dd = {
 962         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 963         .clk_bypass     = &usb_hs_clk_div_ck,
 964         .clk_ref        = &dpll_sys_ref_clk,
 965         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 966         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 967         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 968         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 969         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 970         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 971         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 972         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 973         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 974         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 975         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 976         .min_divider    = 1,
 977 };
 978
 979
 980 static struct clk dpll_usb_ck = {
 981         .name           = "dpll_usb_ck",
 982         .parent         = &dpll_sys_ref_clk,
 983         .dpll_data      = &dpll_usb_dd,
 984         .ops            = &clkops_noncore_dpll_ops,
 985         .recalc         = &omap3_dpll_recalc,
 986         .round_rate     = &omap2_dpll_round_rate,
 987         .set_rate       = &omap3_noncore_dpll_set_rate,
 988         .flags          = CLOCK_IN_OMAP4430,
 989 };
 990
 991 static struct clk dpll_usb_clkdcoldo_ck = {
 992         .name           = "dpll_usb_clkdcoldo_ck",
 993         .parent         = &dpll_usb_ck,
 994         .ops            = &clkops_null,
 995         .recalc         = &followparent_recalc,
 996         .flags          = CLOCK_IN_OMAP4430,
 997 };
 998
 999 static const struct clksel dpll_usb_m2_div[] = {
1000         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1001         { .parent = NULL },
1002 };
1003
1004 static struct clk dpll_usb_m2_ck = {
1005         .name           = "dpll_usb_m2_ck",
1006         .parent         = &dpll_usb_ck,
1007         .clksel         = dpll_usb_m2_div,
1008         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1009         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1010         .ops            = &clkops_null,
1011         .recalc         = &omap2_clksel_recalc,
1012         .round_rate     = &omap2_clksel_round_rate,
1013         .set_rate       = &omap2_clksel_set_rate,
1014         .flags          = CLOCK_IN_OMAP4430,
1015 };
1016
1017 static const struct clksel ducati_clk_mux_sel[] = {
1018         { .parent = &div_core_ck, .rates = div_1_0_rates },
1019         { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
1020         { .parent = NULL },
1021 };
1022
1023 static struct clk ducati_clk_mux_ck = {
1024         .name           = "ducati_clk_mux_ck",
1025         .parent         = &div_core_ck,
1026         .clksel         = ducati_clk_mux_sel,
1027         .init           = &omap2_init_clksel_parent,
1028         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1029         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1030         .ops            = &clkops_null,
1031         .recalc         = &omap2_clksel_recalc,
1032         .flags          = CLOCK_IN_OMAP4430,
1033 };
1034
1035 static struct clk func_12m_fclk = {
1036         .name           = "func_12m_fclk",
1037         .parent         = &dpll_per_m2x2_ck,
1038         .ops            = &clkops_null,
1039         .recalc         = &followparent_recalc,
1040         .flags          = CLOCK_IN_OMAP4430,
1041 };
1042
1043 static struct clk func_24m_clk = {
1044         .name           = "func_24m_clk",
1045         .parent         = &dpll_per_m2_ck,
1046         .ops            = &clkops_null,
1047         .recalc         = &followparent_recalc,
1048         .flags          = CLOCK_IN_OMAP4430,
1049 };
1050
1051 static struct clk func_24mc_fclk = {
1052         .name           = "func_24mc_fclk",
1053         .parent         = &dpll_per_m2x2_ck,
1054         .ops            = &clkops_null,
1055         .recalc         = &followparent_recalc,
1056         .flags          = CLOCK_IN_OMAP4430,
1057 };
1058
1059 static const struct clksel_rate div2_4to8_rates[] = {
1060         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1061         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1062         { .div = 0 },
1063 };
1064
1065 static const struct clksel func_48m_fclk_div[] = {
1066         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1067         { .parent = NULL },
1068 };
1069
1070 static struct clk func_48m_fclk = {
1071         .name           = "func_48m_fclk",
1072         .parent         = &dpll_per_m2x2_ck,
1073         .clksel         = func_48m_fclk_div,
1074         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1075         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1076         .ops            = &clkops_null,
1077         .recalc         = &omap2_clksel_recalc,
1078         .round_rate     = &omap2_clksel_round_rate,
1079         .set_rate       = &omap2_clksel_set_rate,
1080         .flags          = CLOCK_IN_OMAP4430,
1081 };
1082
1083 static struct clk func_48mc_fclk = {
1084         .name           = "func_48mc_fclk",
1085         .parent         = &dpll_per_m2x2_ck,
1086         .ops            = &clkops_null,
1087         .recalc         = &followparent_recalc,
1088         .flags          = CLOCK_IN_OMAP4430,
1089 };
1090
1091 static const struct clksel_rate div2_2to4_rates[] = {
1092         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1093         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1094         { .div = 0 },
1095 };
1096
1097 static const struct clksel func_64m_fclk_div[] = {
1098         { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
1099         { .parent = NULL },
1100 };
1101
1102 static struct clk func_64m_fclk = {
1103         .name           = "func_64m_fclk",
1104         .parent         = &dpll_per_m4_ck,
1105         .clksel         = func_64m_fclk_div,
1106         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1107         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1108         .ops            = &clkops_null,
1109         .recalc         = &omap2_clksel_recalc,
1110         .round_rate     = &omap2_clksel_round_rate,
1111         .set_rate       = &omap2_clksel_set_rate,
1112         .flags          = CLOCK_IN_OMAP4430,
1113 };
1114
1115 static const struct clksel func_96m_fclk_div[] = {
1116         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1117         { .parent = NULL },
1118 };
1119
1120 static struct clk func_96m_fclk = {
1121         .name           = "func_96m_fclk",
1122         .parent         = &dpll_per_m2x2_ck,
1123         .clksel         = func_96m_fclk_div,
1124         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1125         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1126         .ops            = &clkops_null,
1127         .recalc         = &omap2_clksel_recalc,
1128         .round_rate     = &omap2_clksel_round_rate,
1129         .set_rate       = &omap2_clksel_set_rate,
1130         .flags          = CLOCK_IN_OMAP4430,
1131 };
1132
1133 static const struct clksel hsmmc6_fclk_sel[] = {
1134         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1135         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1136         { .parent = NULL },
1137 };
1138
1139 static struct clk hsmmc6_fclk = {
1140         .name           = "hsmmc6_fclk",
1141         .parent         = &func_64m_fclk,
1142         .ops            = &clkops_null,
1143         .recalc         = &followparent_recalc,
1144         .flags          = CLOCK_IN_OMAP4430,
1145 };
1146
1147 static const struct clksel_rate div2_1to8_rates[] = {
1148         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1149         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1150         { .div = 0 },
1151 };
1152
1153 static const struct clksel init_60m_fclk_div[] = {
1154         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1155         { .parent = NULL },
1156 };
1157
1158 static struct clk init_60m_fclk = {
1159         .name           = "init_60m_fclk",
1160         .parent         = &dpll_usb_m2_ck,
1161         .clksel         = init_60m_fclk_div,
1162         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1163         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1164         .ops            = &clkops_null,
1165         .recalc         = &omap2_clksel_recalc,
1166         .round_rate     = &omap2_clksel_round_rate,
1167         .set_rate       = &omap2_clksel_set_rate,
1168         .flags          = CLOCK_IN_OMAP4430,
1169 };
1170
1171 static const struct clksel l3_div_div[] = {
1172         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1173         { .parent = NULL },
1174 };
1175
1176 static struct clk l3_div_ck = {
1177         .name           = "l3_div_ck",
1178         .parent         = &div_core_ck,
1179         .clksel         = l3_div_div,
1180         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1181         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1182         .ops            = &clkops_null,
1183         .recalc         = &omap2_clksel_recalc,
1184         .round_rate     = &omap2_clksel_round_rate,
1185         .set_rate       = &omap2_clksel_set_rate,
1186         .flags          = CLOCK_IN_OMAP4430,
1187 };
1188
1189 static const struct clksel l4_div_div[] = {
1190         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1191         { .parent = NULL },
1192 };
1193
1194 static struct clk l4_div_ck = {
1195         .name           = "l4_div_ck",
1196         .parent         = &l3_div_ck,
1197         .clksel         = l4_div_div,
1198         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1199         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1200         .ops            = &clkops_null,
1201         .recalc         = &omap2_clksel_recalc,
1202         .round_rate     = &omap2_clksel_round_rate,
1203         .set_rate       = &omap2_clksel_set_rate,
1204         .flags          = CLOCK_IN_OMAP4430,
1205 };
1206
1207 static struct clk lp_clk_div_ck = {
1208         .name           = "lp_clk_div_ck",
1209         .parent         = &dpll_abe_m2x2_ck,
1210         .ops            = &clkops_null,
1211         .recalc         = &followparent_recalc,
1212         .flags          = CLOCK_IN_OMAP4430,
1213 };
1214
1215 static const struct clksel l4_wkup_clk_mux_sel[] = {
1216         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1217         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1218         { .parent = NULL },
1219 };
1220
1221 static struct clk l4_wkup_clk_mux_ck = {
1222         .name           = "l4_wkup_clk_mux_ck",
1223         .parent         = &sys_clkin_ck,
1224         .clksel         = l4_wkup_clk_mux_sel,
1225         .init           = &omap2_init_clksel_parent,
1226         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1227         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1228         .ops            = &clkops_null,
1229         .recalc         = &omap2_clksel_recalc,
1230         .flags          = CLOCK_IN_OMAP4430,
1231 };
1232
1233 static const struct clksel per_abe_nc_fclk_div[] = {
1234         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1235         { .parent = NULL },
1236 };
1237
1238 static struct clk per_abe_nc_fclk = {
1239         .name           = "per_abe_nc_fclk",
1240         .parent         = &dpll_abe_m2_ck,
1241         .clksel         = per_abe_nc_fclk_div,
1242         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1243         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1244         .ops            = &clkops_null,
1245         .recalc         = &omap2_clksel_recalc,
1246         .round_rate     = &omap2_clksel_round_rate,
1247         .set_rate       = &omap2_clksel_set_rate,
1248         .flags          = CLOCK_IN_OMAP4430,
1249 };
1250
1251 static const struct clksel mcasp2_fclk_sel[] = {
1252         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1253         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1254         { .parent = NULL },
1255 };
1256
1257 static struct clk mcasp2_fclk = {
1258         .name           = "mcasp2_fclk",
1259         .parent         = &func_96m_fclk,
1260         .ops            = &clkops_null,
1261         .recalc         = &followparent_recalc,
1262         .flags          = CLOCK_IN_OMAP4430,
1263 };
1264
1265 static struct clk mcasp3_fclk = {
1266         .name           = "mcasp3_fclk",
1267         .parent         = &func_96m_fclk,
1268         .ops            = &clkops_null,
1269         .recalc         = &followparent_recalc,
1270         .flags          = CLOCK_IN_OMAP4430,
1271 };
1272
1273 static struct clk ocp_abe_iclk = {
1274         .name           = "ocp_abe_iclk",
1275         .parent         = &aess_fclk,
1276         .ops            = &clkops_null,
1277         .recalc         = &followparent_recalc,
1278         .flags          = CLOCK_IN_OMAP4430,
1279 };
1280
1281 static struct clk per_abe_24m_fclk = {
1282         .name           = "per_abe_24m_fclk",
1283         .parent         = &dpll_abe_m2_ck,
1284         .ops            = &clkops_null,
1285         .recalc         = &followparent_recalc,
1286         .flags          = CLOCK_IN_OMAP4430,
1287 };
1288
1289 static const struct clksel pmd_stm_clock_mux_sel[] = {
1290         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1291         { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1292         { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
1293         { .parent = NULL },
1294 };
1295
1296 static struct clk pmd_stm_clock_mux_ck = {
1297         .name           = "pmd_stm_clock_mux_ck",
1298         .parent         = &sys_clkin_ck,
1299         .ops            = &clkops_null,
1300         .recalc         = &followparent_recalc,
1301         .flags          = CLOCK_IN_OMAP4430,
1302 };
1303
1304 static struct clk pmd_trace_clk_mux_ck = {
1305         .name           = "pmd_trace_clk_mux_ck",
1306         .parent         = &sys_clkin_ck,
1307         .ops            = &clkops_null,
1308         .recalc         = &followparent_recalc,
1309         .flags          = CLOCK_IN_OMAP4430,
1310 };
1311
1312 static struct clk syc_clk_div_ck = {
1313         .name           = "syc_clk_div_ck",
1314         .parent         = &sys_clkin_ck,
1315         .clksel         = dpll_sys_ref_clk_div,
1316         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1317         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1318         .ops            = &clkops_null,
1319         .recalc         = &omap2_clksel_recalc,
1320         .round_rate     = &omap2_clksel_round_rate,
1321         .set_rate       = &omap2_clksel_set_rate,
1322         .flags          = CLOCK_IN_OMAP4430,
1323 };
1324
1325 /* Leaf clocks controlled by modules */
1326
1327 static struct clk aes1_ck = {
1328         .name           = "aes1_ck",
1329         .ops            = &clkops_omap2_dflt,
1330         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1331         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1332         .clkdm_name     = "l4_secure_clkdm",
1333         .parent         = &l3_div_ck,
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk aes2_ck = {
1338         .name           = "aes2_ck",
1339         .ops            = &clkops_omap2_dflt,
1340         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1341         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1342         .clkdm_name     = "l4_secure_clkdm",
1343         .parent         = &l3_div_ck,
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static struct clk aess_ck = {
1348         .name           = "aess_ck",
1349         .ops            = &clkops_omap2_dflt,
1350         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1351         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1352         .clkdm_name     = "abe_clkdm",
1353         .parent         = &aess_fclk,
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk cust_efuse_ck = {
1358         .name           = "cust_efuse_ck",
1359         .ops            = &clkops_omap2_dflt,
1360         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1361         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1362         .clkdm_name     = "l4_cefuse_clkdm",
1363         .parent         = &sys_clkin_ck,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 static struct clk des3des_ck = {
1368         .name           = "des3des_ck",
1369         .ops            = &clkops_omap2_dflt,
1370         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1371         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1372         .clkdm_name     = "l4_secure_clkdm",
1373         .parent         = &l4_div_ck,
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 static const struct clksel dmic_sync_mux_sel[] = {
1378         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1379         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1380         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1381         { .parent = NULL },
1382 };
1383
1384 static struct clk dmic_sync_mux_ck = {
1385         .name           = "dmic_sync_mux_ck",
1386         .parent         = &abe_24m_fclk,
1387         .clksel         = dmic_sync_mux_sel,
1388         .init           = &omap2_init_clksel_parent,
1389         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1390         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1391         .ops            = &clkops_null,
1392         .recalc         = &omap2_clksel_recalc,
1393         .flags          = CLOCK_IN_OMAP4430,
1394 };
1395
1396 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1397         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1398         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1399         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1400         { .parent = NULL },
1401 };
1402
1403 /* Merged func_dmic_abe_gfclk into dmic_ck */
1404 static struct clk dmic_ck = {
1405         .name           = "dmic_ck",
1406         .parent         = &dmic_sync_mux_ck,
1407         .clksel         = func_dmic_abe_gfclk_sel,
1408         .init           = &omap2_init_clksel_parent,
1409         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1410         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1411         .ops            = &clkops_omap2_dflt,
1412         .recalc         = &omap2_clksel_recalc,
1413         .flags          = CLOCK_IN_OMAP4430,
1414         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1415         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1416         .clkdm_name     = "abe_clkdm",
1417 };
1418
1419 static struct clk dss_ck = {
1420         .name           = "dss_ck",
1421         .ops            = &clkops_omap2_dflt,
1422         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1423         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1424         .clkdm_name     = "l3_dss_clkdm",
1425         .parent         = &l3_div_ck,
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk ducati_ck = {
1430         .name           = "ducati_ck",
1431         .ops            = &clkops_omap2_dflt,
1432         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1433         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1434         .clkdm_name     = "ducati_clkdm",
1435         .parent         = &ducati_clk_mux_ck,
1436         .recalc         = &followparent_recalc,
1437 };
1438
1439 static struct clk emif1_ck = {
1440         .name           = "emif1_ck",
1441         .ops            = &clkops_omap2_dflt,
1442         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1443         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1444         .clkdm_name     = "l3_emif_clkdm",
1445         .parent         = &ddrphy_ck,
1446         .recalc         = &followparent_recalc,
1447 };
1448
1449 static struct clk emif2_ck = {
1450         .name           = "emif2_ck",
1451         .ops            = &clkops_omap2_dflt,
1452         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1453         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1454         .clkdm_name     = "l3_emif_clkdm",
1455         .parent         = &ddrphy_ck,
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 static const struct clksel fdif_fclk_div[] = {
1460         { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
1461         { .parent = NULL },
1462 };
1463
1464 /* Merged fdif_fclk into fdif_ck */
1465 static struct clk fdif_ck = {
1466         .name           = "fdif_ck",
1467         .parent         = &dpll_per_m4_ck,
1468         .clksel         = fdif_fclk_div,
1469         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1470         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1471         .ops            = &clkops_omap2_dflt,
1472         .recalc         = &omap2_clksel_recalc,
1473         .round_rate     = &omap2_clksel_round_rate,
1474         .set_rate       = &omap2_clksel_set_rate,
1475         .flags          = CLOCK_IN_OMAP4430,
1476         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1477         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1478         .clkdm_name     = "iss_clkdm",
1479 };
1480
1481 static const struct clksel per_sgx_fclk_div[] = {
1482         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1483         { .parent = NULL },
1484 };
1485
1486 static struct clk per_sgx_fclk = {
1487         .name           = "per_sgx_fclk",
1488         .parent         = &dpll_per_m2x2_ck,
1489         .clksel         = per_sgx_fclk_div,
1490         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1491         .clksel_mask    = OMAP4430_CLKSEL_PER_192M_MASK,
1492         .ops            = &clkops_null,
1493         .recalc         = &omap2_clksel_recalc,
1494         .round_rate     = &omap2_clksel_round_rate,
1495         .set_rate       = &omap2_clksel_set_rate,
1496         .flags          = CLOCK_IN_OMAP4430,
1497 };
1498
1499 static const struct clksel sgx_clk_mux_sel[] = {
1500         { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1501         { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1502         { .parent = NULL },
1503 };
1504
1505 /* Merged sgx_clk_mux into gfx_ck */
1506 static struct clk gfx_ck = {
1507         .name           = "gfx_ck",
1508         .parent         = &dpll_core_m7_ck,
1509         .clksel         = sgx_clk_mux_sel,
1510         .init           = &omap2_init_clksel_parent,
1511         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1512         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1513         .ops            = &clkops_omap2_dflt,
1514         .recalc         = &omap2_clksel_recalc,
1515         .flags          = CLOCK_IN_OMAP4430,
1516         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1517         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1518         .clkdm_name     = "l3_gfx_clkdm",
1519 };
1520
1521 static struct clk gpio1_ck = {
1522         .name           = "gpio1_ck",
1523         .ops            = &clkops_omap2_dflt,
1524         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1525         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1526         .clkdm_name     = "l4_wkup_clkdm",
1527         .parent         = &l4_wkup_clk_mux_ck,
1528         .recalc         = &followparent_recalc,
1529 };
1530
1531 static struct clk gpio2_ck = {
1532         .name           = "gpio2_ck",
1533         .ops            = &clkops_omap2_dflt,
1534         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1535         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1536         .clkdm_name     = "l4_per_clkdm",
1537         .parent         = &l4_div_ck,
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk gpio3_ck = {
1542         .name           = "gpio3_ck",
1543         .ops            = &clkops_omap2_dflt,
1544         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1545         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1546         .clkdm_name     = "l4_per_clkdm",
1547         .parent         = &l4_div_ck,
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk gpio4_ck = {
1552         .name           = "gpio4_ck",
1553         .ops            = &clkops_omap2_dflt,
1554         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1555         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1556         .clkdm_name     = "l4_per_clkdm",
1557         .parent         = &l4_div_ck,
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 static struct clk gpio5_ck = {
1562         .name           = "gpio5_ck",
1563         .ops            = &clkops_omap2_dflt,
1564         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1565         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1566         .clkdm_name     = "l4_per_clkdm",
1567         .parent         = &l4_div_ck,
1568         .recalc         = &followparent_recalc,
1569 };
1570
1571 static struct clk gpio6_ck = {
1572         .name           = "gpio6_ck",
1573         .ops            = &clkops_omap2_dflt,
1574         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1575         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1576         .clkdm_name     = "l4_per_clkdm",
1577         .parent         = &l4_div_ck,
1578         .recalc         = &followparent_recalc,
1579 };
1580
1581 static struct clk gpmc_ck = {
1582         .name           = "gpmc_ck",
1583         .ops            = &clkops_omap2_dflt,
1584         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1585         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1586         .clkdm_name     = "l3_2_clkdm",
1587         .parent         = &l3_div_ck,
1588         .recalc         = &followparent_recalc,
1589 };
1590
1591 static const struct clksel dmt1_clk_mux_sel[] = {
1592         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1593         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1594         { .parent = NULL },
1595 };
1596
1597 /* Merged dmt1_clk_mux into gptimer1_ck */
1598 static struct clk gptimer1_ck = {
1599         .name           = "gptimer1_ck",
1600         .parent         = &sys_clkin_ck,
1601         .clksel         = dmt1_clk_mux_sel,
1602         .init           = &omap2_init_clksel_parent,
1603         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1604         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1605         .ops            = &clkops_omap2_dflt,
1606         .recalc         = &omap2_clksel_recalc,
1607         .flags          = CLOCK_IN_OMAP4430,
1608         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1609         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1610         .clkdm_name     = "l4_wkup_clkdm",
1611 };
1612
1613 /* Merged cm2_dm10_mux into gptimer10_ck */
1614 static struct clk gptimer10_ck = {
1615         .name           = "gptimer10_ck",
1616         .parent         = &sys_clkin_ck,
1617         .clksel         = dmt1_clk_mux_sel,
1618         .init           = &omap2_init_clksel_parent,
1619         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1620         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1621         .ops            = &clkops_omap2_dflt,
1622         .recalc         = &omap2_clksel_recalc,
1623         .flags          = CLOCK_IN_OMAP4430,
1624         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1625         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1626         .clkdm_name     = "l4_per_clkdm",
1627 };
1628
1629 /* Merged cm2_dm11_mux into gptimer11_ck */
1630 static struct clk gptimer11_ck = {
1631         .name           = "gptimer11_ck",
1632         .parent         = &sys_clkin_ck,
1633         .clksel         = dmt1_clk_mux_sel,
1634         .init           = &omap2_init_clksel_parent,
1635         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1636         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1637         .ops            = &clkops_omap2_dflt,
1638         .recalc         = &omap2_clksel_recalc,
1639         .flags          = CLOCK_IN_OMAP4430,
1640         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1641         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1642         .clkdm_name     = "l4_per_clkdm",
1643 };
1644
1645 /* Merged cm2_dm2_mux into gptimer2_ck */
1646 static struct clk gptimer2_ck = {
1647         .name           = "gptimer2_ck",
1648         .parent         = &sys_clkin_ck,
1649         .clksel         = dmt1_clk_mux_sel,
1650         .init           = &omap2_init_clksel_parent,
1651         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1652         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1653         .ops            = &clkops_omap2_dflt,
1654         .recalc         = &omap2_clksel_recalc,
1655         .flags          = CLOCK_IN_OMAP4430,
1656         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1657         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1658         .clkdm_name     = "l4_per_clkdm",
1659 };
1660
1661 /* Merged cm2_dm3_mux into gptimer3_ck */
1662 static struct clk gptimer3_ck = {
1663         .name           = "gptimer3_ck",
1664         .parent         = &sys_clkin_ck,
1665         .clksel         = dmt1_clk_mux_sel,
1666         .init           = &omap2_init_clksel_parent,
1667         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1668         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1669         .ops            = &clkops_omap2_dflt,
1670         .recalc         = &omap2_clksel_recalc,
1671         .flags          = CLOCK_IN_OMAP4430,
1672         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1673         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1674         .clkdm_name     = "l4_per_clkdm",
1675 };
1676
1677 /* Merged cm2_dm4_mux into gptimer4_ck */
1678 static struct clk gptimer4_ck = {
1679         .name           = "gptimer4_ck",
1680         .parent         = &sys_clkin_ck,
1681         .clksel         = dmt1_clk_mux_sel,
1682         .init           = &omap2_init_clksel_parent,
1683         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1684         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1685         .ops            = &clkops_omap2_dflt,
1686         .recalc         = &omap2_clksel_recalc,
1687         .flags          = CLOCK_IN_OMAP4430,
1688         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1689         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1690         .clkdm_name     = "l4_per_clkdm",
1691 };
1692
1693 static const struct clksel timer5_sync_mux_sel[] = {
1694         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1695         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1696         { .parent = NULL },
1697 };
1698
1699 /* Merged timer5_sync_mux into gptimer5_ck */
1700 static struct clk gptimer5_ck = {
1701         .name           = "gptimer5_ck",
1702         .parent         = &syc_clk_div_ck,
1703         .clksel         = timer5_sync_mux_sel,
1704         .init           = &omap2_init_clksel_parent,
1705         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1706         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1707         .ops            = &clkops_omap2_dflt,
1708         .recalc         = &omap2_clksel_recalc,
1709         .flags          = CLOCK_IN_OMAP4430,
1710         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1711         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1712         .clkdm_name     = "abe_clkdm",
1713 };
1714
1715 /* Merged timer6_sync_mux into gptimer6_ck */
1716 static struct clk gptimer6_ck = {
1717         .name           = "gptimer6_ck",
1718         .parent         = &syc_clk_div_ck,
1719         .clksel         = timer5_sync_mux_sel,
1720         .init           = &omap2_init_clksel_parent,
1721         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1722         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1723         .ops            = &clkops_omap2_dflt,
1724         .recalc         = &omap2_clksel_recalc,
1725         .flags          = CLOCK_IN_OMAP4430,
1726         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1727         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1728         .clkdm_name     = "abe_clkdm",
1729 };
1730
1731 /* Merged timer7_sync_mux into gptimer7_ck */
1732 static struct clk gptimer7_ck = {
1733         .name           = "gptimer7_ck",
1734         .parent         = &syc_clk_div_ck,
1735         .clksel         = timer5_sync_mux_sel,
1736         .init           = &omap2_init_clksel_parent,
1737         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1738         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1739         .ops            = &clkops_omap2_dflt,
1740         .recalc         = &omap2_clksel_recalc,
1741         .flags          = CLOCK_IN_OMAP4430,
1742         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1743         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1744         .clkdm_name     = "abe_clkdm",
1745 };
1746
1747 /* Merged timer8_sync_mux into gptimer8_ck */
1748 static struct clk gptimer8_ck = {
1749         .name           = "gptimer8_ck",
1750         .parent         = &syc_clk_div_ck,
1751         .clksel         = timer5_sync_mux_sel,
1752         .init           = &omap2_init_clksel_parent,
1753         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1754         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1755         .ops            = &clkops_omap2_dflt,
1756         .recalc         = &omap2_clksel_recalc,
1757         .flags          = CLOCK_IN_OMAP4430,
1758         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1759         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1760         .clkdm_name     = "abe_clkdm",
1761 };
1762
1763 /* Merged cm2_dm9_mux into gptimer9_ck */
1764 static struct clk gptimer9_ck = {
1765         .name           = "gptimer9_ck",
1766         .parent         = &sys_clkin_ck,
1767         .clksel         = dmt1_clk_mux_sel,
1768         .init           = &omap2_init_clksel_parent,
1769         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1770         .clksel_mask    = OMAP4430_CLKSEL_MASK,
1771         .ops            = &clkops_omap2_dflt,
1772         .recalc         = &omap2_clksel_recalc,
1773         .flags          = CLOCK_IN_OMAP4430,
1774         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1775         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1776         .clkdm_name     = "l4_per_clkdm",
1777 };
1778
1779 static struct clk hdq1w_ck = {
1780         .name           = "hdq1w_ck",
1781         .ops            = &clkops_omap2_dflt,
1782         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1783         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1784         .clkdm_name     = "l4_per_clkdm",
1785         .parent         = &func_12m_fclk,
1786         .recalc         = &followparent_recalc,
1787 };
1788
1789 /* Merged hsi_fclk into hsi_ck */
1790 static struct clk hsi_ck = {
1791         .name           = "hsi_ck",
1792         .parent         = &dpll_per_m2x2_ck,
1793         .clksel         = per_sgx_fclk_div,
1794         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1795         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1796         .ops            = &clkops_omap2_dflt,
1797         .recalc         = &omap2_clksel_recalc,
1798         .round_rate     = &omap2_clksel_round_rate,
1799         .set_rate       = &omap2_clksel_set_rate,
1800         .flags          = CLOCK_IN_OMAP4430,
1801         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1802         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1803         .clkdm_name     = "l3_init_clkdm",
1804 };
1805
1806 static struct clk i2c1_ck = {
1807         .name           = "i2c1_ck",
1808         .ops            = &clkops_omap2_dflt,
1809         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1810         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1811         .clkdm_name     = "l4_per_clkdm",
1812         .parent         = &func_96m_fclk,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk i2c2_ck = {
1817         .name           = "i2c2_ck",
1818         .ops            = &clkops_omap2_dflt,
1819         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1820         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1821         .clkdm_name     = "l4_per_clkdm",
1822         .parent         = &func_96m_fclk,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk i2c3_ck = {
1827         .name           = "i2c3_ck",
1828         .ops            = &clkops_omap2_dflt,
1829         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1830         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1831         .clkdm_name     = "l4_per_clkdm",
1832         .parent         = &func_96m_fclk,
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 static struct clk i2c4_ck = {
1837         .name           = "i2c4_ck",
1838         .ops            = &clkops_omap2_dflt,
1839         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1840         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1841         .clkdm_name     = "l4_per_clkdm",
1842         .parent         = &func_96m_fclk,
1843         .recalc         = &followparent_recalc,
1844 };
1845
1846 static struct clk iss_ck = {
1847         .name           = "iss_ck",
1848         .ops            = &clkops_omap2_dflt,
1849         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1850         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1851         .clkdm_name     = "iss_clkdm",
1852         .parent         = &ducati_clk_mux_ck,
1853         .recalc         = &followparent_recalc,
1854 };
1855
1856 static struct clk ivahd_ck = {
1857         .name           = "ivahd_ck",
1858         .ops            = &clkops_omap2_dflt,
1859         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1860         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1861         .clkdm_name     = "ivahd_clkdm",
1862         .parent         = &dpll_iva_m5_ck,
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk keyboard_ck = {
1867         .name           = "keyboard_ck",
1868         .ops            = &clkops_omap2_dflt,
1869         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1870         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1871         .clkdm_name     = "l4_wkup_clkdm",
1872         .parent         = &sys_32k_ck,
1873         .recalc         = &followparent_recalc,
1874 };
1875
1876 static struct clk l3_instr_interconnect_ck = {
1877         .name           = "l3_instr_interconnect_ck",
1878         .ops            = &clkops_omap2_dflt,
1879         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1880         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1881         .clkdm_name     = "l3_instr_clkdm",
1882         .parent         = &l3_div_ck,
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk l3_interconnect_3_ck = {
1887         .name           = "l3_interconnect_3_ck",
1888         .ops            = &clkops_omap2_dflt,
1889         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1890         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1891         .clkdm_name     = "l3_instr_clkdm",
1892         .parent         = &l3_div_ck,
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mcasp_sync_mux_ck = {
1897         .name           = "mcasp_sync_mux_ck",
1898         .parent         = &abe_24m_fclk,
1899         .clksel         = dmic_sync_mux_sel,
1900         .init           = &omap2_init_clksel_parent,
1901         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1902         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1903         .ops            = &clkops_null,
1904         .recalc         = &omap2_clksel_recalc,
1905         .flags          = CLOCK_IN_OMAP4430,
1906 };
1907
1908 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1909         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1910         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1911         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1912         { .parent = NULL },
1913 };
1914
1915 /* Merged func_mcasp_abe_gfclk into mcasp_ck */
1916 static struct clk mcasp_ck = {
1917         .name           = "mcasp_ck",
1918         .parent         = &mcasp_sync_mux_ck,
1919         .clksel         = func_mcasp_abe_gfclk_sel,
1920         .init           = &omap2_init_clksel_parent,
1921         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1922         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1923         .ops            = &clkops_omap2_dflt,
1924         .recalc         = &omap2_clksel_recalc,
1925         .flags          = CLOCK_IN_OMAP4430,
1926         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1927         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1928         .clkdm_name     = "abe_clkdm",
1929 };
1930
1931 static struct clk mcbsp1_sync_mux_ck = {
1932         .name           = "mcbsp1_sync_mux_ck",
1933         .parent         = &abe_24m_fclk,
1934         .clksel         = dmic_sync_mux_sel,
1935         .init           = &omap2_init_clksel_parent,
1936         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1937         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1938         .ops            = &clkops_null,
1939         .recalc         = &omap2_clksel_recalc,
1940         .flags          = CLOCK_IN_OMAP4430,
1941 };
1942
1943 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1944         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1945         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1946         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1947         { .parent = NULL },
1948 };
1949
1950 /* Merged func_mcbsp1_gfclk into mcbsp1_ck */
1951 static struct clk mcbsp1_ck = {
1952         .name           = "mcbsp1_ck",
1953         .parent         = &mcbsp1_sync_mux_ck,
1954         .clksel         = func_mcbsp1_gfclk_sel,
1955         .init           = &omap2_init_clksel_parent,
1956         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1957         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1958         .ops            = &clkops_omap2_dflt,
1959         .recalc         = &omap2_clksel_recalc,
1960         .flags          = CLOCK_IN_OMAP4430,
1961         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1962         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1963         .clkdm_name     = "abe_clkdm",
1964 };
1965
1966 static struct clk mcbsp2_sync_mux_ck = {
1967         .name           = "mcbsp2_sync_mux_ck",
1968         .parent         = &abe_24m_fclk,
1969         .clksel         = dmic_sync_mux_sel,
1970         .init           = &omap2_init_clksel_parent,
1971         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1972         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1973         .ops            = &clkops_null,
1974         .recalc         = &omap2_clksel_recalc,
1975         .flags          = CLOCK_IN_OMAP4430,
1976 };
1977
1978 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1979         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1980         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1981         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1982         { .parent = NULL },
1983 };
1984
1985 /* Merged func_mcbsp2_gfclk into mcbsp2_ck */
1986 static struct clk mcbsp2_ck = {
1987         .name           = "mcbsp2_ck",
1988         .parent         = &mcbsp2_sync_mux_ck,
1989         .clksel         = func_mcbsp2_gfclk_sel,
1990         .init           = &omap2_init_clksel_parent,
1991         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1992         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1993         .ops            = &clkops_omap2_dflt,
1994         .recalc         = &omap2_clksel_recalc,
1995         .flags          = CLOCK_IN_OMAP4430,
1996         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1997         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1998         .clkdm_name     = "abe_clkdm",
1999 };
2000
2001 static struct clk mcbsp3_sync_mux_ck = {
2002         .name           = "mcbsp3_sync_mux_ck",
2003         .parent         = &abe_24m_fclk,
2004         .clksel         = dmic_sync_mux_sel,
2005         .init           = &omap2_init_clksel_parent,
2006         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2007         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2008         .ops            = &clkops_null,
2009         .recalc         = &omap2_clksel_recalc,
2010         .flags          = CLOCK_IN_OMAP4430,
2011 };
2012
2013 static const struct clksel func_mcbsp3_gfclk_sel[] = {
2014         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
2015         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2016         { .parent = &slimbus_clk, .rates = div_1_2_rates },
2017         { .parent = NULL },
2018 };
2019
2020 /* Merged func_mcbsp3_gfclk into mcbsp3_ck */
2021 static struct clk mcbsp3_ck = {
2022         .name           = "mcbsp3_ck",
2023         .parent         = &mcbsp3_sync_mux_ck,
2024         .clksel         = func_mcbsp3_gfclk_sel,
2025         .init           = &omap2_init_clksel_parent,
2026         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2027         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
2028         .ops            = &clkops_omap2_dflt,
2029         .recalc         = &omap2_clksel_recalc,
2030         .flags          = CLOCK_IN_OMAP4430,
2031         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2032         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2033         .clkdm_name     = "abe_clkdm",
2034 };
2035
2036 static struct clk mcbsp4_sync_mux_ck = {
2037         .name           = "mcbsp4_sync_mux_ck",
2038         .parent         = &func_96m_fclk,
2039         .clksel         = mcasp2_fclk_sel,
2040         .init           = &omap2_init_clksel_parent,
2041         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2042         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2043         .ops            = &clkops_null,
2044         .recalc         = &omap2_clksel_recalc,
2045         .flags          = CLOCK_IN_OMAP4430,
2046 };
2047
2048 static const struct clksel per_mcbsp4_gfclk_sel[] = {
2049         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
2050         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2051         { .parent = NULL },
2052 };
2053
2054 /* Merged per_mcbsp4_gfclk into mcbsp4_ck */
2055 static struct clk mcbsp4_ck = {
2056         .name           = "mcbsp4_ck",
2057         .parent         = &mcbsp4_sync_mux_ck,
2058         .clksel         = per_mcbsp4_gfclk_sel,
2059         .init           = &omap2_init_clksel_parent,
2060         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2061         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2062         .ops            = &clkops_omap2_dflt,
2063         .recalc         = &omap2_clksel_recalc,
2064         .flags          = CLOCK_IN_OMAP4430,
2065         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2066         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2067         .clkdm_name     = "l4_per_clkdm",
2068 };
2069
2070 static struct clk mcspi1_ck = {
2071         .name           = "mcspi1_ck",
2072         .ops            = &clkops_omap2_dflt,
2073         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2074         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2075         .clkdm_name     = "l4_per_clkdm",
2076         .parent         = &func_48m_fclk,
2077         .recalc         = &followparent_recalc,
2078 };
2079
2080 static struct clk mcspi2_ck = {
2081         .name           = "mcspi2_ck",
2082         .ops            = &clkops_omap2_dflt,
2083         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2084         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2085         .clkdm_name     = "l4_per_clkdm",
2086         .parent         = &func_48m_fclk,
2087         .recalc         = &followparent_recalc,
2088 };
2089
2090 static struct clk mcspi3_ck = {
2091         .name           = "mcspi3_ck",
2092         .ops            = &clkops_omap2_dflt,
2093         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2094         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2095         .clkdm_name     = "l4_per_clkdm",
2096         .parent         = &func_48m_fclk,
2097         .recalc         = &followparent_recalc,
2098 };
2099
2100 static struct clk mcspi4_ck = {
2101         .name           = "mcspi4_ck",
2102         .ops            = &clkops_omap2_dflt,
2103         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2104         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2105         .clkdm_name     = "l4_per_clkdm",
2106         .parent         = &func_48m_fclk,
2107         .recalc         = &followparent_recalc,
2108 };
2109
2110 /* Merged hsmmc1_fclk into mmc1_ck */
2111 static struct clk mmc1_ck = {
2112         .name           = "mmc1_ck",
2113         .parent         = &func_64m_fclk,
2114         .clksel         = hsmmc6_fclk_sel,
2115         .init           = &omap2_init_clksel_parent,
2116         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2117         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2118         .ops            = &clkops_omap2_dflt,
2119         .recalc         = &omap2_clksel_recalc,
2120         .flags          = CLOCK_IN_OMAP4430,
2121         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2122         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2123         .clkdm_name     = "l3_init_clkdm",
2124 };
2125
2126 /* Merged hsmmc2_fclk into mmc2_ck */
2127 static struct clk mmc2_ck = {
2128         .name           = "mmc2_ck",
2129         .parent         = &func_64m_fclk,
2130         .clksel         = hsmmc6_fclk_sel,
2131         .init           = &omap2_init_clksel_parent,
2132         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2133         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2134         .ops            = &clkops_omap2_dflt,
2135         .recalc         = &omap2_clksel_recalc,
2136         .flags          = CLOCK_IN_OMAP4430,
2137         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2138         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2139         .clkdm_name     = "l3_init_clkdm",
2140 };
2141
2142 static struct clk mmc3_ck = {
2143         .name           = "mmc3_ck",
2144         .ops            = &clkops_omap2_dflt,
2145         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2146         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2147         .clkdm_name     = "l4_per_clkdm",
2148         .parent         = &func_48m_fclk,
2149         .recalc         = &followparent_recalc,
2150 };
2151
2152 static struct clk mmc4_ck = {
2153         .name           = "mmc4_ck",
2154         .ops            = &clkops_omap2_dflt,
2155         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2156         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2157         .clkdm_name     = "l4_per_clkdm",
2158         .parent         = &func_48m_fclk,
2159         .recalc         = &followparent_recalc,
2160 };
2161
2162 static struct clk mmc5_ck = {
2163         .name           = "mmc5_ck",
2164         .ops            = &clkops_omap2_dflt,
2165         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2166         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2167         .clkdm_name     = "l4_per_clkdm",
2168         .parent         = &func_48m_fclk,
2169         .recalc         = &followparent_recalc,
2170 };
2171
2172 static struct clk ocp_wp1_ck = {
2173         .name           = "ocp_wp1_ck",
2174         .ops            = &clkops_omap2_dflt,
2175         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2176         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2177         .clkdm_name     = "l3_instr_clkdm",
2178         .parent         = &l3_div_ck,
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 static struct clk pdm_ck = {
2183         .name           = "pdm_ck",
2184         .ops            = &clkops_omap2_dflt,
2185         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2186         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2187         .clkdm_name     = "abe_clkdm",
2188         .parent         = &pad_clks_ck,
2189         .recalc         = &followparent_recalc,
2190 };
2191
2192 static struct clk pkaeip29_ck = {
2193         .name           = "pkaeip29_ck",
2194         .ops            = &clkops_omap2_dflt,
2195         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2196         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2197         .clkdm_name     = "l4_secure_clkdm",
2198         .parent         = &l4_div_ck,
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk rng_ck = {
2203         .name           = "rng_ck",
2204         .ops            = &clkops_omap2_dflt,
2205         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2206         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2207         .clkdm_name     = "l4_secure_clkdm",
2208         .parent         = &l4_div_ck,
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 static struct clk sha2md51_ck = {
2213         .name           = "sha2md51_ck",
2214         .ops            = &clkops_omap2_dflt,
2215         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2216         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2217         .clkdm_name     = "l4_secure_clkdm",
2218         .parent         = &l3_div_ck,
2219         .recalc         = &followparent_recalc,
2220 };
2221
2222 static struct clk sl2_ck = {
2223         .name           = "sl2_ck",
2224         .ops            = &clkops_omap2_dflt,
2225         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2226         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2227         .clkdm_name     = "ivahd_clkdm",
2228         .parent         = &dpll_iva_m5_ck,
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 static struct clk slimbus1_ck = {
2233         .name           = "slimbus1_ck",
2234         .ops            = &clkops_omap2_dflt,
2235         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2236         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2237         .clkdm_name     = "abe_clkdm",
2238         .parent         = &ocp_abe_iclk,
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 static struct clk slimbus2_ck = {
2243         .name           = "slimbus2_ck",
2244         .ops            = &clkops_omap2_dflt,
2245         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2246         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2247         .clkdm_name     = "l4_per_clkdm",
2248         .parent         = &l4_div_ck,
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk sr_core_ck = {
2253         .name           = "sr_core_ck",
2254         .ops            = &clkops_omap2_dflt,
2255         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2256         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2257         .clkdm_name     = "l4_ao_clkdm",
2258         .parent         = &l4_wkup_clk_mux_ck,
2259         .recalc         = &followparent_recalc,
2260 };
2261
2262 static struct clk sr_iva_ck = {
2263         .name           = "sr_iva_ck",
2264         .ops            = &clkops_omap2_dflt,
2265         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2266         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2267         .clkdm_name     = "l4_ao_clkdm",
2268         .parent         = &l4_wkup_clk_mux_ck,
2269         .recalc         = &followparent_recalc,
2270 };
2271
2272 static struct clk sr_mpu_ck = {
2273         .name           = "sr_mpu_ck",
2274         .ops            = &clkops_omap2_dflt,
2275         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2276         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2277         .clkdm_name     = "l4_ao_clkdm",
2278         .parent         = &l4_wkup_clk_mux_ck,
2279         .recalc         = &followparent_recalc,
2280 };
2281
2282 static struct clk tesla_ck = {
2283         .name           = "tesla_ck",
2284         .ops            = &clkops_omap2_dflt,
2285         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
2286         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2287         .clkdm_name     = "tesla_clkdm",
2288         .parent         = &dpll_iva_m4_ck,
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292 static struct clk uart1_ck = {
2293         .name           = "uart1_ck",
2294         .ops            = &clkops_omap2_dflt,
2295         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2296         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2297         .clkdm_name     = "l4_per_clkdm",
2298         .parent         = &func_48m_fclk,
2299         .recalc         = &followparent_recalc,
2300 };
2301
2302 static struct clk uart2_ck = {
2303         .name           = "uart2_ck",
2304         .ops            = &clkops_omap2_dflt,
2305         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2306         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2307         .clkdm_name     = "l4_per_clkdm",
2308         .parent         = &func_48m_fclk,
2309         .recalc         = &followparent_recalc,
2310 };
2311
2312 static struct clk uart3_ck = {
2313         .name           = "uart3_ck",
2314         .ops            = &clkops_omap2_dflt,
2315         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2316         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2317         .clkdm_name     = "l4_per_clkdm",
2318         .parent         = &func_48m_fclk,
2319         .recalc         = &followparent_recalc,
2320 };
2321
2322 static struct clk uart4_ck = {
2323         .name           = "uart4_ck",
2324         .ops            = &clkops_omap2_dflt,
2325         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2326         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2327         .clkdm_name     = "l4_per_clkdm",
2328         .parent         = &func_48m_fclk,
2329         .recalc         = &followparent_recalc,
2330 };
2331
2332 static struct clk unipro1_ck = {
2333         .name           = "unipro1_ck",
2334         .ops            = &clkops_omap2_dflt,
2335         .enable_reg     = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
2336         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2337         .clkdm_name     = "l3_init_clkdm",
2338         .parent         = &func_96m_fclk,
2339         .recalc         = &followparent_recalc,
2340 };
2341
2342 static struct clk usb_host_ck = {
2343         .name           = "usb_host_ck",
2344         .ops            = &clkops_omap2_dflt,
2345         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2346         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2347         .clkdm_name     = "l3_init_clkdm",
2348         .parent         = &init_60m_fclk,
2349         .recalc         = &followparent_recalc,
2350 };
2351
2352 static struct clk usb_host_fs_ck = {
2353         .name           = "usb_host_fs_ck",
2354         .ops            = &clkops_omap2_dflt,
2355         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2356         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2357         .clkdm_name     = "l3_init_clkdm",
2358         .parent         = &func_48mc_fclk,
2359         .recalc         = &followparent_recalc,
2360 };
2361
2362 static struct clk usb_otg_ck = {
2363         .name           = "usb_otg_ck",
2364         .ops            = &clkops_omap2_dflt,
2365         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2366         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2367         .clkdm_name     = "l3_init_clkdm",
2368         .parent         = &l3_div_ck,
2369         .recalc         = &followparent_recalc,
2370 };
2371
2372 static struct clk usb_tll_ck = {
2373         .name           = "usb_tll_ck",
2374         .ops            = &clkops_omap2_dflt,
2375         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2376         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2377         .clkdm_name     = "l3_init_clkdm",
2378         .parent         = &l4_div_ck,
2379         .recalc         = &followparent_recalc,
2380 };
2381
2382 static struct clk usbphyocp2scp_ck = {
2383         .name           = "usbphyocp2scp_ck",
2384         .ops            = &clkops_omap2_dflt,
2385         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2386         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2387         .clkdm_name     = "l3_init_clkdm",
2388         .parent         = &l4_div_ck,
2389         .recalc         = &followparent_recalc,
2390 };
2391
2392 static struct clk usim_ck = {
2393         .name           = "usim_ck",
2394         .ops            = &clkops_omap2_dflt,
2395         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2396         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2397         .clkdm_name     = "l4_wkup_clkdm",
2398         .parent         = &sys_32k_ck,
2399         .recalc         = &followparent_recalc,
2400 };
2401
2402 static struct clk wdt2_ck = {
2403         .name           = "wdt2_ck",
2404         .ops            = &clkops_omap2_dflt,
2405         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2406         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2407         .clkdm_name     = "l4_wkup_clkdm",
2408         .parent         = &sys_32k_ck,
2409         .recalc         = &followparent_recalc,
2410 };
2411
2412 static struct clk wdt3_ck = {
2413         .name           = "wdt3_ck",
2414         .ops            = &clkops_omap2_dflt,
2415         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2416         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2417         .clkdm_name     = "abe_clkdm",
2418         .parent         = &sys_32k_ck,
2419         .recalc         = &followparent_recalc,
2420 };
2421
2422 /* Remaining optional clocks */
2423 static const struct clksel otg_60m_gfclk_sel[] = {
2424         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2425         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2426         { .parent = NULL },
2427 };
2428
2429 static struct clk otg_60m_gfclk_ck = {
2430         .name           = "otg_60m_gfclk_ck",
2431         .parent         = &utmi_phy_clkout_ck,
2432         .clksel         = otg_60m_gfclk_sel,
2433         .init           = &omap2_init_clksel_parent,
2434         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2435         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2436         .ops            = &clkops_null,
2437         .recalc         = &omap2_clksel_recalc,
2438         .flags          = CLOCK_IN_OMAP4430,
2439 };
2440
2441 static const struct clksel stm_clk_div_div[] = {
2442         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2443         { .parent = NULL },
2444 };
2445
2446 static struct clk stm_clk_div_ck = {
2447         .name           = "stm_clk_div_ck",
2448         .parent         = &pmd_stm_clock_mux_ck,
2449         .clksel         = stm_clk_div_div,
2450         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2451         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2452         .ops            = &clkops_null,
2453         .recalc         = &omap2_clksel_recalc,
2454         .round_rate     = &omap2_clksel_round_rate,
2455         .set_rate       = &omap2_clksel_set_rate,
2456         .flags          = CLOCK_IN_OMAP4430,
2457 };
2458
2459 static const struct clksel trace_clk_div_div[] = {
2460         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2461         { .parent = NULL },
2462 };
2463
2464 static struct clk trace_clk_div_ck = {
2465         .name           = "trace_clk_div_ck",
2466         .parent         = &pmd_trace_clk_mux_ck,
2467         .clksel         = trace_clk_div_div,
2468         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2469         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2470         .ops            = &clkops_null,
2471         .recalc         = &omap2_clksel_recalc,
2472         .round_rate     = &omap2_clksel_round_rate,
2473         .set_rate       = &omap2_clksel_set_rate,
2474         .flags          = CLOCK_IN_OMAP4430,
2475 };
2476
2477 static const struct clksel_rate div2_14to18_rates[] = {
2478         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2479         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2480         { .div = 0 },
2481 };
2482
2483 static const struct clksel usim_fclk_div[] = {
2484         { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
2485         { .parent = NULL },
2486 };
2487
2488 static struct clk usim_fclk = {
2489         .name           = "usim_fclk",
2490         .parent         = &dpll_per_m4_ck,
2491         .clksel         = usim_fclk_div,
2492         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2493         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2494         .ops            = &clkops_null,
2495         .recalc         = &omap2_clksel_recalc,
2496         .round_rate     = &omap2_clksel_round_rate,
2497         .set_rate       = &omap2_clksel_set_rate,
2498         .flags          = CLOCK_IN_OMAP4430,
2499 };
2500
2501 static const struct clksel utmi_p1_gfclk_sel[] = {
2502         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2503         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2504         { .parent = NULL },
2505 };
2506
2507 static struct clk utmi_p1_gfclk_ck = {
2508         .name           = "utmi_p1_gfclk_ck",
2509         .parent         = &init_60m_fclk,
2510         .clksel         = utmi_p1_gfclk_sel,
2511         .init           = &omap2_init_clksel_parent,
2512         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2513         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2514         .ops            = &clkops_null,
2515         .recalc         = &omap2_clksel_recalc,
2516         .flags          = CLOCK_IN_OMAP4430,
2517 };
2518
2519 static const struct clksel utmi_p2_gfclk_sel[] = {
2520         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2521         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2522         { .parent = NULL },
2523 };
2524
2525 static struct clk utmi_p2_gfclk_ck = {
2526         .name           = "utmi_p2_gfclk_ck",
2527         .parent         = &init_60m_fclk,
2528         .clksel         = utmi_p2_gfclk_sel,
2529         .init           = &omap2_init_clksel_parent,
2530         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2531         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2532         .ops            = &clkops_null,
2533         .recalc         = &omap2_clksel_recalc,
2534         .flags          = CLOCK_IN_OMAP4430,
2535 };
2536
2537 /*
2538  * clkdev
2539  */
2540
2541 static struct omap_clk omap44xx_clks[] = {
2542         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
2543         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
2544         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
2545         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
2546         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
2547         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
2548         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
2549         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
2550         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
2551         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
2552         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
2553         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
2554         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
2555         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
2556         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
2557         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
2558         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
2559         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
2560         CLK(NULL,       "dpll_sys_ref_clk",             &dpll_sys_ref_clk,      CK_443X),
2561         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
2562         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
2563         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
2564         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
2565         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
2566         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
2567         CLK(NULL,       "dpll_abe_m3_ck",               &dpll_abe_m3_ck,        CK_443X),
2568         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
2569         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
2570         CLK(NULL,       "dpll_core_m6_ck",              &dpll_core_m6_ck,       CK_443X),
2571         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
2572         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
2573         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
2574         CLK(NULL,       "dpll_core_m5_ck",              &dpll_core_m5_ck,       CK_443X),
2575         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
2576         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
2577         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
2578         CLK(NULL,       "dpll_core_m4_ck",              &dpll_core_m4_ck,       CK_443X),
2579         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
2580         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
2581         CLK(NULL,       "dpll_core_m3_ck",              &dpll_core_m3_ck,       CK_443X),
2582         CLK(NULL,       "dpll_core_m7_ck",              &dpll_core_m7_ck,       CK_443X),
2583         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
2584         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
2585         CLK(NULL,       "dpll_iva_m4_ck",               &dpll_iva_m4_ck,        CK_443X),
2586         CLK(NULL,       "dpll_iva_m5_ck",               &dpll_iva_m5_ck,        CK_443X),
2587         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
2588         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
2589         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
2590         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
2591         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
2592         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
2593         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
2594         CLK(NULL,       "dpll_per_m3_ck",               &dpll_per_m3_ck,        CK_443X),
2595         CLK(NULL,       "dpll_per_m4_ck",               &dpll_per_m4_ck,        CK_443X),
2596         CLK(NULL,       "dpll_per_m5_ck",               &dpll_per_m5_ck,        CK_443X),
2597         CLK(NULL,       "dpll_per_m6_ck",               &dpll_per_m6_ck,        CK_443X),
2598         CLK(NULL,       "dpll_per_m7_ck",               &dpll_per_m7_ck,        CK_443X),
2599         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
2600         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
2601         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
2602         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
2603         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
2604         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
2605         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
2606         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
2607         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
2608         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
2609         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
2610         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
2611         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
2612         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
2613         CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
2614         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
2615         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
2616         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
2617         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
2618         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
2619         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
2620         CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
2621         CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
2622         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
2623         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
2624         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
2625         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
2626         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
2627         CLK(NULL,       "aes1_ck",                      &aes1_ck,       CK_443X),
2628         CLK(NULL,       "aes2_ck",                      &aes2_ck,       CK_443X),
2629         CLK(NULL,       "aess_ck",                      &aess_ck,       CK_443X),
2630         CLK(NULL,       "cust_efuse_ck",                &cust_efuse_ck, CK_443X),
2631         CLK(NULL,       "des3des_ck",                   &des3des_ck,    CK_443X),
2632         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
2633         CLK(NULL,       "dmic_ck",                      &dmic_ck,       CK_443X),
2634         CLK(NULL,       "dss_ck",                       &dss_ck,        CK_443X),
2635         CLK(NULL,       "ducati_ck",                    &ducati_ck,     CK_443X),
2636         CLK(NULL,       "emif1_ck",                     &emif1_ck,      CK_443X),
2637         CLK(NULL,       "emif2_ck",                     &emif2_ck,      CK_443X),
2638         CLK(NULL,       "fdif_ck",                      &fdif_ck,       CK_443X),
2639         CLK(NULL,       "per_sgx_fclk",                 &per_sgx_fclk,  CK_443X),
2640         CLK(NULL,       "gfx_ck",                       &gfx_ck,        CK_443X),
2641         CLK(NULL,       "gpio1_ck",                     &gpio1_ck,      CK_443X),
2642         CLK(NULL,       "gpio2_ck",                     &gpio2_ck,      CK_443X),
2643         CLK(NULL,       "gpio3_ck",                     &gpio3_ck,      CK_443X),
2644         CLK(NULL,       "gpio4_ck",                     &gpio4_ck,      CK_443X),
2645         CLK(NULL,       "gpio5_ck",                     &gpio5_ck,      CK_443X),
2646         CLK(NULL,       "gpio6_ck",                     &gpio6_ck,      CK_443X),
2647         CLK(NULL,       "gpmc_ck",                      &gpmc_ck,       CK_443X),
2648         CLK(NULL,       "gptimer1_ck",                  &gptimer1_ck,   CK_443X),
2649         CLK(NULL,       "gptimer10_ck",                 &gptimer10_ck,  CK_443X),
2650         CLK(NULL,       "gptimer11_ck",                 &gptimer11_ck,  CK_443X),
2651         CLK(NULL,       "gptimer2_ck",                  &gptimer2_ck,   CK_443X),
2652         CLK(NULL,       "gptimer3_ck",                  &gptimer3_ck,   CK_443X),
2653         CLK(NULL,       "gptimer4_ck",                  &gptimer4_ck,   CK_443X),
2654         CLK(NULL,       "gptimer5_ck",                  &gptimer5_ck,   CK_443X),
2655         CLK(NULL,       "gptimer6_ck",                  &gptimer6_ck,   CK_443X),
2656         CLK(NULL,       "gptimer7_ck",                  &gptimer7_ck,   CK_443X),
2657         CLK(NULL,       "gptimer8_ck",                  &gptimer8_ck,   CK_443X),
2658         CLK(NULL,       "gptimer9_ck",                  &gptimer9_ck,   CK_443X),
2659         CLK("omap2_hdq.0",      "ick",                          &hdq1w_ck,      CK_443X),
2660         CLK(NULL,       "hsi_ck",                       &hsi_ck,        CK_443X),
2661         CLK("i2c_omap.1",       "ick",                          &i2c1_ck,       CK_443X),
2662         CLK("i2c_omap.2",       "ick",                          &i2c2_ck,       CK_443X),
2663         CLK("i2c_omap.3",       "ick",                          &i2c3_ck,       CK_443X),
2664         CLK("i2c_omap.4",       "ick",                          &i2c4_ck,       CK_443X),
2665         CLK(NULL,       "iss_ck",                       &iss_ck,        CK_443X),
2666         CLK(NULL,       "ivahd_ck",                     &ivahd_ck,      CK_443X),
2667         CLK(NULL,       "keyboard_ck",                  &keyboard_ck,   CK_443X),
2668         CLK(NULL,       "l3_instr_interconnect_ck",     &l3_instr_interconnect_ck,      CK_443X),
2669         CLK(NULL,       "l3_interconnect_3_ck",         &l3_interconnect_3_ck,  CK_443X),
2670         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
2671         CLK(NULL,       "mcasp_ck",                     &mcasp_ck,      CK_443X),
2672         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
2673         CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_ck,     CK_443X),
2674         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
2675         CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_ck,     CK_443X),
2676         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
2677         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_ck,     CK_443X),
2678         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
2679         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_ck,     CK_443X),
2680         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_ck,     CK_443X),
2681         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_ck,     CK_443X),
2682         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_ck,     CK_443X),
2683         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_ck,     CK_443X),
2684         CLK("mmci-omap-hs.0",   "fck",                          &mmc1_ck,       CK_443X),
2685         CLK("mmci-omap-hs.1",   "fck",                          &mmc2_ck,       CK_443X),
2686         CLK("mmci-omap-hs.2",   "fck",                          &mmc3_ck,       CK_443X),
2687         CLK("mmci-omap-hs.3",   "fck",                          &mmc4_ck,       CK_443X),
2688         CLK("mmci-omap-hs.4",   "fck",                          &mmc5_ck,       CK_443X),
2689         CLK(NULL,       "ocp_wp1_ck",                   &ocp_wp1_ck,    CK_443X),
2690         CLK(NULL,       "pdm_ck",                       &pdm_ck,        CK_443X),
2691         CLK(NULL,       "pkaeip29_ck",                  &pkaeip29_ck,   CK_443X),
2692         CLK("omap_rng", "ick",                          &rng_ck,        CK_443X),
2693         CLK(NULL,       "sha2md51_ck",                  &sha2md51_ck,   CK_443X),
2694         CLK(NULL,       "sl2_ck",                       &sl2_ck,        CK_443X),
2695         CLK(NULL,       "slimbus1_ck",                  &slimbus1_ck,   CK_443X),
2696         CLK(NULL,       "slimbus2_ck",                  &slimbus2_ck,   CK_443X),
2697         CLK(NULL,       "sr_core_ck",                   &sr_core_ck,    CK_443X),
2698         CLK(NULL,       "sr_iva_ck",                    &sr_iva_ck,     CK_443X),
2699         CLK(NULL,       "sr_mpu_ck",                    &sr_mpu_ck,     CK_443X),
2700         CLK(NULL,       "tesla_ck",                     &tesla_ck,      CK_443X),
2701         CLK(NULL,       "uart1_ck",                     &uart1_ck,      CK_443X),
2702         CLK(NULL,       "uart2_ck",                     &uart2_ck,      CK_443X),
2703         CLK(NULL,       "uart3_ck",                     &uart3_ck,      CK_443X),
2704         CLK(NULL,       "uart4_ck",                     &uart4_ck,      CK_443X),
2705         CLK(NULL,       "unipro1_ck",                   &unipro1_ck,    CK_443X),
2706         CLK(NULL,       "usb_host_ck",                  &usb_host_ck,   CK_443X),
2707         CLK(NULL,       "usb_host_fs_ck",               &usb_host_fs_ck,        CK_443X),
2708         CLK("musb_hdrc",        "ick",                          &usb_otg_ck,    CK_443X),
2709         CLK(NULL,       "usb_tll_ck",                   &usb_tll_ck,    CK_443X),
2710         CLK(NULL,       "usbphyocp2scp_ck",             &usbphyocp2scp_ck,      CK_443X),
2711         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
2712         CLK("omap_wdt", "fck",                          &wdt2_ck,       CK_443X),
2713         CLK(NULL,       "wdt3_ck",                      &wdt3_ck,       CK_443X),
2714         CLK(NULL,       "otg_60m_gfclk_ck",             &otg_60m_gfclk_ck,      CK_443X),
2715         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
2716         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
2717         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
2718         CLK(NULL,       "utmi_p1_gfclk_ck",             &utmi_p1_gfclk_ck,      CK_443X),
2719         CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
2720 };
2721
2722 int __init omap2_clk_init(void)
2723 {
2724         /* struct prcm_config *prcm; */
2725         struct omap_clk *c;
2726         /* u32 clkrate; */
2727         u32 cpu_clkflg;
2728
2729         if (cpu_is_omap44xx()) {
2730                 cpu_mask = RATE_IN_4430;
2731                 cpu_clkflg = CK_443X;
2732         }
2733
2734         clk_init(&omap2_clk_functions);
2735
2736         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2737                                                                           c++)
2738                 clk_preinit(c->lk.clk);
2739
2740         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2741                                                                           c++)
2742                 if (c->cpu & cpu_clkflg) {
2743                         clkdev_add(&c->lk);
2744                         clk_register(c->lk.clk);
2745                         /* TODO
2746                         omap2_init_clk_clkdm(c->lk.clk);
2747                         */
2748                 }
2749
2750         recalculate_root_clocks();
2751
2752         /*
2753          * Only enable those clocks we will need, let the drivers
2754          * enable other clocks as necessary
2755          */
2756         clk_enable_init_clocks();
2757
2758         return 0;
2759 }