4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
7 * Written by Paul Walmsley
10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
13 #include <mach/clockdomain.h>
16 * OMAP2/3-common clockdomains
18 * Even though the 2420 has a single PRCM module from the
19 * interconnect's perspective, internally it does appear to have
20 * separate PRM and CM clockdomains. The usual test case is
21 * sys_clkout/sys_clkout2.
24 /* This is an implicit clockdomain - it is never defined as such in TRM */
25 static struct clockdomain wkup_clkdm = {
27 .pwrdm = { .name = "wkup_pwrdm" },
28 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
31 static struct clockdomain prm_clkdm = {
33 .pwrdm = { .name = "wkup_pwrdm" },
34 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
37 static struct clockdomain cm_clkdm = {
39 .pwrdm = { .name = "core_pwrdm" },
40 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
44 * 2420-only clockdomains
47 #if defined(CONFIG_ARCH_OMAP2420)
49 static struct clockdomain mpu_2420_clkdm = {
51 .pwrdm = { .name = "mpu_pwrdm" },
52 .flags = CLKDM_CAN_HWSUP,
53 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
57 static struct clockdomain iva1_2420_clkdm = {
59 .pwrdm = { .name = "dsp_pwrdm" },
60 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
65 #endif /* CONFIG_ARCH_OMAP2420 */
69 * 2430-only clockdomains
72 #if defined(CONFIG_ARCH_OMAP2430)
74 static struct clockdomain mpu_2430_clkdm = {
76 .pwrdm = { .name = "mpu_pwrdm" },
77 .flags = CLKDM_CAN_HWSUP_SWSUP,
78 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
82 static struct clockdomain mdm_clkdm = {
84 .pwrdm = { .name = "mdm_pwrdm" },
85 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
90 #endif /* CONFIG_ARCH_OMAP2430 */
94 * 24XX-only clockdomains
97 #if defined(CONFIG_ARCH_OMAP24XX)
99 static struct clockdomain dsp_clkdm = {
101 .pwrdm = { .name = "dsp_pwrdm" },
102 .flags = CLKDM_CAN_HWSUP_SWSUP,
103 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
104 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
107 static struct clockdomain gfx_24xx_clkdm = {
109 .pwrdm = { .name = "gfx_pwrdm" },
110 .flags = CLKDM_CAN_HWSUP_SWSUP,
111 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
112 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
115 static struct clockdomain core_l3_24xx_clkdm = {
116 .name = "core_l3_clkdm",
117 .pwrdm = { .name = "core_pwrdm" },
118 .flags = CLKDM_CAN_HWSUP,
119 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
123 static struct clockdomain core_l4_24xx_clkdm = {
124 .name = "core_l4_clkdm",
125 .pwrdm = { .name = "core_pwrdm" },
126 .flags = CLKDM_CAN_HWSUP,
127 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
131 static struct clockdomain dss_24xx_clkdm = {
133 .pwrdm = { .name = "core_pwrdm" },
134 .flags = CLKDM_CAN_HWSUP,
135 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
139 #endif /* CONFIG_ARCH_OMAP24XX */
146 #if defined(CONFIG_ARCH_OMAP34XX)
148 static struct clockdomain mpu_34xx_clkdm = {
150 .pwrdm = { .name = "mpu_pwrdm" },
151 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
152 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
153 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
156 static struct clockdomain neon_clkdm = {
157 .name = "neon_clkdm",
158 .pwrdm = { .name = "neon_pwrdm" },
159 .flags = CLKDM_CAN_HWSUP_SWSUP,
160 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
161 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
164 static struct clockdomain iva2_clkdm = {
165 .name = "iva2_clkdm",
166 .pwrdm = { .name = "iva2_pwrdm" },
167 .flags = CLKDM_CAN_HWSUP_SWSUP,
168 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
169 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
172 static struct clockdomain gfx_3430es1_clkdm = {
174 .pwrdm = { .name = "gfx_pwrdm" },
175 .flags = CLKDM_CAN_HWSUP_SWSUP,
176 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
177 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
180 static struct clockdomain sgx_clkdm = {
182 .pwrdm = { .name = "sgx_pwrdm" },
183 .flags = CLKDM_CAN_HWSUP_SWSUP,
184 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
185 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
189 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
190 * then that information was removed from the 34xx ES2+ TRM. It is
191 * unclear whether the core is still there, but the clockdomain logic
192 * is there, and must be programmed to an appropriate state if the
193 * CORE clockdomain is to become inactive.
195 static struct clockdomain d2d_clkdm = {
197 .pwrdm = { .name = "core_pwrdm" },
198 .flags = CLKDM_CAN_HWSUP,
199 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
203 static struct clockdomain core_l3_34xx_clkdm = {
204 .name = "core_l3_clkdm",
205 .pwrdm = { .name = "core_pwrdm" },
206 .flags = CLKDM_CAN_HWSUP,
207 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
208 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
211 static struct clockdomain core_l4_34xx_clkdm = {
212 .name = "core_l4_clkdm",
213 .pwrdm = { .name = "core_pwrdm" },
214 .flags = CLKDM_CAN_HWSUP,
215 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
219 static struct clockdomain dss_34xx_clkdm = {
221 .pwrdm = { .name = "dss_pwrdm" },
222 .flags = CLKDM_CAN_HWSUP_SWSUP,
223 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
224 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
227 static struct clockdomain cam_clkdm = {
229 .pwrdm = { .name = "cam_pwrdm" },
230 .flags = CLKDM_CAN_HWSUP_SWSUP,
231 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
235 static struct clockdomain usbhost_clkdm = {
236 .name = "usbhost_clkdm",
237 .pwrdm = { .name = "usbhost_pwrdm" },
238 .flags = CLKDM_CAN_HWSUP_SWSUP,
239 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
240 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
243 static struct clockdomain per_clkdm = {
245 .pwrdm = { .name = "per_pwrdm" },
246 .flags = CLKDM_CAN_HWSUP_SWSUP,
247 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
248 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
251 static struct clockdomain emu_clkdm = {
253 .pwrdm = { .name = "emu_pwrdm" },
254 .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
255 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
256 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
259 static struct clockdomain dpll1_clkdm = {
260 .name = "dpll1_clkdm",
261 .pwrdm = { .name = "dpll1_pwrdm" },
262 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
265 static struct clockdomain dpll2_clkdm = {
266 .name = "dpll2_clkdm",
267 .pwrdm = { .name = "dpll2_pwrdm" },
268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
271 static struct clockdomain dpll3_clkdm = {
272 .name = "dpll3_clkdm",
273 .pwrdm = { .name = "dpll3_pwrdm" },
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
277 static struct clockdomain dpll4_clkdm = {
278 .name = "dpll4_clkdm",
279 .pwrdm = { .name = "dpll4_pwrdm" },
280 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
283 static struct clockdomain dpll5_clkdm = {
284 .name = "dpll5_clkdm",
285 .pwrdm = { .name = "dpll5_pwrdm" },
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
289 #endif /* CONFIG_ARCH_OMAP34XX */
292 * Clockdomain-powerdomain hwsup dependencies (34XX only)
295 static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
297 .pwrdm = { .name = "mpu_pwrdm" },
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
301 .pwrdm = { .name = "iva2_pwrdm" },
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
305 .pwrdm = { .name = NULL },
313 static struct clockdomain *clockdomains_omap[] = {
319 #ifdef CONFIG_ARCH_OMAP2420
324 #ifdef CONFIG_ARCH_OMAP2430
329 #ifdef CONFIG_ARCH_OMAP24XX
337 #ifdef CONFIG_ARCH_OMAP34XX