arch/arm/mach-omap2/cm1_54xx.h

   1 /*
   2  * OMAP54xx CM1 instance offset macros
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley (paul@pwsan.com)
   7  * Rajendra Nayak (rnayak@ti.com)
   8  * Benoit Cousson (b-cousson@ti.com)
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  *
  20  */
  21
  22 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
  23 #define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
  24
  25 #include "cm_44xx_54xx.h"
  26
  27 /* CM1 base address */
  28 #define OMAP54XX_CM_CORE_AON_BASE               0x4a004000
  29
  30 #define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg)                         \
  31         OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
  32
  33 /* CM_CORE_AON instances */
  34 #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST    0x0000
  35 #define OMAP54XX_CM_CORE_AON_CKGEN_INST         0x0100
  36 #define OMAP54XX_CM_CORE_AON_MPU_INST           0x0300
  37 #define OMAP54XX_CM_CORE_AON_DSP_INST           0x0400
  38 #define OMAP54XX_CM_CORE_AON_ABE_INST           0x0500
  39 #define OMAP54XX_CM_CORE_AON_RESTORE_INST       0x0e00
  40 #define OMAP54XX_CM_CORE_AON_INSTR_INST         0x0f00
  41
  42 /* CM_CORE_AON clockdomain register offsets (from instance start) */
  43 #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS     0x0000
  44 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS     0x0000
  45 #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS     0x0000
  46
  47 /* CM_CORE_AON */
  48
  49 /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
  50 #define OMAP54XX_REVISION_CM_CORE_AON_OFFSET                    0x0000
  51 #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET        0x0040
  52 #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL               OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
  53 #define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET                   0x0080
  54 #define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET                   0x0084
  55 #define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET          0x0090
  56 #define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET          0x0094
  57 #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET          0x0098
  58 #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET         0x009c
  59 #define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET  0x00a0
  60 #define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET          0x00a4
  61 #define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET          0x00a8
  62 #define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET      0x00ac
  63 #define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET    0x00b0
  64 #define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET          0x00b4
  65 #define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET          0x00b8
  66 #define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET         0x00bc
  67 #define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET          0x00c0
  68 #define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET          0x00c4
  69 #define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET          0x00c8
  70 #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET       0x00cc
  71 #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET      0x00d0
  72 #define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET      0x00d4
  73 #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET      0x00d8
  74 #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET      0x00dc
  75 #define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET        0x00e0
  76 #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET        0x00e4
  77 #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET       0x00e8
  78 #define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET        0x00ec
  79 #define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET      0x00f0
  80
  81 /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
  82 #define OMAP54XX_CM_CLKSEL_CORE_OFFSET                          0x0000
  83 #define OMAP54XX_CM_CLKSEL_CORE                                 OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
  84 #define OMAP54XX_CM_CLKSEL_ABE_OFFSET                           0x0008
  85 #define OMAP54XX_CM_CLKSEL_ABE                                  OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
  86 #define OMAP54XX_CM_DLL_CTRL_OFFSET                             0x0010
  87 #define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET                    0x0020
  88 #define OMAP54XX_CM_CLKMODE_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
  89 #define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET                     0x0024
  90 #define OMAP54XX_CM_IDLEST_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
  91 #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET                   0x0028
  92 #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
  93 #define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET                     0x002c
  94 #define OMAP54XX_CM_CLKSEL_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
  95 #define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET                     0x0030
  96 #define OMAP54XX_CM_DIV_M2_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
  97 #define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET                     0x0034
  98 #define OMAP54XX_CM_DIV_M3_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
  99 #define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET                    0x0038
 100 #define OMAP54XX_CM_DIV_H11_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
 101 #define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET                    0x003c
 102 #define OMAP54XX_CM_DIV_H12_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
 103 #define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET                    0x0040
 104 #define OMAP54XX_CM_DIV_H13_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
 105 #define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET                    0x0044
 106 #define OMAP54XX_CM_DIV_H14_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
 107 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET             0x0048
 108 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET             0x004c
 109 #define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET                    0x0050
 110 #define OMAP54XX_CM_DIV_H21_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
 111 #define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET                    0x0054
 112 #define OMAP54XX_CM_DIV_H22_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
 113 #define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET                    0x0058
 114 #define OMAP54XX_CM_DIV_H23_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
 115 #define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET                    0x005c
 116 #define OMAP54XX_CM_DIV_H24_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
 117 #define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET                     0x0060
 118 #define OMAP54XX_CM_CLKMODE_DPLL_MPU                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
 119 #define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET                      0x0064
 120 #define OMAP54XX_CM_IDLEST_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
 121 #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET                    0x0068
 122 #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
 123 #define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET                      0x006c
 124 #define OMAP54XX_CM_CLKSEL_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
 125 #define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET                      0x0070
 126 #define OMAP54XX_CM_DIV_M2_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
 127 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET              0x0088
 128 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET              0x008c
 129 #define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET                      0x009c
 130 #define OMAP54XX_CM_BYPCLK_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
 131 #define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET                     0x00a0
 132 #define OMAP54XX_CM_CLKMODE_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
 133 #define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET                      0x00a4
 134 #define OMAP54XX_CM_IDLEST_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
 135 #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET                    0x00a8
 136 #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
 137 #define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET                      0x00ac
 138 #define OMAP54XX_CM_CLKSEL_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
 139 #define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET                     0x00b8
 140 #define OMAP54XX_CM_DIV_H11_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
 141 #define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET                     0x00bc
 142 #define OMAP54XX_CM_DIV_H12_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
 143 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET              0x00c8
 144 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET              0x00cc
 145 #define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET                      0x00dc
 146 #define OMAP54XX_CM_BYPCLK_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
 147 #define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET                     0x00e0
 148 #define OMAP54XX_CM_CLKMODE_DPLL_ABE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
 149 #define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET                      0x00e4
 150 #define OMAP54XX_CM_IDLEST_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
 151 #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET                    0x00e8
 152 #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
 153 #define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET                      0x00ec
 154 #define OMAP54XX_CM_CLKSEL_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
 155 #define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET                      0x00f0
 156 #define OMAP54XX_CM_DIV_M2_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
 157 #define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET                      0x00f4
 158 #define OMAP54XX_CM_DIV_M3_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
 159 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET              0x0108
 160 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET              0x010c
 161 #define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET                  0x0160
 162 #define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET                  0x0164
 163 #define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET                      0x0170
 164 #define OMAP54XX_CM_RESTORE_ST_OFFSET                           0x0180
 165
 166 /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
 167 #define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET                        0x0000
 168 #define OMAP54XX_CM_MPU_STATICDEP_OFFSET                        0x0004
 169 #define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET                       0x0008
 170 #define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET                      0x0020
 171 #define OMAP54XX_CM_MPU_MPU_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
 172 #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET              0x0028
 173 #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL                     OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
 174
 175 /* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
 176 #define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET                        0x0000
 177 #define OMAP54XX_CM_DSP_STATICDEP_OFFSET                        0x0004
 178 #define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET                       0x0008
 179 #define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET                      0x0020
 180 #define OMAP54XX_CM_DSP_DSP_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
 181
 182 /* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
 183 #define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET                        0x0000
 184 #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET                   0x0020
 185 #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
 186 #define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET                     0x0028
 187 #define OMAP54XX_CM_ABE_AESS_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
 188 #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET                    0x0030
 189 #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
 190 #define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET                     0x0038
 191 #define OMAP54XX_CM_ABE_DMIC_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
 192 #define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET                    0x0040
 193 #define OMAP54XX_CM_ABE_MCASP_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
 194 #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET                   0x0048
 195 #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
 196 #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET                   0x0050
 197 #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
 198 #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET                   0x0058
 199 #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
 200 #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET                 0x0060
 201 #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL                        OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
 202 #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET                   0x0068
 203 #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
 204 #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET                   0x0070
 205 #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
 206 #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET                   0x0078
 207 #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
 208 #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET                   0x0080
 209 #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
 210 #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET                0x0088
 211 #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL                       OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
 212
 213 #endif