2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
4 * OMAP3 CPU IDLE Routines
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
18 * Based on pm.c for omap2
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
27 #include <linux/export.h>
29 #include <plat/prcm.h>
30 #include <plat/irqs.h>
31 #include "powerdomain.h"
32 #include "clockdomain.h"
33 #include <plat/serial.h>
39 #ifdef CONFIG_CPU_IDLE
42 * The latencies/thresholds for various C states have
43 * to be configured from the respective board files.
44 * These are some default values (which might not provide
45 * the best power savings) used on boards which do not
46 * pass these details from the board file.
48 static struct cpuidle_params cpuidle_params_table[] = {
56 {1500 + 1800, 4000, 1},
58 {2500 + 7500, 12000, 1},
60 {3000 + 8500, 15000, 1},
62 {10000 + 30000, 300000, 1},
64 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
66 /* Mach specific information to be recorded in the C-state driver_data */
67 struct omap3_idle_statedata {
72 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
74 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
76 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
77 struct clockdomain *clkdm)
79 clkdm_allow_idle(clkdm);
83 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
84 struct clockdomain *clkdm)
86 clkdm_deny_idle(clkdm);
91 * omap3_enter_idle - Programs OMAP3 to enter the specified state
92 * @dev: cpuidle device
93 * @drv: cpuidle driver
94 * @index: the index of state to be entered
96 * Called from the CPUidle framework to program the device to the
97 * specified target state selected by the governor.
99 static int omap3_enter_idle(struct cpuidle_device *dev,
100 struct cpuidle_driver *drv,
103 struct omap3_idle_statedata *cx =
104 cpuidle_get_statedata(&dev->states_usage[index]);
105 struct timespec ts_preidle, ts_postidle, ts_idle;
106 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
109 /* Used to keep track of the total time in idle */
110 getnstimeofday(&ts_preidle);
115 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
116 pwrdm_set_next_pwrst(core_pd, core_state);
118 if (omap_irq_pending() || need_resched())
119 goto return_sleep_time;
121 /* Deny idle for C1 */
123 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
124 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
127 /* Execute ARM wfi */
130 /* Re-allow idle for C1 */
132 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
133 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
137 getnstimeofday(&ts_postidle);
138 ts_idle = timespec_sub(ts_postidle, ts_preidle);
143 idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
146 /* Update cpuidle counters */
147 dev->last_residency = idle_time;
153 * next_valid_state - Find next valid C-state
154 * @dev: cpuidle device
155 * @drv: cpuidle driver
156 * @index: Index of currently selected c-state
158 * If the state corresponding to index is valid, index is returned back
159 * to the caller. Else, this function searches for a lower c-state which is
160 * still valid (as defined in omap3_power_states[]) and returns its index.
162 * A state is valid if the 'valid' field is enabled and
163 * if it satisfies the enable_off_mode condition.
165 static int next_valid_state(struct cpuidle_device *dev,
166 struct cpuidle_driver *drv,
169 struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
170 struct cpuidle_state *curr = &drv->states[index];
171 struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
172 u32 mpu_deepest_state = PWRDM_POWER_RET;
173 u32 core_deepest_state = PWRDM_POWER_RET;
176 if (enable_off_mode) {
177 mpu_deepest_state = PWRDM_POWER_OFF;
179 * Erratum i583: valable for ES rev < Es1.2 on 3630.
180 * CORE OFF mode is not supported in a stable form, restrict
181 * instead the CORE state to RET.
183 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
184 core_deepest_state = PWRDM_POWER_OFF;
187 /* Check if current state is valid */
189 (cx->mpu_state >= mpu_deepest_state) &&
190 (cx->core_state >= core_deepest_state)) {
193 int idx = OMAP3_NUM_STATES - 1;
195 /* Reach the current state starting at highest C-state */
196 for (; idx >= 0; idx--) {
197 if (&drv->states[idx] == curr) {
203 /* Should never hit this condition */
204 WARN_ON(next_index == -1);
207 * Drop to next valid state.
208 * Start search from the next (lower) state.
211 for (; idx >= 0; idx--) {
212 cx = cpuidle_get_statedata(&dev->states_usage[idx]);
214 (cx->mpu_state >= mpu_deepest_state) &&
215 (cx->core_state >= core_deepest_state)) {
221 * C1 is always valid.
222 * So, no need to check for 'next_index == -1' outside
231 * omap3_enter_idle_bm - Checks for any bus activity
232 * @dev: cpuidle device
233 * @drv: cpuidle driver
234 * @index: array index of target state to be programmed
236 * This function checks for any pending activity and then programs
237 * the device to the specified or a safer state.
239 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
240 struct cpuidle_driver *drv,
244 u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
245 struct omap3_idle_statedata *cx;
248 if (!omap3_can_sleep()) {
249 new_state_idx = drv->safe_state_index;
254 * Prevent idle completely if CAM is active.
255 * CAM does not have wakeup capability in OMAP3.
257 cam_state = pwrdm_read_pwrst(cam_pd);
258 if (cam_state == PWRDM_POWER_ON) {
259 new_state_idx = drv->safe_state_index;
264 * FIXME: we currently manage device-specific idle states
265 * for PER and CORE in combination with CPU-specific
266 * idle states. This is wrong, and device-specific
267 * idle management needs to be separated out into
272 * Prevent PER off if CORE is not in retention or off as this
273 * would disable PER wakeups completely.
275 cx = cpuidle_get_statedata(&dev->states_usage[index]);
276 core_next_state = cx->core_state;
277 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
278 if ((per_next_state == PWRDM_POWER_OFF) &&
279 (core_next_state > PWRDM_POWER_RET))
280 per_next_state = PWRDM_POWER_RET;
282 /* Are we changing PER target state? */
283 if (per_next_state != per_saved_state)
284 pwrdm_set_next_pwrst(per_pd, per_next_state);
286 new_state_idx = next_valid_state(dev, drv, index);
289 ret = omap3_enter_idle(dev, drv, new_state_idx);
291 /* Restore original PER state if it was modified */
292 if (per_next_state != per_saved_state)
293 pwrdm_set_next_pwrst(per_pd, per_saved_state);
298 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
300 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
304 if (!cpuidle_board_params)
307 for (i = 0; i < OMAP3_NUM_STATES; i++) {
308 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
309 cpuidle_params_table[i].exit_latency =
310 cpuidle_board_params[i].exit_latency;
311 cpuidle_params_table[i].target_residency =
312 cpuidle_board_params[i].target_residency;
317 struct cpuidle_driver omap3_idle_driver = {
318 .name = "omap3_idle",
319 .owner = THIS_MODULE,
322 /* Helper to fill the C-state common data*/
323 static inline void _fill_cstate(struct cpuidle_driver *drv,
324 int idx, const char *descr)
326 struct cpuidle_state *state = &drv->states[idx];
328 state->exit_latency = cpuidle_params_table[idx].exit_latency;
329 state->target_residency = cpuidle_params_table[idx].target_residency;
330 state->flags = CPUIDLE_FLAG_TIME_VALID;
331 state->enter = omap3_enter_idle_bm;
332 sprintf(state->name, "C%d", idx + 1);
333 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
337 /* Helper to register the driver_data */
338 static inline struct omap3_idle_statedata *_fill_cstate_usage(
339 struct cpuidle_device *dev,
342 struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
343 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
345 cx->valid = cpuidle_params_table[idx].valid;
346 cpuidle_set_statedata(state_usage, cx);
352 * omap3_idle_init - Init routine for OMAP3 idle
354 * Registers the OMAP3 specific cpuidle driver to the cpuidle
355 * framework with the valid set of states.
357 int __init omap3_idle_init(void)
359 struct cpuidle_device *dev;
360 struct cpuidle_driver *drv = &omap3_idle_driver;
361 struct omap3_idle_statedata *cx;
363 mpu_pd = pwrdm_lookup("mpu_pwrdm");
364 core_pd = pwrdm_lookup("core_pwrdm");
365 per_pd = pwrdm_lookup("per_pwrdm");
366 cam_pd = pwrdm_lookup("cam_pwrdm");
369 drv->safe_state_index = -1;
370 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
372 /* C1 . MPU WFI + Core active */
373 _fill_cstate(drv, 0, "MPU ON + CORE ON");
374 (&drv->states[0])->enter = omap3_enter_idle;
375 drv->safe_state_index = 0;
376 cx = _fill_cstate_usage(dev, 0);
377 cx->valid = 1; /* C1 is always valid */
378 cx->mpu_state = PWRDM_POWER_ON;
379 cx->core_state = PWRDM_POWER_ON;
381 /* C2 . MPU WFI + Core inactive */
382 _fill_cstate(drv, 1, "MPU ON + CORE ON");
383 cx = _fill_cstate_usage(dev, 1);
384 cx->mpu_state = PWRDM_POWER_ON;
385 cx->core_state = PWRDM_POWER_ON;
387 /* C3 . MPU CSWR + Core inactive */
388 _fill_cstate(drv, 2, "MPU RET + CORE ON");
389 cx = _fill_cstate_usage(dev, 2);
390 cx->mpu_state = PWRDM_POWER_RET;
391 cx->core_state = PWRDM_POWER_ON;
393 /* C4 . MPU OFF + Core inactive */
394 _fill_cstate(drv, 3, "MPU OFF + CORE ON");
395 cx = _fill_cstate_usage(dev, 3);
396 cx->mpu_state = PWRDM_POWER_OFF;
397 cx->core_state = PWRDM_POWER_ON;
399 /* C5 . MPU RET + Core RET */
400 _fill_cstate(drv, 4, "MPU RET + CORE RET");
401 cx = _fill_cstate_usage(dev, 4);
402 cx->mpu_state = PWRDM_POWER_RET;
403 cx->core_state = PWRDM_POWER_RET;
405 /* C6 . MPU OFF + Core RET */
406 _fill_cstate(drv, 5, "MPU OFF + CORE RET");
407 cx = _fill_cstate_usage(dev, 5);
408 cx->mpu_state = PWRDM_POWER_OFF;
409 cx->core_state = PWRDM_POWER_RET;
411 /* C7 . MPU OFF + Core OFF */
412 _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
413 cx = _fill_cstate_usage(dev, 6);
415 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
416 * enable OFF mode in a stable form for previous revisions.
417 * We disable C7 state as a result.
419 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
421 pr_warn("%s: core off state C7 disabled due to i583\n",
424 cx->mpu_state = PWRDM_POWER_OFF;
425 cx->core_state = PWRDM_POWER_OFF;
427 drv->state_count = OMAP3_NUM_STATES;
428 cpuidle_register_driver(&omap3_idle_driver);
430 dev->state_count = OMAP3_NUM_STATES;
431 if (cpuidle_register_device(dev)) {
432 printk(KERN_ERR "%s: CPUidle register device failed\n",
440 int __init omap3_idle_init(void)
444 #endif /* CONFIG_CPU_IDLE */