arch/arm/mach-omap2/cpuidle44xx.c

   1 /*
   2  * OMAP4 CPU idle Routines
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  * Rajendra Nayak <rnayak@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/sched.h>
  14 #include <linux/cpuidle.h>
  15 #include <linux/cpu_pm.h>
  16 #include <linux/export.h>
  17
  18 #include <asm/proc-fns.h>
  19
  20 #include "common.h"
  21 #include "pm.h"
  22 #include "prm.h"
  23 #include "clockdomain.h"
  24
  25 /* Machine specific information */
  26 struct omap4_idle_statedata {
  27         u32 cpu_state;
  28         u32 mpu_logic_state;
  29         u32 mpu_state;
  30 };
  31
  32 static struct omap4_idle_statedata omap4_idle_data[] = {
  33         {
  34                 .cpu_state = PWRDM_POWER_ON,
  35                 .mpu_state = PWRDM_POWER_ON,
  36                 .mpu_logic_state = PWRDM_POWER_RET,
  37         },
  38         {
  39                 .cpu_state = PWRDM_POWER_OFF,
  40                 .mpu_state = PWRDM_POWER_RET,
  41                 .mpu_logic_state = PWRDM_POWER_RET,
  42         },
  43         {
  44                 .cpu_state = PWRDM_POWER_OFF,
  45                 .mpu_state = PWRDM_POWER_RET,
  46                 .mpu_logic_state = PWRDM_POWER_OFF,
  47         },
  48 };
  49
  50 static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
  51 static struct clockdomain *cpu_clkdm[NR_CPUS];
  52
  53 static atomic_t abort_barrier;
  54 static bool cpu_done[NR_CPUS];
  55
  56 /* Private functions */
  57
  58 /**
  59  * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  60  * @dev: cpuidle device
  61  * @drv: cpuidle driver
  62  * @index: the index of state to be entered
  63  *
  64  * Called from the CPUidle framework to program the device to the
  65  * specified low power state selected by the governor.
  66  * Returns the amount of time spent in the low power state.
  67  */
  68 static int omap4_enter_idle_simple(struct cpuidle_device *dev,
  69                         struct cpuidle_driver *drv,
  70                         int index)
  71 {
  72         local_fiq_disable();
  73         omap_do_wfi();
  74         local_fiq_enable();
  75
  76         return index;
  77 }
  78
  79 static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
  80                         struct cpuidle_driver *drv,
  81                         int index)
  82 {
  83         struct omap4_idle_statedata *cx = &omap4_idle_data[index];
  84
  85         local_fiq_disable();
  86
  87         /*
  88          * CPU0 has to wait and stay ON until CPU1 is OFF state.
  89          * This is necessary to honour hardware recommondation
  90          * of triggeing all the possible low power modes once CPU1 is
  91          * out of coherency and in OFF mode.
  92          */
  93         if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
  94                 while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
  95                         cpu_relax();
  96
  97                         /*
  98                          * CPU1 could have already entered & exited idle
  99                          * without hitting off because of a wakeup
 100                          * or a failed attempt to hit off mode.  Check for
 101                          * that here, otherwise we could spin forever
 102                          * waiting for CPU1 off.
 103                          */
 104                         if (cpu_done[1])
 105                             goto fail;
 106
 107                 }
 108         }
 109
 110         /*
 111          * Call idle CPU PM enter notifier chain so that
 112          * VFP and per CPU interrupt context is saved.
 113          */
 114         cpu_pm_enter();
 115
 116         if (dev->cpu == 0) {
 117                 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
 118                 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
 119
 120                 /*
 121                  * Call idle CPU cluster PM enter notifier chain
 122                  * to save GIC and wakeupgen context.
 123                  */
 124                 if ((cx->mpu_state == PWRDM_POWER_RET) &&
 125                         (cx->mpu_logic_state == PWRDM_POWER_OFF))
 126                                 cpu_cluster_pm_enter();
 127         }
 128
 129         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
 130         cpu_done[dev->cpu] = true;
 131
 132         /* Wakeup CPU1 only if it is not offlined */
 133         if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
 134                 clkdm_wakeup(cpu_clkdm[1]);
 135                 clkdm_allow_idle(cpu_clkdm[1]);
 136         }
 137
 138         /*
 139          * Call idle CPU PM exit notifier chain to restore
 140          * VFP and per CPU IRQ context.
 141          */
 142         cpu_pm_exit();
 143
 144         /*
 145          * Call idle CPU cluster PM exit notifier chain
 146          * to restore GIC and wakeupgen context.
 147          */
 148         if ((cx->mpu_state == PWRDM_POWER_RET) &&
 149                 (cx->mpu_logic_state == PWRDM_POWER_OFF))
 150                 cpu_cluster_pm_exit();
 151
 152 fail:
 153         cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
 154         cpu_done[dev->cpu] = false;
 155
 156         local_fiq_enable();
 157
 158         return index;
 159 }
 160
 161 static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
 162
 163 static struct cpuidle_driver omap4_idle_driver = {
 164         .name                           = "omap4_idle",
 165         .owner                          = THIS_MODULE,
 166         .en_core_tk_irqen               = 1,
 167         .states = {
 168                 {
 169                         /* C1 - CPU0 ON + CPU1 ON + MPU ON */
 170                         .exit_latency = 2 + 2,
 171                         .target_residency = 5,
 172                         .flags = CPUIDLE_FLAG_TIME_VALID,
 173                         .enter = omap4_enter_idle_simple,
 174                         .name = "C1",
 175                         .desc = "CPUx ON, MPUSS ON"
 176                 },
 177                 {
 178                         /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
 179                         .exit_latency = 328 + 440,
 180                         .target_residency = 960,
 181                         .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
 182                                  CPUIDLE_FLAG_TIMER_STOP,
 183                         .enter = omap4_enter_idle_coupled,
 184                         .name = "C2",
 185                         .desc = "CPUx OFF, MPUSS CSWR",
 186                 },
 187                 {
 188                         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
 189                         .exit_latency = 460 + 518,
 190                         .target_residency = 1100,
 191                         .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
 192                                  CPUIDLE_FLAG_TIMER_STOP,
 193                         .enter = omap4_enter_idle_coupled,
 194                         .name = "C3",
 195                         .desc = "CPUx OFF, MPUSS OSWR",
 196                 },
 197         },
 198         .state_count = ARRAY_SIZE(omap4_idle_data),
 199         .safe_state_index = 0,
 200 };
 201
 202 /* Public functions */
 203
 204 /**
 205  * omap4_idle_init - Init routine for OMAP4 idle
 206  *
 207  * Registers the OMAP4 specific cpuidle driver to the cpuidle
 208  * framework with the valid set of states.
 209  */
 210 int __init omap4_idle_init(void)
 211 {
 212         struct cpuidle_device *dev;
 213         unsigned int cpu_id = 0;
 214
 215         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 216         cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
 217         cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
 218         if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
 219                 return -ENODEV;
 220
 221         cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
 222         cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
 223         if (!cpu_clkdm[0] || !cpu_clkdm[1])
 224                 return -ENODEV;
 225
 226         if (cpuidle_register_driver(&omap4_idle_driver)) {
 227                 pr_err("%s: CPUidle driver register failed\n", __func__);
 228                 return -EIO;
 229         }
 230
 231         for_each_cpu(cpu_id, cpu_online_mask) {
 232                 dev = &per_cpu(omap4_idle_dev, cpu_id);
 233                 dev->cpu = cpu_id;
 234 #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
 235                 dev->coupled_cpus = *cpu_online_mask;
 236 #endif
 237                 if (cpuidle_register_device(dev)) {
 238                         pr_err("%s: CPUidle register failed\n", __func__);
 239                         cpuidle_unregister_driver(&omap4_idle_driver);
 240                         return -EIO;
 241                 }
 242         }
 243
 244         return 0;
 245 }