2 * linux/arch/arm/mach-omap2/devices.c
4 * OMAP2 platform device setup/initialization
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
19 #include <mach/hardware.h>
20 #include <mach/irqs.h>
21 #include <asm/mach-types.h>
22 #include <asm/mach/map.h>
26 #include <plat/board.h>
27 #include <mach/gpio.h>
30 #include <plat/omap_hwmod.h>
31 #include <plat/omap_device.h>
36 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
38 static struct resource cam_resources[] = {
40 .start = OMAP24XX_CAMERA_BASE,
41 .end = OMAP24XX_CAMERA_BASE + 0xfff,
42 .flags = IORESOURCE_MEM,
45 .start = INT_24XX_CAM_IRQ,
46 .flags = IORESOURCE_IRQ,
50 static struct platform_device omap_cam_device = {
51 .name = "omap24xxcam",
53 .num_resources = ARRAY_SIZE(cam_resources),
54 .resource = cam_resources,
57 static inline void omap_init_camera(void)
59 platform_device_register(&omap_cam_device);
62 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
64 static struct resource omap3isp_resources[] = {
66 .start = OMAP3430_ISP_BASE,
67 .end = OMAP3430_ISP_END,
68 .flags = IORESOURCE_MEM,
71 .start = OMAP3430_ISP_CBUFF_BASE,
72 .end = OMAP3430_ISP_CBUFF_END,
73 .flags = IORESOURCE_MEM,
76 .start = OMAP3430_ISP_CCP2_BASE,
77 .end = OMAP3430_ISP_CCP2_END,
78 .flags = IORESOURCE_MEM,
81 .start = OMAP3430_ISP_CCDC_BASE,
82 .end = OMAP3430_ISP_CCDC_END,
83 .flags = IORESOURCE_MEM,
86 .start = OMAP3430_ISP_HIST_BASE,
87 .end = OMAP3430_ISP_HIST_END,
88 .flags = IORESOURCE_MEM,
91 .start = OMAP3430_ISP_H3A_BASE,
92 .end = OMAP3430_ISP_H3A_END,
93 .flags = IORESOURCE_MEM,
96 .start = OMAP3430_ISP_PREV_BASE,
97 .end = OMAP3430_ISP_PREV_END,
98 .flags = IORESOURCE_MEM,
101 .start = OMAP3430_ISP_RESZ_BASE,
102 .end = OMAP3430_ISP_RESZ_END,
103 .flags = IORESOURCE_MEM,
106 .start = OMAP3430_ISP_SBL_BASE,
107 .end = OMAP3430_ISP_SBL_END,
108 .flags = IORESOURCE_MEM,
111 .start = OMAP3430_ISP_CSI2A_BASE,
112 .end = OMAP3430_ISP_CSI2A_END,
113 .flags = IORESOURCE_MEM,
116 .start = OMAP3430_ISP_CSI2PHY_BASE,
117 .end = OMAP3430_ISP_CSI2PHY_END,
118 .flags = IORESOURCE_MEM,
121 .start = INT_34XX_CAM_IRQ,
122 .flags = IORESOURCE_IRQ,
126 static struct platform_device omap3isp_device = {
129 .num_resources = ARRAY_SIZE(omap3isp_resources),
130 .resource = omap3isp_resources,
133 static inline void omap_init_camera(void)
135 platform_device_register(&omap3isp_device);
138 static inline void omap_init_camera(void)
143 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
145 #define MBOX_REG_SIZE 0x120
147 #ifdef CONFIG_ARCH_OMAP2
148 static struct resource omap2_mbox_resources[] = {
150 .start = OMAP24XX_MAILBOX_BASE,
151 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
152 .flags = IORESOURCE_MEM,
155 .start = INT_24XX_MAIL_U0_MPU,
156 .flags = IORESOURCE_IRQ,
160 .start = INT_24XX_MAIL_U3_MPU,
161 .flags = IORESOURCE_IRQ,
165 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
167 #define omap2_mbox_resources NULL
168 #define omap2_mbox_resources_sz 0
171 #ifdef CONFIG_ARCH_OMAP3
172 static struct resource omap3_mbox_resources[] = {
174 .start = OMAP34XX_MAILBOX_BASE,
175 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
176 .flags = IORESOURCE_MEM,
179 .start = INT_24XX_MAIL_U0_MPU,
180 .flags = IORESOURCE_IRQ,
184 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
186 #define omap3_mbox_resources NULL
187 #define omap3_mbox_resources_sz 0
190 #ifdef CONFIG_ARCH_OMAP4
192 #define OMAP4_MBOX_REG_SIZE 0x130
193 static struct resource omap4_mbox_resources[] = {
195 .start = OMAP44XX_MAILBOX_BASE,
196 .end = OMAP44XX_MAILBOX_BASE +
197 OMAP4_MBOX_REG_SIZE - 1,
198 .flags = IORESOURCE_MEM,
201 .start = OMAP44XX_IRQ_MAIL_U0,
202 .flags = IORESOURCE_IRQ,
206 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
208 #define omap4_mbox_resources NULL
209 #define omap4_mbox_resources_sz 0
212 static struct platform_device mbox_device = {
213 .name = "omap-mailbox",
217 static inline void omap_init_mbox(void)
219 if (cpu_is_omap24xx()) {
220 mbox_device.resource = omap2_mbox_resources;
221 mbox_device.num_resources = omap2_mbox_resources_sz;
222 } else if (cpu_is_omap34xx()) {
223 mbox_device.resource = omap3_mbox_resources;
224 mbox_device.num_resources = omap3_mbox_resources_sz;
225 } else if (cpu_is_omap44xx()) {
226 mbox_device.resource = omap4_mbox_resources;
227 mbox_device.num_resources = omap4_mbox_resources_sz;
229 pr_err("%s: platform not supported\n", __func__);
232 platform_device_register(&mbox_device);
235 static inline void omap_init_mbox(void) { }
236 #endif /* CONFIG_OMAP_MBOX_FWK */
238 static inline void omap_init_sti(void) {}
240 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
242 #include <plat/mcspi.h>
244 #define OMAP2_MCSPI1_BASE 0x48098000
245 #define OMAP2_MCSPI2_BASE 0x4809a000
246 #define OMAP2_MCSPI3_BASE 0x480b8000
247 #define OMAP2_MCSPI4_BASE 0x480ba000
249 #define OMAP4_MCSPI1_BASE 0x48098100
250 #define OMAP4_MCSPI2_BASE 0x4809a100
251 #define OMAP4_MCSPI3_BASE 0x480b8100
252 #define OMAP4_MCSPI4_BASE 0x480ba100
254 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
258 static struct resource omap2_mcspi1_resources[] = {
260 .start = OMAP2_MCSPI1_BASE,
261 .end = OMAP2_MCSPI1_BASE + 0xff,
262 .flags = IORESOURCE_MEM,
266 static struct platform_device omap2_mcspi1 = {
267 .name = "omap2_mcspi",
269 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
270 .resource = omap2_mcspi1_resources,
272 .platform_data = &omap2_mcspi1_config,
276 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
280 static struct resource omap2_mcspi2_resources[] = {
282 .start = OMAP2_MCSPI2_BASE,
283 .end = OMAP2_MCSPI2_BASE + 0xff,
284 .flags = IORESOURCE_MEM,
288 static struct platform_device omap2_mcspi2 = {
289 .name = "omap2_mcspi",
291 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
292 .resource = omap2_mcspi2_resources,
294 .platform_data = &omap2_mcspi2_config,
298 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
299 defined(CONFIG_ARCH_OMAP4)
300 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
304 static struct resource omap2_mcspi3_resources[] = {
306 .start = OMAP2_MCSPI3_BASE,
307 .end = OMAP2_MCSPI3_BASE + 0xff,
308 .flags = IORESOURCE_MEM,
312 static struct platform_device omap2_mcspi3 = {
313 .name = "omap2_mcspi",
315 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
316 .resource = omap2_mcspi3_resources,
318 .platform_data = &omap2_mcspi3_config,
323 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
324 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
328 static struct resource omap2_mcspi4_resources[] = {
330 .start = OMAP2_MCSPI4_BASE,
331 .end = OMAP2_MCSPI4_BASE + 0xff,
332 .flags = IORESOURCE_MEM,
336 static struct platform_device omap2_mcspi4 = {
337 .name = "omap2_mcspi",
339 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
340 .resource = omap2_mcspi4_resources,
342 .platform_data = &omap2_mcspi4_config,
347 #ifdef CONFIG_ARCH_OMAP4
348 static inline void omap4_mcspi_fixup(void)
350 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
351 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
352 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
353 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
354 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
355 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
356 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
357 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
360 static inline void omap4_mcspi_fixup(void)
365 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
366 defined(CONFIG_ARCH_OMAP4)
367 static inline void omap2_mcspi3_init(void)
369 platform_device_register(&omap2_mcspi3);
372 static inline void omap2_mcspi3_init(void)
377 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
378 static inline void omap2_mcspi4_init(void)
380 platform_device_register(&omap2_mcspi4);
383 static inline void omap2_mcspi4_init(void)
388 static void omap_init_mcspi(void)
390 if (cpu_is_omap44xx())
393 platform_device_register(&omap2_mcspi1);
394 platform_device_register(&omap2_mcspi2);
396 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
399 if (cpu_is_omap343x() || cpu_is_omap44xx())
404 static inline void omap_init_mcspi(void) {}
407 static struct resource omap2_pmu_resource = {
410 .flags = IORESOURCE_IRQ,
413 static struct resource omap3_pmu_resource = {
414 .start = INT_34XX_BENCH_MPU_EMUL,
415 .end = INT_34XX_BENCH_MPU_EMUL,
416 .flags = IORESOURCE_IRQ,
419 static struct platform_device omap_pmu_device = {
421 .id = ARM_PMU_DEVICE_CPU,
425 static void omap_init_pmu(void)
427 if (cpu_is_omap24xx())
428 omap_pmu_device.resource = &omap2_pmu_resource;
429 else if (cpu_is_omap34xx())
430 omap_pmu_device.resource = &omap3_pmu_resource;
434 platform_device_register(&omap_pmu_device);
438 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
440 #ifdef CONFIG_ARCH_OMAP2
441 static struct resource omap2_sham_resources[] = {
443 .start = OMAP24XX_SEC_SHA1MD5_BASE,
444 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
445 .flags = IORESOURCE_MEM,
448 .start = INT_24XX_SHA1MD5,
449 .flags = IORESOURCE_IRQ,
452 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
454 #define omap2_sham_resources NULL
455 #define omap2_sham_resources_sz 0
458 #ifdef CONFIG_ARCH_OMAP3
459 static struct resource omap3_sham_resources[] = {
461 .start = OMAP34XX_SEC_SHA1MD5_BASE,
462 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
463 .flags = IORESOURCE_MEM,
466 .start = INT_34XX_SHA1MD52_IRQ,
467 .flags = IORESOURCE_IRQ,
470 .start = OMAP34XX_DMA_SHA1MD5_RX,
471 .flags = IORESOURCE_DMA,
474 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
476 #define omap3_sham_resources NULL
477 #define omap3_sham_resources_sz 0
480 static struct platform_device sham_device = {
485 static void omap_init_sham(void)
487 if (cpu_is_omap24xx()) {
488 sham_device.resource = omap2_sham_resources;
489 sham_device.num_resources = omap2_sham_resources_sz;
490 } else if (cpu_is_omap34xx()) {
491 sham_device.resource = omap3_sham_resources;
492 sham_device.num_resources = omap3_sham_resources_sz;
494 pr_err("%s: platform not supported\n", __func__);
497 platform_device_register(&sham_device);
500 static inline void omap_init_sham(void) { }
503 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
505 #ifdef CONFIG_ARCH_OMAP2
506 static struct resource omap2_aes_resources[] = {
508 .start = OMAP24XX_SEC_AES_BASE,
509 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
510 .flags = IORESOURCE_MEM,
513 .start = OMAP24XX_DMA_AES_TX,
514 .flags = IORESOURCE_DMA,
517 .start = OMAP24XX_DMA_AES_RX,
518 .flags = IORESOURCE_DMA,
521 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
523 #define omap2_aes_resources NULL
524 #define omap2_aes_resources_sz 0
527 #ifdef CONFIG_ARCH_OMAP3
528 static struct resource omap3_aes_resources[] = {
530 .start = OMAP34XX_SEC_AES_BASE,
531 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
532 .flags = IORESOURCE_MEM,
535 .start = OMAP34XX_DMA_AES2_TX,
536 .flags = IORESOURCE_DMA,
539 .start = OMAP34XX_DMA_AES2_RX,
540 .flags = IORESOURCE_DMA,
543 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
545 #define omap3_aes_resources NULL
546 #define omap3_aes_resources_sz 0
549 static struct platform_device aes_device = {
554 static void omap_init_aes(void)
556 if (cpu_is_omap24xx()) {
557 aes_device.resource = omap2_aes_resources;
558 aes_device.num_resources = omap2_aes_resources_sz;
559 } else if (cpu_is_omap34xx()) {
560 aes_device.resource = omap3_aes_resources;
561 aes_device.num_resources = omap3_aes_resources_sz;
563 pr_err("%s: platform not supported\n", __func__);
566 platform_device_register(&aes_device);
570 static inline void omap_init_aes(void) { }
573 /*-------------------------------------------------------------------------*/
575 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
577 #define MMCHS_SYSCONFIG 0x0010
578 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
579 #define MMCHS_SYSSTATUS 0x0014
580 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
582 static struct platform_device dummy_pdev = {
584 .bus = &platform_bus_type,
589 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
591 * Ensure that each MMC controller is fully reset. Controllers
592 * left in an unknown state (by bootloader) may prevent retention
593 * or OFF-mode. This is especially important in cases where the
594 * MMC driver is not enabled, _or_ built as a module.
596 * In order for reset to work, interface, functional and debounce
597 * clocks must be enabled. The debounce clock comes from func_32k_clk
598 * and is not under SW control, so we only enable i- and f-clocks.
600 static void __init omap_hsmmc_reset(void)
602 u32 i, nr_controllers;
604 if (cpu_is_omap242x())
607 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
608 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
610 for (i = 0; i < nr_controllers; i++) {
612 struct clk *iclk, *fclk;
613 struct device *dev = &dummy_pdev.dev;
617 base = OMAP2_MMC1_BASE;
620 base = OMAP2_MMC2_BASE;
623 base = OMAP3_MMC3_BASE;
626 if (!cpu_is_omap44xx())
628 base = OMAP4_MMC4_BASE;
631 if (!cpu_is_omap44xx())
633 base = OMAP4_MMC5_BASE;
637 if (cpu_is_omap44xx())
638 base += OMAP4_MMC_REG_OFFSET;
641 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
642 iclk = clk_get(dev, "ick");
643 if (iclk && clk_enable(iclk))
646 fclk = clk_get(dev, "fck");
647 if (fclk && clk_enable(fclk))
650 if (!iclk || !fclk) {
652 "%s: Unable to enable clocks for MMC%d, "
653 "cannot reset.\n", __func__, i);
657 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
658 v = omap_readl(base + MMCHS_SYSSTATUS);
659 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
660 MMCHS_SYSSTATUS_RESETDONE))
674 static inline void omap_hsmmc_reset(void) {}
677 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
678 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
680 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
683 if ((mmc_controller->slots[0].switch_pin > 0) && \
684 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
685 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
686 OMAP_PIN_INPUT_PULLUP);
687 if ((mmc_controller->slots[0].gpio_wp > 0) && \
688 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
689 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
690 OMAP_PIN_INPUT_PULLUP);
692 if (cpu_is_omap2420() && controller_nr == 0) {
693 omap_mux_init_signal("sdmmc_cmd", 0);
694 omap_mux_init_signal("sdmmc_clki", 0);
695 omap_mux_init_signal("sdmmc_clko", 0);
696 omap_mux_init_signal("sdmmc_dat0", 0);
697 omap_mux_init_signal("sdmmc_dat_dir0", 0);
698 omap_mux_init_signal("sdmmc_cmd_dir", 0);
699 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
700 omap_mux_init_signal("sdmmc_dat1", 0);
701 omap_mux_init_signal("sdmmc_dat2", 0);
702 omap_mux_init_signal("sdmmc_dat3", 0);
703 omap_mux_init_signal("sdmmc_dat_dir1", 0);
704 omap_mux_init_signal("sdmmc_dat_dir2", 0);
705 omap_mux_init_signal("sdmmc_dat_dir3", 0);
709 * Use internal loop-back in MMC/SDIO Module Input Clock
712 if (mmc_controller->slots[0].internal_clock) {
713 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
715 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
719 if (cpu_is_omap34xx()) {
720 if (controller_nr == 0) {
721 omap_mux_init_signal("sdmmc1_clk",
722 OMAP_PIN_INPUT_PULLUP);
723 omap_mux_init_signal("sdmmc1_cmd",
724 OMAP_PIN_INPUT_PULLUP);
725 omap_mux_init_signal("sdmmc1_dat0",
726 OMAP_PIN_INPUT_PULLUP);
727 if (mmc_controller->slots[0].caps &
728 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
729 omap_mux_init_signal("sdmmc1_dat1",
730 OMAP_PIN_INPUT_PULLUP);
731 omap_mux_init_signal("sdmmc1_dat2",
732 OMAP_PIN_INPUT_PULLUP);
733 omap_mux_init_signal("sdmmc1_dat3",
734 OMAP_PIN_INPUT_PULLUP);
736 if (mmc_controller->slots[0].caps &
737 MMC_CAP_8_BIT_DATA) {
738 omap_mux_init_signal("sdmmc1_dat4",
739 OMAP_PIN_INPUT_PULLUP);
740 omap_mux_init_signal("sdmmc1_dat5",
741 OMAP_PIN_INPUT_PULLUP);
742 omap_mux_init_signal("sdmmc1_dat6",
743 OMAP_PIN_INPUT_PULLUP);
744 omap_mux_init_signal("sdmmc1_dat7",
745 OMAP_PIN_INPUT_PULLUP);
748 if (controller_nr == 1) {
750 omap_mux_init_signal("sdmmc2_clk",
751 OMAP_PIN_INPUT_PULLUP);
752 omap_mux_init_signal("sdmmc2_cmd",
753 OMAP_PIN_INPUT_PULLUP);
754 omap_mux_init_signal("sdmmc2_dat0",
755 OMAP_PIN_INPUT_PULLUP);
758 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
759 * in the board-*.c files
761 if (mmc_controller->slots[0].caps &
762 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
763 omap_mux_init_signal("sdmmc2_dat1",
764 OMAP_PIN_INPUT_PULLUP);
765 omap_mux_init_signal("sdmmc2_dat2",
766 OMAP_PIN_INPUT_PULLUP);
767 omap_mux_init_signal("sdmmc2_dat3",
768 OMAP_PIN_INPUT_PULLUP);
770 if (mmc_controller->slots[0].caps &
771 MMC_CAP_8_BIT_DATA) {
772 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
773 OMAP_PIN_INPUT_PULLUP);
774 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
775 OMAP_PIN_INPUT_PULLUP);
776 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
777 OMAP_PIN_INPUT_PULLUP);
778 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
779 OMAP_PIN_INPUT_PULLUP);
784 * For MMC3 the pins need to be muxed in the board-*.c files
789 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
795 for (i = 0; i < nr_controllers; i++) {
796 unsigned long base, size;
797 unsigned int irq = 0;
802 omap2_mmc_mux(mmc_data[i], i);
806 base = OMAP2_MMC1_BASE;
807 irq = INT_24XX_MMC_IRQ;
810 base = OMAP2_MMC2_BASE;
811 irq = INT_24XX_MMC2_IRQ;
814 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
816 base = OMAP3_MMC3_BASE;
817 irq = INT_34XX_MMC3_IRQ;
820 if (!cpu_is_omap44xx())
822 base = OMAP4_MMC4_BASE;
823 irq = OMAP44XX_IRQ_MMC4;
826 if (!cpu_is_omap44xx())
828 base = OMAP4_MMC5_BASE;
829 irq = OMAP44XX_IRQ_MMC5;
835 if (cpu_is_omap2420()) {
836 size = OMAP2420_MMC_SIZE;
838 } else if (cpu_is_omap44xx()) {
840 irq += OMAP44XX_IRQ_GIC_START;
841 size = OMAP4_HSMMC_SIZE;
842 name = "mmci-omap-hs";
844 size = OMAP3_HSMMC_SIZE;
845 name = "mmci-omap-hs";
847 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
853 /*-------------------------------------------------------------------------*/
855 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
856 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
857 #define OMAP_HDQ_BASE 0x480B2000
859 static struct resource omap_hdq_resources[] = {
861 .start = OMAP_HDQ_BASE,
862 .end = OMAP_HDQ_BASE + 0x1C,
863 .flags = IORESOURCE_MEM,
866 .start = INT_24XX_HDQ_IRQ,
867 .flags = IORESOURCE_IRQ,
870 static struct platform_device omap_hdq_dev = {
874 .platform_data = NULL,
876 .num_resources = ARRAY_SIZE(omap_hdq_resources),
877 .resource = omap_hdq_resources,
879 static inline void omap_hdq_init(void)
881 (void) platform_device_register(&omap_hdq_dev);
884 static inline void omap_hdq_init(void) {}
887 /*---------------------------------------------------------------------------*/
889 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
890 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
891 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
892 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
895 static struct resource omap_vout_resource[2] = {
899 static struct platform_device omap_vout_device = {
901 .num_resources = ARRAY_SIZE(omap_vout_resource),
902 .resource = &omap_vout_resource[0],
905 static void omap_init_vout(void)
907 if (platform_device_register(&omap_vout_device) < 0)
908 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
911 static inline void omap_init_vout(void) {}
914 /*-------------------------------------------------------------------------*/
917 * Inorder to avoid any assumptions from bootloader regarding WDT
918 * settings, WDT module is reset during init. This enables the watchdog
919 * timer. Hence it is required to disable the watchdog after the WDT reset
920 * during init. Otherwise the system would reboot as per the default
921 * watchdog timer registers settings.
923 #define OMAP_WDT_WPS (0x34)
924 #define OMAP_WDT_SPR (0x48)
926 static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
932 pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
936 base = omap_hwmod_get_mpu_rt_va(oh);
938 pr_err("%s: Could not get the base address for %s\n",
943 /* Enable the clocks before accessing the WDT registers */
944 ret = omap_hwmod_enable(oh);
946 pr_err("%s: Could not enable clocks for %s\n",
951 /* sequence required to disable watchdog */
952 __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
953 while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
956 __raw_writel(0x5555, base + OMAP_WDT_SPR);
957 while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
960 ret = omap_hwmod_idle(oh);
962 pr_err("%s: Could not disable clocks for %s\n",
968 static void __init omap_disable_wdt(void)
970 if (cpu_class_is_omap2())
971 omap_hwmod_for_each_by_class("wd_timer",
972 omap2_disable_wdt, NULL);
976 static int __init omap2_init_devices(void)
978 /* please keep these calls, and their implementations above,
979 * in alphabetical order so they're easier to sort through.
995 arch_initcall(omap2_init_devices);
997 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
998 struct omap_device_pm_latency omap_wdt_latency[] = {
1000 .deactivate_func = omap_device_idle_hwmods,
1001 .activate_func = omap_device_enable_hwmods,
1002 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
1006 static int __init omap_init_wdt(void)
1009 struct omap_device *od;
1010 struct omap_hwmod *oh;
1011 char *oh_name = "wd_timer2";
1012 char *dev_name = "omap_wdt";
1014 if (!cpu_class_is_omap2())
1017 oh = omap_hwmod_lookup(oh_name);
1019 pr_err("Could not look up wd_timer%d hwmod\n", id);
1023 od = omap_device_build(dev_name, id, oh, NULL, 0,
1025 ARRAY_SIZE(omap_wdt_latency), 0);
1026 WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
1027 dev_name, oh->name);
1030 subsys_initcall(omap_init_wdt);