2 * linux/arch/arm/mach-omap2/devices.c
4 * OMAP2 platform device setup/initialization
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
17 #include <linux/clk.h>
19 #include <mach/hardware.h>
20 #include <asm/mach-types.h>
21 #include <asm/mach/map.h>
23 #include <plat/control.h>
25 #include <plat/board.h>
27 #include <mach/gpio.h>
30 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
32 static struct resource cam_resources[] = {
34 .start = OMAP24XX_CAMERA_BASE,
35 .end = OMAP24XX_CAMERA_BASE + 0xfff,
36 .flags = IORESOURCE_MEM,
39 .start = INT_24XX_CAM_IRQ,
40 .flags = IORESOURCE_IRQ,
44 static struct platform_device omap_cam_device = {
45 .name = "omap24xxcam",
47 .num_resources = ARRAY_SIZE(cam_resources),
48 .resource = cam_resources,
51 static inline void omap_init_camera(void)
53 platform_device_register(&omap_cam_device);
56 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
58 static struct resource omap3isp_resources[] = {
60 .start = OMAP3430_ISP_BASE,
61 .end = OMAP3430_ISP_END,
62 .flags = IORESOURCE_MEM,
65 .start = OMAP3430_ISP_CBUFF_BASE,
66 .end = OMAP3430_ISP_CBUFF_END,
67 .flags = IORESOURCE_MEM,
70 .start = OMAP3430_ISP_CCP2_BASE,
71 .end = OMAP3430_ISP_CCP2_END,
72 .flags = IORESOURCE_MEM,
75 .start = OMAP3430_ISP_CCDC_BASE,
76 .end = OMAP3430_ISP_CCDC_END,
77 .flags = IORESOURCE_MEM,
80 .start = OMAP3430_ISP_HIST_BASE,
81 .end = OMAP3430_ISP_HIST_END,
82 .flags = IORESOURCE_MEM,
85 .start = OMAP3430_ISP_H3A_BASE,
86 .end = OMAP3430_ISP_H3A_END,
87 .flags = IORESOURCE_MEM,
90 .start = OMAP3430_ISP_PREV_BASE,
91 .end = OMAP3430_ISP_PREV_END,
92 .flags = IORESOURCE_MEM,
95 .start = OMAP3430_ISP_RESZ_BASE,
96 .end = OMAP3430_ISP_RESZ_END,
97 .flags = IORESOURCE_MEM,
100 .start = OMAP3430_ISP_SBL_BASE,
101 .end = OMAP3430_ISP_SBL_END,
102 .flags = IORESOURCE_MEM,
105 .start = OMAP3430_ISP_CSI2A_BASE,
106 .end = OMAP3430_ISP_CSI2A_END,
107 .flags = IORESOURCE_MEM,
110 .start = OMAP3430_ISP_CSI2PHY_BASE,
111 .end = OMAP3430_ISP_CSI2PHY_END,
112 .flags = IORESOURCE_MEM,
115 .start = INT_34XX_CAM_IRQ,
116 .flags = IORESOURCE_IRQ,
120 static struct platform_device omap3isp_device = {
123 .num_resources = ARRAY_SIZE(omap3isp_resources),
124 .resource = omap3isp_resources,
127 static inline void omap_init_camera(void)
129 platform_device_register(&omap3isp_device);
132 static inline void omap_init_camera(void)
137 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
139 #define MBOX_REG_SIZE 0x120
141 #ifdef CONFIG_ARCH_OMAP2
142 static struct resource omap_mbox_resources[] = {
144 .start = OMAP24XX_MAILBOX_BASE,
145 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
146 .flags = IORESOURCE_MEM,
149 .start = INT_24XX_MAIL_U0_MPU,
150 .flags = IORESOURCE_IRQ,
153 .start = INT_24XX_MAIL_U3_MPU,
154 .flags = IORESOURCE_IRQ,
159 #ifdef CONFIG_ARCH_OMAP3
160 static struct resource omap_mbox_resources[] = {
162 .start = OMAP34XX_MAILBOX_BASE,
163 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
164 .flags = IORESOURCE_MEM,
167 .start = INT_24XX_MAIL_U0_MPU,
168 .flags = IORESOURCE_IRQ,
173 #ifdef CONFIG_ARCH_OMAP4
175 #define OMAP4_MBOX_REG_SIZE 0x130
176 static struct resource omap_mbox_resources[] = {
178 .start = OMAP44XX_MAILBOX_BASE,
179 .end = OMAP44XX_MAILBOX_BASE +
180 OMAP4_MBOX_REG_SIZE - 1,
181 .flags = IORESOURCE_MEM,
184 .start = INT_44XX_MAIL_U0_MPU,
185 .flags = IORESOURCE_IRQ,
190 static struct platform_device mbox_device = {
191 .name = "omap2-mailbox",
195 static inline void omap_init_mbox(void)
197 if (cpu_is_omap2420() || cpu_is_omap3430() || cpu_is_omap44xx()) {
198 mbox_device.num_resources = ARRAY_SIZE(omap_mbox_resources);
199 mbox_device.resource = omap_mbox_resources;
201 pr_err("%s: platform not supported\n", __func__);
204 platform_device_register(&mbox_device);
207 static inline void omap_init_mbox(void) { }
208 #endif /* CONFIG_OMAP_MBOX_FWK */
210 #if defined(CONFIG_OMAP_STI)
212 #if defined(CONFIG_ARCH_OMAP2)
214 #define OMAP2_STI_BASE 0x48068000
215 #define OMAP2_STI_CHANNEL_BASE 0x54000000
216 #define OMAP2_STI_IRQ 4
218 static struct resource sti_resources[] = {
220 .start = OMAP2_STI_BASE,
221 .end = OMAP2_STI_BASE + 0x7ff,
222 .flags = IORESOURCE_MEM,
225 .start = OMAP2_STI_CHANNEL_BASE,
226 .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
227 .flags = IORESOURCE_MEM,
230 .start = OMAP2_STI_IRQ,
231 .flags = IORESOURCE_IRQ,
234 #elif defined(CONFIG_ARCH_OMAP3)
236 #define OMAP3_SDTI_BASE 0x54500000
237 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
239 static struct resource sti_resources[] = {
241 .start = OMAP3_SDTI_BASE,
242 .end = OMAP3_SDTI_BASE + 0xFFF,
243 .flags = IORESOURCE_MEM,
246 .start = OMAP3_SDTI_CHANNEL_BASE,
247 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
248 .flags = IORESOURCE_MEM,
254 static struct platform_device sti_device = {
257 .num_resources = ARRAY_SIZE(sti_resources),
258 .resource = sti_resources,
261 static inline void omap_init_sti(void)
263 platform_device_register(&sti_device);
266 static inline void omap_init_sti(void) {}
269 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
271 #include <plat/mcspi.h>
273 #define OMAP2_MCSPI1_BASE 0x48098000
274 #define OMAP2_MCSPI2_BASE 0x4809a000
275 #define OMAP2_MCSPI3_BASE 0x480b8000
276 #define OMAP2_MCSPI4_BASE 0x480ba000
278 #define OMAP4_MCSPI1_BASE 0x48098100
279 #define OMAP4_MCSPI2_BASE 0x4809a100
280 #define OMAP4_MCSPI3_BASE 0x480b8100
281 #define OMAP4_MCSPI4_BASE 0x480ba100
283 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
287 static struct resource omap2_mcspi1_resources[] = {
289 .start = OMAP2_MCSPI1_BASE,
290 .end = OMAP2_MCSPI1_BASE + 0xff,
291 .flags = IORESOURCE_MEM,
295 static struct platform_device omap2_mcspi1 = {
296 .name = "omap2_mcspi",
298 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
299 .resource = omap2_mcspi1_resources,
301 .platform_data = &omap2_mcspi1_config,
305 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
309 static struct resource omap2_mcspi2_resources[] = {
311 .start = OMAP2_MCSPI2_BASE,
312 .end = OMAP2_MCSPI2_BASE + 0xff,
313 .flags = IORESOURCE_MEM,
317 static struct platform_device omap2_mcspi2 = {
318 .name = "omap2_mcspi",
320 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
321 .resource = omap2_mcspi2_resources,
323 .platform_data = &omap2_mcspi2_config,
327 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
328 defined(CONFIG_ARCH_OMAP4)
329 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
333 static struct resource omap2_mcspi3_resources[] = {
335 .start = OMAP2_MCSPI3_BASE,
336 .end = OMAP2_MCSPI3_BASE + 0xff,
337 .flags = IORESOURCE_MEM,
341 static struct platform_device omap2_mcspi3 = {
342 .name = "omap2_mcspi",
344 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
345 .resource = omap2_mcspi3_resources,
347 .platform_data = &omap2_mcspi3_config,
352 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
353 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
357 static struct resource omap2_mcspi4_resources[] = {
359 .start = OMAP2_MCSPI4_BASE,
360 .end = OMAP2_MCSPI4_BASE + 0xff,
361 .flags = IORESOURCE_MEM,
365 static struct platform_device omap2_mcspi4 = {
366 .name = "omap2_mcspi",
368 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
369 .resource = omap2_mcspi4_resources,
371 .platform_data = &omap2_mcspi4_config,
376 #ifdef CONFIG_ARCH_OMAP4
377 static inline void omap4_mcspi_fixup(void)
379 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
380 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
381 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
382 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
383 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
384 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
385 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
386 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
389 static inline void omap4_mcspi_fixup(void)
394 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
395 defined(CONFIG_ARCH_OMAP4)
396 static inline void omap2_mcspi3_init(void)
398 platform_device_register(&omap2_mcspi3);
401 static inline void omap2_mcspi3_init(void)
406 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
407 static inline void omap2_mcspi4_init(void)
409 platform_device_register(&omap2_mcspi4);
412 static inline void omap2_mcspi4_init(void)
417 static void omap_init_mcspi(void)
419 if (cpu_is_omap44xx())
422 platform_device_register(&omap2_mcspi1);
423 platform_device_register(&omap2_mcspi2);
425 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
428 if (cpu_is_omap343x() || cpu_is_omap44xx())
433 static inline void omap_init_mcspi(void) {}
436 #ifdef CONFIG_OMAP_SHA1_MD5
437 static struct resource sha1_md5_resources[] = {
439 .start = OMAP24XX_SEC_SHA1MD5_BASE,
440 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
441 .flags = IORESOURCE_MEM,
444 .start = INT_24XX_SHA1MD5,
445 .flags = IORESOURCE_IRQ,
449 static struct platform_device sha1_md5_device = {
450 .name = "OMAP SHA1/MD5",
452 .num_resources = ARRAY_SIZE(sha1_md5_resources),
453 .resource = sha1_md5_resources,
456 static void omap_init_sha1_md5(void)
458 platform_device_register(&sha1_md5_device);
461 static inline void omap_init_sha1_md5(void) { }
464 /*-------------------------------------------------------------------------*/
466 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
468 #define MMCHS_SYSCONFIG 0x0010
469 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
470 #define MMCHS_SYSSTATUS 0x0014
471 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
473 static struct platform_device dummy_pdev = {
475 .bus = &platform_bus_type,
480 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
482 * Ensure that each MMC controller is fully reset. Controllers
483 * left in an unknown state (by bootloader) may prevent retention
484 * or OFF-mode. This is especially important in cases where the
485 * MMC driver is not enabled, _or_ built as a module.
487 * In order for reset to work, interface, functional and debounce
488 * clocks must be enabled. The debounce clock comes from func_32k_clk
489 * and is not under SW control, so we only enable i- and f-clocks.
491 static void __init omap_hsmmc_reset(void)
493 u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
494 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
496 for (i = 0; i < nr_controllers; i++) {
498 struct clk *iclk, *fclk;
499 struct device *dev = &dummy_pdev.dev;
503 base = OMAP2_MMC1_BASE;
506 base = OMAP2_MMC2_BASE;
509 base = OMAP3_MMC3_BASE;
512 if (!cpu_is_omap44xx())
514 base = OMAP4_MMC4_BASE;
517 if (!cpu_is_omap44xx())
519 base = OMAP4_MMC5_BASE;
523 if (cpu_is_omap44xx())
524 base += OMAP4_MMC_REG_OFFSET;
527 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
528 iclk = clk_get(dev, "ick");
529 if (iclk && clk_enable(iclk))
532 fclk = clk_get(dev, "fck");
533 if (fclk && clk_enable(fclk))
536 if (!iclk || !fclk) {
538 "%s: Unable to enable clocks for MMC%d, "
539 "cannot reset.\n", __func__, i);
543 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
544 v = omap_readl(base + MMCHS_SYSSTATUS);
545 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
546 MMCHS_SYSSTATUS_RESETDONE))
560 static inline void omap_hsmmc_reset(void) {}
563 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
564 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
566 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
569 if (cpu_is_omap2420() && controller_nr == 0) {
570 omap_cfg_reg(H18_24XX_MMC_CMD);
571 omap_cfg_reg(H15_24XX_MMC_CLKI);
572 omap_cfg_reg(G19_24XX_MMC_CLKO);
573 omap_cfg_reg(F20_24XX_MMC_DAT0);
574 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
575 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
576 if (mmc_controller->slots[0].wires == 4) {
577 omap_cfg_reg(H14_24XX_MMC_DAT1);
578 omap_cfg_reg(E19_24XX_MMC_DAT2);
579 omap_cfg_reg(D19_24XX_MMC_DAT3);
580 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
581 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
582 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
586 * Use internal loop-back in MMC/SDIO Module Input Clock
589 if (mmc_controller->slots[0].internal_clock) {
590 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
592 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
596 if (cpu_is_omap34xx()) {
597 if (controller_nr == 0) {
598 omap_cfg_reg(N28_3430_MMC1_CLK);
599 omap_cfg_reg(M27_3430_MMC1_CMD);
600 omap_cfg_reg(N27_3430_MMC1_DAT0);
601 if (mmc_controller->slots[0].wires == 4 ||
602 mmc_controller->slots[0].wires == 8) {
603 omap_cfg_reg(N26_3430_MMC1_DAT1);
604 omap_cfg_reg(N25_3430_MMC1_DAT2);
605 omap_cfg_reg(P28_3430_MMC1_DAT3);
607 if (mmc_controller->slots[0].wires == 8) {
608 omap_cfg_reg(P27_3430_MMC1_DAT4);
609 omap_cfg_reg(P26_3430_MMC1_DAT5);
610 omap_cfg_reg(R27_3430_MMC1_DAT6);
611 omap_cfg_reg(R25_3430_MMC1_DAT7);
614 if (controller_nr == 1) {
616 omap_cfg_reg(AE2_3430_MMC2_CLK);
617 omap_cfg_reg(AG5_3430_MMC2_CMD);
618 omap_cfg_reg(AH5_3430_MMC2_DAT0);
621 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
622 * in the board-*.c files
624 if (mmc_controller->slots[0].wires == 4 ||
625 mmc_controller->slots[0].wires == 8) {
626 omap_cfg_reg(AH4_3430_MMC2_DAT1);
627 omap_cfg_reg(AG4_3430_MMC2_DAT2);
628 omap_cfg_reg(AF4_3430_MMC2_DAT3);
630 if (mmc_controller->slots[0].wires == 8) {
631 omap_cfg_reg(AE4_3430_MMC2_DAT4);
632 omap_cfg_reg(AH3_3430_MMC2_DAT5);
633 omap_cfg_reg(AF3_3430_MMC2_DAT6);
634 omap_cfg_reg(AE3_3430_MMC2_DAT7);
639 * For MMC3 the pins need to be muxed in the board-*.c files
644 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
650 for (i = 0; i < nr_controllers; i++) {
651 unsigned long base, size;
652 unsigned int irq = 0;
657 omap2_mmc_mux(mmc_data[i], i);
661 base = OMAP2_MMC1_BASE;
662 irq = INT_24XX_MMC_IRQ;
665 base = OMAP2_MMC2_BASE;
666 irq = INT_24XX_MMC2_IRQ;
669 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
671 base = OMAP3_MMC3_BASE;
672 irq = INT_34XX_MMC3_IRQ;
675 if (!cpu_is_omap44xx())
677 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
678 irq = INT_44XX_MMC4_IRQ;
681 if (!cpu_is_omap44xx())
683 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
684 irq = INT_44XX_MMC5_IRQ;
690 if (cpu_is_omap2420()) {
691 size = OMAP2420_MMC_SIZE;
693 } else if (cpu_is_omap44xx()) {
695 base += OMAP4_MMC_REG_OFFSET;
696 irq += IRQ_GIC_START;
698 size = OMAP4_HSMMC_SIZE;
699 name = "mmci-omap-hs";
701 size = OMAP3_HSMMC_SIZE;
702 name = "mmci-omap-hs";
704 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
710 /*-------------------------------------------------------------------------*/
712 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
713 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
714 #define OMAP_HDQ_BASE 0x480B2000
716 static struct resource omap_hdq_resources[] = {
718 .start = OMAP_HDQ_BASE,
719 .end = OMAP_HDQ_BASE + 0x1C,
720 .flags = IORESOURCE_MEM,
723 .start = INT_24XX_HDQ_IRQ,
724 .flags = IORESOURCE_IRQ,
727 static struct platform_device omap_hdq_dev = {
731 .platform_data = NULL,
733 .num_resources = ARRAY_SIZE(omap_hdq_resources),
734 .resource = omap_hdq_resources,
736 static inline void omap_hdq_init(void)
738 (void) platform_device_register(&omap_hdq_dev);
741 static inline void omap_hdq_init(void) {}
744 /*-------------------------------------------------------------------------*/
746 static int __init omap2_init_devices(void)
748 /* please keep these calls, and their implementations above,
749 * in alphabetical order so they're easier to sort through.
757 omap_init_sha1_md5();
761 arch_initcall(omap2_init_devices);