2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <video/omapdss.h>
28 #include <plat/omap_hwmod.h>
29 #include <plat/omap_device.h>
30 #include <plat/omap-pm.h>
37 #define DISPC_CONTROL 0x0040
38 #define DISPC_CONTROL2 0x0238
39 #define DISPC_IRQSTATUS 0x0018
41 #define DSS_SYSCONFIG 0x10
42 #define DSS_SYSSTATUS 0x14
43 #define DSS_CONTROL 0x40
44 #define DSS_SDI_CONTROL 0x44
45 #define DSS_PLL_CONTROL 0x48
47 #define LCD_EN_MASK (0x1 << 0)
48 #define DIGIT_EN_MASK (0x1 << 1)
50 #define FRAMEDONE_IRQ_SHIFT 0
51 #define EVSYNC_EVEN_IRQ_SHIFT 2
52 #define EVSYNC_ODD_IRQ_SHIFT 3
53 #define FRAMEDONE2_IRQ_SHIFT 22
54 #define FRAMEDONETV_IRQ_SHIFT 24
57 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
58 * reset before deciding that something has gone wrong
60 #define FRAMEDONE_IRQ_TIMEOUT 100
62 static struct platform_device omap_display_device = {
66 .platform_data = NULL,
70 struct omap_dss_hwmod_data {
76 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
77 { "dss_core", "omapdss_dss", -1 },
78 { "dss_dispc", "omapdss_dispc", -1 },
79 { "dss_rfbi", "omapdss_rfbi", -1 },
80 { "dss_venc", "omapdss_venc", -1 },
83 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
84 { "dss_core", "omapdss_dss", -1 },
85 { "dss_dispc", "omapdss_dispc", -1 },
86 { "dss_rfbi", "omapdss_rfbi", -1 },
87 { "dss_venc", "omapdss_venc", -1 },
88 { "dss_dsi1", "omapdss_dsi", 0 },
91 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
92 { "dss_core", "omapdss_dss", -1 },
93 { "dss_dispc", "omapdss_dispc", -1 },
94 { "dss_rfbi", "omapdss_rfbi", -1 },
95 { "dss_venc", "omapdss_venc", -1 },
96 { "dss_dsi1", "omapdss_dsi", 0 },
97 { "dss_dsi2", "omapdss_dsi", 1 },
98 { "dss_hdmi", "omapdss_hdmi", -1 },
101 static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
106 omap_mux_init_signal("hdmi_cec",
107 OMAP_PIN_INPUT_PULLUP);
108 omap_mux_init_signal("hdmi_ddc_scl",
109 OMAP_PIN_INPUT_PULLUP);
110 omap_mux_init_signal("hdmi_ddc_sda",
111 OMAP_PIN_INPUT_PULLUP);
114 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
115 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
116 * internal pull up resistor.
118 if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
119 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
120 reg = omap4_ctrl_pad_readl(control_i2c_1);
121 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
122 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
123 omap4_ctrl_pad_writel(reg, control_i2c_1);
127 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
129 u32 enable_mask, enable_shift;
130 u32 pipd_mask, pipd_shift;
134 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
135 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
136 pipd_mask = OMAP4_DSI1_PIPD_MASK;
137 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
138 } else if (dsi_id == 1) {
139 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
140 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
141 pipd_mask = OMAP4_DSI2_PIPD_MASK;
142 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
147 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
152 reg |= (lanes << enable_shift) & enable_mask;
153 reg |= (lanes << pipd_shift) & pipd_mask;
155 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
160 int omap_hdmi_init(enum omap_hdmi_flags flags)
162 if (cpu_is_omap44xx())
163 omap4_hdmi_mux_pads(flags);
168 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
170 if (cpu_is_omap44xx())
171 return omap4_dsi_mux_pads(dsi_id, lane_mask);
176 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
178 if (cpu_is_omap44xx())
179 omap4_dsi_mux_pads(dsi_id, 0);
182 int __init omap_display_init(struct omap_dss_board_info *board_data)
185 struct omap_hwmod *oh;
186 struct platform_device *pdev;
188 struct omap_display_platform_data pdata;
189 const struct omap_dss_hwmod_data *curr_dss_hwmod;
191 memset(&pdata, 0, sizeof(pdata));
193 if (cpu_is_omap24xx()) {
194 curr_dss_hwmod = omap2_dss_hwmod_data;
195 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
196 } else if (cpu_is_omap34xx()) {
197 curr_dss_hwmod = omap3_dss_hwmod_data;
198 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
200 curr_dss_hwmod = omap4_dss_hwmod_data;
201 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
204 if (board_data->dsi_enable_pads == NULL)
205 board_data->dsi_enable_pads = omap_dsi_enable_pads;
206 if (board_data->dsi_disable_pads == NULL)
207 board_data->dsi_disable_pads = omap_dsi_disable_pads;
209 pdata.board_data = board_data;
210 pdata.board_data->get_context_loss_count =
211 omap_pm_get_dev_context_loss_count;
213 for (i = 0; i < oh_count; i++) {
214 oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
216 pr_err("Could not look up %s\n",
217 curr_dss_hwmod[i].oh_name);
221 pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
222 curr_dss_hwmod[i].id, oh, &pdata,
223 sizeof(struct omap_display_platform_data),
226 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
227 curr_dss_hwmod[i].oh_name))
230 omap_display_device.dev.platform_data = board_data;
232 r = platform_device_register(&omap_display_device);
234 printk(KERN_ERR "Unable to register OMAP-Display device\n");
239 static void dispc_disable_outputs(void)
242 bool lcd_en, digit_en, lcd2_en = false;
244 struct omap_dss_dispc_dev_attr *da;
245 struct omap_hwmod *oh;
247 oh = omap_hwmod_lookup("dss_dispc");
249 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
254 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
258 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
260 /* store value of LCDENABLE and DIGITENABLE bits */
261 v = omap_hwmod_read(oh, DISPC_CONTROL);
262 lcd_en = v & LCD_EN_MASK;
263 digit_en = v & DIGIT_EN_MASK;
265 /* store value of LCDENABLE for LCD2 */
266 if (da->manager_count > 2) {
267 v = omap_hwmod_read(oh, DISPC_CONTROL2);
268 lcd2_en = v & LCD_EN_MASK;
271 if (!(lcd_en | digit_en | lcd2_en))
272 return; /* no managers currently enabled */
275 * If any manager was enabled, we need to disable it before
276 * DSS clocks are disabled or DISPC module is reset
279 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
282 if (da->has_framedonetv_irq) {
283 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
285 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
286 1 << EVSYNC_ODD_IRQ_SHIFT;
291 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
294 * clear any previous FRAMEDONE, FRAMEDONETV,
295 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
297 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
299 /* disable LCD and TV managers */
300 v = omap_hwmod_read(oh, DISPC_CONTROL);
301 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
302 omap_hwmod_write(v, oh, DISPC_CONTROL);
304 /* disable LCD2 manager */
305 if (da->manager_count > 2) {
306 v = omap_hwmod_read(oh, DISPC_CONTROL2);
308 omap_hwmod_write(v, oh, DISPC_CONTROL2);
312 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
315 if (i > FRAMEDONE_IRQ_TIMEOUT) {
316 pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
323 #define MAX_MODULE_SOFTRESET_WAIT 10000
324 int omap_dss_reset(struct omap_hwmod *oh)
326 struct omap_hwmod_opt_clk *oc;
330 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
331 pr_err("dss_core: hwmod data doesn't contain reset data\n");
335 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
337 clk_enable(oc->_clk);
339 dispc_disable_outputs();
341 /* clear SDI registers */
342 if (cpu_is_omap3430()) {
343 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
344 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
348 * clear DSS_CONTROL register to switch DSS clock sources to
351 omap_hwmod_write(0x0, oh, DSS_CONTROL);
353 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
354 & SYSS_RESETDONE_MASK),
355 MAX_MODULE_SOFTRESET_WAIT, c);
357 if (c == MAX_MODULE_SOFTRESET_WAIT)
358 pr_warning("dss_core: waiting for reset to finish failed\n");
360 pr_debug("dss_core: softreset done\n");
362 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
364 clk_disable(oc->_clk);
366 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;