4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 #include <linux/err.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/device.h>
31 #include <linux/omap-dma.h>
34 #include "omap_hwmod.h"
35 #include "omap_device.h"
37 #define OMAP2_DMA_STRIDE 0x60
42 static struct omap_dma_dev_attr *d;
44 static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
46 static u16 reg_map[] = {
49 [IRQSTATUS_L0] = 0x08,
50 [IRQSTATUS_L1] = 0x0c,
51 [IRQSTATUS_L2] = 0x10,
52 [IRQSTATUS_L3] = 0x14,
53 [IRQENABLE_L0] = 0x18,
54 [IRQENABLE_L1] = 0x1c,
55 [IRQENABLE_L2] = 0x20,
56 [IRQENABLE_L3] = 0x24,
58 [OCP_SYSCONFIG] = 0x2c,
64 /* Common register offsets */
79 /* Channel specific register offsets */
86 /* OMAP4 specific registers */
92 static void __iomem *dma_base;
93 static inline void dma_write(u32 val, int reg, int lch)
98 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
99 offset = reg_map[reg] + (stride * lch);
100 __raw_writel(val, dma_base + offset);
103 static inline u32 dma_read(int reg, int lch)
108 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
109 offset = reg_map[reg] + (stride * lch);
110 val = __raw_readl(dma_base + offset);
114 static inline void omap2_disable_irq_lch(int lch)
118 val = dma_read(IRQENABLE_L0, lch);
120 dma_write(val, IRQENABLE_L0, lch);
123 static void omap2_clear_dma(int lch)
125 int i = dma_common_ch_start;
127 for (; i <= dma_common_ch_end; i += 1)
128 dma_write(0, i, lch);
131 static void omap2_show_dma_caps(void)
133 u8 revision = dma_read(REVISION, 0) & 0xff;
134 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
135 revision >> 4, revision & 0xf);
139 static u32 configure_dma_errata(void)
143 * Errata applicable for OMAP2430ES1.0 and all omap2420
146 * Erratum ID: Not Available
147 * Inter Frame DMA buffering issue DMA will wrongly
148 * buffer elements if packing and bursting is enabled. This might
149 * result in data gets stalled in FIFO at the end of the block.
150 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
151 * guarantee no data will stay in the DMA FIFO in case inter frame
155 * Erratum ID: Not Available
156 * DMA may hang when several channels are used in parallel
157 * In the following configuration, DMA channel hanging can occur:
158 * a. Channel i, hardware synchronized, is enabled
159 * b. Another channel (Channel x), software synchronized, is enabled.
160 * c. Channel i is disabled before end of transfer
161 * d. Channel i is reenabled.
162 * e. Steps 1 to 4 are repeated a certain number of times.
163 * f. A third channel (Channel y), software synchronized, is enabled.
164 * Channel x and Channel y may hang immediately after step 'f'.
166 * For any channel used - make sure NextLCH_ID is set to the value j.
168 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
169 (omap_type() == OMAP2430_REV_ES1_0))) {
171 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
172 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
176 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
177 * after a transaction error.
178 * Workaround: SW should explicitely disable the channel.
180 if (cpu_class_is_omap2())
181 SET_DMA_ERRATA(DMA_ERRATA_i378);
184 * Erratum ID: i541: sDMA FIFO draining does not finish
185 * If sDMA channel is disabled on the fly, sDMA enters standby even
186 * through FIFO Drain is still in progress
187 * Workaround: Put sDMA in NoStandby more before a logical channel is
188 * disabled, then put it back to SmartStandby right after the channel
189 * finishes FIFO draining.
191 if (cpu_is_omap34xx())
192 SET_DMA_ERRATA(DMA_ERRATA_i541);
195 * Erratum ID: i88 : Special programming model needed to disable DMA
196 * before end of block.
197 * Workaround: software must ensure that the DMA is configured in No
198 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
200 if (omap_type() == OMAP3430_REV_ES1_0)
201 SET_DMA_ERRATA(DMA_ERRATA_i88);
204 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
205 * read before the DMA controller finished disabling the channel.
207 SET_DMA_ERRATA(DMA_ERRATA_3_3);
210 * Erratum ID: Not Available
211 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
212 * after secure sram context save and restore.
213 * Work around: Hence we need to manually clear those IRQs to avoid
214 * spurious interrupts. This affects only secure devices.
216 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
217 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
222 /* One time initializations */
223 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
225 struct platform_device *pdev;
226 struct omap_system_dma_plat_info *p;
227 struct resource *mem;
228 char *name = "omap_dma_system";
230 dma_stride = OMAP2_DMA_STRIDE;
231 dma_common_ch_start = CSDP;
233 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
235 pr_err("%s: Unable to allocate pdata for %s:%s\n",
236 __func__, name, oh->name);
240 p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
241 p->disable_irq_lch = omap2_disable_irq_lch;
242 p->show_dma_caps = omap2_show_dma_caps;
243 p->clear_dma = omap2_clear_dma;
244 p->dma_write = dma_write;
245 p->dma_read = dma_read;
247 p->clear_lch_regs = NULL;
249 p->errata = configure_dma_errata();
251 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
254 pr_err("%s: Can't build omap_device for %s:%s.\n",
255 __func__, name, oh->name);
256 return PTR_ERR(pdev);
259 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
264 dma_base = ioremap(mem->start, resource_size(mem));
266 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
271 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
272 (d->lch_count), GFP_KERNEL);
275 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
279 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
280 d->dev_caps |= HS_CHANNELS_RESERVED;
282 /* Check the capabilities register for descriptor loading feature */
283 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
284 dma_common_ch_end = CCDN;
286 dma_common_ch_end = CCFN;
291 static int __init omap2_system_dma_init(void)
293 return omap_hwmod_for_each_by_class("dma",
294 omap2_system_dma_init_dev, NULL);
296 arch_initcall(omap2_system_dma_init);