4 * Copyright (C) 2009 Texas Instruments
5 * Vimal Singh <vimalsingh@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/platform_data/mtd-nand-omap2.h>
18 #include <asm/mach/flash.h>
22 #include "gpmc-nand.h"
24 /* minimum size for IO mapping */
25 #define NAND_IO_SIZE 4
27 static struct resource gpmc_nand_resource[] = {
29 .flags = IORESOURCE_MEM,
32 .flags = IORESOURCE_IRQ,
35 .flags = IORESOURCE_IRQ,
39 static struct platform_device gpmc_nand_device = {
42 .num_resources = ARRAY_SIZE(gpmc_nand_resource),
43 .resource = gpmc_nand_resource,
46 static int omap2_nand_gpmc_retime(
47 struct omap_nand_platform_data *gpmc_nand_data,
48 struct gpmc_timings *gpmc_t)
50 struct gpmc_timings t;
53 memset(&t, 0, sizeof(t));
54 t.sync_clk = gpmc_t->sync_clk;
55 t.cs_on = gpmc_t->cs_on;
56 t.adv_on = gpmc_t->adv_on;
59 t.adv_rd_off = gpmc_t->adv_rd_off;
61 t.access = gpmc_t->access;
62 t.oe_off = gpmc_t->oe_off;
63 t.cs_rd_off = gpmc_t->cs_rd_off;
64 t.rd_cycle = gpmc_t->rd_cycle;
67 t.adv_wr_off = gpmc_t->adv_wr_off;
69 if (cpu_is_omap34xx()) {
70 t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
71 t.wr_access = gpmc_t->wr_access;
73 t.we_off = gpmc_t->we_off;
74 t.cs_wr_off = gpmc_t->cs_wr_off;
75 t.wr_cycle = gpmc_t->wr_cycle;
77 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
84 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
86 /* support only OMAP3 class */
87 if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
88 pr_err("BCH ecc is not supported on this CPU\n");
93 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
94 * and AM33xx derivates. Other chips may be added if confirmed to work.
96 if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
97 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
99 pr_err("BCH 4-bit mode is not supported on this CPU\n");
106 int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
107 struct gpmc_timings *gpmc_t)
110 struct gpmc_settings s;
111 struct device *dev = &gpmc_nand_device.dev;
113 memset(&s, 0, sizeof(struct gpmc_settings));
115 gpmc_nand_device.dev.platform_data = gpmc_nand_data;
117 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
118 (unsigned long *)&gpmc_nand_resource[0].start);
120 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
121 gpmc_nand_data->cs, err);
125 gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
128 gpmc_nand_resource[1].start =
129 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
130 gpmc_nand_resource[2].start =
131 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
134 err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
136 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
140 if (gpmc_nand_data->of_node) {
141 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
143 s.device_nand = true;
145 /* Enable RD PIN Monitoring Reg */
146 if (gpmc_nand_data->dev_ready) {
147 s.wait_on_read = true;
148 s.wait_on_write = true;
152 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
153 s.device_width = GPMC_DEVWIDTH_16BIT;
155 s.device_width = GPMC_DEVWIDTH_8BIT;
157 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
161 err = gpmc_configure(GPMC_CONFIG_WP, 0);
166 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
168 if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
171 err = platform_device_register(&gpmc_nand_device);
173 dev_err(dev, "Unable to register NAND device\n");
180 gpmc_cs_free(gpmc_nand_data->cs);