2 * linux/arch/arm/mach-omap2/hsmmc.c
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <mach/hardware.h>
19 #include <plat/omap-pm.h>
21 #include <plat/omap_device.h>
27 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
29 static u16 control_pbias_offset;
30 static u16 control_devconf1_offset;
31 static u16 control_mmc1;
33 #define HSMMC_NAME_LEN 9
35 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
37 static int hsmmc_get_context_loss(struct device *dev)
39 return omap_pm_get_dev_context_loss_count(dev);
43 #define hsmmc_get_context_loss NULL
46 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
47 int power_on, int vdd)
50 struct omap_mmc_platform_data *mmc = dev->platform_data;
52 if (mmc->slots[0].remux)
53 mmc->slots[0].remux(dev, slot, power_on);
56 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
57 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
58 * 1.8V and 3.0V modes, controlled by the PBIAS register.
60 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
61 * is most naturally TWL VSIM; those pins also use PBIAS.
63 * FIXME handle VMMC1A as needed ...
66 if (cpu_is_omap2430()) {
67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68 if ((1 << vdd) >= MMC_VDD_30_31)
69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
75 if (mmc->slots[0].internal_clock) {
76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
81 reg = omap_ctrl_readl(control_pbias_offset);
82 if (cpu_is_omap3630()) {
83 /* Set MMC I/O to 52Mhz */
84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
88 reg |= OMAP2_PBIASSPEEDCTRL0;
90 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91 omap_ctrl_writel(reg, control_pbias_offset);
93 reg = omap_ctrl_readl(control_pbias_offset);
94 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95 omap_ctrl_writel(reg, control_pbias_offset);
99 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
100 int power_on, int vdd)
104 /* 100ms delay required for PBIAS configuration */
108 reg = omap_ctrl_readl(control_pbias_offset);
109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110 if ((1 << vdd) <= MMC_VDD_165_195)
111 reg &= ~OMAP2_PBIASLITEVMODE0;
113 reg |= OMAP2_PBIASLITEVMODE0;
114 omap_ctrl_writel(reg, control_pbias_offset);
116 reg = omap_ctrl_readl(control_pbias_offset);
117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118 OMAP2_PBIASLITEVMODE0);
119 omap_ctrl_writel(reg, control_pbias_offset);
123 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124 int power_on, int vdd)
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
133 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
134 * is most naturally TWL VSIM; those pins also use PBIAS.
136 * FIXME handle VMMC1A as needed ...
138 reg = omap4_ctrl_pad_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
140 OMAP4_MMC1_PWRDNZ_MASK);
141 omap4_ctrl_pad_writel(reg, control_pbias_offset);
144 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
145 int power_on, int vdd)
148 unsigned long timeout;
151 reg = omap4_ctrl_pad_readl(control_pbias_offset);
152 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
153 if ((1 << vdd) <= MMC_VDD_165_195)
154 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
156 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
157 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
158 OMAP4_MMC1_PWRDNZ_MASK);
159 omap4_ctrl_pad_writel(reg, control_pbias_offset);
161 timeout = jiffies + msecs_to_jiffies(5);
163 reg = omap4_ctrl_pad_readl(control_pbias_offset);
164 if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
166 usleep_range(100, 200);
167 } while (!time_after(jiffies, timeout));
169 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
170 pr_err("Pbias Voltage is not same as LDO\n");
171 /* Caution : On VMODE_ERROR Power Down MMC IO */
172 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
173 omap4_ctrl_pad_writel(reg, control_pbias_offset);
176 reg = omap4_ctrl_pad_readl(control_pbias_offset);
177 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
178 OMAP4_MMC1_PWRDNZ_MASK |
179 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
180 omap4_ctrl_pad_writel(reg, control_pbias_offset);
184 static void hsmmc23_before_set_reg(struct device *dev, int slot,
185 int power_on, int vdd)
187 struct omap_mmc_platform_data *mmc = dev->platform_data;
189 if (mmc->slots[0].remux)
190 mmc->slots[0].remux(dev, slot, power_on);
193 /* Only MMC2 supports a CLKIN */
194 if (mmc->slots[0].internal_clock) {
197 reg = omap_ctrl_readl(control_devconf1_offset);
198 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
199 omap_ctrl_writel(reg, control_devconf1_offset);
204 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
210 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
213 if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
214 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
215 OMAP_PIN_INPUT_PULLUP);
216 if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
217 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
218 OMAP_PIN_INPUT_PULLUP);
219 if (cpu_is_omap34xx()) {
220 if (controller_nr == 0) {
221 omap_mux_init_signal("sdmmc1_clk",
222 OMAP_PIN_INPUT_PULLUP);
223 omap_mux_init_signal("sdmmc1_cmd",
224 OMAP_PIN_INPUT_PULLUP);
225 omap_mux_init_signal("sdmmc1_dat0",
226 OMAP_PIN_INPUT_PULLUP);
227 if (mmc_controller->slots[0].caps &
228 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
229 omap_mux_init_signal("sdmmc1_dat1",
230 OMAP_PIN_INPUT_PULLUP);
231 omap_mux_init_signal("sdmmc1_dat2",
232 OMAP_PIN_INPUT_PULLUP);
233 omap_mux_init_signal("sdmmc1_dat3",
234 OMAP_PIN_INPUT_PULLUP);
236 if (mmc_controller->slots[0].caps &
237 MMC_CAP_8_BIT_DATA) {
238 omap_mux_init_signal("sdmmc1_dat4",
239 OMAP_PIN_INPUT_PULLUP);
240 omap_mux_init_signal("sdmmc1_dat5",
241 OMAP_PIN_INPUT_PULLUP);
242 omap_mux_init_signal("sdmmc1_dat6",
243 OMAP_PIN_INPUT_PULLUP);
244 omap_mux_init_signal("sdmmc1_dat7",
245 OMAP_PIN_INPUT_PULLUP);
248 if (controller_nr == 1) {
250 omap_mux_init_signal("sdmmc2_clk",
251 OMAP_PIN_INPUT_PULLUP);
252 omap_mux_init_signal("sdmmc2_cmd",
253 OMAP_PIN_INPUT_PULLUP);
254 omap_mux_init_signal("sdmmc2_dat0",
255 OMAP_PIN_INPUT_PULLUP);
258 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
259 * need to be muxed in the board-*.c files
261 if (mmc_controller->slots[0].caps &
262 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
263 omap_mux_init_signal("sdmmc2_dat1",
264 OMAP_PIN_INPUT_PULLUP);
265 omap_mux_init_signal("sdmmc2_dat2",
266 OMAP_PIN_INPUT_PULLUP);
267 omap_mux_init_signal("sdmmc2_dat3",
268 OMAP_PIN_INPUT_PULLUP);
270 if (mmc_controller->slots[0].caps &
271 MMC_CAP_8_BIT_DATA) {
272 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
273 OMAP_PIN_INPUT_PULLUP);
274 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
275 OMAP_PIN_INPUT_PULLUP);
276 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
277 OMAP_PIN_INPUT_PULLUP);
278 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
279 OMAP_PIN_INPUT_PULLUP);
284 * For MMC3 the pins need to be muxed in the board-*.c files
289 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
290 struct omap_mmc_platform_data *mmc)
294 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
296 pr_err("Cannot allocate memory for controller slot name\n");
302 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
304 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
306 mmc->slots[0].name = hc_name;
308 mmc->slots[0].caps = c->caps;
309 mmc->slots[0].internal_clock = !c->ext_clock;
310 mmc->dma_mask = 0xffffffff;
311 if (cpu_is_omap44xx())
312 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
316 mmc->get_context_loss_count = hsmmc_get_context_loss;
318 mmc->slots[0].switch_pin = c->gpio_cd;
319 mmc->slots[0].gpio_wp = c->gpio_wp;
321 mmc->slots[0].remux = c->remux;
322 mmc->slots[0].init_card = c->init_card;
325 mmc->slots[0].cover = 1;
328 mmc->slots[0].nonremovable = 1;
331 mmc->slots[0].power_saving = 1;
334 mmc->slots[0].no_off = 1;
337 mmc->slots[0].no_regulator_off_init = c->no_off_init;
339 if (c->vcc_aux_disable_is_sleep)
340 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
343 * NOTE: MMC slots should have a Vcc regulator set up.
344 * This may be from a TWL4030-family chip, another
345 * controllable regulator, or a fixed supply.
347 * temporary HACK: ocr_mask instead of fixed supply
349 mmc->slots[0].ocr_mask = c->ocr_mask;
351 if (cpu_is_omap3517() || cpu_is_omap3505())
352 mmc->slots[0].set_power = nop_mmc_set_power;
354 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
356 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
357 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
361 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
362 /* on-chip level shifting via PBIAS0/PBIAS1 */
363 if (cpu_is_omap44xx()) {
364 mmc->slots[0].before_set_reg =
365 omap4_hsmmc1_before_set_reg;
366 mmc->slots[0].after_set_reg =
367 omap4_hsmmc1_after_set_reg;
369 mmc->slots[0].before_set_reg =
370 omap_hsmmc1_before_set_reg;
371 mmc->slots[0].after_set_reg =
372 omap_hsmmc1_after_set_reg;
376 /* OMAP3630 HSMMC1 supports only 4-bit */
377 if (cpu_is_omap3630() &&
378 (c->caps & MMC_CAP_8_BIT_DATA)) {
379 c->caps &= ~MMC_CAP_8_BIT_DATA;
380 c->caps |= MMC_CAP_4_BIT_DATA;
381 mmc->slots[0].caps = c->caps;
387 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
388 c->caps &= ~MMC_CAP_8_BIT_DATA;
389 c->caps |= MMC_CAP_4_BIT_DATA;
393 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
394 /* off-chip level shifting, or none */
395 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
396 mmc->slots[0].after_set_reg = NULL;
401 mmc->slots[0].before_set_reg = NULL;
402 mmc->slots[0].after_set_reg = NULL;
405 pr_err("MMC%d configuration not supported!\n", c->mmc);
412 #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
414 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
416 struct omap_hwmod *oh;
417 struct platform_device *pdev;
418 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
419 struct omap_mmc_platform_data *mmc_data;
420 struct omap_mmc_dev_attr *mmc_dev_attr;
424 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
426 pr_err("Cannot allocate memory for mmc device!\n");
430 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
431 pr_err("%s fails!\n", __func__);
434 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
438 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
440 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
441 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
442 oh = omap_hwmod_lookup(oh_name);
444 pr_err("Could not look up %s\n", oh_name);
445 kfree(mmc_data->slots[0].name);
449 if (oh->dev_attr != NULL) {
450 mmc_dev_attr = oh->dev_attr;
451 mmc_data->controller_flags = mmc_dev_attr->flags;
454 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
455 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
457 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
458 kfree(mmc_data->slots[0].name);
462 * return device handle to board setup code
463 * required to populate for regulator framework structure
465 hsmmcinfo->dev = &pdev->dev;
471 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
475 if (!cpu_is_omap44xx()) {
476 if (cpu_is_omap2430()) {
477 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
478 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
480 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
481 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
484 control_pbias_offset =
485 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
486 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
487 reg = omap4_ctrl_pad_readl(control_mmc1);
488 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
489 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
490 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
491 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
492 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
493 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
494 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
495 omap4_ctrl_pad_writel(reg, control_mmc1);
498 for (; controllers->mmc; controllers++)
499 omap_init_hsmmc(controllers, controllers->mmc);