2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
21 #include <linux/random.h>
22 #include <linux/slab.h>
25 #include <linux/sys_soc.h>
28 #include <asm/cputype.h>
37 #define OMAP4_SILICON_TYPE_STANDARD 0x01
38 #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
40 #define OMAP_SOC_MAX_NAME_LENGTH 16
42 static unsigned int omap_revision;
43 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
44 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
47 unsigned int omap_rev(void)
51 EXPORT_SYMBOL(omap_rev);
55 static u32 val = OMAP2_DEVICETYPE_MASK;
57 if (val < OMAP2_DEVICETYPE_MASK)
60 if (cpu_is_omap24xx()) {
61 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
62 } else if (cpu_is_ti81xx()) {
63 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
64 } else if (soc_is_am33xx() || soc_is_am43xx()) {
65 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
66 } else if (cpu_is_omap34xx()) {
67 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
68 } else if (cpu_is_omap44xx()) {
69 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
70 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
71 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
72 val &= OMAP5_DEVICETYPE_MASK;
76 pr_err("Cannot detect omap type!\n");
80 val &= OMAP2_DEVICETYPE_MASK;
86 EXPORT_SYMBOL(omap_type);
89 /*----------------------------------------------------------------------------*/
91 #define OMAP_TAP_IDCODE 0x0204
92 #define OMAP_TAP_DIE_ID_0 0x0218
93 #define OMAP_TAP_DIE_ID_1 0x021C
94 #define OMAP_TAP_DIE_ID_2 0x0220
95 #define OMAP_TAP_DIE_ID_3 0x0224
97 #define OMAP_TAP_DIE_ID_44XX_0 0x0200
98 #define OMAP_TAP_DIE_ID_44XX_1 0x0208
99 #define OMAP_TAP_DIE_ID_44XX_2 0x020c
100 #define OMAP_TAP_DIE_ID_44XX_3 0x0210
102 #define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
105 u16 hawkeye; /* Silicon type (Hawkeye id) */
106 u8 dev; /* Device type from production_id reg */
107 u32 type; /* Combined type id copied to omap_revision */
110 /* Register values to detect the OMAP version */
111 static struct omap_id omap_ids[] __initdata = {
112 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
113 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
114 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
115 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
116 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
117 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
120 static void __iomem *tap_base;
121 static u16 tap_prod_id;
123 void omap_get_die_id(struct omap_die_id *odi)
125 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
126 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
127 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
128 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
129 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
133 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
134 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
135 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
136 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
139 static int __init omap_feed_randpool(void)
141 struct omap_die_id odi;
143 /* Throw the die ID into the entropy pool at boot */
144 omap_get_die_id(&odi);
145 add_device_randomness(&odi, sizeof(odi));
148 omap_device_initcall(omap_feed_randpool);
150 void __init omap2xxx_check_revision(void)
156 struct omap_die_id odi;
158 idcode = read_tap_reg(OMAP_TAP_IDCODE);
159 prod_id = read_tap_reg(tap_prod_id);
160 hawkeye = (idcode >> 12) & 0xffff;
161 rev = (idcode >> 28) & 0x0f;
162 dev_type = (prod_id >> 16) & 0x0f;
163 omap_get_die_id(&odi);
165 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
166 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
167 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
168 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
169 odi.id_1, (odi.id_1 >> 28) & 0xf);
170 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
171 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
172 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
175 /* Check hawkeye ids */
176 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
177 if (hawkeye == omap_ids[i].hawkeye)
181 if (i == ARRAY_SIZE(omap_ids)) {
182 printk(KERN_ERR "Unknown OMAP CPU id\n");
186 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
187 if (dev_type == omap_ids[j].dev)
191 if (j == ARRAY_SIZE(omap_ids)) {
192 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
193 omap_ids[i].type >> 16);
197 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
198 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
200 pr_info("%s", soc_name);
201 if ((omap_rev() >> 8) & 0x0f)
202 pr_info("%s", soc_rev);
206 #define OMAP3_SHOW_FEATURE(feat) \
207 if (omap3_has_ ##feat()) \
210 static void __init omap3_cpuinfo(void)
212 const char *cpu_name;
215 * OMAP3430 and OMAP3530 are assumed to be same.
217 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
218 * on available features. Upon detection, update the CPU id
219 * and CPU class bits.
221 if (cpu_is_omap3630()) {
222 cpu_name = "OMAP3630";
223 } else if (soc_is_am35xx()) {
224 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
225 } else if (cpu_is_ti816x()) {
227 } else if (soc_is_am335x()) {
229 } else if (soc_is_am437x()) {
231 } else if (cpu_is_ti814x()) {
233 } else if (omap3_has_iva() && omap3_has_sgx()) {
234 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
235 cpu_name = "OMAP3430/3530";
236 } else if (omap3_has_iva()) {
237 cpu_name = "OMAP3525";
238 } else if (omap3_has_sgx()) {
239 cpu_name = "OMAP3515";
241 cpu_name = "OMAP3503";
244 sprintf(soc_name, "%s", cpu_name);
246 /* Print verbose information */
247 pr_info("%s %s (", soc_name, soc_rev);
249 OMAP3_SHOW_FEATURE(l2cache);
250 OMAP3_SHOW_FEATURE(iva);
251 OMAP3_SHOW_FEATURE(sgx);
252 OMAP3_SHOW_FEATURE(neon);
253 OMAP3_SHOW_FEATURE(isp);
254 OMAP3_SHOW_FEATURE(192mhz_clk);
259 #define OMAP3_CHECK_FEATURE(status,feat) \
260 if (((status & OMAP3_ ##feat## _MASK) \
261 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
262 omap_features |= OMAP3_HAS_ ##feat; \
265 void __init omap3xxx_check_features(void)
271 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
273 OMAP3_CHECK_FEATURE(status, L2CACHE);
274 OMAP3_CHECK_FEATURE(status, IVA);
275 OMAP3_CHECK_FEATURE(status, SGX);
276 OMAP3_CHECK_FEATURE(status, NEON);
277 OMAP3_CHECK_FEATURE(status, ISP);
278 if (cpu_is_omap3630())
279 omap_features |= OMAP3_HAS_192MHZ_CLK;
280 if (cpu_is_omap3430() || cpu_is_omap3630())
281 omap_features |= OMAP3_HAS_IO_WAKEUP;
282 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
283 omap_rev() == OMAP3430_REV_ES3_1_2)
284 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
286 omap_features |= OMAP3_HAS_SDRC;
290 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
291 * reserved and therefore return 0 when read. Unfortunately,
292 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
293 * mean that a feature is present even though it isn't so clear
294 * the incorrectly set feature bits.
297 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
300 * TODO: Get additional info (where applicable)
301 * e.g. Size of L2 cache.
307 void __init omap4xxx_check_features(void)
312 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
314 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
315 omap_features = OMAP4_HAS_PERF_SILICON;
318 void __init ti81xx_check_features(void)
320 omap_features = OMAP3_HAS_NEON;
324 void __init am33xx_check_features(void)
328 omap_features = OMAP3_HAS_NEON;
330 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
331 if (status & AM33XX_SGX_MASK)
332 omap_features |= OMAP3_HAS_SGX;
337 void __init omap3xxx_check_revision(void)
345 * We cannot access revision registers on ES1.0.
346 * If the processor type is Cortex-A8 and the revision is 0x0
347 * it means its Cortex r0p0 which is 3430 ES1.0.
349 cpuid = read_cpuid_id();
350 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
351 omap_revision = OMAP3430_REV_ES1_0;
357 * Detection for 34xx ES2.0 and above can be done with just
358 * hawkeye and rev. See TRM 1.5.2 Device Identification.
359 * Note that rev does not map directly to our defined processor
360 * revision numbers as ES1.0 uses value 0.
362 idcode = read_tap_reg(OMAP_TAP_IDCODE);
363 hawkeye = (idcode >> 12) & 0xffff;
364 rev = (idcode >> 28) & 0xff;
368 /* Handle 34xx/35xx devices */
370 case 0: /* Take care of early samples */
372 omap_revision = OMAP3430_REV_ES2_0;
376 omap_revision = OMAP3430_REV_ES2_1;
380 omap_revision = OMAP3430_REV_ES3_0;
384 omap_revision = OMAP3430_REV_ES3_1;
390 /* Use the latest known revision as default */
391 omap_revision = OMAP3430_REV_ES3_1_2;
397 * Handle OMAP/AM 3505/3517 devices
399 * Set the device to be OMAP3517 here. Actual device
400 * is identified later based on the features.
404 omap_revision = AM35XX_REV_ES1_0;
410 omap_revision = AM35XX_REV_ES1_1;
415 /* Handle 36xx devices */
418 case 0: /* Take care of early samples */
419 omap_revision = OMAP3630_REV_ES1_0;
423 omap_revision = OMAP3630_REV_ES1_1;
429 omap_revision = OMAP3630_REV_ES1_2;
436 omap_revision = TI8168_REV_ES1_0;
440 omap_revision = TI8168_REV_ES1_1;
444 omap_revision = TI8168_REV_ES2_0;
450 omap_revision = TI8168_REV_ES2_1;
457 omap_revision = AM335X_REV_ES1_0;
461 omap_revision = AM335X_REV_ES2_0;
467 omap_revision = AM335X_REV_ES2_1;
475 omap_revision = AM437X_REV_ES1_0;
479 omap_revision = AM437X_REV_ES1_1;
485 omap_revision = AM437X_REV_ES1_2;
495 omap_revision = TI8148_REV_ES1_0;
499 omap_revision = TI8148_REV_ES2_0;
505 omap_revision = TI8148_REV_ES2_1;
511 /* Unknown default to latest silicon rev as default */
512 omap_revision = OMAP3630_REV_ES1_2;
514 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
516 sprintf(soc_rev, "ES%s", cpu_rev);
519 void __init omap4xxx_check_revision(void)
526 * The IC rev detection is done with hawkeye and rev.
527 * Note that rev does not map directly to defined processor
528 * revision numbers as ES1.0 uses value 0.
530 idcode = read_tap_reg(OMAP_TAP_IDCODE);
531 hawkeye = (idcode >> 12) & 0xffff;
532 rev = (idcode >> 28) & 0xf;
535 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
536 * Use ARM register to detect the correct ES version
538 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
539 idcode = read_cpuid_id();
540 rev = (idcode & 0xf) - 1;
547 omap_revision = OMAP4430_REV_ES1_0;
551 omap_revision = OMAP4430_REV_ES2_0;
557 omap_revision = OMAP4430_REV_ES2_1;
560 omap_revision = OMAP4430_REV_ES2_2;
564 omap_revision = OMAP4430_REV_ES2_3;
570 omap_revision = OMAP4460_REV_ES1_0;
574 omap_revision = OMAP4460_REV_ES1_1;
582 omap_revision = OMAP4470_REV_ES1_0;
587 /* Unknown default to latest silicon rev as default */
588 omap_revision = OMAP4430_REV_ES2_3;
591 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
592 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
593 (omap_rev() >> 8) & 0xf);
594 pr_info("%s %s\n", soc_name, soc_rev);
597 void __init omap5xxx_check_revision(void)
603 idcode = read_tap_reg(OMAP_TAP_IDCODE);
604 hawkeye = (idcode >> 12) & 0xffff;
605 rev = (idcode >> 28) & 0xff;
610 /* No support for ES1.0 Test chip */
614 omap_revision = OMAP5430_REV_ES2_0;
621 /* No support for ES1.0 Test chip */
625 omap_revision = OMAP5432_REV_ES2_0;
630 /* Unknown default to latest silicon rev as default*/
631 omap_revision = OMAP5430_REV_ES2_0;
634 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
635 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
637 pr_info("%s %s\n", soc_name, soc_rev);
640 void __init dra7xxx_check_revision(void)
646 idcode = read_tap_reg(OMAP_TAP_IDCODE);
647 hawkeye = (idcode >> 12) & 0xffff;
648 rev = (idcode >> 28) & 0xff;
653 omap_revision = DRA752_REV_ES1_0;
656 omap_revision = DRA752_REV_ES1_1;
660 omap_revision = DRA752_REV_ES2_0;
668 omap_revision = DRA722_REV_ES1_0;
671 /* If we have no new revisions */
672 omap_revision = DRA722_REV_ES1_0;
678 /* Unknown default to latest silicon rev as default*/
679 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
680 __func__, idcode, hawkeye, rev);
681 omap_revision = DRA752_REV_ES2_0;
684 sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
685 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
686 (omap_rev() >> 8) & 0xf);
688 pr_info("%s %s\n", soc_name, soc_rev);
692 * Set up things for map_io and processor detection later on. Gets called
693 * pretty much first thing from board init. For multi-omap, this gets
694 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
695 * detect the exact revision later on in omap2_detect_revision() once map_io
698 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
700 omap_revision = class;
703 /* XXX What is this intended to do? */
704 if (cpu_is_omap34xx())
705 tap_prod_id = 0x0210;
707 tap_prod_id = 0x0208;
710 #ifdef CONFIG_SOC_BUS
712 static const char * const omap_types[] = {
713 [OMAP2_DEVICE_TYPE_TEST] = "TST",
714 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
715 [OMAP2_DEVICE_TYPE_SEC] = "HS",
716 [OMAP2_DEVICE_TYPE_GP] = "GP",
717 [OMAP2_DEVICE_TYPE_BAD] = "BAD",
720 static const char * __init omap_get_family(void)
722 if (cpu_is_omap24xx())
723 return kasprintf(GFP_KERNEL, "OMAP2");
724 else if (cpu_is_omap34xx())
725 return kasprintf(GFP_KERNEL, "OMAP3");
726 else if (cpu_is_omap44xx())
727 return kasprintf(GFP_KERNEL, "OMAP4");
728 else if (soc_is_omap54xx())
729 return kasprintf(GFP_KERNEL, "OMAP5");
730 else if (soc_is_am33xx() || soc_is_am335x())
731 return kasprintf(GFP_KERNEL, "AM33xx");
732 else if (soc_is_am43xx())
733 return kasprintf(GFP_KERNEL, "AM43xx");
734 else if (soc_is_dra7xx())
735 return kasprintf(GFP_KERNEL, "DRA7");
737 return kasprintf(GFP_KERNEL, "Unknown");
740 static ssize_t omap_get_type(struct device *dev,
741 struct device_attribute *attr,
744 return sprintf(buf, "%s\n", omap_types[omap_type()]);
747 static struct device_attribute omap_soc_attr =
748 __ATTR(type, S_IRUGO, omap_get_type, NULL);
750 void __init omap_soc_device_init(void)
752 struct device *parent;
753 struct soc_device *soc_dev;
754 struct soc_device_attribute *soc_dev_attr;
756 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
760 soc_dev_attr->machine = soc_name;
761 soc_dev_attr->family = omap_get_family();
762 soc_dev_attr->revision = soc_rev;
764 soc_dev = soc_device_register(soc_dev_attr);
765 if (IS_ERR(soc_dev)) {
770 parent = soc_device_to_device(soc_dev);
771 device_create_file(parent, &omap_soc_attr);
773 #endif /* CONFIG_SOC_BUS */