arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/cputype.h>
  23
  24 #include "common.h"
  25 #include <plat/cpu.h>
  26
  27 #include <mach/id.h>
  28
  29 #include "control.h"
  30
  31 static unsigned int omap_revision;
  32
  33 u32 omap_features;
  34
  35 unsigned int omap_rev(void)
  36 {
  37         return omap_revision;
  38 }
  39 EXPORT_SYMBOL(omap_rev);
  40
  41 int omap_type(void)
  42 {
  43         u32 val = 0;
  44
  45         if (cpu_is_omap24xx()) {
  46                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  47         } else if (cpu_is_am33xx()) {
  48                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  49         } else if (cpu_is_omap34xx()) {
  50                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  51         } else if (cpu_is_omap44xx()) {
  52                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  53         } else {
  54                 pr_err("Cannot detect omap type!\n");
  55                 goto out;
  56         }
  57
  58         val &= OMAP2_DEVICETYPE_MASK;
  59         val >>= 8;
  60
  61 out:
  62         return val;
  63 }
  64 EXPORT_SYMBOL(omap_type);
  65
  66
  67 /*----------------------------------------------------------------------------*/
  68
  69 #define OMAP_TAP_IDCODE         0x0204
  70 #define OMAP_TAP_DIE_ID_0       0x0218
  71 #define OMAP_TAP_DIE_ID_1       0x021C
  72 #define OMAP_TAP_DIE_ID_2       0x0220
  73 #define OMAP_TAP_DIE_ID_3       0x0224
  74
  75 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  76 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  77 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  78 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  79
  80 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
  81
  82 struct omap_id {
  83         u16     hawkeye;        /* Silicon type (Hawkeye id) */
  84         u8      dev;            /* Device type from production_id reg */
  85         u32     type;           /* Combined type id copied to omap_revision */
  86 };
  87
  88 /* Register values to detect the OMAP version */
  89 static struct omap_id omap_ids[] __initdata = {
  90         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
  91         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
  92         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
  93         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
  94         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
  95         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
  96 };
  97
  98 static void __iomem *tap_base;
  99 static u16 tap_prod_id;
 100
 101 void omap_get_die_id(struct omap_die_id *odi)
 102 {
 103         if (cpu_is_omap44xx()) {
 104                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 105                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 106                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 107                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 108
 109                 return;
 110         }
 111         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 112         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 113         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 114         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 115 }
 116
 117 static void __init omap24xx_check_revision(void)
 118 {
 119         int i, j;
 120         u32 idcode, prod_id;
 121         u16 hawkeye;
 122         u8  dev_type, rev;
 123         struct omap_die_id odi;
 124
 125         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 126         prod_id = read_tap_reg(tap_prod_id);
 127         hawkeye = (idcode >> 12) & 0xffff;
 128         rev = (idcode >> 28) & 0x0f;
 129         dev_type = (prod_id >> 16) & 0x0f;
 130         omap_get_die_id(&odi);
 131
 132         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 133                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 134         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 135         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 136                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 137         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 138         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 139         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 140                  prod_id, dev_type);
 141
 142         /* Check hawkeye ids */
 143         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 144                 if (hawkeye == omap_ids[i].hawkeye)
 145                         break;
 146         }
 147
 148         if (i == ARRAY_SIZE(omap_ids)) {
 149                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 150                 return;
 151         }
 152
 153         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 154                 if (dev_type == omap_ids[j].dev)
 155                         break;
 156         }
 157
 158         if (j == ARRAY_SIZE(omap_ids)) {
 159                 printk(KERN_ERR "Unknown OMAP device type. "
 160                                 "Handling it as OMAP%04x\n",
 161                                 omap_ids[i].type >> 16);
 162                 j = i;
 163         }
 164
 165         pr_info("OMAP%04x", omap_rev() >> 16);
 166         if ((omap_rev() >> 8) & 0x0f)
 167                 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
 168         pr_info("\n");
 169 }
 170
 171 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 172         if (((status & OMAP3_ ##feat## _MASK)                           \
 173                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 174                 omap_features |= OMAP3_HAS_ ##feat;                     \
 175         }
 176
 177 static void __init omap3_check_features(void)
 178 {
 179         u32 status;
 180
 181         omap_features = 0;
 182
 183         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 184
 185         OMAP3_CHECK_FEATURE(status, L2CACHE);
 186         OMAP3_CHECK_FEATURE(status, IVA);
 187         OMAP3_CHECK_FEATURE(status, SGX);
 188         OMAP3_CHECK_FEATURE(status, NEON);
 189         OMAP3_CHECK_FEATURE(status, ISP);
 190         if (cpu_is_omap3630())
 191                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 192         if (cpu_is_omap3430() || cpu_is_omap3630())
 193                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 194         if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 195             omap_rev() == OMAP3430_REV_ES3_1_2)
 196                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 197
 198         omap_features |= OMAP3_HAS_SDRC;
 199
 200         /*
 201          * TODO: Get additional info (where applicable)
 202          *       e.g. Size of L2 cache.
 203          */
 204 }
 205
 206 static void __init omap4_check_features(void)
 207 {
 208         u32 si_type;
 209
 210         if (cpu_is_omap443x())
 211                 omap_features |= OMAP4_HAS_MPU_1GHZ;
 212
 213
 214         if (cpu_is_omap446x()) {
 215                 si_type =
 216                         read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
 217                 switch ((si_type & (3 << 16)) >> 16) {
 218                 case 2:
 219                         /* High performance device */
 220                         omap_features |= OMAP4_HAS_MPU_1_5GHZ;
 221                         break;
 222                 case 1:
 223                 default:
 224                         /* Standard device */
 225                         omap_features |= OMAP4_HAS_MPU_1_2GHZ;
 226                         break;
 227                 }
 228         }
 229 }
 230
 231 static void __init ti81xx_check_features(void)
 232 {
 233         omap_features = OMAP3_HAS_NEON;
 234 }
 235
 236 static void __init omap3_check_revision(const char **cpu_rev)
 237 {
 238         u32 cpuid, idcode;
 239         u16 hawkeye;
 240         u8 rev;
 241
 242         /*
 243          * We cannot access revision registers on ES1.0.
 244          * If the processor type is Cortex-A8 and the revision is 0x0
 245          * it means its Cortex r0p0 which is 3430 ES1.0.
 246          */
 247         cpuid = read_cpuid(CPUID_ID);
 248         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 249                 omap_revision = OMAP3430_REV_ES1_0;
 250                 *cpu_rev = "1.0";
 251                 return;
 252         }
 253
 254         /*
 255          * Detection for 34xx ES2.0 and above can be done with just
 256          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 257          * Note that rev does not map directly to our defined processor
 258          * revision numbers as ES1.0 uses value 0.
 259          */
 260         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 261         hawkeye = (idcode >> 12) & 0xffff;
 262         rev = (idcode >> 28) & 0xff;
 263
 264         switch (hawkeye) {
 265         case 0xb7ae:
 266                 /* Handle 34xx/35xx devices */
 267                 switch (rev) {
 268                 case 0: /* Take care of early samples */
 269                 case 1:
 270                         omap_revision = OMAP3430_REV_ES2_0;
 271                         *cpu_rev = "2.0";
 272                         break;
 273                 case 2:
 274                         omap_revision = OMAP3430_REV_ES2_1;
 275                         *cpu_rev = "2.1";
 276                         break;
 277                 case 3:
 278                         omap_revision = OMAP3430_REV_ES3_0;
 279                         *cpu_rev = "3.0";
 280                         break;
 281                 case 4:
 282                         omap_revision = OMAP3430_REV_ES3_1;
 283                         *cpu_rev = "3.1";
 284                         break;
 285                 case 7:
 286                 /* FALLTHROUGH */
 287                 default:
 288                         /* Use the latest known revision as default */
 289                         omap_revision = OMAP3430_REV_ES3_1_2;
 290                         *cpu_rev = "3.1.2";
 291                 }
 292                 break;
 293         case 0xb868:
 294                 /*
 295                  * Handle OMAP/AM 3505/3517 devices
 296                  *
 297                  * Set the device to be OMAP3517 here. Actual device
 298                  * is identified later based on the features.
 299                  */
 300                 switch (rev) {
 301                 case 0:
 302                         omap_revision = OMAP3517_REV_ES1_0;
 303                         *cpu_rev = "1.0";
 304                         break;
 305                 case 1:
 306                 /* FALLTHROUGH */
 307                 default:
 308                         omap_revision = OMAP3517_REV_ES1_1;
 309                         *cpu_rev = "1.1";
 310                 }
 311                 break;
 312         case 0xb891:
 313                 /* Handle 36xx devices */
 314
 315                 switch(rev) {
 316                 case 0: /* Take care of early samples */
 317                         omap_revision = OMAP3630_REV_ES1_0;
 318                         *cpu_rev = "1.0";
 319                         break;
 320                 case 1:
 321                         omap_revision = OMAP3630_REV_ES1_1;
 322                         *cpu_rev = "1.1";
 323                         break;
 324                 case 2:
 325                 /* FALLTHROUGH */
 326                 default:
 327                         omap_revision = OMAP3630_REV_ES1_2;
 328                         *cpu_rev = "1.2";
 329                 }
 330                 break;
 331         case 0xb81e:
 332                 switch (rev) {
 333                 case 0:
 334                         omap_revision = TI8168_REV_ES1_0;
 335                         *cpu_rev = "1.0";
 336                         break;
 337                 case 1:
 338                 /* FALLTHROUGH */
 339                 default:
 340                         omap_revision = TI8168_REV_ES1_1;
 341                         *cpu_rev = "1.1";
 342                         break;
 343                 }
 344                 break;
 345         case 0xb944:
 346                 omap_revision = AM335X_REV_ES1_0;
 347                 *cpu_rev = "1.0";
 348                 break;
 349         case 0xb8f2:
 350                 switch (rev) {
 351                 case 0:
 352                 /* FALLTHROUGH */
 353                 case 1:
 354                         omap_revision = TI8148_REV_ES1_0;
 355                         *cpu_rev = "1.0";
 356                         break;
 357                 case 2:
 358                         omap_revision = TI8148_REV_ES2_0;
 359                         *cpu_rev = "2.0";
 360                         break;
 361                 case 3:
 362                 /* FALLTHROUGH */
 363                 default:
 364                         omap_revision = TI8148_REV_ES2_1;
 365                         *cpu_rev = "2.1";
 366                         break;
 367                 }
 368                 break;
 369         default:
 370                 /* Unknown default to latest silicon rev as default */
 371                 omap_revision = OMAP3630_REV_ES1_2;
 372                 *cpu_rev = "1.2";
 373                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
 374         }
 375 }
 376
 377 static void __init omap4_check_revision(void)
 378 {
 379         u32 idcode;
 380         u16 hawkeye;
 381         u8 rev;
 382
 383         /*
 384          * The IC rev detection is done with hawkeye and rev.
 385          * Note that rev does not map directly to defined processor
 386          * revision numbers as ES1.0 uses value 0.
 387          */
 388         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 389         hawkeye = (idcode >> 12) & 0xffff;
 390         rev = (idcode >> 28) & 0xf;
 391
 392         /*
 393          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 394          * Use ARM register to detect the correct ES version
 395          */
 396         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
 397                 idcode = read_cpuid(CPUID_ID);
 398                 rev = (idcode & 0xf) - 1;
 399         }
 400
 401         switch (hawkeye) {
 402         case 0xb852:
 403                 switch (rev) {
 404                 case 0:
 405                         omap_revision = OMAP4430_REV_ES1_0;
 406                         break;
 407                 case 1:
 408                 default:
 409                         omap_revision = OMAP4430_REV_ES2_0;
 410                 }
 411                 break;
 412         case 0xb95c:
 413                 switch (rev) {
 414                 case 3:
 415                         omap_revision = OMAP4430_REV_ES2_1;
 416                         break;
 417                 case 4:
 418                         omap_revision = OMAP4430_REV_ES2_2;
 419                         break;
 420                 case 6:
 421                 default:
 422                         omap_revision = OMAP4430_REV_ES2_3;
 423                 }
 424                 break;
 425         case 0xb94e:
 426                 switch (rev) {
 427                 case 0:
 428                 default:
 429                         omap_revision = OMAP4460_REV_ES1_0;
 430                         break;
 431                 }
 432                 break;
 433         case 0xb975:
 434                 switch (rev) {
 435                 case 0:
 436                 default:
 437                         omap_revision = OMAP4470_REV_ES1_0;
 438                         break;
 439                 }
 440                 break;
 441         default:
 442                 /* Unknown default to latest silicon rev as default */
 443                 omap_revision = OMAP4430_REV_ES2_3;
 444         }
 445
 446         pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
 447                 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 448 }
 449
 450 #define OMAP3_SHOW_FEATURE(feat)                \
 451         if (omap3_has_ ##feat())                \
 452                 printk(#feat" ");
 453
 454 static void __init omap3_cpuinfo(const char *cpu_rev)
 455 {
 456         const char *cpu_name;
 457
 458         /*
 459          * OMAP3430 and OMAP3530 are assumed to be same.
 460          *
 461          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 462          * on available features. Upon detection, update the CPU id
 463          * and CPU class bits.
 464          */
 465         if (cpu_is_omap3630()) {
 466                 cpu_name = "OMAP3630";
 467         } else if (cpu_is_omap3517()) {
 468                 /* AM35xx devices */
 469                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 470         } else if (cpu_is_ti816x()) {
 471                 cpu_name = "TI816X";
 472         } else if (cpu_is_am335x()) {
 473                 cpu_name =  "AM335X";
 474         } else if (cpu_is_ti814x()) {
 475                 cpu_name = "TI814X";
 476         } else if (omap3_has_iva() && omap3_has_sgx()) {
 477                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 478                 cpu_name = "OMAP3430/3530";
 479         } else if (omap3_has_iva()) {
 480                 cpu_name = "OMAP3525";
 481         } else if (omap3_has_sgx()) {
 482                 cpu_name = "OMAP3515";
 483         } else {
 484                 cpu_name = "OMAP3503";
 485         }
 486
 487         /* Print verbose information */
 488         pr_info("%s ES%s (", cpu_name, cpu_rev);
 489
 490         OMAP3_SHOW_FEATURE(l2cache);
 491         OMAP3_SHOW_FEATURE(iva);
 492         OMAP3_SHOW_FEATURE(sgx);
 493         OMAP3_SHOW_FEATURE(neon);
 494         OMAP3_SHOW_FEATURE(isp);
 495         OMAP3_SHOW_FEATURE(192mhz_clk);
 496
 497         printk(")\n");
 498 }
 499
 500 /*
 501  * Try to detect the exact revision of the omap we're running on
 502  */
 503 void __init omap2_check_revision(void)
 504 {
 505         const char *cpu_rev;
 506
 507         /*
 508          * At this point we have an idea about the processor revision set
 509          * earlier with omap2_set_globals_tap().
 510          */
 511         if (cpu_is_omap24xx()) {
 512                 omap24xx_check_revision();
 513         } else if (cpu_is_omap34xx()) {
 514                 omap3_check_revision(&cpu_rev);
 515
 516                 /* TI81XX doesn't have feature register */
 517                 if (!cpu_is_ti81xx())
 518                         omap3_check_features();
 519                 else
 520                         ti81xx_check_features();
 521
 522                 omap3_cpuinfo(cpu_rev);
 523                 return;
 524         } else if (cpu_is_omap44xx()) {
 525                 omap4_check_revision();
 526                 omap4_check_features();
 527                 return;
 528         } else {
 529                 pr_err("OMAP revision unknown, please fix!\n");
 530         }
 531 }
 532
 533 /*
 534  * Set up things for map_io and processor detection later on. Gets called
 535  * pretty much first thing from board init. For multi-omap, this gets
 536  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 537  * detect the exact revision later on in omap2_detect_revision() once map_io
 538  * is done.
 539  */
 540 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 541 {
 542         omap_revision = omap2_globals->class;
 543         tap_base = omap2_globals->tap;
 544
 545         if (cpu_is_omap34xx())
 546                 tap_prod_id = 0x0210;
 547         else
 548                 tap_prod_id = 0x0208;
 549 }