2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
29 #include <asm/mach/map.h>
31 #include <plat/sram.h>
32 #include <plat/sdrc.h>
33 #include <plat/gpmc.h>
34 #include <plat/serial.h>
36 #include "clock2xxx.h"
37 #include "clock3xxx.h"
38 #include "clock44xx.h"
41 #include <plat/omap-pm.h>
42 #include <plat/powerdomain.h>
43 #include "powerdomains.h"
45 #include <plat/clockdomain.h>
46 #include "clockdomains.h"
48 #include <plat/omap_hwmod.h>
49 #include <plat/multi.h>
52 * The machine specific code may provide the extra mapping besides the
53 * default mapping provided here.
56 #ifdef CONFIG_ARCH_OMAP2
57 static struct map_desc omap24xx_io_desc[] __initdata = {
59 .virtual = L3_24XX_VIRT,
60 .pfn = __phys_to_pfn(L3_24XX_PHYS),
61 .length = L3_24XX_SIZE,
65 .virtual = L4_24XX_VIRT,
66 .pfn = __phys_to_pfn(L4_24XX_PHYS),
67 .length = L4_24XX_SIZE,
72 #ifdef CONFIG_ARCH_OMAP2420
73 static struct map_desc omap242x_io_desc[] __initdata = {
75 .virtual = DSP_MEM_2420_VIRT,
76 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
77 .length = DSP_MEM_2420_SIZE,
81 .virtual = DSP_IPI_2420_VIRT,
82 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
83 .length = DSP_IPI_2420_SIZE,
87 .virtual = DSP_MMU_2420_VIRT,
88 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
89 .length = DSP_MMU_2420_SIZE,
96 #ifdef CONFIG_ARCH_OMAP2430
97 static struct map_desc omap243x_io_desc[] __initdata = {
99 .virtual = L4_WK_243X_VIRT,
100 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
101 .length = L4_WK_243X_SIZE,
105 .virtual = OMAP243X_GPMC_VIRT,
106 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
107 .length = OMAP243X_GPMC_SIZE,
111 .virtual = OMAP243X_SDRC_VIRT,
112 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
113 .length = OMAP243X_SDRC_SIZE,
117 .virtual = OMAP243X_SMS_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
119 .length = OMAP243X_SMS_SIZE,
126 #ifdef CONFIG_ARCH_OMAP3
127 static struct map_desc omap34xx_io_desc[] __initdata = {
129 .virtual = L3_34XX_VIRT,
130 .pfn = __phys_to_pfn(L3_34XX_PHYS),
131 .length = L3_34XX_SIZE,
135 .virtual = L4_34XX_VIRT,
136 .pfn = __phys_to_pfn(L4_34XX_PHYS),
137 .length = L4_34XX_SIZE,
141 .virtual = OMAP34XX_GPMC_VIRT,
142 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
143 .length = OMAP34XX_GPMC_SIZE,
147 .virtual = OMAP343X_SMS_VIRT,
148 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
149 .length = OMAP343X_SMS_SIZE,
153 .virtual = OMAP343X_SDRC_VIRT,
154 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
155 .length = OMAP343X_SDRC_SIZE,
159 .virtual = L4_PER_34XX_VIRT,
160 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
161 .length = L4_PER_34XX_SIZE,
165 .virtual = L4_EMU_34XX_VIRT,
166 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
167 .length = L4_EMU_34XX_SIZE,
170 #if defined(CONFIG_DEBUG_LL) && \
171 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
173 .virtual = ZOOM_UART_VIRT,
174 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
181 #ifdef CONFIG_ARCH_OMAP4
182 static struct map_desc omap44xx_io_desc[] __initdata = {
184 .virtual = L3_44XX_VIRT,
185 .pfn = __phys_to_pfn(L3_44XX_PHYS),
186 .length = L3_44XX_SIZE,
190 .virtual = L4_44XX_VIRT,
191 .pfn = __phys_to_pfn(L4_44XX_PHYS),
192 .length = L4_44XX_SIZE,
196 .virtual = OMAP44XX_GPMC_VIRT,
197 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
198 .length = OMAP44XX_GPMC_SIZE,
202 .virtual = OMAP44XX_EMIF1_VIRT,
203 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
204 .length = OMAP44XX_EMIF1_SIZE,
208 .virtual = OMAP44XX_EMIF2_VIRT,
209 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
210 .length = OMAP44XX_EMIF2_SIZE,
214 .virtual = OMAP44XX_DMM_VIRT,
215 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
216 .length = OMAP44XX_DMM_SIZE,
220 .virtual = L4_PER_44XX_VIRT,
221 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
222 .length = L4_PER_44XX_SIZE,
226 .virtual = L4_EMU_44XX_VIRT,
227 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
228 .length = L4_EMU_44XX_SIZE,
234 static void __init _omap2_map_common_io(void)
236 /* Normally devicemaps_init() would flush caches and tlb after
237 * mdesc->map_io(), but we must also do it here because of the CPU
238 * revision check below.
240 local_flush_tlb_all();
243 omap2_check_revision();
247 #ifdef CONFIG_ARCH_OMAP2420
248 void __init omap242x_map_common_io(void)
250 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
251 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
252 _omap2_map_common_io();
256 #ifdef CONFIG_ARCH_OMAP2430
257 void __init omap243x_map_common_io(void)
259 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
260 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
261 _omap2_map_common_io();
265 #ifdef CONFIG_ARCH_OMAP3
266 void __init omap34xx_map_common_io(void)
268 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
269 _omap2_map_common_io();
273 #ifdef CONFIG_ARCH_OMAP4
274 void __init omap44xx_map_common_io(void)
276 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
277 _omap2_map_common_io();
282 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
284 * Sets the CORE DPLL3 M2 divider to the same value that it's at
285 * currently. This has the effect of setting the SDRC SDRAM AC timing
286 * registers to the values currently defined by the kernel. Currently
287 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
288 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
289 * or passes along the return value of clk_set_rate().
291 static int __init _omap2_init_reprogram_sdrc(void)
293 struct clk *dpll3_m2_ck;
297 if (!cpu_is_omap34xx())
300 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
301 if (IS_ERR(dpll3_m2_ck))
304 rate = clk_get_rate(dpll3_m2_ck);
305 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
306 v = clk_set_rate(dpll3_m2_ck, rate);
308 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
310 clk_put(dpll3_m2_ck);
316 * Initialize asm_irq_base for entry-macro.S
318 static inline void omap_irq_base_init(void)
320 extern void __iomem *omap_irq_base;
323 if (cpu_is_omap24xx())
324 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
325 else if (cpu_is_omap34xx())
326 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
327 else if (cpu_is_omap44xx())
328 omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
330 pr_err("Could not initialize omap_irq_base\n");
334 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
335 struct omap_sdrc_params *sdrc_cs1)
337 u8 skip_setup_idle = 0;
339 pwrdm_init(powerdomains_omap);
340 clkdm_init(clockdomains_omap, clkdm_autodeps);
341 if (cpu_is_omap242x())
342 omap2420_hwmod_init();
343 else if (cpu_is_omap243x())
344 omap2430_hwmod_init();
345 else if (cpu_is_omap34xx())
346 omap3xxx_hwmod_init();
347 else if (cpu_is_omap44xx())
348 omap44xx_hwmod_init();
350 /* The OPP tables have to be registered before a clk init */
351 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
353 if (cpu_is_omap2420())
355 else if (cpu_is_omap2430())
357 else if (cpu_is_omap34xx())
359 else if (cpu_is_omap44xx())
362 pr_err("Could not init clock framework - unknown CPU\n");
364 omap_serial_early_init();
366 #ifndef CONFIG_PM_RUNTIME
369 omap_hwmod_late_init(skip_setup_idle);
370 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
371 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
372 _omap2_init_reprogram_sdrc();
376 omap_irq_base_init();
380 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
383 u8 omap_readb(u32 pa)
385 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
387 EXPORT_SYMBOL(omap_readb);
389 u16 omap_readw(u32 pa)
391 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
393 EXPORT_SYMBOL(omap_readw);
395 u32 omap_readl(u32 pa)
397 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
399 EXPORT_SYMBOL(omap_readl);
401 void omap_writeb(u8 v, u32 pa)
403 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
405 EXPORT_SYMBOL(omap_writeb);
407 void omap_writew(u16 v, u32 pa)
409 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
411 EXPORT_SYMBOL(omap_writew);
413 void omap_writel(u32 v, u32 pa)
415 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
417 EXPORT_SYMBOL(omap_writel);