2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
23 #include <linux/clk.h>
24 #include <linux/omapfb.h>
28 #include <asm/mach/map.h>
30 #include <plat/sram.h>
31 #include <plat/sdrc.h>
32 #include <plat/serial.h>
34 #include "clock2xxx.h"
35 #include "clock3xxx.h"
36 #include "clock44xx.h"
38 #include <plat/common.h>
39 #include <plat/omap-pm.h>
41 #include "powerdomain.h"
43 #include "clockdomain.h"
44 #include <plat/omap_hwmod.h>
45 #include <plat/multi.h>
46 #include <plat/common.h>
49 * The machine specific code may provide the extra mapping besides the
50 * default mapping provided here.
53 #ifdef CONFIG_ARCH_OMAP2
54 static struct map_desc omap24xx_io_desc[] __initdata = {
56 .virtual = L3_24XX_VIRT,
57 .pfn = __phys_to_pfn(L3_24XX_PHYS),
58 .length = L3_24XX_SIZE,
62 .virtual = L4_24XX_VIRT,
63 .pfn = __phys_to_pfn(L4_24XX_PHYS),
64 .length = L4_24XX_SIZE,
69 #ifdef CONFIG_SOC_OMAP2420
70 static struct map_desc omap242x_io_desc[] __initdata = {
72 .virtual = DSP_MEM_2420_VIRT,
73 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
74 .length = DSP_MEM_2420_SIZE,
78 .virtual = DSP_IPI_2420_VIRT,
79 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
80 .length = DSP_IPI_2420_SIZE,
84 .virtual = DSP_MMU_2420_VIRT,
85 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
86 .length = DSP_MMU_2420_SIZE,
93 #ifdef CONFIG_SOC_OMAP2430
94 static struct map_desc omap243x_io_desc[] __initdata = {
96 .virtual = L4_WK_243X_VIRT,
97 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
98 .length = L4_WK_243X_SIZE,
102 .virtual = OMAP243X_GPMC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
104 .length = OMAP243X_GPMC_SIZE,
108 .virtual = OMAP243X_SDRC_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
110 .length = OMAP243X_SDRC_SIZE,
114 .virtual = OMAP243X_SMS_VIRT,
115 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
116 .length = OMAP243X_SMS_SIZE,
123 #ifdef CONFIG_ARCH_OMAP3
124 static struct map_desc omap34xx_io_desc[] __initdata = {
126 .virtual = L3_34XX_VIRT,
127 .pfn = __phys_to_pfn(L3_34XX_PHYS),
128 .length = L3_34XX_SIZE,
132 .virtual = L4_34XX_VIRT,
133 .pfn = __phys_to_pfn(L4_34XX_PHYS),
134 .length = L4_34XX_SIZE,
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
167 #if defined(CONFIG_DEBUG_LL) && \
168 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
170 .virtual = ZOOM_UART_VIRT,
171 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
179 #ifdef CONFIG_SOC_OMAPTI816X
180 static struct map_desc omapti816x_io_desc[] __initdata = {
182 .virtual = L4_34XX_VIRT,
183 .pfn = __phys_to_pfn(L4_34XX_PHYS),
184 .length = L4_34XX_SIZE,
190 #ifdef CONFIG_ARCH_OMAP4
191 static struct map_desc omap44xx_io_desc[] __initdata = {
193 .virtual = L3_44XX_VIRT,
194 .pfn = __phys_to_pfn(L3_44XX_PHYS),
195 .length = L3_44XX_SIZE,
199 .virtual = L4_44XX_VIRT,
200 .pfn = __phys_to_pfn(L4_44XX_PHYS),
201 .length = L4_44XX_SIZE,
205 .virtual = OMAP44XX_GPMC_VIRT,
206 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
207 .length = OMAP44XX_GPMC_SIZE,
211 .virtual = OMAP44XX_EMIF1_VIRT,
212 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
213 .length = OMAP44XX_EMIF1_SIZE,
217 .virtual = OMAP44XX_EMIF2_VIRT,
218 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
219 .length = OMAP44XX_EMIF2_SIZE,
223 .virtual = OMAP44XX_DMM_VIRT,
224 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
225 .length = OMAP44XX_DMM_SIZE,
229 .virtual = L4_PER_44XX_VIRT,
230 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
231 .length = L4_PER_44XX_SIZE,
235 .virtual = L4_EMU_44XX_VIRT,
236 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
237 .length = L4_EMU_44XX_SIZE,
243 #ifdef CONFIG_SOC_OMAP2420
244 void __init omap242x_map_common_io(void)
246 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
247 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
251 #ifdef CONFIG_SOC_OMAP2430
252 void __init omap243x_map_common_io(void)
254 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
255 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
259 #ifdef CONFIG_ARCH_OMAP3
260 void __init omap34xx_map_common_io(void)
262 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
266 #ifdef CONFIG_SOC_OMAPTI816X
267 void __init omapti816x_map_common_io(void)
269 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
273 #ifdef CONFIG_ARCH_OMAP4
274 void __init omap44xx_map_common_io(void)
276 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
281 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
283 * Sets the CORE DPLL3 M2 divider to the same value that it's at
284 * currently. This has the effect of setting the SDRC SDRAM AC timing
285 * registers to the values currently defined by the kernel. Currently
286 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
287 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
288 * or passes along the return value of clk_set_rate().
290 static int __init _omap2_init_reprogram_sdrc(void)
292 struct clk *dpll3_m2_ck;
296 if (!cpu_is_omap34xx())
299 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
300 if (IS_ERR(dpll3_m2_ck))
303 rate = clk_get_rate(dpll3_m2_ck);
304 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
305 v = clk_set_rate(dpll3_m2_ck, rate);
307 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
309 clk_put(dpll3_m2_ck);
314 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
316 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
319 /* See irq.c, omap4-common.c and entry-macro.S */
320 void __iomem *omap_irq_base;
322 static void __init omap_common_init_early(void)
324 omap2_check_revision();
326 omap_init_consistent_dma_size();
329 static void __init omap_hwmod_init_postsetup(void)
333 /* Set the default postsetup state for all hwmods */
334 #ifdef CONFIG_PM_RUNTIME
335 postsetup_state = _HWMOD_STATE_IDLE;
337 postsetup_state = _HWMOD_STATE_ENABLED;
339 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
342 * Set the default postsetup state for unusual modules (like
345 * The postsetup_state is not actually used until
346 * omap_hwmod_late_init(), so boards that desire full watchdog
347 * coverage of kernel initialization can reprogram the
348 * postsetup_state between the calls to
349 * omap2_init_common_infra() and omap_sdrc_init().
351 * XXX ideally we could detect whether the MPU WDT was currently
352 * enabled here and make this conditional
354 postsetup_state = _HWMOD_STATE_DISABLED;
355 omap_hwmod_for_each_by_class("wd_timer",
356 _set_hwmod_postsetup_state,
359 omap_pm_if_early_init();
362 void __init omap2420_init_early(void)
364 omap2_set_globals_242x();
365 omap_common_init_early();
366 omap2xxx_voltagedomains_init();
367 omap242x_powerdomains_init();
368 omap242x_clockdomains_init();
369 omap2420_hwmod_init();
370 omap_hwmod_init_postsetup();
374 void __init omap2430_init_early(void)
376 omap2_set_globals_243x();
377 omap_common_init_early();
378 omap2xxx_voltagedomains_init();
379 omap243x_powerdomains_init();
380 omap243x_clockdomains_init();
381 omap2430_hwmod_init();
382 omap_hwmod_init_postsetup();
387 * Currently only board-omap3beagle.c should call this because of the
388 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
390 void __init omap3_init_early(void)
392 omap2_set_globals_3xxx();
393 omap_common_init_early();
394 omap3xxx_voltagedomains_init();
395 omap3xxx_powerdomains_init();
396 omap3xxx_clockdomains_init();
397 omap3xxx_hwmod_init();
398 omap_hwmod_init_postsetup();
402 void __init omap3430_init_early(void)
407 void __init omap35xx_init_early(void)
412 void __init omap3630_init_early(void)
417 void __init am35xx_init_early(void)
422 void __init ti816x_init_early(void)
424 omap2_set_globals_ti816x();
425 omap_common_init_early();
426 omap3xxx_voltagedomains_init();
427 omap3xxx_powerdomains_init();
428 omap3xxx_clockdomains_init();
429 omap3xxx_hwmod_init();
430 omap_hwmod_init_postsetup();
434 void __init omap4430_init_early(void)
436 omap2_set_globals_443x();
437 omap_common_init_early();
438 omap44xx_voltagedomains_init();
439 omap44xx_powerdomains_init();
440 omap44xx_clockdomains_init();
441 omap44xx_hwmod_init();
442 omap_hwmod_init_postsetup();
446 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
447 struct omap_sdrc_params *sdrc_cs1)
451 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
452 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
453 _omap2_init_reprogram_sdrc();
458 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
461 u8 omap_readb(u32 pa)
463 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
465 EXPORT_SYMBOL(omap_readb);
467 u16 omap_readw(u32 pa)
469 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
471 EXPORT_SYMBOL(omap_readw);
473 u32 omap_readl(u32 pa)
475 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
477 EXPORT_SYMBOL(omap_readl);
479 void omap_writeb(u8 v, u32 pa)
481 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
483 EXPORT_SYMBOL(omap_writeb);
485 void omap_writew(u16 v, u32 pa)
487 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
489 EXPORT_SYMBOL(omap_writew);
491 void omap_writel(u32 v, u32 pa)
493 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
495 EXPORT_SYMBOL(omap_writel);