arch/arm/mach-omap2/io.c

   1 /*
   2  * linux/arch/arm/mach-omap2/io.c
   3  *
   4  * OMAP2 I/O mapping code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Copyright (C) 2007-2009 Texas Instruments
   8  *
   9  * Author:
  10  *      Juha Yrjola <juha.yrjola@nokia.com>
  11  *      Syed Khasim <x0khasim@ti.com>
  12  *
  13  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/tlb.h>
  26 #include <asm/mach/map.h>
  27
  28 #include <linux/omap-dma.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "soc.h"
  32 #include "iomap.h"
  33 #include "voltage.h"
  34 #include "powerdomain.h"
  35 #include "clockdomain.h"
  36 #include "common.h"
  37 #include "clock.h"
  38 #include "clock2xxx.h"
  39 #include "clock3xxx.h"
  40 #include "clock44xx.h"
  41 #include "omap-pm.h"
  42 #include "sdrc.h"
  43 #include "control.h"
  44 #include "serial.h"
  45 #include "sram.h"
  46 #include "cm2xxx.h"
  47 #include "cm3xxx.h"
  48 #include "cm33xx.h"
  49 #include "cm44xx.h"
  50 #include "prm.h"
  51 #include "cm.h"
  52 #include "prcm_mpu44xx.h"
  53 #include "prminst44xx.h"
  54 #include "prm2xxx.h"
  55 #include "prm3xxx.h"
  56 #include "prm33xx.h"
  57 #include "prm44xx.h"
  58 #include "opp2xxx.h"
  59
  60 /*
  61  * omap_clk_soc_init: points to a function that does the SoC-specific
  62  * clock initializations
  63  */
  64 static int (*omap_clk_soc_init)(void);
  65
  66 /*
  67  * The machine specific code may provide the extra mapping besides the
  68  * default mapping provided here.
  69  */
  70
  71 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
  72 static struct map_desc omap24xx_io_desc[] __initdata = {
  73         {
  74                 .virtual        = L3_24XX_VIRT,
  75                 .pfn            = __phys_to_pfn(L3_24XX_PHYS),
  76                 .length         = L3_24XX_SIZE,
  77                 .type           = MT_DEVICE
  78         },
  79         {
  80                 .virtual        = L4_24XX_VIRT,
  81                 .pfn            = __phys_to_pfn(L4_24XX_PHYS),
  82                 .length         = L4_24XX_SIZE,
  83                 .type           = MT_DEVICE
  84         },
  85 };
  86
  87 #ifdef CONFIG_SOC_OMAP2420
  88 static struct map_desc omap242x_io_desc[] __initdata = {
  89         {
  90                 .virtual        = DSP_MEM_2420_VIRT,
  91                 .pfn            = __phys_to_pfn(DSP_MEM_2420_PHYS),
  92                 .length         = DSP_MEM_2420_SIZE,
  93                 .type           = MT_DEVICE
  94         },
  95         {
  96                 .virtual        = DSP_IPI_2420_VIRT,
  97                 .pfn            = __phys_to_pfn(DSP_IPI_2420_PHYS),
  98                 .length         = DSP_IPI_2420_SIZE,
  99                 .type           = MT_DEVICE
 100         },
 101         {
 102                 .virtual        = DSP_MMU_2420_VIRT,
 103                 .pfn            = __phys_to_pfn(DSP_MMU_2420_PHYS),
 104                 .length         = DSP_MMU_2420_SIZE,
 105                 .type           = MT_DEVICE
 106         },
 107 };
 108
 109 #endif
 110
 111 #ifdef CONFIG_SOC_OMAP2430
 112 static struct map_desc omap243x_io_desc[] __initdata = {
 113         {
 114                 .virtual        = L4_WK_243X_VIRT,
 115                 .pfn            = __phys_to_pfn(L4_WK_243X_PHYS),
 116                 .length         = L4_WK_243X_SIZE,
 117                 .type           = MT_DEVICE
 118         },
 119         {
 120                 .virtual        = OMAP243X_GPMC_VIRT,
 121                 .pfn            = __phys_to_pfn(OMAP243X_GPMC_PHYS),
 122                 .length         = OMAP243X_GPMC_SIZE,
 123                 .type           = MT_DEVICE
 124         },
 125         {
 126                 .virtual        = OMAP243X_SDRC_VIRT,
 127                 .pfn            = __phys_to_pfn(OMAP243X_SDRC_PHYS),
 128                 .length         = OMAP243X_SDRC_SIZE,
 129                 .type           = MT_DEVICE
 130         },
 131         {
 132                 .virtual        = OMAP243X_SMS_VIRT,
 133                 .pfn            = __phys_to_pfn(OMAP243X_SMS_PHYS),
 134                 .length         = OMAP243X_SMS_SIZE,
 135                 .type           = MT_DEVICE
 136         },
 137 };
 138 #endif
 139 #endif
 140
 141 #ifdef  CONFIG_ARCH_OMAP3
 142 static struct map_desc omap34xx_io_desc[] __initdata = {
 143         {
 144                 .virtual        = L3_34XX_VIRT,
 145                 .pfn            = __phys_to_pfn(L3_34XX_PHYS),
 146                 .length         = L3_34XX_SIZE,
 147                 .type           = MT_DEVICE
 148         },
 149         {
 150                 .virtual        = L4_34XX_VIRT,
 151                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 152                 .length         = L4_34XX_SIZE,
 153                 .type           = MT_DEVICE
 154         },
 155         {
 156                 .virtual        = OMAP34XX_GPMC_VIRT,
 157                 .pfn            = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
 158                 .length         = OMAP34XX_GPMC_SIZE,
 159                 .type           = MT_DEVICE
 160         },
 161         {
 162                 .virtual        = OMAP343X_SMS_VIRT,
 163                 .pfn            = __phys_to_pfn(OMAP343X_SMS_PHYS),
 164                 .length         = OMAP343X_SMS_SIZE,
 165                 .type           = MT_DEVICE
 166         },
 167         {
 168                 .virtual        = OMAP343X_SDRC_VIRT,
 169                 .pfn            = __phys_to_pfn(OMAP343X_SDRC_PHYS),
 170                 .length         = OMAP343X_SDRC_SIZE,
 171                 .type           = MT_DEVICE
 172         },
 173         {
 174                 .virtual        = L4_PER_34XX_VIRT,
 175                 .pfn            = __phys_to_pfn(L4_PER_34XX_PHYS),
 176                 .length         = L4_PER_34XX_SIZE,
 177                 .type           = MT_DEVICE
 178         },
 179         {
 180                 .virtual        = L4_EMU_34XX_VIRT,
 181                 .pfn            = __phys_to_pfn(L4_EMU_34XX_PHYS),
 182                 .length         = L4_EMU_34XX_SIZE,
 183                 .type           = MT_DEVICE
 184         },
 185 };
 186 #endif
 187
 188 #ifdef CONFIG_SOC_TI81XX
 189 static struct map_desc omapti81xx_io_desc[] __initdata = {
 190         {
 191                 .virtual        = L4_34XX_VIRT,
 192                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 193                 .length         = L4_34XX_SIZE,
 194                 .type           = MT_DEVICE
 195         }
 196 };
 197 #endif
 198
 199 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 200 static struct map_desc omapam33xx_io_desc[] __initdata = {
 201         {
 202                 .virtual        = L4_34XX_VIRT,
 203                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 204                 .length         = L4_34XX_SIZE,
 205                 .type           = MT_DEVICE
 206         },
 207         {
 208                 .virtual        = L4_WK_AM33XX_VIRT,
 209                 .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
 210                 .length         = L4_WK_AM33XX_SIZE,
 211                 .type           = MT_DEVICE
 212         }
 213 };
 214 #endif
 215
 216 #ifdef  CONFIG_ARCH_OMAP4
 217 static struct map_desc omap44xx_io_desc[] __initdata = {
 218         {
 219                 .virtual        = L3_44XX_VIRT,
 220                 .pfn            = __phys_to_pfn(L3_44XX_PHYS),
 221                 .length         = L3_44XX_SIZE,
 222                 .type           = MT_DEVICE,
 223         },
 224         {
 225                 .virtual        = L4_44XX_VIRT,
 226                 .pfn            = __phys_to_pfn(L4_44XX_PHYS),
 227                 .length         = L4_44XX_SIZE,
 228                 .type           = MT_DEVICE,
 229         },
 230         {
 231                 .virtual        = L4_PER_44XX_VIRT,
 232                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
 233                 .length         = L4_PER_44XX_SIZE,
 234                 .type           = MT_DEVICE,
 235         },
 236 };
 237 #endif
 238
 239 #ifdef CONFIG_SOC_OMAP5
 240 static struct map_desc omap54xx_io_desc[] __initdata = {
 241         {
 242                 .virtual        = L3_54XX_VIRT,
 243                 .pfn            = __phys_to_pfn(L3_54XX_PHYS),
 244                 .length         = L3_54XX_SIZE,
 245                 .type           = MT_DEVICE,
 246         },
 247         {
 248                 .virtual        = L4_54XX_VIRT,
 249                 .pfn            = __phys_to_pfn(L4_54XX_PHYS),
 250                 .length         = L4_54XX_SIZE,
 251                 .type           = MT_DEVICE,
 252         },
 253         {
 254                 .virtual        = L4_WK_54XX_VIRT,
 255                 .pfn            = __phys_to_pfn(L4_WK_54XX_PHYS),
 256                 .length         = L4_WK_54XX_SIZE,
 257                 .type           = MT_DEVICE,
 258         },
 259         {
 260                 .virtual        = L4_PER_54XX_VIRT,
 261                 .pfn            = __phys_to_pfn(L4_PER_54XX_PHYS),
 262                 .length         = L4_PER_54XX_SIZE,
 263                 .type           = MT_DEVICE,
 264         },
 265 };
 266 #endif
 267
 268 #ifdef CONFIG_SOC_DRA7XX
 269 static struct map_desc dra7xx_io_desc[] __initdata = {
 270         {
 271                 .virtual        = L4_CFG_MPU_DRA7XX_VIRT,
 272                 .pfn            = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
 273                 .length         = L4_CFG_MPU_DRA7XX_SIZE,
 274                 .type           = MT_DEVICE,
 275         },
 276         {
 277                 .virtual        = L3_MAIN_SN_DRA7XX_VIRT,
 278                 .pfn            = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
 279                 .length         = L3_MAIN_SN_DRA7XX_SIZE,
 280                 .type           = MT_DEVICE,
 281         },
 282         {
 283                 .virtual        = L4_PER1_DRA7XX_VIRT,
 284                 .pfn            = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
 285                 .length         = L4_PER1_DRA7XX_SIZE,
 286                 .type           = MT_DEVICE,
 287         },
 288         {
 289                 .virtual        = L4_PER2_DRA7XX_VIRT,
 290                 .pfn            = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
 291                 .length         = L4_PER2_DRA7XX_SIZE,
 292                 .type           = MT_DEVICE,
 293         },
 294         {
 295                 .virtual        = L4_PER3_DRA7XX_VIRT,
 296                 .pfn            = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
 297                 .length         = L4_PER3_DRA7XX_SIZE,
 298                 .type           = MT_DEVICE,
 299         },
 300         {
 301                 .virtual        = L4_CFG_DRA7XX_VIRT,
 302                 .pfn            = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
 303                 .length         = L4_CFG_DRA7XX_SIZE,
 304                 .type           = MT_DEVICE,
 305         },
 306         {
 307                 .virtual        = L4_WKUP_DRA7XX_VIRT,
 308                 .pfn            = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
 309                 .length         = L4_WKUP_DRA7XX_SIZE,
 310                 .type           = MT_DEVICE,
 311         },
 312 };
 313 #endif
 314
 315 #ifdef CONFIG_SOC_OMAP2420
 316 void __init omap242x_map_io(void)
 317 {
 318         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 319         iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
 320 }
 321 #endif
 322
 323 #ifdef CONFIG_SOC_OMAP2430
 324 void __init omap243x_map_io(void)
 325 {
 326         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 327         iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
 328 }
 329 #endif
 330
 331 #ifdef CONFIG_ARCH_OMAP3
 332 void __init omap3_map_io(void)
 333 {
 334         iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 335 }
 336 #endif
 337
 338 #ifdef CONFIG_SOC_TI81XX
 339 void __init ti81xx_map_io(void)
 340 {
 341         iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
 342 }
 343 #endif
 344
 345 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 346 void __init am33xx_map_io(void)
 347 {
 348         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 349 }
 350 #endif
 351
 352 #ifdef CONFIG_ARCH_OMAP4
 353 void __init omap4_map_io(void)
 354 {
 355         iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
 356 }
 357 #endif
 358
 359 #ifdef CONFIG_SOC_OMAP5
 360 void __init omap5_map_io(void)
 361 {
 362         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
 363 }
 364 #endif
 365
 366 #ifdef CONFIG_SOC_DRA7XX
 367 void __init dra7xx_map_io(void)
 368 {
 369         iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
 370 }
 371 #endif
 372 /*
 373  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 374  *
 375  * Sets the CORE DPLL3 M2 divider to the same value that it's at
 376  * currently.  This has the effect of setting the SDRC SDRAM AC timing
 377  * registers to the values currently defined by the kernel.  Currently
 378  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 379  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 380  * or passes along the return value of clk_set_rate().
 381  */
 382 static int __init _omap2_init_reprogram_sdrc(void)
 383 {
 384         struct clk *dpll3_m2_ck;
 385         int v = -EINVAL;
 386         long rate;
 387
 388         if (!cpu_is_omap34xx())
 389                 return 0;
 390
 391         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
 392         if (IS_ERR(dpll3_m2_ck))
 393                 return -EINVAL;
 394
 395         rate = clk_get_rate(dpll3_m2_ck);
 396         pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
 397         v = clk_set_rate(dpll3_m2_ck, rate);
 398         if (v)
 399                 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
 400
 401         clk_put(dpll3_m2_ck);
 402
 403         return v;
 404 }
 405
 406 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 407 {
 408         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 409 }
 410
 411 static void __init omap_hwmod_init_postsetup(void)
 412 {
 413         u8 postsetup_state;
 414
 415         /* Set the default postsetup state for all hwmods */
 416 #ifdef CONFIG_PM
 417         postsetup_state = _HWMOD_STATE_IDLE;
 418 #else
 419         postsetup_state = _HWMOD_STATE_ENABLED;
 420 #endif
 421         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 422
 423         omap_pm_if_early_init();
 424 }
 425
 426 static void __init __maybe_unused omap_common_late_init(void)
 427 {
 428         omap_mux_late_init();
 429         omap2_common_pm_late_init();
 430         omap_soc_device_init();
 431 }
 432
 433 #ifdef CONFIG_SOC_OMAP2420
 434 void __init omap2420_init_early(void)
 435 {
 436         omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
 437         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
 438                                OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
 439         omap2_control_base_init();
 440         omap2xxx_check_revision();
 441         omap2_prcm_base_init();
 442         omap2xxx_voltagedomains_init();
 443         omap242x_powerdomains_init();
 444         omap242x_clockdomains_init();
 445         omap2420_hwmod_init();
 446         omap_hwmod_init_postsetup();
 447         omap_clk_soc_init = omap2420_dt_clk_init;
 448         rate_table = omap2420_rate_table;
 449 }
 450
 451 void __init omap2420_init_late(void)
 452 {
 453         omap_common_late_init();
 454         omap2_pm_init();
 455         omap2_clk_enable_autoidle_all();
 456 }
 457 #endif
 458
 459 #ifdef CONFIG_SOC_OMAP2430
 460 void __init omap2430_init_early(void)
 461 {
 462         omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
 463         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
 464                                OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
 465         omap2_control_base_init();
 466         omap2xxx_check_revision();
 467         omap2_prcm_base_init();
 468         omap2xxx_voltagedomains_init();
 469         omap243x_powerdomains_init();
 470         omap243x_clockdomains_init();
 471         omap2430_hwmod_init();
 472         omap_hwmod_init_postsetup();
 473         omap_clk_soc_init = omap2430_dt_clk_init;
 474         rate_table = omap2430_rate_table;
 475 }
 476
 477 void __init omap2430_init_late(void)
 478 {
 479         omap_common_late_init();
 480         omap2_pm_init();
 481         omap2_clk_enable_autoidle_all();
 482 }
 483 #endif
 484
 485 /*
 486  * Currently only board-omap3beagle.c should call this because of the
 487  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 488  */
 489 #ifdef CONFIG_ARCH_OMAP3
 490 void __init omap3_init_early(void)
 491 {
 492         omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
 493         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
 494                                OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
 495         /* XXX: remove these once OMAP3 is DT only */
 496         if (!of_have_populated_dt()) {
 497                 omap2_set_globals_control(
 498                         OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
 499                 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
 500                 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
 501                                      NULL);
 502         }
 503         omap2_control_base_init();
 504         omap3xxx_check_revision();
 505         omap3xxx_check_features();
 506         omap2_prcm_base_init();
 507         /* XXX: remove these once OMAP3 is DT only */
 508         if (!of_have_populated_dt()) {
 509                 omap3xxx_prm_init(NULL);
 510                 omap3xxx_cm_init(NULL);
 511         }
 512         omap3xxx_voltagedomains_init();
 513         omap3xxx_powerdomains_init();
 514         omap3xxx_clockdomains_init();
 515         omap3xxx_hwmod_init();
 516         omap_hwmod_init_postsetup();
 517         if (!of_have_populated_dt()) {
 518                 omap3_control_legacy_iomap_init();
 519                 if (soc_is_am35xx())
 520                         omap_clk_soc_init = am35xx_clk_legacy_init;
 521                 else if (cpu_is_omap3630())
 522                         omap_clk_soc_init = omap36xx_clk_legacy_init;
 523                 else if (omap_rev() == OMAP3430_REV_ES1_0)
 524                         omap_clk_soc_init = omap3430es1_clk_legacy_init;
 525                 else
 526                         omap_clk_soc_init = omap3430_clk_legacy_init;
 527         }
 528 }
 529
 530 void __init omap3430_init_early(void)
 531 {
 532         omap3_init_early();
 533         if (of_have_populated_dt())
 534                 omap_clk_soc_init = omap3430_dt_clk_init;
 535 }
 536
 537 void __init omap35xx_init_early(void)
 538 {
 539         omap3_init_early();
 540         if (of_have_populated_dt())
 541                 omap_clk_soc_init = omap3430_dt_clk_init;
 542 }
 543
 544 void __init omap3630_init_early(void)
 545 {
 546         omap3_init_early();
 547         if (of_have_populated_dt())
 548                 omap_clk_soc_init = omap3630_dt_clk_init;
 549 }
 550
 551 void __init am35xx_init_early(void)
 552 {
 553         omap3_init_early();
 554         if (of_have_populated_dt())
 555                 omap_clk_soc_init = am35xx_dt_clk_init;
 556 }
 557
 558 void __init omap3_init_late(void)
 559 {
 560         omap_common_late_init();
 561         omap3_pm_init();
 562         omap2_clk_enable_autoidle_all();
 563 }
 564
 565 void __init omap3430_init_late(void)
 566 {
 567         omap_common_late_init();
 568         omap3_pm_init();
 569         omap2_clk_enable_autoidle_all();
 570 }
 571
 572 void __init omap35xx_init_late(void)
 573 {
 574         omap_common_late_init();
 575         omap3_pm_init();
 576         omap2_clk_enable_autoidle_all();
 577 }
 578
 579 void __init omap3630_init_late(void)
 580 {
 581         omap_common_late_init();
 582         omap3_pm_init();
 583         omap2_clk_enable_autoidle_all();
 584 }
 585
 586 void __init am35xx_init_late(void)
 587 {
 588         omap_common_late_init();
 589         omap3_pm_init();
 590         omap2_clk_enable_autoidle_all();
 591 }
 592
 593 void __init ti81xx_init_late(void)
 594 {
 595         omap_common_late_init();
 596         omap2_clk_enable_autoidle_all();
 597 }
 598 #endif
 599
 600 #ifdef CONFIG_SOC_TI81XX
 601 void __init ti814x_init_early(void)
 602 {
 603         omap2_set_globals_tap(TI814X_CLASS,
 604                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 605         omap2_control_base_init();
 606         omap3xxx_check_revision();
 607         ti81xx_check_features();
 608         omap2_prcm_base_init();
 609         omap3xxx_voltagedomains_init();
 610         omap3xxx_powerdomains_init();
 611         ti81xx_clockdomains_init();
 612         ti81xx_hwmod_init();
 613         omap_hwmod_init_postsetup();
 614         if (of_have_populated_dt())
 615                 omap_clk_soc_init = ti81xx_dt_clk_init;
 616 }
 617
 618 void __init ti816x_init_early(void)
 619 {
 620         omap2_set_globals_tap(TI816X_CLASS,
 621                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 622         omap2_control_base_init();
 623         omap3xxx_check_revision();
 624         ti81xx_check_features();
 625         omap2_prcm_base_init();
 626         omap3xxx_voltagedomains_init();
 627         omap3xxx_powerdomains_init();
 628         ti81xx_clockdomains_init();
 629         ti81xx_hwmod_init();
 630         omap_hwmod_init_postsetup();
 631         if (of_have_populated_dt())
 632                 omap_clk_soc_init = ti81xx_dt_clk_init;
 633 }
 634 #endif
 635
 636 #ifdef CONFIG_SOC_AM33XX
 637 void __init am33xx_init_early(void)
 638 {
 639         omap2_set_globals_tap(AM335X_CLASS,
 640                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 641         omap2_control_base_init();
 642         omap3xxx_check_revision();
 643         am33xx_check_features();
 644         omap2_prcm_base_init();
 645         am33xx_powerdomains_init();
 646         am33xx_clockdomains_init();
 647         am33xx_hwmod_init();
 648         omap_hwmod_init_postsetup();
 649         omap_clk_soc_init = am33xx_dt_clk_init;
 650 }
 651
 652 void __init am33xx_init_late(void)
 653 {
 654         omap_common_late_init();
 655 }
 656 #endif
 657
 658 #ifdef CONFIG_SOC_AM43XX
 659 void __init am43xx_init_early(void)
 660 {
 661         omap2_set_globals_tap(AM335X_CLASS,
 662                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 663         omap2_control_base_init();
 664         omap3xxx_check_revision();
 665         am33xx_check_features();
 666         omap2_prcm_base_init();
 667         am43xx_powerdomains_init();
 668         am43xx_clockdomains_init();
 669         am43xx_hwmod_init();
 670         omap_hwmod_init_postsetup();
 671         omap_l2_cache_init();
 672         omap_clk_soc_init = am43xx_dt_clk_init;
 673 }
 674
 675 void __init am43xx_init_late(void)
 676 {
 677         omap_common_late_init();
 678 }
 679 #endif
 680
 681 #ifdef CONFIG_ARCH_OMAP4
 682 void __init omap4430_init_early(void)
 683 {
 684         omap2_set_globals_tap(OMAP443X_CLASS,
 685                               OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
 686         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
 687         omap2_control_base_init();
 688         omap4xxx_check_revision();
 689         omap4xxx_check_features();
 690         omap2_prcm_base_init();
 691         omap4_pm_init_early();
 692         omap44xx_voltagedomains_init();
 693         omap44xx_powerdomains_init();
 694         omap44xx_clockdomains_init();
 695         omap44xx_hwmod_init();
 696         omap_hwmod_init_postsetup();
 697         omap_l2_cache_init();
 698         omap_clk_soc_init = omap4xxx_dt_clk_init;
 699 }
 700
 701 void __init omap4430_init_late(void)
 702 {
 703         omap_common_late_init();
 704         omap4_pm_init();
 705         omap2_clk_enable_autoidle_all();
 706 }
 707 #endif
 708
 709 #ifdef CONFIG_SOC_OMAP5
 710 void __init omap5_init_early(void)
 711 {
 712         omap2_set_globals_tap(OMAP54XX_CLASS,
 713                               OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
 714         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 715         omap2_control_base_init();
 716         omap4_pm_init_early();
 717         omap2_prcm_base_init();
 718         omap5xxx_check_revision();
 719         omap54xx_voltagedomains_init();
 720         omap54xx_powerdomains_init();
 721         omap54xx_clockdomains_init();
 722         omap54xx_hwmod_init();
 723         omap_hwmod_init_postsetup();
 724         omap_clk_soc_init = omap5xxx_dt_clk_init;
 725 }
 726
 727 void __init omap5_init_late(void)
 728 {
 729         omap_common_late_init();
 730         omap4_pm_init();
 731         omap2_clk_enable_autoidle_all();
 732 }
 733 #endif
 734
 735 #ifdef CONFIG_SOC_DRA7XX
 736 void __init dra7xx_init_early(void)
 737 {
 738         omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
 739         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 740         omap2_control_base_init();
 741         omap4_pm_init_early();
 742         omap2_prcm_base_init();
 743         dra7xxx_check_revision();
 744         dra7xx_powerdomains_init();
 745         dra7xx_clockdomains_init();
 746         dra7xx_hwmod_init();
 747         omap_hwmod_init_postsetup();
 748         omap_clk_soc_init = dra7xx_dt_clk_init;
 749 }
 750
 751 void __init dra7xx_init_late(void)
 752 {
 753         omap_common_late_init();
 754         omap4_pm_init();
 755         omap2_clk_enable_autoidle_all();
 756 }
 757 #endif
 758
 759
 760 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 761                                       struct omap_sdrc_params *sdrc_cs1)
 762 {
 763         omap_sram_init();
 764
 765         if (cpu_is_omap24xx() || omap3_has_sdrc()) {
 766                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 767                 _omap2_init_reprogram_sdrc();
 768         }
 769 }
 770
 771 int __init omap_clk_init(void)
 772 {
 773         int ret = 0;
 774
 775         if (!omap_clk_soc_init)
 776                 return 0;
 777
 778         ti_clk_init_features();
 779
 780         if (of_have_populated_dt()) {
 781                 ret = omap_control_init();
 782                 if (ret)
 783                         return ret;
 784
 785                 ret = omap_prcm_init();
 786                 if (ret)
 787                         return ret;
 788
 789                 of_clk_init(NULL);
 790
 791                 ti_dt_clk_init_retry_clks();
 792
 793                 ti_dt_clockdomains_setup();
 794         }
 795
 796         ret = omap_clk_soc_init();
 797
 798         return ret;
 799 }