2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
29 #include <asm/mach/map.h>
32 #include <plat/sram.h>
33 #include <plat/sdrc.h>
34 #include <plat/gpmc.h>
35 #include <plat/serial.h>
36 #include <plat/vram.h>
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "clock44xx.h"
42 #include <plat/omap-pm.h>
43 #include <plat/powerdomain.h>
44 #include "powerdomains.h"
46 #include <plat/clockdomain.h>
47 #include "clockdomains.h"
49 #include <plat/omap_hwmod.h>
52 * The machine specific code may provide the extra mapping besides the
53 * default mapping provided here.
56 #ifdef CONFIG_ARCH_OMAP2
57 static struct map_desc omap24xx_io_desc[] __initdata = {
59 .virtual = L3_24XX_VIRT,
60 .pfn = __phys_to_pfn(L3_24XX_PHYS),
61 .length = L3_24XX_SIZE,
65 .virtual = L4_24XX_VIRT,
66 .pfn = __phys_to_pfn(L4_24XX_PHYS),
67 .length = L4_24XX_SIZE,
72 #ifdef CONFIG_ARCH_OMAP2420
73 static struct map_desc omap242x_io_desc[] __initdata = {
75 .virtual = DSP_MEM_2420_VIRT,
76 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
77 .length = DSP_MEM_2420_SIZE,
81 .virtual = DSP_IPI_2420_VIRT,
82 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
83 .length = DSP_IPI_2420_SIZE,
87 .virtual = DSP_MMU_2420_VIRT,
88 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
89 .length = DSP_MMU_2420_SIZE,
96 #ifdef CONFIG_ARCH_OMAP2430
97 static struct map_desc omap243x_io_desc[] __initdata = {
99 .virtual = L4_WK_243X_VIRT,
100 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
101 .length = L4_WK_243X_SIZE,
105 .virtual = OMAP243X_GPMC_VIRT,
106 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
107 .length = OMAP243X_GPMC_SIZE,
111 .virtual = OMAP243X_SDRC_VIRT,
112 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
113 .length = OMAP243X_SDRC_SIZE,
117 .virtual = OMAP243X_SMS_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
119 .length = OMAP243X_SMS_SIZE,
126 #ifdef CONFIG_ARCH_OMAP3
127 static struct map_desc omap34xx_io_desc[] __initdata = {
129 .virtual = L3_34XX_VIRT,
130 .pfn = __phys_to_pfn(L3_34XX_PHYS),
131 .length = L3_34XX_SIZE,
135 .virtual = L4_34XX_VIRT,
136 .pfn = __phys_to_pfn(L4_34XX_PHYS),
137 .length = L4_34XX_SIZE,
141 .virtual = OMAP34XX_GPMC_VIRT,
142 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
143 .length = OMAP34XX_GPMC_SIZE,
147 .virtual = OMAP343X_SMS_VIRT,
148 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
149 .length = OMAP343X_SMS_SIZE,
153 .virtual = OMAP343X_SDRC_VIRT,
154 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
155 .length = OMAP343X_SDRC_SIZE,
159 .virtual = L4_PER_34XX_VIRT,
160 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
161 .length = L4_PER_34XX_SIZE,
165 .virtual = L4_EMU_34XX_VIRT,
166 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
167 .length = L4_EMU_34XX_SIZE,
170 #if defined(CONFIG_DEBUG_LL) && \
171 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
173 .virtual = ZOOM_UART_VIRT,
174 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
181 #ifdef CONFIG_ARCH_OMAP4
182 static struct map_desc omap44xx_io_desc[] __initdata = {
184 .virtual = L3_44XX_VIRT,
185 .pfn = __phys_to_pfn(L3_44XX_PHYS),
186 .length = L3_44XX_SIZE,
190 .virtual = L4_44XX_VIRT,
191 .pfn = __phys_to_pfn(L4_44XX_PHYS),
192 .length = L4_44XX_SIZE,
196 .virtual = OMAP44XX_GPMC_VIRT,
197 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
198 .length = OMAP44XX_GPMC_SIZE,
202 .virtual = OMAP44XX_EMIF1_VIRT,
203 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
204 .length = OMAP44XX_EMIF1_SIZE,
208 .virtual = OMAP44XX_EMIF2_VIRT,
209 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
210 .length = OMAP44XX_EMIF2_SIZE,
214 .virtual = OMAP44XX_DMM_VIRT,
215 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
216 .length = OMAP44XX_DMM_SIZE,
220 .virtual = L4_PER_44XX_VIRT,
221 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
222 .length = L4_PER_44XX_SIZE,
226 .virtual = L4_EMU_44XX_VIRT,
227 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
228 .length = L4_EMU_44XX_SIZE,
234 static void __init _omap2_map_common_io(void)
236 /* Normally devicemaps_init() would flush caches and tlb after
237 * mdesc->map_io(), but we must also do it here because of the CPU
238 * revision check below.
240 local_flush_tlb_all();
243 omap2_check_revision();
245 omapfb_reserve_sdram();
246 omap_vram_reserve_sdram();
249 #ifdef CONFIG_ARCH_OMAP2420
250 void __init omap242x_map_common_io(void)
252 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
253 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
254 _omap2_map_common_io();
258 #ifdef CONFIG_ARCH_OMAP2430
259 void __init omap243x_map_common_io(void)
261 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
262 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
263 _omap2_map_common_io();
267 #ifdef CONFIG_ARCH_OMAP3
268 void __init omap34xx_map_common_io(void)
270 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
271 _omap2_map_common_io();
275 #ifdef CONFIG_ARCH_OMAP4
276 void __init omap44xx_map_common_io(void)
278 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
279 _omap2_map_common_io();
284 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
286 * Sets the CORE DPLL3 M2 divider to the same value that it's at
287 * currently. This has the effect of setting the SDRC SDRAM AC timing
288 * registers to the values currently defined by the kernel. Currently
289 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
290 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
291 * or passes along the return value of clk_set_rate().
293 static int __init _omap2_init_reprogram_sdrc(void)
295 struct clk *dpll3_m2_ck;
299 if (!cpu_is_omap34xx())
302 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
306 rate = clk_get_rate(dpll3_m2_ck);
307 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
308 v = clk_set_rate(dpll3_m2_ck, rate);
310 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
312 clk_put(dpll3_m2_ck);
317 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
318 struct omap_sdrc_params *sdrc_cs1)
320 u8 skip_setup_idle = 0;
322 pwrdm_init(powerdomains_omap);
323 clkdm_init(clockdomains_omap, clkdm_autodeps);
324 if (cpu_is_omap242x())
325 omap2420_hwmod_init();
326 else if (cpu_is_omap243x())
327 omap2430_hwmod_init();
328 else if (cpu_is_omap34xx())
329 omap3xxx_hwmod_init();
331 /* The OPP tables have to be registered before a clk init */
332 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
334 if (cpu_is_omap2420())
336 else if (cpu_is_omap2430())
338 else if (cpu_is_omap34xx())
340 else if (cpu_is_omap44xx())
343 pr_err("Could not init clock framework - unknown CPU\n");
345 omap_serial_early_init();
347 #ifndef CONFIG_PM_RUNTIME
350 if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
351 omap_hwmod_late_init(skip_setup_idle);
353 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
354 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
355 _omap2_init_reprogram_sdrc();