2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
29 #include <asm/mach/map.h>
32 #include <plat/sram.h>
33 #include <plat/sdrc.h>
34 #include <plat/gpmc.h>
35 #include <plat/serial.h>
37 #include "clock2xxx.h"
38 #include "clock3xxx.h"
39 #include "clock44xx.h"
41 #include <plat/omap-pm.h>
42 #include <plat/powerdomain.h>
43 #include "powerdomains.h"
45 #include <plat/clockdomain.h>
46 #include "clockdomains.h"
47 #include <plat/omap_hwmod.h>
50 * The machine specific code may provide the extra mapping besides the
51 * default mapping provided here.
54 #ifdef CONFIG_ARCH_OMAP2
55 static struct map_desc omap24xx_io_desc[] __initdata = {
57 .virtual = L3_24XX_VIRT,
58 .pfn = __phys_to_pfn(L3_24XX_PHYS),
59 .length = L3_24XX_SIZE,
63 .virtual = L4_24XX_VIRT,
64 .pfn = __phys_to_pfn(L4_24XX_PHYS),
65 .length = L4_24XX_SIZE,
70 #ifdef CONFIG_ARCH_OMAP2420
71 static struct map_desc omap242x_io_desc[] __initdata = {
73 .virtual = DSP_MEM_2420_VIRT,
74 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
75 .length = DSP_MEM_2420_SIZE,
79 .virtual = DSP_IPI_2420_VIRT,
80 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
81 .length = DSP_IPI_2420_SIZE,
85 .virtual = DSP_MMU_2420_VIRT,
86 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
87 .length = DSP_MMU_2420_SIZE,
94 #ifdef CONFIG_ARCH_OMAP2430
95 static struct map_desc omap243x_io_desc[] __initdata = {
97 .virtual = L4_WK_243X_VIRT,
98 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
99 .length = L4_WK_243X_SIZE,
103 .virtual = OMAP243X_GPMC_VIRT,
104 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
105 .length = OMAP243X_GPMC_SIZE,
109 .virtual = OMAP243X_SDRC_VIRT,
110 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
111 .length = OMAP243X_SDRC_SIZE,
115 .virtual = OMAP243X_SMS_VIRT,
116 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
117 .length = OMAP243X_SMS_SIZE,
124 #ifdef CONFIG_ARCH_OMAP3
125 static struct map_desc omap34xx_io_desc[] __initdata = {
127 .virtual = L3_34XX_VIRT,
128 .pfn = __phys_to_pfn(L3_34XX_PHYS),
129 .length = L3_34XX_SIZE,
133 .virtual = L4_34XX_VIRT,
134 .pfn = __phys_to_pfn(L4_34XX_PHYS),
135 .length = L4_34XX_SIZE,
139 .virtual = OMAP34XX_GPMC_VIRT,
140 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
141 .length = OMAP34XX_GPMC_SIZE,
145 .virtual = OMAP343X_SMS_VIRT,
146 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
147 .length = OMAP343X_SMS_SIZE,
151 .virtual = OMAP343X_SDRC_VIRT,
152 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
153 .length = OMAP343X_SDRC_SIZE,
157 .virtual = L4_PER_34XX_VIRT,
158 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
159 .length = L4_PER_34XX_SIZE,
163 .virtual = L4_EMU_34XX_VIRT,
164 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
165 .length = L4_EMU_34XX_SIZE,
168 #if defined(CONFIG_DEBUG_LL) && \
169 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
171 .virtual = ZOOM_UART_VIRT,
172 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
179 #ifdef CONFIG_ARCH_OMAP4
180 static struct map_desc omap44xx_io_desc[] __initdata = {
182 .virtual = L3_44XX_VIRT,
183 .pfn = __phys_to_pfn(L3_44XX_PHYS),
184 .length = L3_44XX_SIZE,
188 .virtual = L4_44XX_VIRT,
189 .pfn = __phys_to_pfn(L4_44XX_PHYS),
190 .length = L4_44XX_SIZE,
194 .virtual = OMAP44XX_GPMC_VIRT,
195 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
196 .length = OMAP44XX_GPMC_SIZE,
200 .virtual = OMAP44XX_EMIF1_VIRT,
201 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
202 .length = OMAP44XX_EMIF1_SIZE,
206 .virtual = OMAP44XX_EMIF2_VIRT,
207 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
208 .length = OMAP44XX_EMIF2_SIZE,
212 .virtual = OMAP44XX_DMM_VIRT,
213 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
214 .length = OMAP44XX_DMM_SIZE,
218 .virtual = L4_PER_44XX_VIRT,
219 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
220 .length = L4_PER_44XX_SIZE,
224 .virtual = L4_EMU_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
226 .length = L4_EMU_44XX_SIZE,
232 static void __init _omap2_map_common_io(void)
234 /* Normally devicemaps_init() would flush caches and tlb after
235 * mdesc->map_io(), but we must also do it here because of the CPU
236 * revision check below.
238 local_flush_tlb_all();
241 omap2_check_revision();
245 #ifdef CONFIG_ARCH_OMAP2420
246 void __init omap242x_map_common_io(void)
248 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
249 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
250 _omap2_map_common_io();
254 #ifdef CONFIG_ARCH_OMAP2430
255 void __init omap243x_map_common_io(void)
257 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
258 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
259 _omap2_map_common_io();
263 #ifdef CONFIG_ARCH_OMAP3
264 void __init omap34xx_map_common_io(void)
266 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
267 _omap2_map_common_io();
271 #ifdef CONFIG_ARCH_OMAP4
272 void __init omap44xx_map_common_io(void)
274 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
275 _omap2_map_common_io();
280 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
282 * Sets the CORE DPLL3 M2 divider to the same value that it's at
283 * currently. This has the effect of setting the SDRC SDRAM AC timing
284 * registers to the values currently defined by the kernel. Currently
285 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
286 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
287 * or passes along the return value of clk_set_rate().
289 static int __init _omap2_init_reprogram_sdrc(void)
291 struct clk *dpll3_m2_ck;
295 if (!cpu_is_omap34xx())
298 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
302 rate = clk_get_rate(dpll3_m2_ck);
303 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
304 v = clk_set_rate(dpll3_m2_ck, rate);
306 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
308 clk_put(dpll3_m2_ck);
313 void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
314 struct omap_sdrc_params *sdrc_cs1)
316 pwrdm_init(powerdomains_omap);
317 clkdm_init(clockdomains_omap, clkdm_autodeps);
318 if (cpu_is_omap242x())
319 omap2420_hwmod_init();
320 else if (cpu_is_omap243x())
321 omap2430_hwmod_init();
322 else if (cpu_is_omap34xx())
323 omap3xxx_hwmod_init();
325 /* The OPP tables have to be registered before a clk init */
326 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
328 if (cpu_is_omap2420())
330 else if (cpu_is_omap2430())
332 else if (cpu_is_omap34xx())
334 else if (cpu_is_omap44xx())
337 pr_err("Could not init clock framework - unknown CPU\n");
339 omap_serial_early_init();
340 if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
341 omap_hwmod_late_init();
343 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
344 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
345 _omap2_init_reprogram_sdrc();