arch/arm/mach-omap2/mux.c

   1 /*
   2  * linux/arch/arm/mach-omap2/mux.c
   3  *
   4  * OMAP2 and OMAP3 pin multiplexing configurations
   5  *
   6  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
   7  * Copyright (C) 2003 - 2008 Nokia Corporation
   8  *
   9  * Written by Tony Lindgren
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24  *
  25  */
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/ctype.h>
  33 #include <linux/debugfs.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/uaccess.h>
  36
  37 #include <asm/system.h>
  38
  39 #include <plat/control.h>
  40 #include <plat/mux.h>
  41
  42 #include "mux.h"
  43
  44 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
  45 #define OMAP_MUX_BASE_SZ                0x5ca
  46 #define MUXABLE_GPIO_MODE3              BIT(0)
  47
  48 struct omap_mux_entry {
  49         struct omap_mux         mux;
  50         struct list_head        node;
  51 };
  52
  53 static unsigned long mux_phys;
  54 static void __iomem *mux_base;
  55 static u8 omap_mux_flags;
  56
  57 u16 omap_mux_read(u16 reg)
  58 {
  59         if (cpu_is_omap24xx())
  60                 return __raw_readb(mux_base + reg);
  61         else
  62                 return __raw_readw(mux_base + reg);
  63 }
  64
  65 void omap_mux_write(u16 val, u16 reg)
  66 {
  67         if (cpu_is_omap24xx())
  68                 __raw_writeb(val, mux_base + reg);
  69         else
  70                 __raw_writew(val, mux_base + reg);
  71 }
  72
  73 void omap_mux_write_array(struct omap_board_mux *board_mux)
  74 {
  75         while (board_mux->reg_offset !=  OMAP_MUX_TERMINATOR) {
  76                 omap_mux_write(board_mux->value, board_mux->reg_offset);
  77                 board_mux++;
  78         }
  79 }
  80
  81 #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX)
  82
  83 static struct omap_mux_cfg arch_mux_cfg;
  84
  85 /* NOTE: See mux.h for the enumeration */
  86
  87 static struct pin_config __initdata_or_module omap24xx_pins[] = {
  88 /*
  89  *      description                     mux     mux     pull    pull    debug
  90  *                                      offset  mode    ena     type
  91  */
  92
  93 /* 24xx I2C */
  94 MUX_CFG_24XX("M19_24XX_I2C1_SCL",       0x111,  0,      0,      0,      1)
  95 MUX_CFG_24XX("L15_24XX_I2C1_SDA",       0x112,  0,      0,      0,      1)
  96 MUX_CFG_24XX("J15_24XX_I2C2_SCL",       0x113,  0,      0,      1,      1)
  97 MUX_CFG_24XX("H19_24XX_I2C2_SDA",       0x114,  0,      0,      0,      1)
  98
  99 /* Menelaus interrupt */
 100 MUX_CFG_24XX("W19_24XX_SYS_NIRQ",       0x12c,  0,      1,      1,      1)
 101
 102 /* 24xx clocks */
 103 MUX_CFG_24XX("W14_24XX_SYS_CLKOUT",     0x137,  0,      1,      1,      1)
 104
 105 /* 24xx GPMC chipselects, wait pin monitoring */
 106 MUX_CFG_24XX("E2_GPMC_NCS2",            0x08e,  0,      1,      1,      1)
 107 MUX_CFG_24XX("L2_GPMC_NCS7",            0x093,  0,      1,      1,      1)
 108 MUX_CFG_24XX("L3_GPMC_WAIT0",           0x09a,  0,      1,      1,      1)
 109 MUX_CFG_24XX("N7_GPMC_WAIT1",           0x09b,  0,      1,      1,      1)
 110 MUX_CFG_24XX("M1_GPMC_WAIT2",           0x09c,  0,      1,      1,      1)
 111 MUX_CFG_24XX("P1_GPMC_WAIT3",           0x09d,  0,      1,      1,      1)
 112
 113 /* 24xx McBSP */
 114 MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX",    0x124,  1,      1,      0,      1)
 115 MUX_CFG_24XX("R14_24XX_MCBSP2_FSX",     0x125,  1,      1,      0,      1)
 116 MUX_CFG_24XX("W15_24XX_MCBSP2_DR",      0x126,  1,      1,      0,      1)
 117 MUX_CFG_24XX("V15_24XX_MCBSP2_DX",      0x127,  1,      1,      0,      1)
 118
 119 /* 24xx GPIO */
 120 MUX_CFG_24XX("M21_242X_GPIO11",         0x0c9,  3,      1,      1,      1)
 121 MUX_CFG_24XX("P21_242X_GPIO12",         0x0ca,  3,      0,      0,      1)
 122 MUX_CFG_24XX("AA10_242X_GPIO13",        0x0e5,  3,      0,      0,      1)
 123 MUX_CFG_24XX("AA6_242X_GPIO14",         0x0e6,  3,      0,      0,      1)
 124 MUX_CFG_24XX("AA4_242X_GPIO15",         0x0e7,  3,      0,      0,      1)
 125 MUX_CFG_24XX("Y11_242X_GPIO16",         0x0e8,  3,      0,      0,      1)
 126 MUX_CFG_24XX("AA12_242X_GPIO17",        0x0e9,  3,      0,      0,      1)
 127 MUX_CFG_24XX("AA8_242X_GPIO58",         0x0ea,  3,      0,      0,      1)
 128 MUX_CFG_24XX("Y20_24XX_GPIO60",         0x12c,  3,      0,      0,      1)
 129 MUX_CFG_24XX("W4__24XX_GPIO74",         0x0f2,  3,      0,      0,      1)
 130 MUX_CFG_24XX("N15_24XX_GPIO85",         0x103,  3,      0,      0,      1)
 131 MUX_CFG_24XX("M15_24XX_GPIO92",         0x10a,  3,      0,      0,      1)
 132 MUX_CFG_24XX("P20_24XX_GPIO93",         0x10b,  3,      0,      0,      1)
 133 MUX_CFG_24XX("P18_24XX_GPIO95",         0x10d,  3,      0,      0,      1)
 134 MUX_CFG_24XX("M18_24XX_GPIO96",         0x10e,  3,      0,      0,      1)
 135 MUX_CFG_24XX("L14_24XX_GPIO97",         0x10f,  3,      0,      0,      1)
 136 MUX_CFG_24XX("J15_24XX_GPIO99",         0x113,  3,      1,      1,      1)
 137 MUX_CFG_24XX("V14_24XX_GPIO117",        0x128,  3,      1,      0,      1)
 138 MUX_CFG_24XX("P14_24XX_GPIO125",        0x140,  3,      1,      1,      1)
 139
 140 /* 242x DBG GPIO */
 141 MUX_CFG_24XX("V4_242X_GPIO49",          0xd3,   3,      0,      0,      1)
 142 MUX_CFG_24XX("W2_242X_GPIO50",          0xd4,   3,      0,      0,      1)
 143 MUX_CFG_24XX("U4_242X_GPIO51",          0xd5,   3,      0,      0,      1)
 144 MUX_CFG_24XX("V3_242X_GPIO52",          0xd6,   3,      0,      0,      1)
 145 MUX_CFG_24XX("V2_242X_GPIO53",          0xd7,   3,      0,      0,      1)
 146 MUX_CFG_24XX("V6_242X_GPIO53",          0xcf,   3,      0,      0,      1)
 147 MUX_CFG_24XX("T4_242X_GPIO54",          0xd8,   3,      0,      0,      1)
 148 MUX_CFG_24XX("Y4_242X_GPIO54",          0xd0,   3,      0,      0,      1)
 149 MUX_CFG_24XX("T3_242X_GPIO55",          0xd9,   3,      0,      0,      1)
 150 MUX_CFG_24XX("U2_242X_GPIO56",          0xda,   3,      0,      0,      1)
 151
 152 /* 24xx external DMA requests */
 153 MUX_CFG_24XX("AA10_242X_DMAREQ0",       0x0e5,  2,      0,      0,      1)
 154 MUX_CFG_24XX("AA6_242X_DMAREQ1",        0x0e6,  2,      0,      0,      1)
 155 MUX_CFG_24XX("E4_242X_DMAREQ2",         0x074,  2,      0,      0,      1)
 156 MUX_CFG_24XX("G4_242X_DMAREQ3",         0x073,  2,      0,      0,      1)
 157 MUX_CFG_24XX("D3_242X_DMAREQ4",         0x072,  2,      0,      0,      1)
 158 MUX_CFG_24XX("E3_242X_DMAREQ5",         0x071,  2,      0,      0,      1)
 159
 160 /* UART3 */
 161 MUX_CFG_24XX("K15_24XX_UART3_TX",       0x118,  0,      0,      0,      1)
 162 MUX_CFG_24XX("K14_24XX_UART3_RX",       0x119,  0,      0,      0,      1)
 163
 164 /* MMC/SDIO */
 165 MUX_CFG_24XX("G19_24XX_MMC_CLKO",       0x0f3,  0,      0,      0,      1)
 166 MUX_CFG_24XX("H18_24XX_MMC_CMD",        0x0f4,  0,      0,      0,      1)
 167 MUX_CFG_24XX("F20_24XX_MMC_DAT0",       0x0f5,  0,      0,      0,      1)
 168 MUX_CFG_24XX("H14_24XX_MMC_DAT1",       0x0f6,  0,      0,      0,      1)
 169 MUX_CFG_24XX("E19_24XX_MMC_DAT2",       0x0f7,  0,      0,      0,      1)
 170 MUX_CFG_24XX("D19_24XX_MMC_DAT3",       0x0f8,  0,      0,      0,      1)
 171 MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0",   0x0f9,  0,      0,      0,      1)
 172 MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1",   0x0fa,  0,      0,      0,      1)
 173 MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2",   0x0fb,  0,      0,      0,      1)
 174 MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3",   0x0fc,  0,      0,      0,      1)
 175 MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR",    0x0fd,  0,      0,      0,      1)
 176 MUX_CFG_24XX("H15_24XX_MMC_CLKI",       0x0fe,  0,      0,      0,      1)
 177
 178 /* Full speed USB */
 179 MUX_CFG_24XX("J20_24XX_USB0_PUEN",      0x11d,  0,      0,      0,      1)
 180 MUX_CFG_24XX("J19_24XX_USB0_VP",        0x11e,  0,      0,      0,      1)
 181 MUX_CFG_24XX("K20_24XX_USB0_VM",        0x11f,  0,      0,      0,      1)
 182 MUX_CFG_24XX("J18_24XX_USB0_RCV",       0x120,  0,      0,      0,      1)
 183 MUX_CFG_24XX("K19_24XX_USB0_TXEN",      0x121,  0,      0,      0,      1)
 184 MUX_CFG_24XX("J14_24XX_USB0_SE0",       0x122,  0,      0,      0,      1)
 185 MUX_CFG_24XX("K18_24XX_USB0_DAT",       0x123,  0,      0,      0,      1)
 186
 187 MUX_CFG_24XX("N14_24XX_USB1_SE0",       0x0ed,  2,      0,      0,      1)
 188 MUX_CFG_24XX("W12_24XX_USB1_SE0",       0x0dd,  3,      0,      0,      1)
 189 MUX_CFG_24XX("P15_24XX_USB1_DAT",       0x0ee,  2,      0,      0,      1)
 190 MUX_CFG_24XX("R13_24XX_USB1_DAT",       0x0e0,  3,      0,      0,      1)
 191 MUX_CFG_24XX("W20_24XX_USB1_TXEN",      0x0ec,  2,      0,      0,      1)
 192 MUX_CFG_24XX("P13_24XX_USB1_TXEN",      0x0df,  3,      0,      0,      1)
 193 MUX_CFG_24XX("V19_24XX_USB1_RCV",       0x0eb,  2,      0,      0,      1)
 194 MUX_CFG_24XX("V12_24XX_USB1_RCV",       0x0de,  3,      0,      0,      1)
 195
 196 MUX_CFG_24XX("AA10_24XX_USB2_SE0",      0x0e5,  2,      0,      0,      1)
 197 MUX_CFG_24XX("Y11_24XX_USB2_DAT",       0x0e8,  2,      0,      0,      1)
 198 MUX_CFG_24XX("AA12_24XX_USB2_TXEN",     0x0e9,  2,      0,      0,      1)
 199 MUX_CFG_24XX("AA6_24XX_USB2_RCV",       0x0e6,  2,      0,      0,      1)
 200 MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0",    0x0e7,  2,      0,      0,      1)
 201
 202 /* Keypad GPIO*/
 203 MUX_CFG_24XX("T19_24XX_KBR0",           0x106,  3,      1,      1,      1)
 204 MUX_CFG_24XX("R19_24XX_KBR1",           0x107,  3,      1,      1,      1)
 205 MUX_CFG_24XX("V18_24XX_KBR2",           0x139,  3,      1,      1,      1)
 206 MUX_CFG_24XX("M21_24XX_KBR3",           0xc9,   3,      1,      1,      1)
 207 MUX_CFG_24XX("E5__24XX_KBR4",           0x138,  3,      1,      1,      1)
 208 MUX_CFG_24XX("M18_24XX_KBR5",           0x10e,  3,      1,      1,      1)
 209 MUX_CFG_24XX("R20_24XX_KBC0",           0x108,  3,      0,      0,      1)
 210 MUX_CFG_24XX("M14_24XX_KBC1",           0x109,  3,      0,      0,      1)
 211 MUX_CFG_24XX("H19_24XX_KBC2",           0x114,  3,      0,      0,      1)
 212 MUX_CFG_24XX("V17_24XX_KBC3",           0x135,  3,      0,      0,      1)
 213 MUX_CFG_24XX("P21_24XX_KBC4",           0xca,   3,      0,      0,      1)
 214 MUX_CFG_24XX("L14_24XX_KBC5",           0x10f,  3,      0,      0,      1)
 215 MUX_CFG_24XX("N19_24XX_KBC6",           0x110,  3,      0,      0,      1)
 216
 217 /* 24xx Menelaus Keypad GPIO */
 218 MUX_CFG_24XX("B3__24XX_KBR5",           0x30,   3,      1,      1,      1)
 219 MUX_CFG_24XX("AA4_24XX_KBC2",           0xe7,   3,      0,      0,      1)
 220 MUX_CFG_24XX("B13_24XX_KBC6",           0x110,  3,      0,      0,      1)
 221
 222 /* 2430 USB */
 223 MUX_CFG_24XX("AD9_2430_USB0_PUEN",      0x133,  4,      0,      0,      1)
 224 MUX_CFG_24XX("Y11_2430_USB0_VP",        0x134,  4,      0,      0,      1)
 225 MUX_CFG_24XX("AD7_2430_USB0_VM",        0x135,  4,      0,      0,      1)
 226 MUX_CFG_24XX("AE7_2430_USB0_RCV",       0x136,  4,      0,      0,      1)
 227 MUX_CFG_24XX("AD4_2430_USB0_TXEN",      0x137,  4,      0,      0,      1)
 228 MUX_CFG_24XX("AF9_2430_USB0_SE0",       0x138,  4,      0,      0,      1)
 229 MUX_CFG_24XX("AE6_2430_USB0_DAT",       0x139,  4,      0,      0,      1)
 230 MUX_CFG_24XX("AD24_2430_USB1_SE0",      0x107,  2,      0,      0,      1)
 231 MUX_CFG_24XX("AB24_2430_USB1_RCV",      0x108,  2,      0,      0,      1)
 232 MUX_CFG_24XX("Y25_2430_USB1_TXEN",      0x109,  2,      0,      0,      1)
 233 MUX_CFG_24XX("AA26_2430_USB1_DAT",      0x10A,  2,      0,      0,      1)
 234
 235 /* 2430 HS-USB */
 236 MUX_CFG_24XX("AD9_2430_USB0HS_DATA3",   0x133,  0,      0,      0,      1)
 237 MUX_CFG_24XX("Y11_2430_USB0HS_DATA4",   0x134,  0,      0,      0,      1)
 238 MUX_CFG_24XX("AD7_2430_USB0HS_DATA5",   0x135,  0,      0,      0,      1)
 239 MUX_CFG_24XX("AE7_2430_USB0HS_DATA6",   0x136,  0,      0,      0,      1)
 240 MUX_CFG_24XX("AD4_2430_USB0HS_DATA2",   0x137,  0,      0,      0,      1)
 241 MUX_CFG_24XX("AF9_2430_USB0HS_DATA0",   0x138,  0,      0,      0,      1)
 242 MUX_CFG_24XX("AE6_2430_USB0HS_DATA1",   0x139,  0,      0,      0,      1)
 243 MUX_CFG_24XX("AE8_2430_USB0HS_CLK",     0x13A,  0,      0,      0,      1)
 244 MUX_CFG_24XX("AD8_2430_USB0HS_DIR",     0x13B,  0,      0,      0,      1)
 245 MUX_CFG_24XX("AE5_2430_USB0HS_STP",     0x13c,  0,      1,      1,      1)
 246 MUX_CFG_24XX("AE9_2430_USB0HS_NXT",     0x13D,  0,      0,      0,      1)
 247 MUX_CFG_24XX("AC7_2430_USB0HS_DATA7",   0x13E,  0,      0,      0,      1)
 248
 249 /* 2430 McBSP */
 250 MUX_CFG_24XX("AD6_2430_MCBSP_CLKS",     0x011E, 0,      0,      0,      1)
 251
 252 MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR",    0x011A, 0,      0,      0,      1)
 253 MUX_CFG_24XX("AD5_2430_MCBSP1_FSR",     0x011B, 0,      0,      0,      1)
 254 MUX_CFG_24XX("AA1_2430_MCBSP1_DX",      0x011C, 0,      0,      0,      1)
 255 MUX_CFG_24XX("AF3_2430_MCBSP1_DR",      0x011D, 0,      0,      0,      1)
 256 MUX_CFG_24XX("AB3_2430_MCBSP1_FSX",     0x011F, 0,      0,      0,      1)
 257 MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX",     0x0120, 0,      0,      0,      1)
 258
 259 MUX_CFG_24XX("AC10_2430_MCBSP2_FSX",    0x012E, 1,      0,      0,      1)
 260 MUX_CFG_24XX("AD16_2430_MCBSP2_CLX",    0x012F, 1,      0,      0,      1)
 261 MUX_CFG_24XX("AE13_2430_MCBSP2_DX",     0x0130, 1,      0,      0,      1)
 262 MUX_CFG_24XX("AD13_2430_MCBSP2_DR",     0x0131, 1,      0,      0,      1)
 263 MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0,      0,      0,      1)
 264 MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0,      0,      0,      1)
 265 MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0,      0,      0,      1)
 266 MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0,      0,      0,      1)
 267
 268 MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX",    0x0103, 0,      0,      0,      1)
 269 MUX_CFG_24XX("AE4_2430_MCBSP3_FSX",     0x0104, 0,      0,      0,      1)
 270 MUX_CFG_24XX("AE2_2430_MCBSP3_DR",      0x0105, 0,      0,      0,      1)
 271 MUX_CFG_24XX("AF4_2430_MCBSP3_DX",      0x0106, 0,      0,      0,      1)
 272
 273 MUX_CFG_24XX("N3_2430_MCBSP4_CLKX",     0x010B, 1,      0,      0,      1)
 274 MUX_CFG_24XX("AD23_2430_MCBSP4_DR",     0x010C, 1,      0,      0,      1)
 275 MUX_CFG_24XX("AB25_2430_MCBSP4_DX",     0x010D, 1,      0,      0,      1)
 276 MUX_CFG_24XX("AC25_2430_MCBSP4_FSX",    0x010E, 1,      0,      0,      1)
 277
 278 MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX",   0x00ED, 1,      0,      0,      1)
 279 MUX_CFG_24XX("AF12_2430_MCBSP5_FSX",    0x00ED, 1,      0,      0,      1)
 280 MUX_CFG_24XX("K7_2430_MCBSP5_DX",       0x00EF, 1,      0,      0,      1)
 281 MUX_CFG_24XX("M1_2430_MCBSP5_DR",       0x00F0, 1,      0,      0,      1)
 282
 283 /* 2430 MCSPI1 */
 284 MUX_CFG_24XX("Y18_2430_MCSPI1_CLK",     0x010F, 0,      0,      0,      1)
 285 MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO",   0x0110, 0,      0,      0,      1)
 286 MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI",   0x0111, 0,      0,      0,      1)
 287 MUX_CFG_24XX("U1_2430_MCSPI1_CS0",      0x0112, 0,      0,      0,      1)
 288
 289 /* Touchscreen GPIO */
 290 MUX_CFG_24XX("AF19_2430_GPIO_85",       0x0113, 3,      0,      0,      1)
 291
 292 };
 293
 294 #define OMAP24XX_PINS_SZ        ARRAY_SIZE(omap24xx_pins)
 295
 296 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
 297
 298 static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
 299 {
 300         u16 orig;
 301         u8 warn = 0, debug = 0;
 302
 303         orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
 304
 305 #ifdef  CONFIG_OMAP_MUX_DEBUG
 306         debug = cfg->debug;
 307 #endif
 308         warn = (orig != reg);
 309         if (debug || warn)
 310                 printk(KERN_WARNING
 311                         "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
 312                         cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
 313                         orig, reg);
 314 }
 315 #else
 316 #define omap2_cfg_debug(x, y)   do {} while (0)
 317 #endif
 318
 319 static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
 320 {
 321         static DEFINE_SPINLOCK(mux_spin_lock);
 322         unsigned long flags;
 323         u8 reg = 0;
 324
 325         spin_lock_irqsave(&mux_spin_lock, flags);
 326         reg |= cfg->mask & 0x7;
 327         if (cfg->pull_val)
 328                 reg |= OMAP2_PULL_ENA;
 329         if (cfg->pu_pd_val)
 330                 reg |= OMAP2_PULL_UP;
 331         omap2_cfg_debug(cfg, reg);
 332         omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
 333         spin_unlock_irqrestore(&mux_spin_lock, flags);
 334
 335         return 0;
 336 }
 337
 338 int __init omap2_mux_init(void)
 339 {
 340         u32 mux_pbase;
 341
 342         if (cpu_is_omap2420())
 343                 mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
 344         else if (cpu_is_omap2430())
 345                 mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
 346         else
 347                 return -ENODEV;
 348
 349         mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
 350         if (!mux_base) {
 351                 printk(KERN_ERR "mux: Could not ioremap\n");
 352                 return -ENODEV;
 353         }
 354
 355         if (cpu_is_omap24xx()) {
 356                 arch_mux_cfg.pins       = omap24xx_pins;
 357                 arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
 358                 arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
 359
 360                 return omap_mux_register(&arch_mux_cfg);
 361         }
 362
 363         return 0;
 364 }
 365
 366 #else
 367 int __init omap2_mux_init(void)
 368 {
 369         return 0;
 370 }
 371 #endif  /* CONFIG_OMAP_MUX */
 372
 373 /*----------------------------------------------------------------------------*/
 374
 375 #ifdef CONFIG_ARCH_OMAP2PLUS
 376 static LIST_HEAD(muxmodes);
 377 static DEFINE_MUTEX(muxmode_mutex);
 378
 379 #ifdef CONFIG_OMAP_MUX
 380
 381 static char *omap_mux_options;
 382
 383 int __init omap_mux_init_gpio(int gpio, int val)
 384 {
 385         struct omap_mux_entry *e;
 386         int found = 0;
 387
 388         if (!gpio)
 389                 return -EINVAL;
 390
 391         list_for_each_entry(e, &muxmodes, node) {
 392                 struct omap_mux *m = &e->mux;
 393                 if (gpio == m->gpio) {
 394                         u16 old_mode;
 395                         u16 mux_mode;
 396
 397                         old_mode = omap_mux_read(m->reg_offset);
 398                         mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
 399                         if (omap_mux_flags & MUXABLE_GPIO_MODE3)
 400                                 mux_mode |= OMAP_MUX_MODE3;
 401                         else
 402                                 mux_mode |= OMAP_MUX_MODE4;
 403                         printk(KERN_DEBUG "mux: Setting signal "
 404                                 "%s.gpio%i 0x%04x -> 0x%04x\n",
 405                                 m->muxnames[0], gpio, old_mode, mux_mode);
 406                         omap_mux_write(mux_mode, m->reg_offset);
 407                         found++;
 408                 }
 409         }
 410
 411         if (found == 1)
 412                 return 0;
 413
 414         if (found > 1) {
 415                 printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
 416                 return -EINVAL;
 417         }
 418
 419         printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
 420
 421         return -ENODEV;
 422 }
 423
 424 int __init omap_mux_init_signal(char *muxname, int val)
 425 {
 426         struct omap_mux_entry *e;
 427         char *m0_name = NULL, *mode_name = NULL;
 428         int found = 0;
 429
 430         mode_name = strchr(muxname, '.');
 431         if (mode_name) {
 432                 *mode_name = '\0';
 433                 mode_name++;
 434                 m0_name = muxname;
 435         } else {
 436                 mode_name = muxname;
 437         }
 438
 439         list_for_each_entry(e, &muxmodes, node) {
 440                 struct omap_mux *m = &e->mux;
 441                 char *m0_entry = m->muxnames[0];
 442                 int i;
 443
 444                 if (m0_name && strcmp(m0_name, m0_entry))
 445                         continue;
 446
 447                 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
 448                         char *mode_cur = m->muxnames[i];
 449
 450                         if (!mode_cur)
 451                                 continue;
 452
 453                         if (!strcmp(mode_name, mode_cur)) {
 454                                 u16 old_mode;
 455                                 u16 mux_mode;
 456
 457                                 old_mode = omap_mux_read(m->reg_offset);
 458                                 mux_mode = val | i;
 459                                 printk(KERN_DEBUG "mux: Setting signal "
 460                                         "%s.%s 0x%04x -> 0x%04x\n",
 461                                         m0_entry, muxname, old_mode, mux_mode);
 462                                 omap_mux_write(mux_mode, m->reg_offset);
 463                                 found++;
 464                         }
 465                 }
 466         }
 467
 468         if (found == 1)
 469                 return 0;
 470
 471         if (found > 1) {
 472                 printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
 473                                 found, muxname);
 474                 return -EINVAL;
 475         }
 476
 477         printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
 478
 479         return -ENODEV;
 480 }
 481
 482 #ifdef CONFIG_DEBUG_FS
 483
 484 #define OMAP_MUX_MAX_NR_FLAGS   10
 485 #define OMAP_MUX_TEST_FLAG(val, mask)                           \
 486         if (((val) & (mask)) == (mask)) {                       \
 487                 i++;                                            \
 488                 flags[i] =  #mask;                              \
 489         }
 490
 491 /* REVISIT: Add checking for non-optimal mux settings */
 492 static inline void omap_mux_decode(struct seq_file *s, u16 val)
 493 {
 494         char *flags[OMAP_MUX_MAX_NR_FLAGS];
 495         char mode[sizeof("OMAP_MUX_MODE") + 1];
 496         int i = -1;
 497
 498         sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
 499         i++;
 500         flags[i] = mode;
 501
 502         OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
 503         if (val & OMAP_OFF_EN) {
 504                 if (!(val & OMAP_OFFOUT_EN)) {
 505                         if (!(val & OMAP_OFF_PULL_UP)) {
 506                                 OMAP_MUX_TEST_FLAG(val,
 507                                         OMAP_PIN_OFF_INPUT_PULLDOWN);
 508                         } else {
 509                                 OMAP_MUX_TEST_FLAG(val,
 510                                         OMAP_PIN_OFF_INPUT_PULLUP);
 511                         }
 512                 } else {
 513                         if (!(val & OMAP_OFFOUT_VAL)) {
 514                                 OMAP_MUX_TEST_FLAG(val,
 515                                         OMAP_PIN_OFF_OUTPUT_LOW);
 516                         } else {
 517                                 OMAP_MUX_TEST_FLAG(val,
 518                                         OMAP_PIN_OFF_OUTPUT_HIGH);
 519                         }
 520                 }
 521         }
 522
 523         if (val & OMAP_INPUT_EN) {
 524                 if (val & OMAP_PULL_ENA) {
 525                         if (!(val & OMAP_PULL_UP)) {
 526                                 OMAP_MUX_TEST_FLAG(val,
 527                                         OMAP_PIN_INPUT_PULLDOWN);
 528                         } else {
 529                                 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
 530                         }
 531                 } else {
 532                         OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
 533                 }
 534         } else {
 535                 i++;
 536                 flags[i] = "OMAP_PIN_OUTPUT";
 537         }
 538
 539         do {
 540                 seq_printf(s, "%s", flags[i]);
 541                 if (i > 0)
 542                         seq_printf(s, " | ");
 543         } while (i-- > 0);
 544 }
 545
 546 #define OMAP_MUX_DEFNAME_LEN    16
 547
 548 static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
 549 {
 550         struct omap_mux_entry *e;
 551
 552         list_for_each_entry(e, &muxmodes, node) {
 553                 struct omap_mux *m = &e->mux;
 554                 char m0_def[OMAP_MUX_DEFNAME_LEN];
 555                 char *m0_name = m->muxnames[0];
 556                 u16 val;
 557                 int i, mode;
 558
 559                 if (!m0_name)
 560                         continue;
 561
 562                 /* REVISIT: Needs to be updated if mode0 names get longer */
 563                 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
 564                         if (m0_name[i] == '\0') {
 565                                 m0_def[i] = m0_name[i];
 566                                 break;
 567                         }
 568                         m0_def[i] = toupper(m0_name[i]);
 569                 }
 570                 val = omap_mux_read(m->reg_offset);
 571                 mode = val & OMAP_MUX_MODE7;
 572
 573                 seq_printf(s, "OMAP%i_MUX(%s, ",
 574                                         cpu_is_omap34xx() ? 3 : 0, m0_def);
 575                 omap_mux_decode(s, val);
 576                 seq_printf(s, "),\n");
 577         }
 578
 579         return 0;
 580 }
 581
 582 static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
 583 {
 584         return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
 585 }
 586
 587 static const struct file_operations omap_mux_dbg_board_fops = {
 588         .open           = omap_mux_dbg_board_open,
 589         .read           = seq_read,
 590         .llseek         = seq_lseek,
 591         .release        = single_release,
 592 };
 593
 594 static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
 595 {
 596         struct omap_mux *m = s->private;
 597         const char *none = "NA";
 598         u16 val;
 599         int mode;
 600
 601         val = omap_mux_read(m->reg_offset);
 602         mode = val & OMAP_MUX_MODE7;
 603
 604         seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
 605                         m->muxnames[0], m->muxnames[mode],
 606                         mux_phys + m->reg_offset, m->reg_offset, val,
 607                         m->balls[0] ? m->balls[0] : none,
 608                         m->balls[1] ? m->balls[1] : none);
 609         seq_printf(s, "mode: ");
 610         omap_mux_decode(s, val);
 611         seq_printf(s, "\n");
 612         seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
 613                         m->muxnames[0] ? m->muxnames[0] : none,
 614                         m->muxnames[1] ? m->muxnames[1] : none,
 615                         m->muxnames[2] ? m->muxnames[2] : none,
 616                         m->muxnames[3] ? m->muxnames[3] : none,
 617                         m->muxnames[4] ? m->muxnames[4] : none,
 618                         m->muxnames[5] ? m->muxnames[5] : none,
 619                         m->muxnames[6] ? m->muxnames[6] : none,
 620                         m->muxnames[7] ? m->muxnames[7] : none);
 621
 622         return 0;
 623 }
 624
 625 #define OMAP_MUX_MAX_ARG_CHAR  7
 626
 627 static ssize_t omap_mux_dbg_signal_write(struct file *file,
 628                                                 const char __user *user_buf,
 629                                                 size_t count, loff_t *ppos)
 630 {
 631         char buf[OMAP_MUX_MAX_ARG_CHAR];
 632         struct seq_file *seqf;
 633         struct omap_mux *m;
 634         unsigned long val;
 635         int buf_size, ret;
 636
 637         if (count > OMAP_MUX_MAX_ARG_CHAR)
 638                 return -EINVAL;
 639
 640         memset(buf, 0, sizeof(buf));
 641         buf_size = min(count, sizeof(buf) - 1);
 642
 643         if (copy_from_user(buf, user_buf, buf_size))
 644                 return -EFAULT;
 645
 646         ret = strict_strtoul(buf, 0x10, &val);
 647         if (ret < 0)
 648                 return ret;
 649
 650         if (val > 0xffff)
 651                 return -EINVAL;
 652
 653         seqf = file->private_data;
 654         m = seqf->private;
 655
 656         omap_mux_write((u16)val, m->reg_offset);
 657         *ppos += count;
 658
 659         return count;
 660 }
 661
 662 static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
 663 {
 664         return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
 665 }
 666
 667 static const struct file_operations omap_mux_dbg_signal_fops = {
 668         .open           = omap_mux_dbg_signal_open,
 669         .read           = seq_read,
 670         .write          = omap_mux_dbg_signal_write,
 671         .llseek         = seq_lseek,
 672         .release        = single_release,
 673 };
 674
 675 static struct dentry *mux_dbg_dir;
 676
 677 static void __init omap_mux_dbg_init(void)
 678 {
 679         struct omap_mux_entry *e;
 680
 681         mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
 682         if (!mux_dbg_dir)
 683                 return;
 684
 685         (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
 686                                         NULL, &omap_mux_dbg_board_fops);
 687
 688         list_for_each_entry(e, &muxmodes, node) {
 689                 struct omap_mux *m = &e->mux;
 690
 691                 (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
 692                                         m, &omap_mux_dbg_signal_fops);
 693         }
 694 }
 695
 696 #else
 697 static inline void omap_mux_dbg_init(void)
 698 {
 699 }
 700 #endif  /* CONFIG_DEBUG_FS */
 701
 702 static void __init omap_mux_free_names(struct omap_mux *m)
 703 {
 704         int i;
 705
 706         for (i = 0; i < OMAP_MUX_NR_MODES; i++)
 707                 kfree(m->muxnames[i]);
 708
 709 #ifdef CONFIG_DEBUG_FS
 710         for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
 711                 kfree(m->balls[i]);
 712 #endif
 713
 714 }
 715
 716 /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
 717 static int __init omap_mux_late_init(void)
 718 {
 719         struct omap_mux_entry *e, *tmp;
 720
 721         list_for_each_entry_safe(e, tmp, &muxmodes, node) {
 722                 struct omap_mux *m = &e->mux;
 723                 u16 mode = omap_mux_read(m->reg_offset);
 724
 725                 if (OMAP_MODE_GPIO(mode))
 726                         continue;
 727
 728 #ifndef CONFIG_DEBUG_FS
 729                 mutex_lock(&muxmode_mutex);
 730                 list_del(&e->node);
 731                 mutex_unlock(&muxmode_mutex);
 732                 omap_mux_free_names(m);
 733                 kfree(m);
 734 #endif
 735
 736         }
 737
 738         omap_mux_dbg_init();
 739
 740         return 0;
 741 }
 742 late_initcall(omap_mux_late_init);
 743
 744 static void __init omap_mux_package_fixup(struct omap_mux *p,
 745                                         struct omap_mux *superset)
 746 {
 747         while (p->reg_offset !=  OMAP_MUX_TERMINATOR) {
 748                 struct omap_mux *s = superset;
 749                 int found = 0;
 750
 751                 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
 752                         if (s->reg_offset == p->reg_offset) {
 753                                 *s = *p;
 754                                 found++;
 755                                 break;
 756                         }
 757                         s++;
 758                 }
 759                 if (!found)
 760                         printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
 761                                         p->reg_offset);
 762                 p++;
 763         }
 764 }
 765
 766 #ifdef CONFIG_DEBUG_FS
 767
 768 static void __init omap_mux_package_init_balls(struct omap_ball *b,
 769                                 struct omap_mux *superset)
 770 {
 771         while (b->reg_offset != OMAP_MUX_TERMINATOR) {
 772                 struct omap_mux *s = superset;
 773                 int found = 0;
 774
 775                 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
 776                         if (s->reg_offset == b->reg_offset) {
 777                                 s->balls[0] = b->balls[0];
 778                                 s->balls[1] = b->balls[1];
 779                                 found++;
 780                                 break;
 781                         }
 782                         s++;
 783                 }
 784                 if (!found)
 785                         printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
 786                                         b->reg_offset);
 787                 b++;
 788         }
 789 }
 790
 791 #else   /* CONFIG_DEBUG_FS */
 792
 793 static inline void omap_mux_package_init_balls(struct omap_ball *b,
 794                                         struct omap_mux *superset)
 795 {
 796 }
 797
 798 #endif  /* CONFIG_DEBUG_FS */
 799
 800 static int __init omap_mux_setup(char *options)
 801 {
 802         if (!options)
 803                 return 0;
 804
 805         omap_mux_options = options;
 806
 807         return 1;
 808 }
 809 __setup("omap_mux=", omap_mux_setup);
 810
 811 /*
 812  * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
 813  * cmdline options only override the bootloader values.
 814  * During development, please enable CONFIG_DEBUG_FS, and use the
 815  * signal specific entries under debugfs.
 816  */
 817 static void __init omap_mux_set_cmdline_signals(void)
 818 {
 819         char *options, *next_opt, *token;
 820
 821         if (!omap_mux_options)
 822                 return;
 823
 824         options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
 825         if (!options)
 826                 return;
 827
 828         strcpy(options, omap_mux_options);
 829         next_opt = options;
 830
 831         while ((token = strsep(&next_opt, ",")) != NULL) {
 832                 char *keyval, *name;
 833                 unsigned long val;
 834
 835                 keyval = token;
 836                 name = strsep(&keyval, "=");
 837                 if (name) {
 838                         int res;
 839
 840                         res = strict_strtoul(keyval, 0x10, &val);
 841                         if (res < 0)
 842                                 continue;
 843
 844                         omap_mux_init_signal(name, (u16)val);
 845                 }
 846         }
 847
 848         kfree(options);
 849 }
 850
 851 static int __init omap_mux_copy_names(struct omap_mux *src,
 852                                         struct omap_mux *dst)
 853 {
 854         int i;
 855
 856         for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
 857                 if (src->muxnames[i]) {
 858                         dst->muxnames[i] =
 859                                 kmalloc(strlen(src->muxnames[i]) + 1,
 860                                         GFP_KERNEL);
 861                         if (!dst->muxnames[i])
 862                                 goto free;
 863                         strcpy(dst->muxnames[i], src->muxnames[i]);
 864                 }
 865         }
 866
 867 #ifdef CONFIG_DEBUG_FS
 868         for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
 869                 if (src->balls[i]) {
 870                         dst->balls[i] =
 871                                 kmalloc(strlen(src->balls[i]) + 1,
 872                                         GFP_KERNEL);
 873                         if (!dst->balls[i])
 874                                 goto free;
 875                         strcpy(dst->balls[i], src->balls[i]);
 876                 }
 877         }
 878 #endif
 879
 880         return 0;
 881
 882 free:
 883         omap_mux_free_names(dst);
 884         return -ENOMEM;
 885
 886 }
 887
 888 #endif  /* CONFIG_OMAP_MUX */
 889
 890 static u16 omap_mux_get_by_gpio(int gpio)
 891 {
 892         struct omap_mux_entry *e;
 893         u16 offset = OMAP_MUX_TERMINATOR;
 894
 895         list_for_each_entry(e, &muxmodes, node) {
 896                 struct omap_mux *m = &e->mux;
 897                 if (m->gpio == gpio) {
 898                         offset = m->reg_offset;
 899                         break;
 900                 }
 901         }
 902
 903         return offset;
 904 }
 905
 906 /* Needed for dynamic muxing of GPIO pins for off-idle */
 907 u16 omap_mux_get_gpio(int gpio)
 908 {
 909         u16 offset;
 910
 911         offset = omap_mux_get_by_gpio(gpio);
 912         if (offset == OMAP_MUX_TERMINATOR) {
 913                 printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
 914                 return offset;
 915         }
 916
 917         return omap_mux_read(offset);
 918 }
 919
 920 /* Needed for dynamic muxing of GPIO pins for off-idle */
 921 void omap_mux_set_gpio(u16 val, int gpio)
 922 {
 923         u16 offset;
 924
 925         offset = omap_mux_get_by_gpio(gpio);
 926         if (offset == OMAP_MUX_TERMINATOR) {
 927                 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
 928                 return;
 929         }
 930
 931         omap_mux_write(val, offset);
 932 }
 933
 934 static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
 935 {
 936         struct omap_mux_entry *entry;
 937         struct omap_mux *m;
 938
 939         entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
 940         if (!entry)
 941                 return NULL;
 942
 943         m = &entry->mux;
 944         memcpy(m, src, sizeof(struct omap_mux_entry));
 945
 946 #ifdef CONFIG_OMAP_MUX
 947         if (omap_mux_copy_names(src, m)) {
 948                 kfree(entry);
 949                 return NULL;
 950         }
 951 #endif
 952
 953         mutex_lock(&muxmode_mutex);
 954         list_add_tail(&entry->node, &muxmodes);
 955         mutex_unlock(&muxmode_mutex);
 956
 957         return m;
 958 }
 959
 960 /*
 961  * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
 962  * the GPIO to mux offset mapping that is needed for dynamic muxing
 963  * of GPIO pins for off-idle.
 964  */
 965 static void __init omap_mux_init_list(struct omap_mux *superset)
 966 {
 967         while (superset->reg_offset !=  OMAP_MUX_TERMINATOR) {
 968                 struct omap_mux *entry;
 969
 970 #ifdef CONFIG_OMAP_MUX
 971                 if (!superset->muxnames || !superset->muxnames[0]) {
 972                         superset++;
 973                         continue;
 974                 }
 975 #else
 976                 /* Skip pins that are not muxed as GPIO by bootloader */
 977                 if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
 978                         superset++;
 979                         continue;
 980                 }
 981 #endif
 982
 983                 entry = omap_mux_list_add(superset);
 984                 if (!entry) {
 985                         printk(KERN_ERR "mux: Could not add entry\n");
 986                         return;
 987                 }
 988                 superset++;
 989         }
 990 }
 991
 992 #ifdef CONFIG_OMAP_MUX
 993
 994 static void omap_mux_init_package(struct omap_mux *superset,
 995                                   struct omap_mux *package_subset,
 996                                   struct omap_ball *package_balls)
 997 {
 998         if (package_subset)
 999                 omap_mux_package_fixup(package_subset, superset);
1000         if (package_balls)
1001                 omap_mux_package_init_balls(package_balls, superset);
1002 }
1003
1004 static void omap_mux_init_signals(struct omap_board_mux *board_mux)
1005 {
1006         omap_mux_set_cmdline_signals();
1007         omap_mux_write_array(board_mux);
1008 }
1009
1010 #else
1011
1012 static void omap_mux_init_package(struct omap_mux *superset,
1013                                   struct omap_mux *package_subset,
1014                                   struct omap_ball *package_balls)
1015 {
1016 }
1017
1018 static void omap_mux_init_signals(struct omap_board_mux *board_mux)
1019 {
1020 }
1021
1022 #endif
1023
1024 int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
1025                                 struct omap_mux *superset,
1026                                 struct omap_mux *package_subset,
1027                                 struct omap_board_mux *board_mux,
1028                                 struct omap_ball *package_balls)
1029 {
1030         if (mux_base)
1031                 return -EBUSY;
1032
1033         mux_phys = mux_pbase;
1034         mux_base = ioremap(mux_pbase, mux_size);
1035         if (!mux_base) {
1036                 printk(KERN_ERR "mux: Could not ioremap\n");
1037                 return -ENODEV;
1038         }
1039
1040         if (cpu_is_omap24xx())
1041                 omap_mux_flags = MUXABLE_GPIO_MODE3;
1042
1043         omap_mux_init_package(superset, package_subset, package_balls);
1044         omap_mux_init_list(superset);
1045         omap_mux_init_signals(board_mux);
1046
1047         return 0;
1048 }
1049
1050 #endif  /* CONFIG_ARCH_OMAP3 */
1051