arch/arm/mach-omap2/mux33xx.c

   1 /*
   2  * AM33XX mux data
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
   7  *
   8  * Copyright (C) 2009 Nokia
   9  * Copyright (C) 2009 Texas Instruments
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/debugfs.h>
  20 #include <linux/slab.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/gpio.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/suspend.h>
  26
  27 #include "cm33xx.h"
  28 #include "control.h"
  29 #include "mux.h"
  30
  31 #define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)         \
  32 {                                                                       \
  33         .reg_offset     = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET),       \
  34         .gpio           = (g),                                          \
  35         .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
  36 }
  37
  38 /* AM33XX pin mux super set */
  39 static struct omap_mux am33xx_muxmodes[] = {
  40         _AM33XX_MUXENTRY(GPMC_AD0, 0,
  41                 "gpmc_ad0", "mmc1_dat0", NULL, NULL,
  42                 NULL, NULL, NULL, "gpio1_0"),
  43         _AM33XX_MUXENTRY(GPMC_AD1, 0,
  44                 "gpmc_ad1", "mmc1_dat1", NULL, NULL,
  45                 NULL, NULL, NULL, "gpio1_1"),
  46         _AM33XX_MUXENTRY(GPMC_AD2, 0,
  47                 "gpmc_ad2", "mmc1_dat2", NULL, NULL,
  48                 NULL, NULL, NULL, "gpio1_2"),
  49         _AM33XX_MUXENTRY(GPMC_AD3, 0,
  50                 "gpmc_ad3", "mmc1_dat3", NULL, NULL,
  51                 NULL, NULL, NULL, "gpio1_3"),
  52         _AM33XX_MUXENTRY(GPMC_AD4, 0,
  53                 "gpmc_ad4", "mmc1_dat4", NULL, NULL,
  54                 NULL, NULL, NULL, "gpio1_4"),
  55         _AM33XX_MUXENTRY(GPMC_AD5, 0,
  56                 "gpmc_ad5", "mmc1_dat5", NULL, NULL,
  57                 NULL, NULL, NULL, "gpio1_5"),
  58         _AM33XX_MUXENTRY(GPMC_AD6, 0,
  59                 "gpmc_ad6", "mmc1_dat6", NULL, NULL,
  60                 NULL, NULL, NULL, "gpio1_6"),
  61         _AM33XX_MUXENTRY(GPMC_AD7, 0,
  62                 "gpmc_ad7", "mmc1_dat7", NULL, NULL,
  63                 NULL, NULL, NULL, "gpio1_7"),
  64         _AM33XX_MUXENTRY(GPMC_AD8, 0,
  65                 "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
  66                 "ehrpwm2a", "pr1_mii_mt0_clk", NULL, "gpio0_22"),
  67         _AM33XX_MUXENTRY(GPMC_AD9, 0,
  68                 "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
  69                 "ehrpwm2b", "pr1_mii0_col", NULL, "gpio0_23"),
  70         _AM33XX_MUXENTRY(GPMC_AD10, 0,
  71                 "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
  72                 "ehrpwm2_tripzone_input", "pr1_mii0_txen", NULL, "gpio0_26"),
  73         _AM33XX_MUXENTRY(GPMC_AD11, 0,
  74                 "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
  75                 "ehrpwm0_synco", "pr1_mii0_txd3", NULL, "gpio0_27"),
  76         _AM33XX_MUXENTRY(GPMC_AD12, 0,
  77                 "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
  78                 "eqep2a_in", "pr1_mii0_txd2", "pr1_pru0_pru_r30_14", "gpio1_12"),
  79         _AM33XX_MUXENTRY(GPMC_AD13, 0,
  80                 "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
  81                 "eqep2b_in", "pr1_mii0_txd1", "pr1_pru0_pru_r30_15", "gpio1_13"),
  82         _AM33XX_MUXENTRY(GPMC_AD14, 0,
  83                 "gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
  84                 "eqep2_index", "pr1_mii0_txd0", "pr1_pru0_pru_r31_14", "gpio1_14"),
  85         _AM33XX_MUXENTRY(GPMC_AD15, 0,
  86                 "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
  87                 "eqep2_strobe", "pr1_ecap0_ecap_capin_apwm_o", "pr1_pru0_pru_r31_15", "gpio1_15"),
  88         _AM33XX_MUXENTRY(GPMC_A0, 0,
  89                 "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
  90                 "gpmc_a16","pr1_mii_mt1_clk", "ehrpwm1_tripzone_input", "gpio1_16"),
  91         _AM33XX_MUXENTRY(GPMC_A1, 0,
  92                 "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
  93                 "gpmc_a17", "pr1_mii1_txd3", "ehrpwm0_synco", "gpio1_17"),
  94         _AM33XX_MUXENTRY(GPMC_A2, 0,
  95                 "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
  96                 "gpmc_a18", "pr1_mii1_txd2", "ehrpwm1a", "gpio1_18"),
  97         _AM33XX_MUXENTRY(GPMC_A3, 0,
  98                 "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
  99                 "gpmc_a19", "pr1_mii1_txd1", "ehrpwm1b", "gpio1_19"),
 100         _AM33XX_MUXENTRY(GPMC_A4, 0,
 101                 "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
 102                 "gpmc_a20", "pr1_mii1_txd0", "eqep1a_in", "gpio1_20"),
 103         _AM33XX_MUXENTRY(GPMC_A5, 0,
 104                 "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
 105                 "gpmc_a21", "pr1_mii1_rxd3", "eqep1b_in", "gpio1_21"),
 106         _AM33XX_MUXENTRY(GPMC_A6, 0,
 107                 "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
 108                 "gpmc_a22", "pr1_mii1_rxd2", "eqep1_index", "gpio1_22"),
 109         _AM33XX_MUXENTRY(GPMC_A7, 0,
 110                 "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
 111                 "gpmc_a23", "pr1_mii1_rxd1", "eqep1_strobe", "gpio1_23"),
 112         _AM33XX_MUXENTRY(GPMC_A8, 0,
 113                 "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
 114                 "gpmc_a24", "pr1_mii1_rxd0", "mcasp0_aclkx", "gpio1_24"),
 115         _AM33XX_MUXENTRY(GPMC_A9, 0,
 116                 "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
 117                 "gpmc_a25", "pr1_mii_mr1_clk", "mcasp0_fsx", "gpio1_25"),
 118         _AM33XX_MUXENTRY(GPMC_A10, 0,
 119                 "gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
 120                 "gpmc_a26", "pr1_mii1_rxdv", "mcasp0_axr0", "gpio1_26"),
 121         _AM33XX_MUXENTRY(GPMC_A11, 0,
 122                 "gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
 123                 "gpmc_a27", "pr1_mii1_rxer", "mcasp0_axr1", "gpio1_27"),
 124         _AM33XX_MUXENTRY(GPMC_WAIT0, 0,
 125                 "gpmc_wait0", "mii2_crs", "gpmc_csn4", "rmii2_crs_dv",
 126                 "mmc1_sdcd", "pr1_mii1_col", "uart4_rxd", "gpio0_30"),
 127         _AM33XX_MUXENTRY(GPMC_WPN, 0,
 128                 "gpmc_wpn", "mii2_rxerr", "gpmc_csn5", "rmii2_rxerr",
 129                 "mmc2_sdcd", "pr1_mii1_txen", "uart4_txd", "gpio0_31"),
 130         _AM33XX_MUXENTRY(GPMC_BEN1, 0,
 131                 "gpmc_ben1", "mii2_col", "gpmc_csn6", "mmc2_dat3",
 132                 "gpmc_dir", "pr1_mii1_rxlink", "mcasp0_aclkr", "gpio1_28"),
 133         _AM33XX_MUXENTRY(GPMC_CSN0, 0,
 134                 "gpmc_csn0", NULL, NULL, NULL,
 135                 NULL, NULL, NULL, "gpio1_29"),
 136         _AM33XX_MUXENTRY(GPMC_CSN1, 0,
 137                 "gpmc_csn1", "gpmc_clk", "mmc1_clk", "pr1_edio_data_in6",
 138                 "pr1_edio_data_out6", "pr1_pru1_pru_r30_12", "pr1_pru1_pru_r31_12", "gpio1_30"),
 139         _AM33XX_MUXENTRY(GPMC_CSN2, 0,
 140                 "gpmc_csn2", "gpmc_be1n", "mmc1_cmd", "pr1_edio_data_in7",
 141                 "pr1_edio_data_out7", "pr1_pru1_pru_r30_13", "pr1_pru1_pru_r31_13", "gpio1_31"),
 142         _AM33XX_MUXENTRY(GPMC_CSN3, 0,
 143                 "gpmc_csn3", NULL, NULL, "mmc2_cmd",
 144                 "pr1_mii0_crs", "pr1_mdio_data", "emu4", "gpio2_0"),
 145         _AM33XX_MUXENTRY(GPMC_CLK, 0,
 146                 "gpmc_clk", "lcd_memory_clk_mux", "gpmc_wait1", "mmc2_clk",
 147                 "pr1_mii1_crs", "pr1_mdio_mdclk", "mcasp0_fsr", "gpio2_1"),
 148         _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
 149                 "gpmc_advn_ale", NULL, "timer4", NULL,
 150                 NULL, NULL, NULL, "gpio2_2"),
 151         _AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
 152                 "gpmc_oen_ren", NULL, "timer7", NULL,
 153                 NULL, NULL, NULL, "gpio2_3"),
 154         _AM33XX_MUXENTRY(GPMC_WEN, 0,
 155                 "gpmc_wen", NULL, "timer6", NULL,
 156                 NULL, NULL, NULL, "gpio2_4"),
 157         _AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
 158                 "gpmc_ben0_cle", NULL, "timer5", NULL,
 159                 NULL, NULL, NULL, "gpio2_5"),
 160         _AM33XX_MUXENTRY(LCD_DATA0, 0,
 161                 "lcd_data0", "gpmc_a0", "pr1_mii_mt0_clk2", "ehrpwm2a",
 162                 NULL, "pr1_pru1_pru_r30_02", "pr1_pru1_pru_r31_0", "gpio2_6"),
 163         _AM33XX_MUXENTRY(LCD_DATA1, 0,
 164                 "lcd_data1", "gpmc_a1", "pr1_mii0_txen", "ehrpwm2b",
 165                 NULL, "pr1_pru1_pru_r30_1", "pr1_pru1_pru_r31_1", "gpio2_7"),
 166         _AM33XX_MUXENTRY(LCD_DATA2, 0,
 167                 "lcd_data2", "gpmc_a2", "pr1_mii0_txd3", "ehrpwm2_tripzone_input",
 168                 NULL, "pr1_mii0_txd3", "ehrpwm2_tripzone_input", "gpio2_8"),
 169         _AM33XX_MUXENTRY(LCD_DATA3, 0,
 170                 "lcd_data3", "gpmc_a3", "pr1_mii0_txd2", "ehrpwm0_synco",
 171                 NULL, "pr1_pru1_pru_r30_3", "pr1_pru1_pru_r31_3", "gpio2_9"),
 172         _AM33XX_MUXENTRY(LCD_DATA4, 0,
 173                 "lcd_data4", "gpmc_a4", "pr1_mii0_txd1", "eqep2a_in",
 174                 NULL, "pr1_pru1_pru_r30_4", "pr1_pru1_pru_r31_4", "gpio2_10"),
 175         _AM33XX_MUXENTRY(LCD_DATA5, 0,
 176                 "lcd_data5", "gpmc_a5", "pr1_mii0_txd0", "eqep2b_in",
 177                 NULL, "pr1_pru1_pru_r30_5", "pr1_pru1_pru_r31_5", "gpio2_11"),
 178         _AM33XX_MUXENTRY(LCD_DATA6, 0,
 179                 "lcd_data6", "gpmc_a6", "pr1_edio_data_in6", "eqep2_index",
 180                 "pr1_edio_data_out6", "pr1_pru1_pru_r30_6", "pr1_pru1_pru_r31_6", "gpio2_12"),
 181         _AM33XX_MUXENTRY(LCD_DATA7, 0,
 182                 "lcd_data7", "gpmc_a7", "pr1_edio_data_in7", "eqep2_strobe",
 183                 "pr1_edio_data_out7", "pr1_pru1_pru_r30_7", "pr1_pru1_pru_r31_7", "gpio2_13"),
 184         _AM33XX_MUXENTRY(LCD_DATA8, 0,
 185                 "lcd_data8", "gpmc_a12", "ehrpwm1_tripzone_input", "mcasp0_aclkx",
 186                 "uart5_txd", "pr1_mii0_rxd3", "uart2_ctsn", "gpio2_14"),
 187         _AM33XX_MUXENTRY(LCD_DATA9, 0,
 188                 "lcd_data9", "gpmc_a13", "ehrpwm0_synco", "mcasp0_fsx",
 189                 "uart5_rxd", "pr1_mii0_rxd2", "uart2_rtsn", "gpio2_15"),
 190         _AM33XX_MUXENTRY(LCD_DATA10, 0,
 191                 "lcd_data10", "gpmc_a14", "ehrpwm1a", "mcasp0_axr0",
 192                 NULL, "pr1_mii0_rxd1,uart3_ctsn", "gpio2_16"),
 193         _AM33XX_MUXENTRY(LCD_DATA11, 0,
 194                 "lcd_data11", "gpmc_a15", "ehrpwm1b", "mcasp0_ahclkr",
 195                 "mcasp0_axr2", "pr1_mii0_rxd0", "uart3_rtsn", "gpio2_17"),
 196         _AM33XX_MUXENTRY(LCD_DATA12, 0,
 197                 "lcd_data12", "gpmc_a16", "eqep1a_in", "mcasp0_aclkr",
 198                 "mcasp0_axr2", "pr1_mii0_rxlink", "uart4_ctsn", "gpio0_8"),
 199         _AM33XX_MUXENTRY(LCD_DATA13, 0,
 200                 "lcd_data13", "gpmc_a17", "eqep1b_in", "mcasp0_fsr",
 201                 "mcasp0_axr3", "pr1_mii0_rxer", "uart4_rtsn", "gpio0_9"),
 202         _AM33XX_MUXENTRY(LCD_DATA14, 0,
 203                 "lcd_data14", "gpmc_a18", "eqep1_index", "mcasp0_axr1",
 204                 "uart5_rxd", "pr1_mii_mr0_clk", "uart5_ctsn", "gpio0_10"),
 205         _AM33XX_MUXENTRY(LCD_DATA15, 0,
 206                 "lcd_data15", "gpmc_a19", "eqep1_strobe", "mcasp0_ahclkx",
 207                 "mcasp0_axr3", "pr1_mii0_rxdv", "uart5_rtsn", "gpio0_11"),
 208         _AM33XX_MUXENTRY(LCD_VSYNC, 0,
 209                 "lcd_vsync", "gpmc_a8", NULL, "pr1_edio_data_in2",
 210                 "pr1_edio_data_out2", "pr1_pru1_pru_r30_8", "pr1_pru1_pru_r31_8", "gpio2_22"),
 211         _AM33XX_MUXENTRY(LCD_HSYNC, 0,
 212                 "lcd_hsync", "gpmc_a9", NULL, "pr1_edio_data_in3",
 213                 "pr1_edio_data_out3", "pr1_pru1_pru_r30_9", "pr1_pru1_pru_r31_9", "gpio2_23"),
 214         _AM33XX_MUXENTRY(LCD_PCLK, 0,
 215                 "lcd_pclk", "gpmc_a10", "pr1_mii0_crs", "pr1_edio_data_in4",
 216                 "pr1_edio_data_out4", "pr1_pru1_pru_r30_10", "pr1_pru1_pru_r31_10", "gpio2_24"),
 217         _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
 218                 "lcd_ac_bias_en", "gpmc_a11", "pr1_mii1_crs", "pr1_edio_data_in5",
 219                 "pr1_edio_data_out5", "pr1_pru1_pru_r30_11", "pr1_pru1_pru_r31_11", "gpio2_25"),
 220         _AM33XX_MUXENTRY(MMC0_DAT3, 0,
 221                 "mmc0_dat3", "gpmc_a20", "uart4_ctsn", "timer5",
 222                 "uart1_dcdn", "pr1_pru0_pru_r30_8", "pr1_pru0_pru_r31_8", "gpio2_26"),
 223         _AM33XX_MUXENTRY(MMC0_DAT2, 0,
 224                 "mmc0_dat2", "gpmc_a21", "uart4_rtsn", "timer6",
 225                 "uart1_dsrn", "pr1_pru0_pru_r30_9", "pr1_pru0_pru_r31_9", "gpio2_27"),
 226         _AM33XX_MUXENTRY(MMC0_DAT1, 0,
 227                 "mmc0_dat1", "gpmc_a22", "uart5_ctsn", "uart3_rxd",
 228                 "uart1_dtrn", "pr1_pru0_pru_r30_10", "pr1_pru0_pru_r31_10", "gpio2_28"),
 229         _AM33XX_MUXENTRY(MMC0_DAT0, 0,
 230                 "mmc0_dat0", "gpmc_a23", "uart5_rtsn", "uart3_txd",
 231                 "uart1_rin", "pr1_pru0_pru_r30_11", "pr1_pru0_pru_r31_11", "gpio2_29"),
 232         _AM33XX_MUXENTRY(MMC0_CLK, 0,
 233                 "mmc0_clk", "gpmc_a24", "uart3_ctsn", "uart2_rxd",
 234                 "d_can1_tx", "pr1_pru0_pru_r30_12", "pr1_pru0_pru_r31_12", "gpio2_30"),
 235         _AM33XX_MUXENTRY(MMC0_CMD, 0,
 236                 "mmc0_cmd", "gpmc_a25", "uart3_rtsn", "uart2_txd",
 237                 "d_can1_rx", "pr1_pru0_pru_r30_13", "pr1_pru0_pru_r31_13", "gpio2_31"),
 238         _AM33XX_MUXENTRY(MII1_COL, 0,
 239                 "gmii1_col", "rmii2_refclk", "spi1_sclk", "uart5_rxd",
 240                 "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
 241         _AM33XX_MUXENTRY(MII1_CRS, 0,
 242                 "gmii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
 243                 "mcasp1_aclkx", "uart5_ctsn", "uart2_rxd", "gpio3_1"),
 244         _AM33XX_MUXENTRY(MII1_RXERR, 0,
 245                 "gmii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
 246                 "mcasp1_fsx", "uart5_rtsn", "uart2_txd", "gpio3_2"),
 247         _AM33XX_MUXENTRY(MII1_TXEN, 0,
 248                 "gmii1_txen", "rmii1_txen", "rgmii1_tctl", "timer4",
 249                 "mcasp1_axr0", "eqep0_index", "mmc2_cmd", "gpio3_3"),
 250         _AM33XX_MUXENTRY(MII1_RXDV, 0,
 251                 "gmii1_rxdv", "lcd_memory_clk", "rgmii1_rctl", "uart5_txd",
 252                 "mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", "gpio3_4"),
 253         _AM33XX_MUXENTRY(MII1_TXD3, 0,
 254                 "gmii1_txd3", "d_can0_tx", "rgmii1_td3", "uart4_rxd",
 255                 "mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", "gpio0_16"),
 256         _AM33XX_MUXENTRY(MII1_TXD2, 0,
 257                 "gmii1_txd2", "d_can0_rx", "rgmii1_td2", "uart4_txd",
 258                 "mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", "gpio0_17"),
 259         _AM33XX_MUXENTRY(MII1_TXD1, 0,
 260                 "gmii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
 261                 "mcasp1_axr1", "eqep0a_in", "mmc1_cmd", "gpio0_21"),
 262         _AM33XX_MUXENTRY(MII1_TXD0, 0,
 263                 "gmii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
 264                 "mcasp1_aclkr", "eqep0b_in", "mmc1_clk", "gpio0_28"),
 265         _AM33XX_MUXENTRY(MII1_TXCLK, 0,
 266                 "gmii1_txclk", "uart2_rxd", "rgmii1_tclk", "mmc0_dat7",
 267                 "mmc1_dat0", "uart1_dcdn", "mcasp0_aclkx", "gpio3_9"),
 268         _AM33XX_MUXENTRY(MII1_RXCLK, 0,
 269                 "gmii1_rxclk", "uart2_txd", "rgmii1_rclk", "mmc0_dat6",
 270                 "mmc1_dat1", "uart1_dsrn", "mcasp0_fsx", "gpio3_10"),
 271         _AM33XX_MUXENTRY(MII1_RXD3, 0,
 272                 "gmii1_rxd3", "uart3_rxd", "rgmii1_rd3", "mmc0_dat5",
 273                 "mmc1_dat2", "uart1_dtrn", "mcasp0_axr0", "gpio2_18"),
 274         _AM33XX_MUXENTRY(MII1_RXD2, 0,
 275                 "gmii1_rxd2", "uart3_txd", "rgmii1_rd2", "mmc0_dat4",
 276                 "mmc1_dat3", "uart1_rin", "mcasp0_axr1", "gpio2_19"),
 277         _AM33XX_MUXENTRY(MII1_RXD1, 0,
 278                 "gmii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
 279                 "mcasp1_fsr", "eqep0_strobe", "mmc2_clk", "gpio2_20"),
 280         _AM33XX_MUXENTRY(MII1_RXD0, 0,
 281                 "gmii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
 282                 "mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", "gpio2_21"),
 283         _AM33XX_MUXENTRY(MII1_REFCLK, 0,
 284                 "rmii1_refclk", "xdma_event_intr2", "spi1_cs0", "uart5_txd",
 285                 "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
 286         _AM33XX_MUXENTRY(MDIO_DATA, 0,
 287                 "mdio_data", "timer6", "uart5_rxd", "uart3_ctsn",
 288                 "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
 289         _AM33XX_MUXENTRY(MDIO_CLK, 0,
 290                 "mdio_clk", "timer5", "uart5_txd", "uart3_rtsn",
 291                 "mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
 292         _AM33XX_MUXENTRY(SPI0_SCLK, 0,
 293                 "spi0_sclk", "uart2_rxd", "i2c2_sda", "ehrpwm0a",
 294                 "pr1_uart0_cts_n", "pr1_edio_sof", "emu2", "gpio0_2"),
 295         _AM33XX_MUXENTRY(SPI0_D0, 0,
 296                 "spi0_d0", "uart2_txd", "i2c2_scl", "ehrpwm0b",
 297                 "pr1_uart0_rts_n", "pr1_edio_latch_in", "emu3", "gpio0_3"),
 298         _AM33XX_MUXENTRY(SPI0_D1, 0,
 299                 "spi0_d1", "mmc1_sdwp", "i2c1_sda", "ehrpwm0_tripzone_input",
 300                 "pr1_uart0_rxd", "pr1_edio_data_in0", "pr1_edio_data_out0", "gpio0_4"),
 301         _AM33XX_MUXENTRY(SPI0_CS0, 0,
 302                 "spi0_cs0", "mmc2_sdwp", "i2c1_scl", "ehrpwm0_synci",
 303                 "pr1_uart0_txd", "pr1_edio_data_in1", "pr1_edio_data_out1", "gpio0_5"),
 304         _AM33XX_MUXENTRY(SPI0_CS1, 0,
 305                 "spi0_cs1", "uart3_rxd", "ecap1_in_pwm1_out", "mmc0_pow",
 306                 "xdma_event_intr2", "mmc0_sdcd", "emu4", "gpio0_6"),
 307         _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
 308                 "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", "pr1_ecap0_ecap_capin_apwm_o",
 309                 "spi1_sclk", "mmc0_sdwp", "xdma_event_intr2", "gpio0_7"),
 310         _AM33XX_MUXENTRY(UART0_CTSN, 0,
 311                 "uart0_ctsn", "uart4_rxd", "d_can1_tx", "i2c1_sda",
 312                 "spi1_d0", "timer7", "pr1_edc_sync0_out", "gpio1_8"),
 313         _AM33XX_MUXENTRY(UART0_RTSN, 0,
 314                 "uart0_rtsn", "uart4_txd", "d_can1_rx", "i2c1_scl",
 315                 "spi1_d1", "spi1_cs0", "pr1_edc_sync1_out", "gpio1_9"),
 316         _AM33XX_MUXENTRY(UART0_RXD, 0,
 317                 "uart0_rxd", "spi1_cs0", "d_can0_tx", "i2c2_sda",
 318                 "ecap2_in_pwm2_out", "pr1_pru1_pru_r30_14", "pr1_pru1_pru_r31_14", "gpio1_10"),
 319         _AM33XX_MUXENTRY(UART0_TXD, 0,
 320                 "uart0_txd", "spi1_cs1", "d_can0_rx", "i2c2_scl",
 321                 "ecap1_in_pwm1_out", "pr1_pru1_pru_r30_15", "pr1_pru1_pru_r31_15", "gpio1_11"),
 322         _AM33XX_MUXENTRY(UART1_CTSN, 0,
 323                 "uart1_ctsn", "timer6", "d_can0_tx", "i2c2_sda",
 324                 "spi1_cs0", "pr1_uart0_cts_n", "pr1_edc_latch0_in", "gpio0_12"),
 325         _AM33XX_MUXENTRY(UART1_RTSN, 0,
 326                 "uart1_rtsn", "timer5", "d_can0_rx", "i2c2_scl",
 327                 "spi1_cs1", "pr1_uart0_rts_n", "pr1_edc_latch1_in", "gpio0_13"),
 328         _AM33XX_MUXENTRY(UART1_RXD, 0,
 329                 "uart1_rxd", "mmc1_sdwp", "d_can1_tx", "i2c1_sda",
 330                 NULL, "pr1_uart0_rxd_mux1", "pr1_pru1_pru_r31_16", "gpio0_14"),
 331         _AM33XX_MUXENTRY(UART1_TXD, 0,
 332                 "uart1_txd", "mmc2_sdwp", "d_can1_rx", "i2c1_scl",
 333                 NULL, "pr1_uart0_txd_mux1", "pr1_pru0_pru_r31_16", "gpio0_15"),
 334         _AM33XX_MUXENTRY(I2C0_SDA, 0,
 335                 "i2c0_sda", "timer4", "uart2_ctsn", "ecap2_in_pwm2_out",
 336                 NULL, NULL, NULL, "gpio3_5"),
 337         _AM33XX_MUXENTRY(I2C0_SCL, 0,
 338                 "i2c0_scl", "timer7", "uart2_rtsn", "ecap1_in_pwm1_out",
 339                 NULL, NULL, NULL, "gpio3_6"),
 340         _AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
 341                 "mcasp0_aclkx", "ehrpwm0a", NULL, "spi1_sclk",
 342                 "mmc0_sdcd", "pr1_pru0_pru_r30_0", "pr1_pru0_pru_r31_0", "gpio3_14"),
 343         _AM33XX_MUXENTRY(MCASP0_FSX, 0,
 344                 "mcasp0_fsx", "ehrpwm0b", NULL, "spi1_d0",
 345                 "mmc1_sdcd", "pr1_pru0_pru_r30_1", "pr1_pru0_pru_r31_1", "gpio3_15"),
 346         _AM33XX_MUXENTRY(MCASP0_AXR0, 0,
 347                 "mcasp0_axr0", "ehrpwm0_tripzone_input", NULL, "spi1_d1",
 348                 "mmc2_sdcd", "pr1_pru0_pru_r30_2", "pr1_pru0_pru_r31_2", "gpio3_16"),
 349         _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
 350                 "mcasp0_ahclkr", "ehrpwm0_synci", "mcasp0_axr2", "spi1_cs0",
 351                 "ecap2_in_pwm2_out", "pr1_pru0_pru_r30_3", "pr1_pru0_pru_r31_3", "gpio3_17"),
 352         _AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
 353                 "mcasp0_aclkr", "eqep0a_in", "mcasp0_axr2", "mcasp1_aclkx",
 354                 "mmc0_sdwp", "pr1_pru0_pru_r30_4", "pr1_pru0_pru_r31_4", "gpio3_18"),
 355         _AM33XX_MUXENTRY(MCASP0_FSR, 0,
 356                 "mcasp0_fsr", "eqep0b_in", "mcasp0_axr3", "mcasp1_fsx",
 357                 "emu2", "pr1_pru0_pru_r30_5", "pr1_pru0_pru_r31_5", "gpio3_19"),
 358         _AM33XX_MUXENTRY(MCASP0_AXR1, 0,
 359                 "mcasp0_axr1", "eqep0_index", NULL, "mcasp1_axr0",
 360                 "emu3", "pr1_pru0_pru_r30_6", "pr1_pru0_pru_r31_6", "gpio3_20"),
 361         _AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
 362                 "mcasp0_ahclkx", "eqep0_strobe", "mcasp0_axr3", "mcasp1_axr1",
 363                 "emu4", "pr1_pru0_pru_r30_7", "pr1_pru0_pru_r31_7", "gpio3_21"),
 364         _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
 365                 "xdma_event_intr0", NULL, "timer4", "clkout1",
 366                 "spi1_cs1", "pr1_pru1_pru_r31_16", "emu2", "gpio0_19"),
 367         _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
 368                 "xdma_event_intr1", NULL, "tclkin", "clkout2",
 369                 "timer7", "pr1_pru0_pru_r31_16", "emu3", "gpio0_20"),
 370         _AM33XX_MUXENTRY(WARMRSTN, 0,
 371                 "warmrstn", NULL, NULL, NULL,
 372                 NULL, NULL, NULL, NULL),
 373         _AM33XX_MUXENTRY(PWRONRSTN, 0,
 374                 "porz", NULL, NULL, NULL,
 375                 NULL, NULL, NULL, NULL),
 376         _AM33XX_MUXENTRY(NMIN, 0,
 377                 "nmin", NULL, NULL, NULL,
 378                 NULL, NULL, NULL, NULL),
 379         _AM33XX_MUXENTRY(XTALIN, 0,
 380                 "osc0_in", NULL, NULL, NULL,
 381                 NULL, NULL, NULL, NULL),
 382         _AM33XX_MUXENTRY(XTALOUT, 0,
 383                 "osc0_out", NULL, NULL, NULL,
 384                 NULL, NULL, NULL, NULL),
 385         _AM33XX_MUXENTRY(TMS, 0,
 386                 "tms", NULL, NULL, NULL,
 387                 NULL, NULL, NULL, NULL),
 388         _AM33XX_MUXENTRY(TDI, 0,
 389                 "tdi", NULL, NULL, NULL,
 390                 NULL, NULL, NULL, NULL),
 391         _AM33XX_MUXENTRY(TDO, 0,
 392                 "tdo", NULL, NULL, NULL,
 393                 NULL, NULL, NULL, NULL),
 394         _AM33XX_MUXENTRY(TCK, 0,
 395                 "tck", NULL, NULL, NULL,
 396                 NULL, NULL, NULL, NULL),
 397         _AM33XX_MUXENTRY(TRSTN, 0,
 398                 "trstn", NULL, NULL, NULL,
 399                 NULL, NULL, NULL, NULL),
 400         _AM33XX_MUXENTRY(EMU0, 0,
 401                 "emu0", NULL, NULL, NULL,
 402                 NULL, NULL, NULL, "gpio3_7"),
 403         _AM33XX_MUXENTRY(EMU1, 0,
 404                 "emu1", NULL, NULL, NULL,
 405                 NULL, NULL, NULL, "gpio3_8"),
 406         _AM33XX_MUXENTRY(RTC_XTALIN, 0,
 407                 "osc1_in", NULL, NULL, NULL,
 408                 NULL, NULL, NULL, NULL),
 409         _AM33XX_MUXENTRY(RTC_XTALOUT, 0,
 410                 "osc1_out", NULL, NULL, NULL,
 411                 NULL, NULL, NULL, NULL),
 412         _AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
 413                 "rtc_pwronrstn", NULL, NULL, NULL,
 414                 NULL, NULL, NULL, NULL),
 415         _AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
 416                 "pmic_power_en", NULL, NULL, NULL,
 417                 NULL, NULL, NULL, NULL),
 418         _AM33XX_MUXENTRY(EXT_WAKEUP, 0,
 419                 "ext_wakeup", NULL, NULL, NULL,
 420                 NULL, NULL, NULL, NULL),
 421         _AM33XX_MUXENTRY(RTC_KALDO_ENN, 0,
 422                 "rtc_kaldo_enn", NULL, NULL, NULL,
 423                 NULL, NULL, NULL, NULL),
 424         _AM33XX_MUXENTRY(USB0_DM, 0,
 425                 "usb0_dm", NULL, NULL, NULL,
 426                 NULL, NULL, NULL, NULL),
 427         _AM33XX_MUXENTRY(USB0_DP, 0,
 428                 "usb0_dp", NULL, NULL, NULL,
 429                 NULL, NULL, NULL, NULL),
 430         _AM33XX_MUXENTRY(USB0_CE, 0,
 431                 "usb0_ce", NULL, NULL, NULL,
 432                 NULL, NULL, NULL, NULL),
 433         _AM33XX_MUXENTRY(USB0_ID, 0,
 434                 "usb0_id", NULL, NULL, NULL,
 435                 NULL, NULL, NULL, NULL),
 436         _AM33XX_MUXENTRY(USB0_VBUS, 0,
 437                 "usb0_vbus", NULL, NULL, NULL,
 438                 NULL, NULL, NULL, NULL),
 439         _AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
 440                 "usb0_drvvbus", NULL, NULL, NULL,
 441                 NULL, NULL, NULL, "gpio0_18"),
 442         _AM33XX_MUXENTRY(USB1_DM, 0,
 443                 "usb0_dm", NULL, NULL, NULL,
 444                 NULL, NULL, NULL, NULL),
 445         _AM33XX_MUXENTRY(USB1_DP, 0,
 446                 "usb0_dp", NULL, NULL, NULL,
 447                 NULL, NULL, NULL, NULL),
 448         _AM33XX_MUXENTRY(USB1_CE, 0,
 449                 "usb0_ce", NULL, NULL, NULL,
 450                 NULL, NULL, NULL, NULL),
 451         _AM33XX_MUXENTRY(USB1_ID, 0,
 452                 "usb0_id", NULL, NULL, NULL,
 453                 NULL, NULL, NULL, NULL),
 454         _AM33XX_MUXENTRY(USB1_VBUS, 0,
 455                 "usb0_vbus", NULL, NULL, NULL,
 456                 NULL, NULL, NULL, NULL),
 457         _AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
 458                 "usb1_drvvbus", NULL, NULL, NULL,
 459                 NULL, NULL, NULL, "gpio3_13"),
 460         { .reg_offset = OMAP_MUX_TERMINATOR },
 461 };
 462
 463 int __init am33xx_mux_init(struct omap_board_mux *board_subset)
 464 {
 465         return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
 466                         AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
 467                         NULL, board_subset, NULL);
 468 }
 469
 470 #ifdef CONFIG_SUSPEND
 471 struct am33xx_padconf_regs {
 472         u16 offset;
 473         u32 val;
 474 };
 475
 476 static struct am33xx_padconf_regs am33xx_lp_padconf[] = {
 477         {.offset = AM33XX_CONTROL_GMII_SEL_OFFSET},
 478         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET},
 479         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET},
 480         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET},
 481         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET},
 482         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET},
 483         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET},
 484         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET},
 485         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET},
 486         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET},
 487         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET},
 488         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET},
 489         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET},
 490         {.offset = AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET},
 491         {.offset = AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET},
 492         {.offset = AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET},
 493         {.offset = AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET},
 494         {.offset = AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET},
 495         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET},
 496         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET},
 497         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET},
 498         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET},
 499         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET},
 500         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET},
 501         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET},
 502         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET},
 503         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET},
 504         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET},
 505         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET},
 506         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET},
 507         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET},
 508         {.offset = AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET},
 509         {.offset = AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET},
 510         {.offset = AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET},
 511 };
 512 #endif /* CONFIG_SUSPEND */
 513
 514 struct susp_io_pad_conf {
 515         u32 enabled;
 516         u32 val;
 517 };
 518
 519 static u32 susp_io_pad_conf_enabled;
 520 static struct susp_io_pad_conf pad_array[MAX_IO_PADCONF];
 521
 522 struct standby_gpio_pad_struct {
 523         u32 enabled;
 524         u32 gpio_request_success;
 525         u32 pin_val;
 526         u32 trigger;
 527         u32 gpio_pin;
 528         u32 curr_pin_mux;
 529 };
 530
 531 static struct standby_gpio_pad_struct standby_gpio_array[MAX_IO_PADCONF];
 532
 533 /*
 534  * Expected input: 1/0
 535  * Example: "echo 1 > enable_suspend_io_pad_conf" enables IO PAD Config
 536  */
 537 static int susp_io_pad_enable_set(void *data, u64 val)
 538 {
 539         u32 *enabled = data;
 540
 541         *enabled = val & 0x1;
 542
 543         return 0;
 544 }
 545
 546 static int susp_io_pad_enable_get(void *data, u64 *val)
 547 {
 548         u32 *enabled = data;
 549
 550         *val = *enabled;
 551
 552         return 0;
 553 }
 554
 555 DEFINE_SIMPLE_ATTRIBUTE(susp_io_pad_enable_fops, susp_io_pad_enable_get,
 556                         susp_io_pad_enable_set, "%llx\n");
 557
 558 static unsigned int am335x_pin_mux_addr_to_skip[] = {
 559         0x9bc,
 560         0x9c4, 0x9c8, 0x9cc,
 561         0x9ec,
 562         0x9f0, 0x9f4,
 563         0xa08, 0xa0c,
 564         0xa10, 0xa14, 0xa18,
 565         0xa20, 0xa24, 0xa28, 0xa2c,
 566         0xa30,
 567 };
 568
 569 static int susp_io_pad_status_show(struct seq_file *s, void *unused)
 570 {
 571         struct omap_mux *mux_arr = &am33xx_muxmodes[0];
 572         u32 *enabled = s->private;
 573         int i;
 574
 575         if (!*enabled) {
 576                 pr_err("%s: IO PAD Configuration is not enabled\n", __func__);
 577                 return 0;
 578         }
 579
 580         for (i = 0; i < MAX_IO_PADCONF;) {
 581                 int off, j, addr_match = 0;
 582
 583                 if (pad_array[i].enabled) {
 584                         int mode = pad_array[i].val & OMAP_MUX_MODE7;
 585                         seq_printf(s, "%s.%s (0x%08x = 0x%02x)\n",
 586                                 mux_arr->muxnames[0], mux_arr->muxnames[mode],
 587                                 (unsigned int)(AM33XX_CONTROL_PADCONF_MUX_PBASE
 588                                 + mux_arr->reg_offset),
 589                                 pad_array[i].val);
 590                 }
 591
 592                 i++;
 593
 594                 /*
 595                  * AM335x pin-mux register offset sequence is broken, meaning
 596                  * there is no pin-mux setting at some offset and at some
 597                  * offsets, the modes are not supposed to be changed. Because
 598                  * of this, the "am33xx_muxmodes" array above will not have any
 599                  * values at these indexes. Hence the pad_array &
 600                  * am33xx_muxmodes array will be out of sync at these index.
 601                  * Handle missing pin-mux entries accordingly by using a special
 602                  * array that indicate these offsets.
 603                  */
 604                 off = ((i * 4) + 0x800);
 605                 for (j = 0; j < ARRAY_SIZE(am335x_pin_mux_addr_to_skip); j++) {
 606                         if (off == am335x_pin_mux_addr_to_skip[j]) {
 607                                 addr_match = 1;
 608                                 break;
 609                         }
 610                 }
 611                 if (addr_match == 0)
 612                         mux_arr++;
 613         }
 614
 615         return 0;
 616 }
 617
 618 /*
 619  * Expected input: pinmux_name=<value1>
 620  *      pinmux_name = Pin-mux name that is to be setup during suspend with value
 621  *              <value1>. Pin-mux name should be in "mode0_name.function_name"
 622  *              format. Internally the pin-mux offset is calculated from the
 623  *              pin-mux names. Invalid pin-mux names and values are ignored.
 624  *              Remember, NO spaces anywhere in the input.
 625  *
 626  * Example:
 627  *        echo mcasp0_aclkx.gpio3_14=0x27 > suspend_pad_conf
 628  *              stores 0x27 as the value to be written to the pinmux (with
 629  *              mode0_name.function_name as mcasp0_aclkx.gpio3_14) when entering
 630  *              suspend
 631  */
 632 static ssize_t susp_io_pad_write(struct file *file,
 633                                          const char __user *user_buf,
 634                                          size_t count, loff_t *ppos)
 635 {
 636         struct seq_file *seqf;
 637         u32 *enabled, val;
 638         char *export_string, *token, *name;
 639
 640         seqf = file->private_data;
 641         enabled = seqf->private;
 642
 643         if (!*enabled) {
 644                 pr_err("%s: IO PAD Configuration is not enabled\n", __func__);
 645                 return -EINVAL;
 646         }
 647
 648         export_string = kzalloc(count + 1, GFP_KERNEL);
 649         if (!export_string)
 650                 return -ENOMEM;
 651
 652         if (copy_from_user(export_string, user_buf, count)) {
 653                 kfree(export_string);
 654                 return -EFAULT;
 655         }
 656
 657         token = export_string;
 658         name = strsep(&token, "=");
 659         if (name) {
 660                 struct omap_mux_partition *partition = NULL;
 661                 struct omap_mux *mux = NULL;
 662                 int mux_index, mux_mode;
 663                 int res;
 664
 665                 mux_mode = omap_mux_get_by_name(name, &partition, &mux);
 666                 if (mux_mode < 0) {
 667                         pr_err("%s: Invalid mux name (%s). Ignoring the"
 668                                         " value\n", __func__, name);
 669                         goto err_out;
 670                 }
 671
 672                 res = kstrtouint(token, 0, &val);
 673                 if (res < 0) {
 674                         pr_err("%s: Invalid value (%s). Ignoring\n",
 675                                                 __func__, token);
 676                         goto err_out;
 677                 }
 678
 679                 mux_index = (mux->reg_offset -
 680                         AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4;
 681
 682                 if (mux_index > MAX_IO_PADCONF) {
 683                         pr_err("%s: Invalid index (0x%x). Ignoring\n",
 684                                                 __func__, mux_index);
 685                         goto err_out;
 686                 }
 687
 688                 pad_array[mux_index].enabled = true;
 689                 pad_array[mux_index].val = val;
 690         } else {
 691                 pr_err("%s: Invalid mux name (%s). Ignoring the entry\n",
 692                                                 __func__, export_string);
 693         }
 694
 695 err_out:
 696         *ppos += count;
 697         kfree(export_string);
 698         return count;
 699 }
 700
 701 static int susp_io_pad_open(struct inode *inode, struct file *file)
 702 {
 703         return single_open(file, susp_io_pad_status_show, inode->i_private);
 704 }
 705
 706 static const struct file_operations susp_io_pad_fops = {
 707         .open           = susp_io_pad_open,
 708         .read           = seq_read,
 709         .write          = susp_io_pad_write,
 710         .release        = single_release,
 711 };
 712
 713 static int standby_gpio_status_show(struct seq_file *s, void *unused)
 714 {
 715         struct omap_mux *mux_arr = &am33xx_muxmodes[0];
 716
 717         int i;
 718
 719         for (i = 0; i < MAX_IO_PADCONF;) {
 720                 int off, j, addr_match = 0;
 721                 char *trigger;
 722
 723                 if (standby_gpio_array[i].enabled) {
 724                         switch (standby_gpio_array[i].trigger) {
 725                         case IRQF_TRIGGER_RISING:
 726                                 trigger = "rising";
 727                                 break;
 728
 729                         case IRQF_TRIGGER_FALLING:
 730                                 trigger = "falling";
 731                                 break;
 732
 733                         case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
 734                         /* fall through */
 735                         default:
 736                                 trigger = "falling_rising";
 737                                 break;
 738                         }
 739
 740                         seq_printf(s, "%s.%s (0x%08x = 0x%02x), trigger = %s\n",
 741                                 mux_arr->muxnames[0],
 742                                 mux_arr->muxnames[OMAP_MUX_MODE7],
 743                                 (unsigned int)(AM33XX_CONTROL_PADCONF_MUX_PBASE
 744                                 + mux_arr->reg_offset),
 745                                 standby_gpio_array[i].pin_val,
 746                                 trigger);
 747
 748
 749                 }
 750
 751                 /*
 752                  * AM335x pin-mux register offset sequence is broken, meaning
 753                  * there is no pin-mux setting at some offset and at some
 754                  * offsets, the modes are not supposed to be changed. Because
 755                  * of this, the "am33xx_muxmodes" array above will not have any
 756                  * values at these indexes. Hence the standby_gpio_array &
 757                  * am33xx_muxmodes array will be out of sync at these index.
 758                  * Handle missing pin-mux entries accordingly by using a special
 759                  * array that indicate these offsets.
 760                  */
 761
 762                 i++;
 763                 off = ((i * 4) + 0x800);
 764                 for (j = 0; j < ARRAY_SIZE(am335x_pin_mux_addr_to_skip); j++) {
 765                         if (off == am335x_pin_mux_addr_to_skip[j]) {
 766                                 addr_match = 1;
 767                                 break;
 768                         }
 769                 }
 770                 if (addr_match == 0)
 771                         mux_arr++;
 772         }
 773
 774         return 0;
 775 }
 776
 777 /*
 778  * Expected input: pinmux_name=<value1>,<trigger>
 779  *      pinmux_name = Pin-mux name that is to be setup as gpio during standby
 780  *              suspend with gpio interrupt trigger mode as per <trigger> field
 781  *              with value <value1>.
 782  *              Pin-mux name should be in "mode0_name.mode7_function_name"
 783  *              format. Internally the pin-mux offset is calculated from the
 784  *              pin-mux names. Invalid pin-mux names and values are ignored.
 785  *              Remember,
 786  *                      - No spaces anywhere in the input.
 787  *                      - <value1> field is a must
 788  *                      - <trigger> field is a must and must be one of "rising",
 789  *                        "falling"
 790  *
 791  * Example:
 792  *        echo uart0_rxd.gpio1_10=0x27,rising > standby_gpio_pad_conf
 793  *              sets up uart0_rxd.gpio1_10 for gpio mode with interrupt trigger
 794  *              as rising and pin-mux value as 0x27 when entering standby mode.
 795  */
 796 static ssize_t standby_gpio_pad_write(struct file *file,
 797                                          const char __user *user_buf,
 798                                          size_t count, loff_t *ppos)
 799 {
 800         u32 trigger;
 801         char *export_string, *token, *name;
 802
 803         export_string = kzalloc(count + 1, GFP_KERNEL);
 804         if (!export_string)
 805                 return -ENOMEM;
 806
 807         if (copy_from_user(export_string, user_buf, count)) {
 808                 kfree(export_string);
 809                 return -EFAULT;
 810         }
 811
 812         export_string[count-1] = '\0';   /* force null terminator */
 813         token = export_string;
 814         name = strsep(&token, "=");
 815         if (name) {
 816                 struct omap_mux_partition *partition = NULL;
 817                 struct omap_mux *mux = NULL;
 818                 int mux_index, mux_mode, gpio_bank, gpio_pin, res, pin_val;
 819                 char *gpio_name;
 820
 821                 mux_mode = omap_mux_get_by_name(name, &partition, &mux);
 822                 if (mux_mode < 0) {
 823                         pr_err("%s: Invalid mux name (%s). Ignoring the"
 824                                         " value\n", __func__, name);
 825                         goto err_out;
 826                 }
 827
 828                 name = strsep(&token, ",");
 829                 if (!name) {
 830                         pr_err("%s: Invalid value (%s). Ignoring\n",
 831                                 __func__, token);
 832                         goto err_out;
 833                 }
 834
 835                 res = kstrtouint(name, 0, &pin_val);
 836                 if (res < 0) {
 837                         pr_err("%s: Invalid pin mux value (%s). Ignoring\n",
 838                                                 __func__, token);
 839                         goto err_out;
 840                 }
 841
 842                 if (token && !strncmp("rising", token, 6)) {
 843                         trigger = IRQF_TRIGGER_RISING;
 844                 } else if (token && !strncmp("falling", token, 7)) {
 845                         trigger = IRQF_TRIGGER_FALLING;
 846                 } else {
 847                         pr_err("%s: Invalid trigger (%s). Defaulting to"
 848                                         " falling_rising\n", __func__, token);
 849                         trigger = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
 850                 }
 851
 852                 /* confirm whether a gpio pin exists here */
 853                 gpio_name = mux->muxnames[OMAP_MUX_MODE7];
 854
 855                 if (!gpio_name) {
 856                         pr_err("%s: Invalid mux name (%s)\n", __func__, name);
 857                         goto err_out;
 858                 } else if (strncmp(gpio_name, "gpio", 4)) {
 859                         pr_err("%s: Invalid mux name found (%s)\n",
 860                                         __func__, gpio_name);
 861                         goto err_out;
 862                 }
 863
 864                 /*
 865                  * parse the string name and get the gpio bank & pin number.
 866                  * gpio_name will be in the format of "gpioX_Y" where
 867                  *      X = bank
 868                  *      Y = pin number
 869                  */
 870                 gpio_bank = *(gpio_name + 4) - '0';
 871
 872                 gpio_name += 6;
 873                 res = kstrtoint(gpio_name, 10, &gpio_pin);
 874                 if (res < 0) {
 875                         pr_err("%s: Invalid gpio pin number (%s). Ignoring\n",
 876                                 __func__, gpio_name);
 877                         goto err_out;
 878                 }
 879
 880                 mux_index = (mux->reg_offset -
 881                         AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET) / 4;
 882
 883                 if (mux_index > MAX_IO_PADCONF) {
 884                         pr_err("%s: Invalid index (0x%x). Ignoring\n",
 885                                                 __func__, mux_index);
 886                         goto err_out;
 887                 }
 888
 889                 standby_gpio_array[mux_index].enabled = true;
 890                 standby_gpio_array[mux_index].pin_val = pin_val;
 891                 standby_gpio_array[mux_index].trigger = trigger;
 892                 standby_gpio_array[mux_index].gpio_pin =
 893                                                 ((gpio_bank * 32) + gpio_pin);
 894         } else {
 895                 pr_err("%s: Invalid mux name (%s). Ignoring the entry\n",
 896                                                 __func__, export_string);
 897         }
 898
 899 err_out:
 900         *ppos += count;
 901         kfree(export_string);
 902         return count;
 903 }
 904
 905 static int standby_gpio_pad_open(struct inode *inode, struct file *file)
 906 {
 907         return single_open(file, standby_gpio_status_show, inode->i_private);
 908 }
 909
 910 static const struct file_operations standby_gpio_pad_conf_fops = {
 911         .open           = standby_gpio_pad_open,
 912         .read           = seq_read,
 913         .write          = standby_gpio_pad_write,
 914         .release        = single_release,
 915 };
 916
 917 void am33xx_mux_dbg_create_entry(struct dentry *mux_dbg_dir)
 918 {
 919         struct dentry *mux_dbg_suspend_io_conf_dir;
 920
 921         if (!mux_dbg_dir)
 922                 return;
 923
 924         /*
 925          * create a directory by the name suspend_io_pad_conf in
 926          * <debugfs-mount-dir>/<mux_dbg_dir>/
 927          */
 928         mux_dbg_suspend_io_conf_dir = debugfs_create_dir("suspend_io_pad_conf",
 929                                                                 mux_dbg_dir);
 930         if (!mux_dbg_suspend_io_conf_dir)
 931                 return;
 932
 933         memset(pad_array, 0, sizeof(pad_array));
 934
 935         (void)debugfs_create_file("enable_suspend_io_pad_conf",
 936                                                 S_IRUGO | S_IWUSR,
 937                                                 mux_dbg_suspend_io_conf_dir,
 938                                                 &susp_io_pad_conf_enabled,
 939                                                 &susp_io_pad_enable_fops);
 940         (void)debugfs_create_file("suspend_pad_conf", S_IRUGO | S_IWUSR,
 941                                                 mux_dbg_suspend_io_conf_dir,
 942                                                 &susp_io_pad_conf_enabled,
 943                                                 &susp_io_pad_fops);
 944         (void)debugfs_create_file("standby_gpio_pad_conf", S_IRUGO | S_IWUSR,
 945                                                 mux_dbg_dir,
 946                                                 &susp_io_pad_conf_enabled,
 947                                                 &standby_gpio_pad_conf_fops);
 948 }
 949
 950 void am33xx_setup_pinmux_on_suspend(void)
 951 {
 952         u32 reg_off, i;
 953
 954         if (susp_io_pad_conf_enabled == 1) {
 955                 reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
 956                 for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
 957                         if (pad_array[i].enabled)
 958                                 writel(pad_array[i].val,
 959                                                 AM33XX_CTRL_REGADDR(reg_off));
 960                 }
 961         }
 962 }
 963
 964 static u32 am33xx_lp_padconf_complete[MAX_IO_PADCONF];
 965
 966 void am335x_save_padconf(void)
 967 {
 968         struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
 969         u32 reg_off;
 970         int i;
 971         if (susp_io_pad_conf_enabled == 1) {
 972                 i = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
 973                 reg_off = 0;
 974
 975                 for (; i < AM33XX_CONTROL_PADCONF_MUX_SIZE; i += 4, reg_off++)
 976                         am33xx_lp_padconf_complete[reg_off] =
 977                                                 readl(AM33XX_CTRL_REGADDR(i));
 978         } else {
 979                 for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
 980                         temp->val = readl(AM33XX_CTRL_REGADDR(temp->offset));
 981         }
 982 }
 983
 984 void am335x_restore_padconf(void)
 985 {
 986         struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
 987         u32 reg_off;
 988         int i;
 989         if (susp_io_pad_conf_enabled == 1) {
 990                 i = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
 991                 reg_off = 0;
 992                 for (; i < AM33XX_CONTROL_PADCONF_MUX_SIZE; i += 4, reg_off++)
 993                         writel(am33xx_lp_padconf_complete[reg_off],
 994                                                         AM33XX_CTRL_REGADDR(i));
 995         } else {
 996                 for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
 997                         writel(temp->val, AM33XX_CTRL_REGADDR(temp->offset));
 998         }
 999 }
1000
1001 /*
1002  * Dummy GPIO interrupt Handler
1003  */
1004 static irqreturn_t gpio_irq(int irq, void *dev_id)
1005 {
1006         return IRQ_HANDLED;
1007 }
1008
1009 void am33xx_standby_setup(unsigned int state)
1010 {
1011         u32 reg_off, i;
1012
1013         if (state != PM_SUSPEND_STANDBY)
1014                 return;
1015
1016         writel(0x2, AM33XX_CM_PER_GPIO1_CLKCTRL);
1017         writel(0x2, AM33XX_CM_PER_GPIO2_CLKCTRL);
1018         writel(0x2, AM33XX_CM_PER_GPIO3_CLKCTRL);
1019
1020         reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
1021         for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
1022                 if (standby_gpio_array[i].enabled) {
1023                         int ret, reg_val, irq;
1024                         u32 gpio_pin = standby_gpio_array[i].gpio_pin;
1025
1026                         reg_val = readl(AM33XX_CTRL_REGADDR(reg_off));
1027                         standby_gpio_array[i].curr_pin_mux = reg_val;
1028                         reg_val = standby_gpio_array[i].pin_val;
1029                         writel(reg_val, AM33XX_CTRL_REGADDR(reg_off));
1030
1031                         ret = gpio_request(gpio_pin, "pm_standby");
1032                         if (ret) {
1033                                 pr_err("%s: Error in gpio request (%d)\n",
1034                                                 __func__, ret);
1035                                 continue;
1036                         }
1037                         irq = gpio_to_irq(gpio_pin);
1038                         if (irq < 0) {
1039                                 gpio_free(gpio_pin);
1040                                 pr_err("%s: gpio_to_irq failed (%d)\n",
1041                                                                 __func__, irq);
1042                                 continue;
1043                         }
1044                         ret = request_irq(irq, gpio_irq,
1045                                                 standby_gpio_array[i].trigger,
1046                                                 "pm_standby", NULL);
1047                         if (ret) {
1048                                 gpio_free(gpio_pin);
1049                                 pr_err("%s: interrupt request failed (%d)\n",
1050                                                                 __func__, ret);
1051                                 continue;
1052                         }
1053
1054                         standby_gpio_array[i].gpio_request_success = true;
1055                 }
1056         }
1057
1058 }
1059
1060 void am33xx_standby_release(unsigned int state)
1061 {
1062         u32 reg_off, i;
1063
1064         if (state != PM_SUSPEND_STANDBY)
1065                 return;
1066
1067         reg_off = AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET;
1068         for (i = 0; i < MAX_IO_PADCONF; reg_off += 4, i++) {
1069                 u32 gpio_pin = standby_gpio_array[i].gpio_pin;
1070
1071                 if (standby_gpio_array[i].enabled) {
1072                         writel(standby_gpio_array[i].curr_pin_mux,
1073                                                 AM33XX_CTRL_REGADDR(reg_off));
1074
1075                         if (standby_gpio_array[i].gpio_request_success ==
1076                                                                         true) {
1077                                 int irq;
1078
1079                                 irq = gpio_to_irq(gpio_pin);
1080                                 gpio_free(gpio_pin);
1081                                 free_irq(irq, 0);
1082                         }
1083                 }
1084         }
1085 }