2 * OMAP WakeupGen Source file
4 * OMAP WakeupGen is the interrupt controller extension used along
5 * with ARM GIC to wake the CPU out from low power states on
6 * external interrupts. It is responsible for generating wakeup
7 * event from the incoming interrupts and enable bits. It is
8 * implemented in MPU always ON power domain. During normal operation,
9 * WakeupGen delivers external interrupts directly to the GIC.
11 * Copyright (C) 2011 Texas Instruments, Inc.
12 * Santosh Shilimkar <santosh.shilimkar@ti.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/irqchip.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
26 #include <linux/platform_device.h>
27 #include <linux/cpu.h>
28 #include <linux/notifier.h>
29 #include <linux/cpu_pm.h>
31 #include "omap-wakeupgen.h"
32 #include "omap-secure.h"
35 #include "omap4-sar-layout.h"
39 #define AM43XX_NR_REG_BANKS 7
40 #define AM43XX_IRQS 224
41 #define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
42 #define MAX_IRQS AM43XX_IRQS
43 #define DEFAULT_NR_REG_BANKS 5
44 #define DEFAULT_IRQS 160
45 #define WKG_MASK_ALL 0x00000000
46 #define WKG_UNMASK_ALL 0xffffffff
47 #define CPU_ENA_OFFSET 0x400
50 #define OMAP4_NR_BANKS 4
51 #define OMAP4_NR_IRQS 128
53 static void __iomem *wakeupgen_base;
54 static void __iomem *sar_base;
55 static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
56 static unsigned int irq_target_cpu[MAX_IRQS];
57 static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
58 static unsigned int max_irqs = DEFAULT_IRQS;
59 static unsigned int omap_secure_apis;
62 * Static helper functions.
64 static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
66 return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
67 (cpu * CPU_ENA_OFFSET) + (idx * 4));
70 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
72 writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
73 (cpu * CPU_ENA_OFFSET) + (idx * 4));
76 static inline void sar_writel(u32 val, u32 offset, u8 idx)
78 writel_relaxed(val, sar_base + offset + (idx * 4));
81 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
84 * Each WakeupGen register controls 32 interrupt.
85 * i.e. 1 bit per SPI IRQ
87 *reg_index = irq >> 5;
88 *bit_posn = irq %= 32;
93 static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
98 if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
101 val = wakeupgen_readl(i, cpu);
102 val &= ~BIT(bit_number);
103 wakeupgen_writel(val, i, cpu);
106 static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
111 if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
114 val = wakeupgen_readl(i, cpu);
115 val |= BIT(bit_number);
116 wakeupgen_writel(val, i, cpu);
120 * Architecture specific Mask extension
122 static void wakeupgen_mask(struct irq_data *d)
126 raw_spin_lock_irqsave(&wakeupgen_lock, flags);
127 _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
128 raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
129 irq_chip_mask_parent(d);
133 * Architecture specific Unmask extension
135 static void wakeupgen_unmask(struct irq_data *d)
139 raw_spin_lock_irqsave(&wakeupgen_lock, flags);
140 _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
141 raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
142 irq_chip_unmask_parent(d);
145 #ifdef CONFIG_HOTPLUG_CPU
146 static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
148 static void _wakeupgen_save_masks(unsigned int cpu)
152 for (i = 0; i < irq_banks; i++)
153 per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
156 static void _wakeupgen_restore_masks(unsigned int cpu)
160 for (i = 0; i < irq_banks; i++)
161 wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
164 static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
168 for (i = 0; i < irq_banks; i++)
169 wakeupgen_writel(reg, i, cpu);
173 * Mask or unmask all interrupts on given CPU.
174 * 0 = Mask all interrupts on the 'cpu'
175 * 1 = Unmask all interrupts on the 'cpu'
176 * Ensure that the initial mask is maintained. This is faster than
177 * iterating through GIC registers to arrive at the correct masks.
179 static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
183 raw_spin_lock_irqsave(&wakeupgen_lock, flags);
185 _wakeupgen_save_masks(cpu);
186 _wakeupgen_set_all(cpu, WKG_MASK_ALL);
188 _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
189 _wakeupgen_restore_masks(cpu);
191 raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
196 static inline void omap4_irq_save_context(void)
200 if (omap_rev() == OMAP4430_REV_ES1_0)
203 for (i = 0; i < irq_banks; i++) {
204 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
205 val = wakeupgen_readl(i, 0);
206 sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
207 val = wakeupgen_readl(i, 1);
208 sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
211 * Disable the secure interrupts for CPUx. The restore
212 * code blindly restores secure and non-secure interrupt
213 * masks from SAR RAM. Secure interrupts are not suppose
214 * to be enabled from HLOS. So overwrite the SAR location
215 * so that the secure interrupt remains disabled.
217 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
218 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
221 /* Save AuxBoot* registers */
222 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
223 writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
224 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
225 writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
227 /* Save SyncReq generation logic */
228 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
229 writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
230 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
231 writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
233 /* Set the Backup Bit Mask status */
234 val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
235 val |= SAR_BACKUP_STATUS_WAKEUPGEN;
236 writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
240 static inline void omap5_irq_save_context(void)
244 for (i = 0; i < irq_banks; i++) {
245 /* Save the CPUx interrupt mask for IRQ 0 to 159 */
246 val = wakeupgen_readl(i, 0);
247 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
248 val = wakeupgen_readl(i, 1);
249 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
250 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
251 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
254 /* Save AuxBoot* registers */
255 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
256 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
257 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
258 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
260 /* Set the Backup Bit Mask status */
261 val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
262 val |= SAR_BACKUP_STATUS_WAKEUPGEN;
263 writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
268 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
269 * ROM code. WakeupGen IP is integrated along with GIC to manage the
270 * interrupt wakeups from CPU low power states. It manages
271 * masking/unmasking of Shared peripheral interrupts(SPI). So the
272 * interrupt enable/disable control should be in sync and consistent
273 * at WakeupGen and GIC so that interrupts are not lost.
275 static void irq_save_context(void)
278 sar_base = omap4_get_sar_ram_base();
280 if (soc_is_omap54xx())
281 omap5_irq_save_context();
283 omap4_irq_save_context();
287 * Clear WakeupGen SAR backup status.
289 static void irq_sar_clear(void)
292 u32 offset = SAR_BACKUP_STATUS_OFFSET;
294 if (soc_is_omap54xx())
295 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
297 val = readl_relaxed(sar_base + offset);
298 val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
299 writel_relaxed(val, sar_base + offset);
303 * Save GIC and Wakeupgen interrupt context using secure API
304 * for HS/EMU devices.
306 static void irq_save_secure_context(void)
309 ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
312 if (ret != API_HAL_RET_VALUE_OK)
313 pr_err("GIC and Wakeupgen context save failed\n");
317 #ifdef CONFIG_HOTPLUG_CPU
318 static int irq_cpu_hotplug_notify(struct notifier_block *self,
319 unsigned long action, void *hcpu)
321 unsigned int cpu = (unsigned int)hcpu;
325 wakeupgen_irqmask_all(cpu, 0);
328 wakeupgen_irqmask_all(cpu, 1);
334 static struct notifier_block irq_hotplug_notifier = {
335 .notifier_call = irq_cpu_hotplug_notify,
338 static void __init irq_hotplug_init(void)
340 register_hotcpu_notifier(&irq_hotplug_notifier);
343 static void __init irq_hotplug_init(void)
348 static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
351 case CPU_CLUSTER_PM_ENTER:
352 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
355 irq_save_secure_context();
357 case CPU_CLUSTER_PM_EXIT:
358 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
365 static struct notifier_block irq_notifier_block = {
366 .notifier_call = irq_notifier,
369 static void __init irq_pm_init(void)
371 /* FIXME: Remove this when MPU OSWR support is added */
372 if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
373 cpu_pm_register_notifier(&irq_notifier_block);
376 static void __init irq_pm_init(void)
380 void __iomem *omap_get_wakeupgen_base(void)
382 return wakeupgen_base;
385 int omap_secure_apis_support(void)
387 return omap_secure_apis;
390 static struct irq_chip wakeupgen_chip = {
392 .irq_eoi = irq_chip_eoi_parent,
393 .irq_mask = wakeupgen_mask,
394 .irq_unmask = wakeupgen_unmask,
395 .irq_retrigger = irq_chip_retrigger_hierarchy,
396 .irq_set_type = irq_chip_set_type_parent,
397 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
399 .irq_set_affinity = irq_chip_set_affinity_parent,
403 static int wakeupgen_domain_xlate(struct irq_domain *domain,
404 struct device_node *controller,
406 unsigned int intsize,
407 unsigned long *out_hwirq,
408 unsigned int *out_type)
410 if (domain->of_node != controller)
411 return -EINVAL; /* Shouldn't happen, really... */
413 return -EINVAL; /* Not GIC compliant */
415 return -EINVAL; /* No PPI should point to this domain */
417 *out_hwirq = intspec[1];
418 *out_type = intspec[2];
422 static int wakeupgen_domain_alloc(struct irq_domain *domain,
424 unsigned int nr_irqs, void *data)
426 struct of_phandle_args *args = data;
427 struct of_phandle_args parent_args;
428 irq_hw_number_t hwirq;
431 if (args->args_count != 3)
432 return -EINVAL; /* Not GIC compliant */
433 if (args->args[0] != 0)
434 return -EINVAL; /* No PPI should point to this domain */
436 hwirq = args->args[1];
437 if (hwirq >= MAX_IRQS)
438 return -EINVAL; /* Can't deal with this */
440 for (i = 0; i < nr_irqs; i++)
441 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
442 &wakeupgen_chip, NULL);
445 parent_args.np = domain->parent->of_node;
446 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
449 static const struct irq_domain_ops wakeupgen_domain_ops = {
450 .xlate = wakeupgen_domain_xlate,
451 .alloc = wakeupgen_domain_alloc,
452 .free = irq_domain_free_irqs_common,
456 * Initialise the wakeupgen module.
458 static int __init wakeupgen_init(struct device_node *node,
459 struct device_node *parent)
461 struct irq_domain *parent_domain, *domain;
463 unsigned int boot_cpu = smp_processor_id();
467 pr_err("%s: no parent, giving up\n", node->full_name);
471 parent_domain = irq_find_host(parent);
472 if (!parent_domain) {
473 pr_err("%s: unable to obtain parent domain\n", node->full_name);
476 /* Not supported on OMAP4 ES1.0 silicon */
477 if (omap_rev() == OMAP4430_REV_ES1_0) {
478 WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
482 /* Static mapping, never released */
483 wakeupgen_base = of_iomap(node, 0);
484 if (WARN_ON(!wakeupgen_base))
487 if (cpu_is_omap44xx()) {
488 irq_banks = OMAP4_NR_BANKS;
489 max_irqs = OMAP4_NR_IRQS;
490 omap_secure_apis = 1;
491 } else if (soc_is_am43xx()) {
492 irq_banks = AM43XX_NR_REG_BANKS;
493 max_irqs = AM43XX_IRQS;
496 domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
497 node, &wakeupgen_domain_ops,
500 iounmap(wakeupgen_base);
504 /* Clear all IRQ bitmasks at wakeupGen level */
505 for (i = 0; i < irq_banks; i++) {
506 wakeupgen_writel(0, i, CPU0_ID);
507 if (!soc_is_am43xx())
508 wakeupgen_writel(0, i, CPU1_ID);
512 * FIXME: Add support to set_smp_affinity() once the core
513 * GIC code has necessary hooks in place.
516 /* Associate all the IRQs to boot CPU like GIC init does. */
517 for (i = 0; i < max_irqs; i++)
518 irq_target_cpu[i] = boot_cpu;
521 * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
522 * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
523 * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
525 * This needs to be set one time thanks to always ON domain.
527 * We do not support ES1 behavior anymore. OMAP5 is assumed to be
528 * ES2.0, and the same is applicable for DRA7.
530 if (soc_is_omap54xx() || soc_is_dra7xx()) {
531 val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
533 omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
541 IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);