arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * XXX handle crossbar/shared link difference for L3?
  13  * XXX these should be marked initdata for multi-OMAP kernels
  14  */
  15
  16 #include <linux/i2c-omap.h>
  17 #include <linux/platform_data/spi-omap2-mcspi.h>
  18 #include <linux/omap-dma.h>
  19 #include <linux/platform_data/mailbox-omap.h>
  20 #include <plat/dmtimer.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "l3_2xxx.h"
  24 #include "l4_2xxx.h"
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "i2c.h"
  31 #include "mmc.h"
  32 #include "serial.h"
  33 #include "wd_timer.h"
  34
  35 /*
  36  * OMAP2420 hardware module integration data
  37  *
  38  * All of the data in this section should be autogeneratable from the
  39  * TI hardware database or other technical documentation.  Data that
  40  * is driver-specific or driver-kernel integration-specific belongs
  41  * elsewhere.
  42  */
  43
  44 /*
  45  * IP blocks
  46  */
  47
  48 /* IVA1 (IVA1) */
  49 static struct omap_hwmod_class iva1_hwmod_class = {
  50         .name           = "iva1",
  51 };
  52
  53 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
  54         { .name = "iva", .rst_shift = 8 },
  55 };
  56
  57 static struct omap_hwmod omap2420_iva_hwmod = {
  58         .name           = "iva",
  59         .class          = &iva1_hwmod_class,
  60         .clkdm_name     = "iva1_clkdm",
  61         .rst_lines      = omap2420_iva_resets,
  62         .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
  63         .main_clk       = "iva1_ifck",
  64 };
  65
  66 /* DSP */
  67 static struct omap_hwmod_class dsp_hwmod_class = {
  68         .name           = "dsp",
  69 };
  70
  71 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
  72         { .name = "logic", .rst_shift = 0 },
  73         { .name = "mmu", .rst_shift = 1 },
  74 };
  75
  76 static struct omap_hwmod omap2420_dsp_hwmod = {
  77         .name           = "dsp",
  78         .class          = &dsp_hwmod_class,
  79         .clkdm_name     = "dsp_clkdm",
  80         .rst_lines      = omap2420_dsp_resets,
  81         .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
  82         .main_clk       = "dsp_fck",
  83 };
  84
  85 /* I2C common */
  86 static struct omap_hwmod_class_sysconfig i2c_sysc = {
  87         .rev_offs       = 0x00,
  88         .sysc_offs      = 0x20,
  89         .syss_offs      = 0x10,
  90         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  91         .sysc_fields    = &omap_hwmod_sysc_type1,
  92 };
  93
  94 static struct omap_hwmod_class i2c_class = {
  95         .name           = "i2c",
  96         .sysc           = &i2c_sysc,
  97         .rev            = OMAP_I2C_IP_VERSION_1,
  98         .reset          = &omap_i2c_reset,
  99 };
 100
 101 static struct omap_i2c_dev_attr i2c_dev_attr = {
 102         .flags          = OMAP_I2C_FLAG_NO_FIFO |
 103                           OMAP_I2C_FLAG_SIMPLE_CLOCK |
 104                           OMAP_I2C_FLAG_16BIT_DATA_REG |
 105                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 106 };
 107
 108 /* I2C1 */
 109 static struct omap_hwmod omap2420_i2c1_hwmod = {
 110         .name           = "i2c1",
 111         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 112         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 113         .main_clk       = "i2c1_fck",
 114         .prcm           = {
 115                 .omap2 = {
 116                         .module_offs = CORE_MOD,
 117                         .prcm_reg_id = 1,
 118                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
 119                         .idlest_reg_id = 1,
 120                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
 121                 },
 122         },
 123         .class          = &i2c_class,
 124         .dev_attr       = &i2c_dev_attr,
 125         /*
 126          * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
 127          * while a transfer is active seems to cause the I2C block to
 128          * timeout. Why? Good question."
 129          */
 130         .flags          = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
 131 };
 132
 133 /* I2C2 */
 134 static struct omap_hwmod omap2420_i2c2_hwmod = {
 135         .name           = "i2c2",
 136         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 137         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 138         .main_clk       = "i2c2_fck",
 139         .prcm           = {
 140                 .omap2 = {
 141                         .module_offs = CORE_MOD,
 142                         .prcm_reg_id = 1,
 143                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
 144                         .idlest_reg_id = 1,
 145                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
 146                 },
 147         },
 148         .class          = &i2c_class,
 149         .dev_attr       = &i2c_dev_attr,
 150         .flags          = HWMOD_16BIT_REG,
 151 };
 152
 153 /* dma attributes */
 154 static struct omap_dma_dev_attr dma_dev_attr = {
 155         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 156                                                 IS_CSSA_32 | IS_CDSA_32,
 157         .lch_count = 32,
 158 };
 159
 160 static struct omap_hwmod omap2420_dma_system_hwmod = {
 161         .name           = "dma",
 162         .class          = &omap2xxx_dma_hwmod_class,
 163         .mpu_irqs       = omap2_dma_system_irqs,
 164         .main_clk       = "core_l3_ck",
 165         .dev_attr       = &dma_dev_attr,
 166         .flags          = HWMOD_NO_IDLEST,
 167 };
 168
 169 /* mailbox */
 170 static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
 171         { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
 172         { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
 173 };
 174
 175 static struct omap_mbox_pdata omap2420_mailbox_attrs = {
 176         .num_users      = 4,
 177         .num_fifos      = 6,
 178         .info_cnt       = ARRAY_SIZE(omap2420_mailbox_info),
 179         .info           = omap2420_mailbox_info,
 180 };
 181
 182 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
 183         { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
 184         { .name = "iva", .irq = 34 + OMAP_INTC_START, },
 185         { .irq = -1 },
 186 };
 187
 188 static struct omap_hwmod omap2420_mailbox_hwmod = {
 189         .name           = "mailbox",
 190         .class          = &omap2xxx_mailbox_hwmod_class,
 191         .mpu_irqs       = omap2420_mailbox_irqs,
 192         .main_clk       = "mailboxes_ick",
 193         .prcm           = {
 194                 .omap2 = {
 195                         .prcm_reg_id = 1,
 196                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
 197                         .module_offs = CORE_MOD,
 198                         .idlest_reg_id = 1,
 199                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 200                 },
 201         },
 202         .dev_attr       = &omap2420_mailbox_attrs,
 203 };
 204
 205 /*
 206  * 'mcbsp' class
 207  * multi channel buffered serial port controller
 208  */
 209
 210 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
 211         .name = "mcbsp",
 212 };
 213
 214 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 215         { .role = "pad_fck", .clk = "mcbsp_clks" },
 216         { .role = "prcm_fck", .clk = "func_96m_ck" },
 217 };
 218
 219 /* mcbsp1 */
 220 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
 221         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
 222         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
 223         { .irq = -1 },
 224 };
 225
 226 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 227         .name           = "mcbsp1",
 228         .class          = &omap2420_mcbsp_hwmod_class,
 229         .mpu_irqs       = omap2420_mcbsp1_irqs,
 230         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
 231         .main_clk       = "mcbsp1_fck",
 232         .prcm           = {
 233                 .omap2 = {
 234                         .prcm_reg_id = 1,
 235                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
 236                         .module_offs = CORE_MOD,
 237                         .idlest_reg_id = 1,
 238                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
 239                 },
 240         },
 241         .opt_clks       = mcbsp_opt_clks,
 242         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 243 };
 244
 245 /* mcbsp2 */
 246 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
 247         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
 248         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
 249         { .irq = -1 },
 250 };
 251
 252 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 253         .name           = "mcbsp2",
 254         .class          = &omap2420_mcbsp_hwmod_class,
 255         .mpu_irqs       = omap2420_mcbsp2_irqs,
 256         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
 257         .main_clk       = "mcbsp2_fck",
 258         .prcm           = {
 259                 .omap2 = {
 260                         .prcm_reg_id = 1,
 261                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
 262                         .module_offs = CORE_MOD,
 263                         .idlest_reg_id = 1,
 264                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
 265                 },
 266         },
 267         .opt_clks       = mcbsp_opt_clks,
 268         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 269 };
 270
 271 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
 272         .rev_offs       = 0x3c,
 273         .sysc_offs      = 0x64,
 274         .syss_offs      = 0x68,
 275         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 276         .sysc_fields    = &omap_hwmod_sysc_type1,
 277 };
 278
 279 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 280         .name   = "msdi",
 281         .sysc   = &omap2420_msdi_sysc,
 282         .reset  = &omap_msdi_reset,
 283 };
 284
 285 /* msdi1 */
 286 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
 287         { .irq = 83 + OMAP_INTC_START, },
 288         { .irq = -1 },
 289 };
 290
 291 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
 292         { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
 293         { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
 294         { .dma_req = -1 }
 295 };
 296
 297 static struct omap_hwmod omap2420_msdi1_hwmod = {
 298         .name           = "msdi1",
 299         .class          = &omap2420_msdi_hwmod_class,
 300         .mpu_irqs       = omap2420_msdi1_irqs,
 301         .sdma_reqs      = omap2420_msdi1_sdma_reqs,
 302         .main_clk       = "mmc_fck",
 303         .prcm           = {
 304                 .omap2 = {
 305                         .prcm_reg_id = 1,
 306                         .module_bit = OMAP2420_EN_MMC_SHIFT,
 307                         .module_offs = CORE_MOD,
 308                         .idlest_reg_id = 1,
 309                         .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
 310                 },
 311         },
 312         .flags          = HWMOD_16BIT_REG,
 313 };
 314
 315 /* HDQ1W/1-wire */
 316 static struct omap_hwmod omap2420_hdq1w_hwmod = {
 317         .name           = "hdq1w",
 318         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
 319         .main_clk       = "hdq_fck",
 320         .prcm           = {
 321                 .omap2 = {
 322                         .module_offs = CORE_MOD,
 323                         .prcm_reg_id = 1,
 324                         .module_bit = OMAP24XX_EN_HDQ_SHIFT,
 325                         .idlest_reg_id = 1,
 326                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
 327                 },
 328         },
 329         .class          = &omap2_hdq1w_class,
 330 };
 331
 332 /*
 333  * interfaces
 334  */
 335
 336 /* L4 CORE -> I2C1 interface */
 337 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 338         .master         = &omap2xxx_l4_core_hwmod,
 339         .slave          = &omap2420_i2c1_hwmod,
 340         .clk            = "i2c1_ick",
 341         .addr           = omap2_i2c1_addr_space,
 342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 343 };
 344
 345 /* L4 CORE -> I2C2 interface */
 346 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 347         .master         = &omap2xxx_l4_core_hwmod,
 348         .slave          = &omap2420_i2c2_hwmod,
 349         .clk            = "i2c2_ick",
 350         .addr           = omap2_i2c2_addr_space,
 351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 352 };
 353
 354 /* IVA <- L3 interface */
 355 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 356         .master         = &omap2xxx_l3_main_hwmod,
 357         .slave          = &omap2420_iva_hwmod,
 358         .clk            = "core_l3_ck",
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 /* DSP <- L3 interface */
 363 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
 364         .master         = &omap2xxx_l3_main_hwmod,
 365         .slave          = &omap2420_dsp_hwmod,
 366         .clk            = "dsp_ick",
 367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 368 };
 369
 370 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 371         {
 372                 .pa_start       = 0x48028000,
 373                 .pa_end         = 0x48028000 + SZ_1K - 1,
 374                 .flags          = ADDR_TYPE_RT
 375         },
 376         { }
 377 };
 378
 379 /* l4_wkup -> timer1 */
 380 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 381         .master         = &omap2xxx_l4_wkup_hwmod,
 382         .slave          = &omap2xxx_timer1_hwmod,
 383         .clk            = "gpt1_ick",
 384         .addr           = omap2420_timer1_addrs,
 385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 386 };
 387
 388 /* l4_wkup -> wd_timer2 */
 389 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 390         {
 391                 .pa_start       = 0x48022000,
 392                 .pa_end         = 0x4802207f,
 393                 .flags          = ADDR_TYPE_RT
 394         },
 395         { }
 396 };
 397
 398 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 399         .master         = &omap2xxx_l4_wkup_hwmod,
 400         .slave          = &omap2xxx_wd_timer2_hwmod,
 401         .clk            = "mpu_wdt_ick",
 402         .addr           = omap2420_wd_timer2_addrs,
 403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 404 };
 405
 406 /* l4_wkup -> gpio1 */
 407 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 408         {
 409                 .pa_start       = 0x48018000,
 410                 .pa_end         = 0x480181ff,
 411                 .flags          = ADDR_TYPE_RT
 412         },
 413         { }
 414 };
 415
 416 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
 417         .master         = &omap2xxx_l4_wkup_hwmod,
 418         .slave          = &omap2xxx_gpio1_hwmod,
 419         .clk            = "gpios_ick",
 420         .addr           = omap2420_gpio1_addr_space,
 421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 422 };
 423
 424 /* l4_wkup -> gpio2 */
 425 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
 426         {
 427                 .pa_start       = 0x4801a000,
 428                 .pa_end         = 0x4801a1ff,
 429                 .flags          = ADDR_TYPE_RT
 430         },
 431         { }
 432 };
 433
 434 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
 435         .master         = &omap2xxx_l4_wkup_hwmod,
 436         .slave          = &omap2xxx_gpio2_hwmod,
 437         .clk            = "gpios_ick",
 438         .addr           = omap2420_gpio2_addr_space,
 439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 440 };
 441
 442 /* l4_wkup -> gpio3 */
 443 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
 444         {
 445                 .pa_start       = 0x4801c000,
 446                 .pa_end         = 0x4801c1ff,
 447                 .flags          = ADDR_TYPE_RT
 448         },
 449         { }
 450 };
 451
 452 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
 453         .master         = &omap2xxx_l4_wkup_hwmod,
 454         .slave          = &omap2xxx_gpio3_hwmod,
 455         .clk            = "gpios_ick",
 456         .addr           = omap2420_gpio3_addr_space,
 457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 458 };
 459
 460 /* l4_wkup -> gpio4 */
 461 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
 462         {
 463                 .pa_start       = 0x4801e000,
 464                 .pa_end         = 0x4801e1ff,
 465                 .flags          = ADDR_TYPE_RT
 466         },
 467         { }
 468 };
 469
 470 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 471         .master         = &omap2xxx_l4_wkup_hwmod,
 472         .slave          = &omap2xxx_gpio4_hwmod,
 473         .clk            = "gpios_ick",
 474         .addr           = omap2420_gpio4_addr_space,
 475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 476 };
 477
 478 /* dma_system -> L3 */
 479 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
 480         .master         = &omap2420_dma_system_hwmod,
 481         .slave          = &omap2xxx_l3_main_hwmod,
 482         .clk            = "core_l3_ck",
 483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 484 };
 485
 486 /* l4_core -> dma_system */
 487 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 488         .master         = &omap2xxx_l4_core_hwmod,
 489         .slave          = &omap2420_dma_system_hwmod,
 490         .clk            = "sdma_ick",
 491         .addr           = omap2_dma_system_addrs,
 492         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 493 };
 494
 495 /* l4_core -> mailbox */
 496 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
 497         .master         = &omap2xxx_l4_core_hwmod,
 498         .slave          = &omap2420_mailbox_hwmod,
 499         .addr           = omap2_mailbox_addrs,
 500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 501 };
 502
 503 /* l4_core -> mcbsp1 */
 504 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
 505         .master         = &omap2xxx_l4_core_hwmod,
 506         .slave          = &omap2420_mcbsp1_hwmod,
 507         .clk            = "mcbsp1_ick",
 508         .addr           = omap2_mcbsp1_addrs,
 509         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 510 };
 511
 512 /* l4_core -> mcbsp2 */
 513 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
 514         .master         = &omap2xxx_l4_core_hwmod,
 515         .slave          = &omap2420_mcbsp2_hwmod,
 516         .clk            = "mcbsp2_ick",
 517         .addr           = omap2xxx_mcbsp2_addrs,
 518         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 519 };
 520
 521 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
 522         {
 523                 .pa_start       = 0x4809c000,
 524                 .pa_end         = 0x4809c000 + SZ_128 - 1,
 525                 .flags          = ADDR_TYPE_RT,
 526         },
 527         { }
 528 };
 529
 530 /* l4_core -> msdi1 */
 531 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
 532         .master         = &omap2xxx_l4_core_hwmod,
 533         .slave          = &omap2420_msdi1_hwmod,
 534         .clk            = "mmc_ick",
 535         .addr           = omap2420_msdi1_addrs,
 536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 537 };
 538
 539 /* l4_core -> hdq1w interface */
 540 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
 541         .master         = &omap2xxx_l4_core_hwmod,
 542         .slave          = &omap2420_hdq1w_hwmod,
 543         .clk            = "hdq_ick",
 544         .addr           = omap2_hdq1w_addr_space,
 545         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 546         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 547 };
 548
 549
 550 /* l4_wkup -> 32ksync_counter */
 551 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
 552         {
 553                 .pa_start       = 0x48004000,
 554                 .pa_end         = 0x4800401f,
 555                 .flags          = ADDR_TYPE_RT
 556         },
 557         { }
 558 };
 559
 560 static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
 561         {
 562                 .pa_start       = 0x6800a000,
 563                 .pa_end         = 0x6800afff,
 564                 .flags          = ADDR_TYPE_RT
 565         },
 566         { }
 567 };
 568
 569 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
 570         .master         = &omap2xxx_l4_wkup_hwmod,
 571         .slave          = &omap2xxx_counter_32k_hwmod,
 572         .clk            = "sync_32k_ick",
 573         .addr           = omap2420_counter_32k_addrs,
 574         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 575 };
 576
 577 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
 578         .master         = &omap2xxx_l3_main_hwmod,
 579         .slave          = &omap2xxx_gpmc_hwmod,
 580         .clk            = "core_l3_ck",
 581         .addr           = omap2420_gpmc_addrs,
 582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 583 };
 584
 585 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 586         &omap2xxx_l3_main__l4_core,
 587         &omap2xxx_mpu__l3_main,
 588         &omap2xxx_dss__l3,
 589         &omap2xxx_l4_core__mcspi1,
 590         &omap2xxx_l4_core__mcspi2,
 591         &omap2xxx_l4_core__l4_wkup,
 592         &omap2_l4_core__uart1,
 593         &omap2_l4_core__uart2,
 594         &omap2_l4_core__uart3,
 595         &omap2420_l4_core__i2c1,
 596         &omap2420_l4_core__i2c2,
 597         &omap2420_l3__iva,
 598         &omap2420_l3__dsp,
 599         &omap2420_l4_wkup__timer1,
 600         &omap2xxx_l4_core__timer2,
 601         &omap2xxx_l4_core__timer3,
 602         &omap2xxx_l4_core__timer4,
 603         &omap2xxx_l4_core__timer5,
 604         &omap2xxx_l4_core__timer6,
 605         &omap2xxx_l4_core__timer7,
 606         &omap2xxx_l4_core__timer8,
 607         &omap2xxx_l4_core__timer9,
 608         &omap2xxx_l4_core__timer10,
 609         &omap2xxx_l4_core__timer11,
 610         &omap2xxx_l4_core__timer12,
 611         &omap2420_l4_wkup__wd_timer2,
 612         &omap2xxx_l4_core__dss,
 613         &omap2xxx_l4_core__dss_dispc,
 614         &omap2xxx_l4_core__dss_rfbi,
 615         &omap2xxx_l4_core__dss_venc,
 616         &omap2420_l4_wkup__gpio1,
 617         &omap2420_l4_wkup__gpio2,
 618         &omap2420_l4_wkup__gpio3,
 619         &omap2420_l4_wkup__gpio4,
 620         &omap2420_dma_system__l3,
 621         &omap2420_l4_core__dma_system,
 622         &omap2420_l4_core__mailbox,
 623         &omap2420_l4_core__mcbsp1,
 624         &omap2420_l4_core__mcbsp2,
 625         &omap2420_l4_core__msdi1,
 626         &omap2xxx_l4_core__rng,
 627         &omap2xxx_l4_core__sham,
 628         &omap2xxx_l4_core__aes,
 629         &omap2420_l4_core__hdq1w,
 630         &omap2420_l4_wkup__counter_32k,
 631         &omap2420_l3__gpmc,
 632         NULL,
 633 };
 634
 635 int __init omap2420_hwmod_init(void)
 636 {
 637         omap_hwmod_init();
 638         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 639 }