2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <linux/i2c-omap.h>
17 #include <linux/platform_data/asoc-ti-mcbsp.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include <linux/omap-dma.h>
20 #include <linux/platform_data/mailbox-omap.h>
21 #include <plat/dmtimer.h>
23 #include "omap_hwmod.h"
28 #include "omap_hwmod_common_data.h"
29 #include "prm-regbits-24xx.h"
30 #include "cm-regbits-24xx.h"
35 * OMAP2430 hardware module integration data
37 * All of the data in this section should be autogeneratable from the
38 * TI hardware database or other technical documentation. Data that
39 * is driver-specific or driver-kernel integration-specific belongs
48 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
49 { .name = "logic", .rst_shift = 0 },
50 { .name = "mmu", .rst_shift = 1 },
53 static struct omap_hwmod omap2430_iva_hwmod = {
55 .class = &iva_hwmod_class,
56 .clkdm_name = "dsp_clkdm",
57 .rst_lines = omap2430_iva_resets,
58 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
59 .main_clk = "dsp_fck",
63 static struct omap_hwmod_class_sysconfig i2c_sysc = {
67 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
68 SYSS_HAS_RESET_STATUS),
69 .sysc_fields = &omap_hwmod_sysc_type1,
72 static struct omap_hwmod_class i2c_class = {
75 .rev = OMAP_I2C_IP_VERSION_1,
76 .reset = &omap_i2c_reset,
79 static struct omap_i2c_dev_attr i2c_dev_attr = {
80 .fifo_depth = 8, /* bytes */
81 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
82 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
86 static struct omap_hwmod omap2430_i2c1_hwmod = {
88 .flags = HWMOD_16BIT_REG,
89 .mpu_irqs = omap2_i2c1_mpu_irqs,
90 .sdma_reqs = omap2_i2c1_sdma_reqs,
91 .main_clk = "i2chs1_fck",
95 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
96 * I2CHS IP's do not follow the usual pattern.
97 * prcm_reg_id alone cannot be used to program
98 * the iclk and fclk. Needs to be handled using
99 * additional flags when clk handling is moved
100 * to hwmod framework.
102 .module_offs = CORE_MOD,
104 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
106 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
110 .dev_attr = &i2c_dev_attr,
114 static struct omap_hwmod omap2430_i2c2_hwmod = {
116 .flags = HWMOD_16BIT_REG,
117 .mpu_irqs = omap2_i2c2_mpu_irqs,
118 .sdma_reqs = omap2_i2c2_sdma_reqs,
119 .main_clk = "i2chs2_fck",
122 .module_offs = CORE_MOD,
124 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
126 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
130 .dev_attr = &i2c_dev_attr,
134 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
135 { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
139 static struct omap_hwmod omap2430_gpio5_hwmod = {
141 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
142 .mpu_irqs = omap243x_gpio5_irqs,
143 .main_clk = "gpio5_fck",
147 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
148 .module_offs = CORE_MOD,
150 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
153 .class = &omap2xxx_gpio_hwmod_class,
154 .dev_attr = &omap2xxx_gpio_dev_attr,
158 static struct omap_dma_dev_attr dma_dev_attr = {
159 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
160 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
164 static struct omap_hwmod omap2430_dma_system_hwmod = {
166 .class = &omap2xxx_dma_hwmod_class,
167 .mpu_irqs = omap2_dma_system_irqs,
168 .main_clk = "core_l3_ck",
169 .dev_attr = &dma_dev_attr,
170 .flags = HWMOD_NO_IDLEST,
174 static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
175 { .name = "dsp", .tx_id = 0, .rx_id = 1 },
178 static struct omap_mbox_pdata omap2430_mailbox_attrs = {
181 .info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
182 .info = omap2430_mailbox_info,
185 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
186 { .irq = 26 + OMAP_INTC_START, },
190 static struct omap_hwmod omap2430_mailbox_hwmod = {
192 .class = &omap2xxx_mailbox_hwmod_class,
193 .mpu_irqs = omap2430_mailbox_irqs,
194 .main_clk = "mailboxes_ick",
198 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
199 .module_offs = CORE_MOD,
201 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
204 .dev_attr = &omap2430_mailbox_attrs,
208 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
209 { .irq = 91 + OMAP_INTC_START, },
213 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
214 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
215 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
216 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
217 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
221 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
225 static struct omap_hwmod omap2430_mcspi3_hwmod = {
227 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
228 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
229 .main_clk = "mcspi3_fck",
232 .module_offs = CORE_MOD,
234 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
236 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
239 .class = &omap2xxx_mcspi_class,
240 .dev_attr = &omap_mcspi3_dev_attr,
244 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
248 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
249 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
253 .sysc_fields = &omap_hwmod_sysc_type1,
256 static struct omap_hwmod_class usbotg_class = {
258 .sysc = &omap2430_usbhsotg_sysc,
262 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
264 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
265 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
269 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
270 .name = "usb_otg_hs",
271 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
272 .main_clk = "usbhs_ick",
276 .module_bit = OMAP2430_EN_USBHS_MASK,
277 .module_offs = CORE_MOD,
279 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
282 .class = &usbotg_class,
284 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
285 * broken when autoidle is enabled
286 * workaround is to disable the autoidle bit at module level.
288 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
289 | HWMOD_SWSUP_MSTANDBY,
294 * multi channel buffered serial port controller
297 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
300 .sysc_flags = (SYSC_HAS_SOFTRESET),
301 .sysc_fields = &omap_hwmod_sysc_type1,
304 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
306 .sysc = &omap2430_mcbsp_sysc,
307 .rev = MCBSP_CONFIG_TYPE2,
310 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
311 { .role = "pad_fck", .clk = "mcbsp_clks" },
312 { .role = "prcm_fck", .clk = "func_96m_ck" },
316 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
317 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
318 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
319 { .name = "ovr", .irq = 61 + OMAP_INTC_START, },
320 { .name = "common", .irq = 64 + OMAP_INTC_START, },
324 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
326 .class = &omap2430_mcbsp_hwmod_class,
327 .mpu_irqs = omap2430_mcbsp1_irqs,
328 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
329 .main_clk = "mcbsp1_fck",
333 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
334 .module_offs = CORE_MOD,
336 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
339 .opt_clks = mcbsp_opt_clks,
340 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
344 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
345 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
346 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
347 { .name = "common", .irq = 16 + OMAP_INTC_START, },
351 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
353 .class = &omap2430_mcbsp_hwmod_class,
354 .mpu_irqs = omap2430_mcbsp2_irqs,
355 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
356 .main_clk = "mcbsp2_fck",
360 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
361 .module_offs = CORE_MOD,
363 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
366 .opt_clks = mcbsp_opt_clks,
367 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
371 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
372 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
373 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
374 { .name = "common", .irq = 17 + OMAP_INTC_START, },
378 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
380 .class = &omap2430_mcbsp_hwmod_class,
381 .mpu_irqs = omap2430_mcbsp3_irqs,
382 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
383 .main_clk = "mcbsp3_fck",
387 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
388 .module_offs = CORE_MOD,
390 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
393 .opt_clks = mcbsp_opt_clks,
394 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
398 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
399 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
400 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
401 { .name = "common", .irq = 18 + OMAP_INTC_START, },
405 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
406 { .name = "rx", .dma_req = 20 },
407 { .name = "tx", .dma_req = 19 },
411 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
413 .class = &omap2430_mcbsp_hwmod_class,
414 .mpu_irqs = omap2430_mcbsp4_irqs,
415 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
416 .main_clk = "mcbsp4_fck",
420 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
421 .module_offs = CORE_MOD,
423 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
426 .opt_clks = mcbsp_opt_clks,
427 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
431 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
432 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
433 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
434 { .name = "common", .irq = 19 + OMAP_INTC_START, },
438 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
439 { .name = "rx", .dma_req = 22 },
440 { .name = "tx", .dma_req = 21 },
444 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
446 .class = &omap2430_mcbsp_hwmod_class,
447 .mpu_irqs = omap2430_mcbsp5_irqs,
448 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
449 .main_clk = "mcbsp5_fck",
453 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
454 .module_offs = CORE_MOD,
456 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
459 .opt_clks = mcbsp_opt_clks,
460 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
463 /* MMC/SD/SDIO common */
464 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
468 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
469 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
470 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
471 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
472 .sysc_fields = &omap_hwmod_sysc_type1,
475 static struct omap_hwmod_class omap2430_mmc_class = {
477 .sysc = &omap2430_mmc_sysc,
481 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
482 { .irq = 83 + OMAP_INTC_START, },
486 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
487 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
488 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
492 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
493 { .role = "dbck", .clk = "mmchsdb1_fck" },
496 static struct omap_mmc_dev_attr mmc1_dev_attr = {
497 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
500 static struct omap_hwmod omap2430_mmc1_hwmod = {
502 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
503 .mpu_irqs = omap2430_mmc1_mpu_irqs,
504 .sdma_reqs = omap2430_mmc1_sdma_reqs,
505 .opt_clks = omap2430_mmc1_opt_clks,
506 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
507 .main_clk = "mmchs1_fck",
510 .module_offs = CORE_MOD,
512 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
514 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
517 .dev_attr = &mmc1_dev_attr,
518 .class = &omap2430_mmc_class,
522 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
523 { .irq = 86 + OMAP_INTC_START, },
527 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
528 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
529 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
533 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
534 { .role = "dbck", .clk = "mmchsdb2_fck" },
537 static struct omap_hwmod omap2430_mmc2_hwmod = {
539 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
540 .mpu_irqs = omap2430_mmc2_mpu_irqs,
541 .sdma_reqs = omap2430_mmc2_sdma_reqs,
542 .opt_clks = omap2430_mmc2_opt_clks,
543 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
544 .main_clk = "mmchs2_fck",
547 .module_offs = CORE_MOD,
549 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
551 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
554 .class = &omap2430_mmc_class,
558 static struct omap_hwmod omap2430_hdq1w_hwmod = {
560 .mpu_irqs = omap2_hdq1w_mpu_irqs,
561 .main_clk = "hdq_fck",
564 .module_offs = CORE_MOD,
566 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
568 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
571 .class = &omap2_hdq1w_class,
578 /* L3 -> L4_CORE interface */
579 /* l3_core -> usbhsotg interface */
580 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
581 .master = &omap2430_usbhsotg_hwmod,
582 .slave = &omap2xxx_l3_main_hwmod,
584 .user = OCP_USER_MPU,
587 /* L4 CORE -> I2C1 interface */
588 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
589 .master = &omap2xxx_l4_core_hwmod,
590 .slave = &omap2430_i2c1_hwmod,
592 .addr = omap2_i2c1_addr_space,
593 .user = OCP_USER_MPU | OCP_USER_SDMA,
596 /* L4 CORE -> I2C2 interface */
597 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
598 .master = &omap2xxx_l4_core_hwmod,
599 .slave = &omap2430_i2c2_hwmod,
601 .addr = omap2_i2c2_addr_space,
602 .user = OCP_USER_MPU | OCP_USER_SDMA,
605 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
607 .pa_start = OMAP243X_HS_BASE,
608 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
609 .flags = ADDR_TYPE_RT
614 /* l4_core ->usbhsotg interface */
615 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
616 .master = &omap2xxx_l4_core_hwmod,
617 .slave = &omap2430_usbhsotg_hwmod,
619 .addr = omap2430_usbhsotg_addrs,
620 .user = OCP_USER_MPU,
623 /* L4 CORE -> MMC1 interface */
624 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
625 .master = &omap2xxx_l4_core_hwmod,
626 .slave = &omap2430_mmc1_hwmod,
628 .addr = omap2430_mmc1_addr_space,
629 .user = OCP_USER_MPU | OCP_USER_SDMA,
632 /* L4 CORE -> MMC2 interface */
633 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
634 .master = &omap2xxx_l4_core_hwmod,
635 .slave = &omap2430_mmc2_hwmod,
637 .addr = omap2430_mmc2_addr_space,
638 .user = OCP_USER_MPU | OCP_USER_SDMA,
641 /* l4 core -> mcspi3 interface */
642 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
643 .master = &omap2xxx_l4_core_hwmod,
644 .slave = &omap2430_mcspi3_hwmod,
646 .addr = omap2430_mcspi3_addr_space,
647 .user = OCP_USER_MPU | OCP_USER_SDMA,
650 /* IVA2 <- L3 interface */
651 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
652 .master = &omap2xxx_l3_main_hwmod,
653 .slave = &omap2430_iva_hwmod,
655 .user = OCP_USER_MPU | OCP_USER_SDMA,
658 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
660 .pa_start = 0x49018000,
661 .pa_end = 0x49018000 + SZ_1K - 1,
662 .flags = ADDR_TYPE_RT
667 /* l4_wkup -> timer1 */
668 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
669 .master = &omap2xxx_l4_wkup_hwmod,
670 .slave = &omap2xxx_timer1_hwmod,
672 .addr = omap2430_timer1_addrs,
673 .user = OCP_USER_MPU | OCP_USER_SDMA,
676 /* l4_wkup -> wd_timer2 */
677 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
679 .pa_start = 0x49016000,
680 .pa_end = 0x4901607f,
681 .flags = ADDR_TYPE_RT
686 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
687 .master = &omap2xxx_l4_wkup_hwmod,
688 .slave = &omap2xxx_wd_timer2_hwmod,
689 .clk = "mpu_wdt_ick",
690 .addr = omap2430_wd_timer2_addrs,
691 .user = OCP_USER_MPU | OCP_USER_SDMA,
694 /* l4_wkup -> gpio1 */
695 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
697 .pa_start = 0x4900C000,
698 .pa_end = 0x4900C1ff,
699 .flags = ADDR_TYPE_RT
704 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
705 .master = &omap2xxx_l4_wkup_hwmod,
706 .slave = &omap2xxx_gpio1_hwmod,
708 .addr = omap2430_gpio1_addr_space,
709 .user = OCP_USER_MPU | OCP_USER_SDMA,
712 /* l4_wkup -> gpio2 */
713 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
715 .pa_start = 0x4900E000,
716 .pa_end = 0x4900E1ff,
717 .flags = ADDR_TYPE_RT
722 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
723 .master = &omap2xxx_l4_wkup_hwmod,
724 .slave = &omap2xxx_gpio2_hwmod,
726 .addr = omap2430_gpio2_addr_space,
727 .user = OCP_USER_MPU | OCP_USER_SDMA,
730 /* l4_wkup -> gpio3 */
731 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
733 .pa_start = 0x49010000,
734 .pa_end = 0x490101ff,
735 .flags = ADDR_TYPE_RT
740 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
741 .master = &omap2xxx_l4_wkup_hwmod,
742 .slave = &omap2xxx_gpio3_hwmod,
744 .addr = omap2430_gpio3_addr_space,
745 .user = OCP_USER_MPU | OCP_USER_SDMA,
748 /* l4_wkup -> gpio4 */
749 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
751 .pa_start = 0x49012000,
752 .pa_end = 0x490121ff,
753 .flags = ADDR_TYPE_RT
758 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
759 .master = &omap2xxx_l4_wkup_hwmod,
760 .slave = &omap2xxx_gpio4_hwmod,
762 .addr = omap2430_gpio4_addr_space,
763 .user = OCP_USER_MPU | OCP_USER_SDMA,
766 /* l4_core -> gpio5 */
767 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
769 .pa_start = 0x480B6000,
770 .pa_end = 0x480B61ff,
771 .flags = ADDR_TYPE_RT
776 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
777 .master = &omap2xxx_l4_core_hwmod,
778 .slave = &omap2430_gpio5_hwmod,
780 .addr = omap2430_gpio5_addr_space,
781 .user = OCP_USER_MPU | OCP_USER_SDMA,
784 /* dma_system -> L3 */
785 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
786 .master = &omap2430_dma_system_hwmod,
787 .slave = &omap2xxx_l3_main_hwmod,
789 .user = OCP_USER_MPU | OCP_USER_SDMA,
792 /* l4_core -> dma_system */
793 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
794 .master = &omap2xxx_l4_core_hwmod,
795 .slave = &omap2430_dma_system_hwmod,
797 .addr = omap2_dma_system_addrs,
798 .user = OCP_USER_MPU | OCP_USER_SDMA,
801 /* l4_core -> mailbox */
802 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
803 .master = &omap2xxx_l4_core_hwmod,
804 .slave = &omap2430_mailbox_hwmod,
805 .addr = omap2_mailbox_addrs,
806 .user = OCP_USER_MPU | OCP_USER_SDMA,
809 /* l4_core -> mcbsp1 */
810 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
811 .master = &omap2xxx_l4_core_hwmod,
812 .slave = &omap2430_mcbsp1_hwmod,
814 .addr = omap2_mcbsp1_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA,
818 /* l4_core -> mcbsp2 */
819 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
820 .master = &omap2xxx_l4_core_hwmod,
821 .slave = &omap2430_mcbsp2_hwmod,
823 .addr = omap2xxx_mcbsp2_addrs,
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
827 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
830 .pa_start = 0x4808C000,
831 .pa_end = 0x4808C0ff,
832 .flags = ADDR_TYPE_RT
837 /* l4_core -> mcbsp3 */
838 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
839 .master = &omap2xxx_l4_core_hwmod,
840 .slave = &omap2430_mcbsp3_hwmod,
842 .addr = omap2430_mcbsp3_addrs,
843 .user = OCP_USER_MPU | OCP_USER_SDMA,
846 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
849 .pa_start = 0x4808E000,
850 .pa_end = 0x4808E0ff,
851 .flags = ADDR_TYPE_RT
856 /* l4_core -> mcbsp4 */
857 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
858 .master = &omap2xxx_l4_core_hwmod,
859 .slave = &omap2430_mcbsp4_hwmod,
861 .addr = omap2430_mcbsp4_addrs,
862 .user = OCP_USER_MPU | OCP_USER_SDMA,
865 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
868 .pa_start = 0x48096000,
869 .pa_end = 0x480960ff,
870 .flags = ADDR_TYPE_RT
875 /* l4_core -> mcbsp5 */
876 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
877 .master = &omap2xxx_l4_core_hwmod,
878 .slave = &omap2430_mcbsp5_hwmod,
880 .addr = omap2430_mcbsp5_addrs,
881 .user = OCP_USER_MPU | OCP_USER_SDMA,
884 /* l4_core -> hdq1w */
885 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
886 .master = &omap2xxx_l4_core_hwmod,
887 .slave = &omap2430_hdq1w_hwmod,
889 .addr = omap2_hdq1w_addr_space,
890 .user = OCP_USER_MPU | OCP_USER_SDMA,
891 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
894 /* l4_wkup -> 32ksync_counter */
895 static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
897 .pa_start = 0x49020000,
898 .pa_end = 0x4902001f,
899 .flags = ADDR_TYPE_RT
904 static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
906 .pa_start = 0x6e000000,
907 .pa_end = 0x6e000fff,
908 .flags = ADDR_TYPE_RT
913 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
914 .master = &omap2xxx_l4_wkup_hwmod,
915 .slave = &omap2xxx_counter_32k_hwmod,
916 .clk = "sync_32k_ick",
917 .addr = omap2430_counter_32k_addrs,
918 .user = OCP_USER_MPU | OCP_USER_SDMA,
921 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
922 .master = &omap2xxx_l3_main_hwmod,
923 .slave = &omap2xxx_gpmc_hwmod,
925 .addr = omap2430_gpmc_addrs,
926 .user = OCP_USER_MPU | OCP_USER_SDMA,
929 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
930 &omap2xxx_l3_main__l4_core,
931 &omap2xxx_mpu__l3_main,
933 &omap2430_usbhsotg__l3,
934 &omap2430_l4_core__i2c1,
935 &omap2430_l4_core__i2c2,
936 &omap2xxx_l4_core__l4_wkup,
937 &omap2_l4_core__uart1,
938 &omap2_l4_core__uart2,
939 &omap2_l4_core__uart3,
940 &omap2430_l4_core__usbhsotg,
941 &omap2430_l4_core__mmc1,
942 &omap2430_l4_core__mmc2,
943 &omap2xxx_l4_core__mcspi1,
944 &omap2xxx_l4_core__mcspi2,
945 &omap2430_l4_core__mcspi3,
947 &omap2430_l4_wkup__timer1,
948 &omap2xxx_l4_core__timer2,
949 &omap2xxx_l4_core__timer3,
950 &omap2xxx_l4_core__timer4,
951 &omap2xxx_l4_core__timer5,
952 &omap2xxx_l4_core__timer6,
953 &omap2xxx_l4_core__timer7,
954 &omap2xxx_l4_core__timer8,
955 &omap2xxx_l4_core__timer9,
956 &omap2xxx_l4_core__timer10,
957 &omap2xxx_l4_core__timer11,
958 &omap2xxx_l4_core__timer12,
959 &omap2430_l4_wkup__wd_timer2,
960 &omap2xxx_l4_core__dss,
961 &omap2xxx_l4_core__dss_dispc,
962 &omap2xxx_l4_core__dss_rfbi,
963 &omap2xxx_l4_core__dss_venc,
964 &omap2430_l4_wkup__gpio1,
965 &omap2430_l4_wkup__gpio2,
966 &omap2430_l4_wkup__gpio3,
967 &omap2430_l4_wkup__gpio4,
968 &omap2430_l4_core__gpio5,
969 &omap2430_dma_system__l3,
970 &omap2430_l4_core__dma_system,
971 &omap2430_l4_core__mailbox,
972 &omap2430_l4_core__mcbsp1,
973 &omap2430_l4_core__mcbsp2,
974 &omap2430_l4_core__mcbsp3,
975 &omap2430_l4_core__mcbsp4,
976 &omap2430_l4_core__mcbsp5,
977 &omap2430_l4_core__hdq1w,
978 &omap2xxx_l4_core__rng,
979 &omap2xxx_l4_core__sham,
980 &omap2xxx_l4_core__aes,
981 &omap2430_l4_wkup__counter_32k,
986 int __init omap2430_hwmod_init(void)
989 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);