arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21
  22 #include "omap_hwmod_common_data.h"
  23
  24 #include "prm-regbits-24xx.h"
  25 #include "cm-regbits-24xx.h"
  26
  27 /*
  28  * OMAP2430 hardware module integration data
  29  *
  30  * ALl of the data in this section should be autogeneratable from the
  31  * TI hardware database or other technical documentation.  Data that
  32  * is driver-specific or driver-kernel integration-specific belongs
  33  * elsewhere.
  34  */
  35
  36 static struct omap_hwmod omap2430_mpu_hwmod;
  37 static struct omap_hwmod omap2430_iva_hwmod;
  38 static struct omap_hwmod omap2430_l3_main_hwmod;
  39 static struct omap_hwmod omap2430_l4_core_hwmod;
  40 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  41 static struct omap_hwmod omap2430_gpio1_hwmod;
  42 static struct omap_hwmod omap2430_gpio2_hwmod;
  43 static struct omap_hwmod omap2430_gpio3_hwmod;
  44 static struct omap_hwmod omap2430_gpio4_hwmod;
  45 static struct omap_hwmod omap2430_gpio5_hwmod;
  46
  47 /* L3 -> L4_CORE interface */
  48 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  49         .master = &omap2430_l3_main_hwmod,
  50         .slave  = &omap2430_l4_core_hwmod,
  51         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  52 };
  53
  54 /* MPU -> L3 interface */
  55 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  56         .master = &omap2430_mpu_hwmod,
  57         .slave  = &omap2430_l3_main_hwmod,
  58         .user   = OCP_USER_MPU,
  59 };
  60
  61 /* Slave interfaces on the L3 interconnect */
  62 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  63         &omap2430_mpu__l3_main,
  64 };
  65
  66 /* Master interfaces on the L3 interconnect */
  67 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
  68         &omap2430_l3_main__l4_core,
  69 };
  70
  71 /* L3 */
  72 static struct omap_hwmod omap2430_l3_main_hwmod = {
  73         .name           = "l3_main",
  74         .class          = &l3_hwmod_class,
  75         .masters        = omap2430_l3_main_masters,
  76         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
  77         .slaves         = omap2430_l3_main_slaves,
  78         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
  79         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
  80         .flags          = HWMOD_NO_IDLEST,
  81 };
  82
  83 static struct omap_hwmod omap2430_l4_wkup_hwmod;
  84 static struct omap_hwmod omap2430_uart1_hwmod;
  85 static struct omap_hwmod omap2430_uart2_hwmod;
  86 static struct omap_hwmod omap2430_uart3_hwmod;
  87 static struct omap_hwmod omap2430_i2c1_hwmod;
  88 static struct omap_hwmod omap2430_i2c2_hwmod;
  89
  90 /* I2C IP block address space length (in bytes) */
  91 #define OMAP2_I2C_AS_LEN                128
  92
  93 /* L4 CORE -> I2C1 interface */
  94 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
  95         {
  96                 .pa_start       = 0x48070000,
  97                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
  98                 .flags          = ADDR_TYPE_RT,
  99         },
 100 };
 101
 102 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 103         .master         = &omap2430_l4_core_hwmod,
 104         .slave          = &omap2430_i2c1_hwmod,
 105         .clk            = "i2c1_ick",
 106         .addr           = omap2430_i2c1_addr_space,
 107         .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
 108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 109 };
 110
 111 /* L4 CORE -> I2C2 interface */
 112 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
 113         {
 114                 .pa_start       = 0x48072000,
 115                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 116                 .flags          = ADDR_TYPE_RT,
 117         },
 118 };
 119
 120 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 121         .master         = &omap2430_l4_core_hwmod,
 122         .slave          = &omap2430_i2c2_hwmod,
 123         .clk            = "i2c2_ick",
 124         .addr           = omap2430_i2c2_addr_space,
 125         .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
 126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 127 };
 128
 129 /* L4_CORE -> L4_WKUP interface */
 130 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 131         .master = &omap2430_l4_core_hwmod,
 132         .slave  = &omap2430_l4_wkup_hwmod,
 133         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 134 };
 135
 136 /* L4 CORE -> UART1 interface */
 137 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
 138         {
 139                 .pa_start       = OMAP2_UART1_BASE,
 140                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 141                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 142         },
 143 };
 144
 145 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 146         .master         = &omap2430_l4_core_hwmod,
 147         .slave          = &omap2430_uart1_hwmod,
 148         .clk            = "uart1_ick",
 149         .addr           = omap2430_uart1_addr_space,
 150         .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
 151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 152 };
 153
 154 /* L4 CORE -> UART2 interface */
 155 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
 156         {
 157                 .pa_start       = OMAP2_UART2_BASE,
 158                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 159                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 160         },
 161 };
 162
 163 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 164         .master         = &omap2430_l4_core_hwmod,
 165         .slave          = &omap2430_uart2_hwmod,
 166         .clk            = "uart2_ick",
 167         .addr           = omap2430_uart2_addr_space,
 168         .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
 169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 170 };
 171
 172 /* L4 PER -> UART3 interface */
 173 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
 174         {
 175                 .pa_start       = OMAP2_UART3_BASE,
 176                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 177                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 178         },
 179 };
 180
 181 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 182         .master         = &omap2430_l4_core_hwmod,
 183         .slave          = &omap2430_uart3_hwmod,
 184         .clk            = "uart3_ick",
 185         .addr           = omap2430_uart3_addr_space,
 186         .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
 187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 188 };
 189
 190 /* Slave interfaces on the L4_CORE interconnect */
 191 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 192         &omap2430_l3_main__l4_core,
 193 };
 194
 195 /* Master interfaces on the L4_CORE interconnect */
 196 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 197         &omap2430_l4_core__l4_wkup,
 198 };
 199
 200 /* L4 CORE */
 201 static struct omap_hwmod omap2430_l4_core_hwmod = {
 202         .name           = "l4_core",
 203         .class          = &l4_hwmod_class,
 204         .masters        = omap2430_l4_core_masters,
 205         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 206         .slaves         = omap2430_l4_core_slaves,
 207         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 208         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 209         .flags          = HWMOD_NO_IDLEST,
 210 };
 211
 212 /* Slave interfaces on the L4_WKUP interconnect */
 213 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 214         &omap2430_l4_core__l4_wkup,
 215         &omap2_l4_core__uart1,
 216         &omap2_l4_core__uart2,
 217         &omap2_l4_core__uart3,
 218 };
 219
 220 /* Master interfaces on the L4_WKUP interconnect */
 221 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 222 };
 223
 224 /* L4 WKUP */
 225 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 226         .name           = "l4_wkup",
 227         .class          = &l4_hwmod_class,
 228         .masters        = omap2430_l4_wkup_masters,
 229         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 230         .slaves         = omap2430_l4_wkup_slaves,
 231         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 232         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 233         .flags          = HWMOD_NO_IDLEST,
 234 };
 235
 236 /* Master interfaces on the MPU device */
 237 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 238         &omap2430_mpu__l3_main,
 239 };
 240
 241 /* MPU */
 242 static struct omap_hwmod omap2430_mpu_hwmod = {
 243         .name           = "mpu",
 244         .class          = &mpu_hwmod_class,
 245         .main_clk       = "mpu_ck",
 246         .masters        = omap2430_mpu_masters,
 247         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 248         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 249 };
 250
 251 /*
 252  * IVA2_1 interface data
 253  */
 254
 255 /* IVA2 <- L3 interface */
 256 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 257         .master         = &omap2430_l3_main_hwmod,
 258         .slave          = &omap2430_iva_hwmod,
 259         .clk            = "dsp_fck",
 260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 261 };
 262
 263 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 264         &omap2430_l3__iva,
 265 };
 266
 267 /*
 268  * IVA2 (IVA2)
 269  */
 270
 271 static struct omap_hwmod omap2430_iva_hwmod = {
 272         .name           = "iva",
 273         .class          = &iva_hwmod_class,
 274         .masters        = omap2430_iva_masters,
 275         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 276         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 277 };
 278
 279 /* l4_wkup -> wd_timer2 */
 280 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 281         {
 282                 .pa_start       = 0x49016000,
 283                 .pa_end         = 0x4901607f,
 284                 .flags          = ADDR_TYPE_RT
 285         },
 286 };
 287
 288 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 289         .master         = &omap2430_l4_wkup_hwmod,
 290         .slave          = &omap2430_wd_timer2_hwmod,
 291         .clk            = "mpu_wdt_ick",
 292         .addr           = omap2430_wd_timer2_addrs,
 293         .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
 294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 295 };
 296
 297 /*
 298  * 'wd_timer' class
 299  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 300  * overflow condition
 301  */
 302
 303 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
 304         .rev_offs       = 0x0,
 305         .sysc_offs      = 0x0010,
 306         .syss_offs      = 0x0014,
 307         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 308                            SYSC_HAS_AUTOIDLE),
 309         .sysc_fields    = &omap_hwmod_sysc_type1,
 310 };
 311
 312 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
 313         .name = "wd_timer",
 314         .sysc = &omap2430_wd_timer_sysc,
 315 };
 316
 317 /* wd_timer2 */
 318 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 319         &omap2430_l4_wkup__wd_timer2,
 320 };
 321
 322 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
 323         .name           = "wd_timer2",
 324         .class          = &omap2430_wd_timer_hwmod_class,
 325         .main_clk       = "mpu_wdt_fck",
 326         .prcm           = {
 327                 .omap2 = {
 328                         .prcm_reg_id = 1,
 329                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 330                         .module_offs = WKUP_MOD,
 331                         .idlest_reg_id = 1,
 332                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 333                 },
 334         },
 335         .slaves         = omap2430_wd_timer2_slaves,
 336         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
 337         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 338 };
 339
 340 /* UART */
 341
 342 static struct omap_hwmod_class_sysconfig uart_sysc = {
 343         .rev_offs       = 0x50,
 344         .sysc_offs      = 0x54,
 345         .syss_offs      = 0x58,
 346         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 347                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 348                            SYSC_HAS_AUTOIDLE),
 349         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 350         .sysc_fields    = &omap_hwmod_sysc_type1,
 351 };
 352
 353 static struct omap_hwmod_class uart_class = {
 354         .name = "uart",
 355         .sysc = &uart_sysc,
 356 };
 357
 358 /* UART1 */
 359
 360 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 361         { .irq = INT_24XX_UART1_IRQ, },
 362 };
 363
 364 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 365         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 366         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 367 };
 368
 369 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
 370         &omap2_l4_core__uart1,
 371 };
 372
 373 static struct omap_hwmod omap2430_uart1_hwmod = {
 374         .name           = "uart1",
 375         .mpu_irqs       = uart1_mpu_irqs,
 376         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 377         .sdma_reqs      = uart1_sdma_reqs,
 378         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 379         .main_clk       = "uart1_fck",
 380         .prcm           = {
 381                 .omap2 = {
 382                         .module_offs = CORE_MOD,
 383                         .prcm_reg_id = 1,
 384                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 385                         .idlest_reg_id = 1,
 386                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 387                 },
 388         },
 389         .slaves         = omap2430_uart1_slaves,
 390         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
 391         .class          = &uart_class,
 392         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 393 };
 394
 395 /* UART2 */
 396
 397 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 398         { .irq = INT_24XX_UART2_IRQ, },
 399 };
 400
 401 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 402         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 403         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 404 };
 405
 406 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
 407         &omap2_l4_core__uart2,
 408 };
 409
 410 static struct omap_hwmod omap2430_uart2_hwmod = {
 411         .name           = "uart2",
 412         .mpu_irqs       = uart2_mpu_irqs,
 413         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 414         .sdma_reqs      = uart2_sdma_reqs,
 415         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 416         .main_clk       = "uart2_fck",
 417         .prcm           = {
 418                 .omap2 = {
 419                         .module_offs = CORE_MOD,
 420                         .prcm_reg_id = 1,
 421                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 422                         .idlest_reg_id = 1,
 423                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 424                 },
 425         },
 426         .slaves         = omap2430_uart2_slaves,
 427         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
 428         .class          = &uart_class,
 429         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 430 };
 431
 432 /* UART3 */
 433
 434 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 435         { .irq = INT_24XX_UART3_IRQ, },
 436 };
 437
 438 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 439         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 440         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 441 };
 442
 443 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
 444         &omap2_l4_core__uart3,
 445 };
 446
 447 static struct omap_hwmod omap2430_uart3_hwmod = {
 448         .name           = "uart3",
 449         .mpu_irqs       = uart3_mpu_irqs,
 450         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 451         .sdma_reqs      = uart3_sdma_reqs,
 452         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 453         .main_clk       = "uart3_fck",
 454         .prcm           = {
 455                 .omap2 = {
 456                         .module_offs = CORE_MOD,
 457                         .prcm_reg_id = 2,
 458                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 459                         .idlest_reg_id = 2,
 460                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 461                 },
 462         },
 463         .slaves         = omap2430_uart3_slaves,
 464         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
 465         .class          = &uart_class,
 466         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 467 };
 468
 469 /* I2C common */
 470 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 471         .rev_offs       = 0x00,
 472         .sysc_offs      = 0x20,
 473         .syss_offs      = 0x10,
 474         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 475         .sysc_fields    = &omap_hwmod_sysc_type1,
 476 };
 477
 478 static struct omap_hwmod_class i2c_class = {
 479         .name           = "i2c",
 480         .sysc           = &i2c_sysc,
 481 };
 482
 483 static struct omap_i2c_dev_attr i2c_dev_attr;
 484
 485 /* I2C1 */
 486
 487 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 488         .fifo_depth     = 8, /* bytes */
 489 };
 490
 491 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
 492         { .irq = INT_24XX_I2C1_IRQ, },
 493 };
 494
 495 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
 496         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 497         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 498 };
 499
 500 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
 501         &omap2430_l4_core__i2c1,
 502 };
 503
 504 static struct omap_hwmod omap2430_i2c1_hwmod = {
 505         .name           = "i2c1",
 506         .mpu_irqs       = i2c1_mpu_irqs,
 507         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
 508         .sdma_reqs      = i2c1_sdma_reqs,
 509         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
 510         .main_clk       = "i2chs1_fck",
 511         .prcm           = {
 512                 .omap2 = {
 513                         /*
 514                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
 515                          * I2CHS IP's do not follow the usual pattern.
 516                          * prcm_reg_id alone cannot be used to program
 517                          * the iclk and fclk. Needs to be handled using
 518                          * additonal flags when clk handling is moved
 519                          * to hwmod framework.
 520                          */
 521                         .module_offs = CORE_MOD,
 522                         .prcm_reg_id = 1,
 523                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
 524                         .idlest_reg_id = 1,
 525                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
 526                 },
 527         },
 528         .slaves         = omap2430_i2c1_slaves,
 529         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
 530         .class          = &i2c_class,
 531         .dev_attr       = &i2c1_dev_attr,
 532         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 533 };
 534
 535 /* I2C2 */
 536
 537 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 538         .fifo_depth     = 8, /* bytes */
 539 };
 540
 541 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
 542         { .irq = INT_24XX_I2C2_IRQ, },
 543 };
 544
 545 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
 546         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 547         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 548 };
 549
 550 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
 551         &omap2430_l4_core__i2c2,
 552 };
 553
 554 static struct omap_hwmod omap2430_i2c2_hwmod = {
 555         .name           = "i2c2",
 556         .mpu_irqs       = i2c2_mpu_irqs,
 557         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
 558         .sdma_reqs      = i2c2_sdma_reqs,
 559         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
 560         .main_clk       = "i2chs2_fck",
 561         .prcm           = {
 562                 .omap2 = {
 563                         .module_offs = CORE_MOD,
 564                         .prcm_reg_id = 1,
 565                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
 566                         .idlest_reg_id = 1,
 567                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
 568                 },
 569         },
 570         .slaves         = omap2430_i2c2_slaves,
 571         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
 572         .class          = &i2c_class,
 573         .dev_attr       = &i2c2_dev_attr,
 574         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 575 };
 576
 577 /* l4_wkup -> gpio1 */
 578 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
 579         {
 580                 .pa_start       = 0x4900C000,
 581                 .pa_end         = 0x4900C1ff,
 582                 .flags          = ADDR_TYPE_RT
 583         },
 584 };
 585
 586 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
 587         .master         = &omap2430_l4_wkup_hwmod,
 588         .slave          = &omap2430_gpio1_hwmod,
 589         .clk            = "gpios_ick",
 590         .addr           = omap2430_gpio1_addr_space,
 591         .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
 592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 593 };
 594
 595 /* l4_wkup -> gpio2 */
 596 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
 597         {
 598                 .pa_start       = 0x4900E000,
 599                 .pa_end         = 0x4900E1ff,
 600                 .flags          = ADDR_TYPE_RT
 601         },
 602 };
 603
 604 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
 605         .master         = &omap2430_l4_wkup_hwmod,
 606         .slave          = &omap2430_gpio2_hwmod,
 607         .clk            = "gpios_ick",
 608         .addr           = omap2430_gpio2_addr_space,
 609         .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
 610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 611 };
 612
 613 /* l4_wkup -> gpio3 */
 614 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
 615         {
 616                 .pa_start       = 0x49010000,
 617                 .pa_end         = 0x490101ff,
 618                 .flags          = ADDR_TYPE_RT
 619         },
 620 };
 621
 622 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
 623         .master         = &omap2430_l4_wkup_hwmod,
 624         .slave          = &omap2430_gpio3_hwmod,
 625         .clk            = "gpios_ick",
 626         .addr           = omap2430_gpio3_addr_space,
 627         .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
 628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 629 };
 630
 631 /* l4_wkup -> gpio4 */
 632 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
 633         {
 634                 .pa_start       = 0x49012000,
 635                 .pa_end         = 0x490121ff,
 636                 .flags          = ADDR_TYPE_RT
 637         },
 638 };
 639
 640 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
 641         .master         = &omap2430_l4_wkup_hwmod,
 642         .slave          = &omap2430_gpio4_hwmod,
 643         .clk            = "gpios_ick",
 644         .addr           = omap2430_gpio4_addr_space,
 645         .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
 646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 647 };
 648
 649 /* l4_core -> gpio5 */
 650 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
 651         {
 652                 .pa_start       = 0x480B6000,
 653                 .pa_end         = 0x480B61ff,
 654                 .flags          = ADDR_TYPE_RT
 655         },
 656 };
 657
 658 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
 659         .master         = &omap2430_l4_core_hwmod,
 660         .slave          = &omap2430_gpio5_hwmod,
 661         .clk            = "gpio5_ick",
 662         .addr           = omap2430_gpio5_addr_space,
 663         .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
 664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 665 };
 666
 667 /* gpio dev_attr */
 668 static struct omap_gpio_dev_attr gpio_dev_attr = {
 669         .bank_width = 32,
 670         .dbck_flag = false,
 671 };
 672
 673 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
 674         .rev_offs       = 0x0000,
 675         .sysc_offs      = 0x0010,
 676         .syss_offs      = 0x0014,
 677         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 678                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 679         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 680         .sysc_fields    = &omap_hwmod_sysc_type1,
 681 };
 682
 683 /*
 684  * 'gpio' class
 685  * general purpose io module
 686  */
 687 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
 688         .name = "gpio",
 689         .sysc = &omap243x_gpio_sysc,
 690         .rev = 0,
 691 };
 692
 693 /* gpio1 */
 694 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
 695         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
 696 };
 697
 698 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
 699         &omap2430_l4_wkup__gpio1,
 700 };
 701
 702 static struct omap_hwmod omap2430_gpio1_hwmod = {
 703         .name           = "gpio1",
 704         .mpu_irqs       = omap243x_gpio1_irqs,
 705         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
 706         .main_clk       = "gpios_fck",
 707         .prcm           = {
 708                 .omap2 = {
 709                         .prcm_reg_id = 1,
 710                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 711                         .module_offs = WKUP_MOD,
 712                         .idlest_reg_id = 1,
 713                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
 714                 },
 715         },
 716         .slaves         = omap2430_gpio1_slaves,
 717         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
 718         .class          = &omap243x_gpio_hwmod_class,
 719         .dev_attr       = &gpio_dev_attr,
 720         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 721 };
 722
 723 /* gpio2 */
 724 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
 725         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
 726 };
 727
 728 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
 729         &omap2430_l4_wkup__gpio2,
 730 };
 731
 732 static struct omap_hwmod omap2430_gpio2_hwmod = {
 733         .name           = "gpio2",
 734         .mpu_irqs       = omap243x_gpio2_irqs,
 735         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
 736         .main_clk       = "gpios_fck",
 737         .prcm           = {
 738                 .omap2 = {
 739                         .prcm_reg_id = 1,
 740                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 741                         .module_offs = WKUP_MOD,
 742                         .idlest_reg_id = 1,
 743                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 744                 },
 745         },
 746         .slaves         = omap2430_gpio2_slaves,
 747         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
 748         .class          = &omap243x_gpio_hwmod_class,
 749         .dev_attr       = &gpio_dev_attr,
 750         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 751 };
 752
 753 /* gpio3 */
 754 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
 755         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
 756 };
 757
 758 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
 759         &omap2430_l4_wkup__gpio3,
 760 };
 761
 762 static struct omap_hwmod omap2430_gpio3_hwmod = {
 763         .name           = "gpio3",
 764         .mpu_irqs       = omap243x_gpio3_irqs,
 765         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
 766         .main_clk       = "gpios_fck",
 767         .prcm           = {
 768                 .omap2 = {
 769                         .prcm_reg_id = 1,
 770                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 771                         .module_offs = WKUP_MOD,
 772                         .idlest_reg_id = 1,
 773                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 774                 },
 775         },
 776         .slaves         = omap2430_gpio3_slaves,
 777         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
 778         .class          = &omap243x_gpio_hwmod_class,
 779         .dev_attr       = &gpio_dev_attr,
 780         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 781 };
 782
 783 /* gpio4 */
 784 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
 785         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
 786 };
 787
 788 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
 789         &omap2430_l4_wkup__gpio4,
 790 };
 791
 792 static struct omap_hwmod omap2430_gpio4_hwmod = {
 793         .name           = "gpio4",
 794         .mpu_irqs       = omap243x_gpio4_irqs,
 795         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
 796         .main_clk       = "gpios_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 801                         .module_offs = WKUP_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap2430_gpio4_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
 808         .class          = &omap243x_gpio_hwmod_class,
 809         .dev_attr       = &gpio_dev_attr,
 810         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 811 };
 812
 813 /* gpio5 */
 814 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
 815         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
 816 };
 817
 818 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
 819         &omap2430_l4_core__gpio5,
 820 };
 821
 822 static struct omap_hwmod omap2430_gpio5_hwmod = {
 823         .name           = "gpio5",
 824         .mpu_irqs       = omap243x_gpio5_irqs,
 825         .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
 826         .main_clk       = "gpio5_fck",
 827         .prcm           = {
 828                 .omap2 = {
 829                         .prcm_reg_id = 2,
 830                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
 831                         .module_offs = CORE_MOD,
 832                         .idlest_reg_id = 2,
 833                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
 834                 },
 835         },
 836         .slaves         = omap2430_gpio5_slaves,
 837         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
 838         .class          = &omap243x_gpio_hwmod_class,
 839         .dev_attr       = &gpio_dev_attr,
 840         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 841 };
 842
 843 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 844         &omap2430_l3_main_hwmod,
 845         &omap2430_l4_core_hwmod,
 846         &omap2430_l4_wkup_hwmod,
 847         &omap2430_mpu_hwmod,
 848         &omap2430_iva_hwmod,
 849         &omap2430_wd_timer2_hwmod,
 850         &omap2430_uart1_hwmod,
 851         &omap2430_uart2_hwmod,
 852         &omap2430_uart3_hwmod,
 853         &omap2430_i2c1_hwmod,
 854         &omap2430_i2c2_hwmod,
 855
 856         /* gpio class */
 857         &omap2430_gpio1_hwmod,
 858         &omap2430_gpio2_hwmod,
 859         &omap2430_gpio3_hwmod,
 860         &omap2430_gpio4_hwmod,
 861         &omap2430_gpio5_hwmod,
 862         NULL,
 863 };
 864
 865 int __init omap2430_hwmod_init(void)
 866 {
 867         return omap_hwmod_init(omap2430_hwmods);
 868 }