arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/i2c-omap.h>
  18
  19 #include "omap_hwmod.h"
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/spi-omap2-mcspi.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24
  25 #include "control.h"
  26 #include "cm33xx.h"
  27 #include "prm33xx.h"
  28 #include "prm-regbits-33xx.h"
  29 #include "i2c.h"
  30 #include "mmc.h"
  31
  32 /*
  33  * IP blocks
  34  */
  35
  36 /*
  37  * 'emif_fw' class
  38  * instance(s): emif_fw
  39  */
  40 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
  41         .name           = "emif_fw",
  42 };
  43
  44 /* emif_fw */
  45 static struct omap_hwmod am33xx_emif_fw_hwmod = {
  46         .name           = "emif_fw",
  47         .class          = &am33xx_emif_fw_hwmod_class,
  48         .clkdm_name     = "l4fw_clkdm",
  49         .main_clk       = "l4fw_gclk",
  50         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  51         .prcm           = {
  52                 .omap4  = {
  53                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
  54                         .modulemode     = MODULEMODE_SWCTRL,
  55                 },
  56         },
  57 };
  58
  59 /*
  60  * 'emif' class
  61  * instance(s): emif
  62  */
  63 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
  64         .rev_offs       = 0x0000,
  65 };
  66
  67 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
  68         .name           = "emif",
  69         .sysc           = &am33xx_emif_sysc,
  70 };
  71
  72 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
  73         { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
  74         { .irq = -1 },
  75 };
  76
  77 /* emif */
  78 static struct omap_hwmod am33xx_emif_hwmod = {
  79         .name           = "emif",
  80         .class          = &am33xx_emif_hwmod_class,
  81         .clkdm_name     = "l3_clkdm",
  82         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  83         .mpu_irqs       = am33xx_emif_irqs,
  84         .main_clk       = "dpll_ddr_m2_div2_ck",
  85         .prcm           = {
  86                 .omap4  = {
  87                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  88                         .modulemode     = MODULEMODE_SWCTRL,
  89                 },
  90         },
  91 };
  92
  93 /*
  94  * 'l3' class
  95  * instance(s): l3_main, l3_s, l3_instr
  96  */
  97 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  98         .name           = "l3",
  99 };
 100
 101 /* l3_main (l3_fast) */
 102 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
 103         { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
 104         { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
 105         { .irq = -1 },
 106 };
 107
 108 static struct omap_hwmod am33xx_l3_main_hwmod = {
 109         .name           = "l3_main",
 110         .class          = &am33xx_l3_hwmod_class,
 111         .clkdm_name     = "l3_clkdm",
 112         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 113         .mpu_irqs       = am33xx_l3_main_irqs,
 114         .main_clk       = "l3_gclk",
 115         .prcm           = {
 116                 .omap4  = {
 117                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
 118                         .modulemode     = MODULEMODE_SWCTRL,
 119                 },
 120         },
 121 };
 122
 123 /* l3_s */
 124 static struct omap_hwmod am33xx_l3_s_hwmod = {
 125         .name           = "l3_s",
 126         .class          = &am33xx_l3_hwmod_class,
 127         .clkdm_name     = "l3s_clkdm",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod am33xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &am33xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_clkdm",
 135         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 136         .main_clk       = "l3_gclk",
 137         .prcm           = {
 138                 .omap4  = {
 139                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
 140                         .modulemode     = MODULEMODE_SWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /*
 146  * 'l4' class
 147  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
 148  */
 149 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
 150         .name           = "l4",
 151 };
 152
 153 /* l4_ls */
 154 static struct omap_hwmod am33xx_l4_ls_hwmod = {
 155         .name           = "l4_ls",
 156         .class          = &am33xx_l4_hwmod_class,
 157         .clkdm_name     = "l4ls_clkdm",
 158         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 159         .main_clk       = "l4ls_gclk",
 160         .prcm           = {
 161                 .omap4  = {
 162                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
 163                         .modulemode     = MODULEMODE_SWCTRL,
 164                 },
 165         },
 166 };
 167
 168 /* l4_hs */
 169 static struct omap_hwmod am33xx_l4_hs_hwmod = {
 170         .name           = "l4_hs",
 171         .class          = &am33xx_l4_hwmod_class,
 172         .clkdm_name     = "l4hs_clkdm",
 173         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 174         .main_clk       = "l4hs_gclk",
 175         .prcm           = {
 176                 .omap4  = {
 177                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
 178                         .modulemode     = MODULEMODE_SWCTRL,
 179                 },
 180         },
 181 };
 182
 183
 184 /* l4_wkup */
 185 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
 186         .name           = "l4_wkup",
 187         .class          = &am33xx_l4_hwmod_class,
 188         .clkdm_name     = "l4_wkup_clkdm",
 189         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 190         .prcm           = {
 191                 .omap4  = {
 192                         .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 193                         .modulemode     = MODULEMODE_SWCTRL,
 194                 },
 195         },
 196 };
 197
 198 /* l4_fw */
 199 static struct omap_hwmod am33xx_l4_fw_hwmod = {
 200         .name           = "l4_fw",
 201         .class          = &am33xx_l4_hwmod_class,
 202         .clkdm_name     = "l4fw_clkdm",
 203         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 204         .prcm           = {
 205                 .omap4  = {
 206                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
 207                         .modulemode     = MODULEMODE_SWCTRL,
 208                 },
 209         },
 210 };
 211
 212 /*
 213  * 'mpu' class
 214  */
 215 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 216         .name   = "mpu",
 217 };
 218
 219 /* mpu */
 220 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
 221         { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
 222         { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
 223         { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
 224         { .name = "bench", .irq = 3 + OMAP_INTC_START, },
 225         { .irq = -1 },
 226 };
 227
 228 static struct omap_hwmod am33xx_mpu_hwmod = {
 229         .name           = "mpu",
 230         .class          = &am33xx_mpu_hwmod_class,
 231         .clkdm_name     = "mpu_clkdm",
 232         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 233         .mpu_irqs       = am33xx_mpu_irqs,
 234         .main_clk       = "dpll_mpu_m2_ck",
 235         .prcm           = {
 236                 .omap4  = {
 237                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 238                         .modulemode     = MODULEMODE_SWCTRL,
 239                 },
 240         },
 241 };
 242
 243 /*
 244  * 'wakeup m3' class
 245  * Wakeup controller sub-system under wakeup domain
 246  */
 247 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 248         .name           = "wkup_m3",
 249 };
 250
 251 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
 252         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 253 };
 254
 255 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
 256         { .name = "txev", .irq = 78 + OMAP_INTC_START, },
 257         { .irq = -1 },
 258 };
 259
 260 /* wkup_m3  */
 261 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 262         .name           = "wkup_m3",
 263         .class          = &am33xx_wkup_m3_hwmod_class,
 264         .clkdm_name     = "l4_wkup_aon_clkdm",
 265         /* Keep hardreset asserted */
 266         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
 267         .mpu_irqs       = am33xx_wkup_m3_irqs,
 268         .main_clk       = "dpll_core_m4_div2_ck",
 269         .prcm           = {
 270                 .omap4  = {
 271                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
 272                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
 273                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
 274                         .modulemode     = MODULEMODE_SWCTRL,
 275                 },
 276         },
 277         .rst_lines      = am33xx_wkup_m3_resets,
 278         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
 279 };
 280
 281 /*
 282  * 'pru-icss' class
 283  * Programmable Real-Time Unit and Industrial Communication Subsystem
 284  */
 285 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 286         .name   = "pruss",
 287 };
 288
 289 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 290         { .name = "pruss", .rst_shift = 1 },
 291 };
 292
 293 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
 294         { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
 295         { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
 296         { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
 297         { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
 298         { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
 299         { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
 300         { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
 301         { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
 302         { .irq = -1 },
 303 };
 304
 305 /* pru-icss */
 306 /* Pseudo hwmod for reset control purpose only */
 307 static struct omap_hwmod am33xx_pruss_hwmod = {
 308         .name           = "pruss",
 309         .class          = &am33xx_pruss_hwmod_class,
 310         .clkdm_name     = "pruss_ocp_clkdm",
 311         .mpu_irqs       = am33xx_pruss_irqs,
 312         .main_clk       = "pruss_ocp_gclk",
 313         .prcm           = {
 314                 .omap4  = {
 315                         .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
 316                         .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
 317                         .modulemode     = MODULEMODE_SWCTRL,
 318                 },
 319         },
 320         .rst_lines      = am33xx_pruss_resets,
 321         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 322 };
 323
 324 /* gfx */
 325 /* Pseudo hwmod for reset control purpose only */
 326 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 327         .name   = "gfx",
 328 };
 329
 330 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 331         { .name = "gfx", .rst_shift = 0 },
 332 };
 333
 334 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
 335         { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
 336         { .irq = -1 },
 337 };
 338
 339 static struct omap_hwmod am33xx_gfx_hwmod = {
 340         .name           = "gfx",
 341         .class          = &am33xx_gfx_hwmod_class,
 342         .clkdm_name     = "gfx_l3_clkdm",
 343         .mpu_irqs       = am33xx_gfx_irqs,
 344         .main_clk       = "gfx_fck_div_ck",
 345         .prcm           = {
 346                 .omap4  = {
 347                         .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
 348                         .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
 349                         .modulemode     = MODULEMODE_SWCTRL,
 350                 },
 351         },
 352         .rst_lines      = am33xx_gfx_resets,
 353         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 354 };
 355
 356 /*
 357  * 'prcm' class
 358  * power and reset manager (whole prcm infrastructure)
 359  */
 360 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 361         .name   = "prcm",
 362 };
 363
 364 /* prcm */
 365 static struct omap_hwmod am33xx_prcm_hwmod = {
 366         .name           = "prcm",
 367         .class          = &am33xx_prcm_hwmod_class,
 368         .clkdm_name     = "l4_wkup_clkdm",
 369 };
 370
 371 /*
 372  * 'adc/tsc' class
 373  * TouchScreen Controller (Anolog-To-Digital Converter)
 374  */
 375 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
 376         .rev_offs       = 0x00,
 377         .sysc_offs      = 0x10,
 378         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 379         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 380                         SIDLE_SMART_WKUP),
 381         .sysc_fields    = &omap_hwmod_sysc_type2,
 382 };
 383
 384 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
 385         .name           = "adc_tsc",
 386         .sysc           = &am33xx_adc_tsc_sysc,
 387 };
 388
 389 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
 390         { .irq = 16 + OMAP_INTC_START, },
 391         { .irq = -1 },
 392 };
 393
 394 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 395         .name           = "adc_tsc",
 396         .class          = &am33xx_adc_tsc_hwmod_class,
 397         .clkdm_name     = "l4_wkup_clkdm",
 398         .mpu_irqs       = am33xx_adc_tsc_irqs,
 399         .main_clk       = "adc_tsc_fck",
 400         .prcm           = {
 401                 .omap4  = {
 402                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 403                         .modulemode     = MODULEMODE_SWCTRL,
 404                 },
 405         },
 406 };
 407
 408 /*
 409  * Modules omap_hwmod structures
 410  *
 411  * The following IPs are excluded for the moment because:
 412  * - They do not need an explicit SW control using omap_hwmod API.
 413  * - They still need to be validated with the driver
 414  *   properly adapted to omap_hwmod / omap_device
 415  *
 416  *    - cEFUSE (doesn't fall under any ocp_if)
 417  *    - clkdiv32k
 418  *    - debugss
 419  *    - ocp watch point
 420  *    - aes0
 421  *    - sha0
 422  */
 423 #if 0
 424 /*
 425  * 'cefuse' class
 426  */
 427 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 428         .name           = "cefuse",
 429 };
 430
 431 static struct omap_hwmod am33xx_cefuse_hwmod = {
 432         .name           = "cefuse",
 433         .class          = &am33xx_cefuse_hwmod_class,
 434         .clkdm_name     = "l4_cefuse_clkdm",
 435         .main_clk       = "cefuse_fck",
 436         .prcm           = {
 437                 .omap4  = {
 438                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 439                         .modulemode     = MODULEMODE_SWCTRL,
 440                 },
 441         },
 442 };
 443
 444 /*
 445  * 'clkdiv32k' class
 446  */
 447 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 448         .name           = "clkdiv32k",
 449 };
 450
 451 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 452         .name           = "clkdiv32k",
 453         .class          = &am33xx_clkdiv32k_hwmod_class,
 454         .clkdm_name     = "clk_24mhz_clkdm",
 455         .main_clk       = "clkdiv32k_ick",
 456         .prcm           = {
 457                 .omap4  = {
 458                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 459                         .modulemode     = MODULEMODE_SWCTRL,
 460                 },
 461         },
 462 };
 463
 464 /*
 465  * 'debugss' class
 466  * debug sub system
 467  */
 468 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 469         .name           = "debugss",
 470 };
 471
 472 static struct omap_hwmod am33xx_debugss_hwmod = {
 473         .name           = "debugss",
 474         .class          = &am33xx_debugss_hwmod_class,
 475         .clkdm_name     = "l3_aon_clkdm",
 476         .main_clk       = "debugss_ick",
 477         .prcm           = {
 478                 .omap4  = {
 479                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 480                         .modulemode     = MODULEMODE_SWCTRL,
 481                 },
 482         },
 483 };
 484
 485 /* ocpwp */
 486 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 487         .name           = "ocpwp",
 488 };
 489
 490 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 491         .name           = "ocpwp",
 492         .class          = &am33xx_ocpwp_hwmod_class,
 493         .clkdm_name     = "l4ls_clkdm",
 494         .main_clk       = "l4ls_gclk",
 495         .prcm           = {
 496                 .omap4  = {
 497                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 498                         .modulemode     = MODULEMODE_SWCTRL,
 499                 },
 500         },
 501 };
 502
 503 /*
 504  * 'aes' class
 505  */
 506 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
 507         .name           = "aes",
 508 };
 509
 510 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
 511         { .irq = 102 + OMAP_INTC_START, },
 512         { .irq = -1 },
 513 };
 514
 515 static struct omap_hwmod am33xx_aes0_hwmod = {
 516         .name           = "aes0",
 517         .class          = &am33xx_aes_hwmod_class,
 518         .clkdm_name     = "l3_clkdm",
 519         .mpu_irqs       = am33xx_aes0_irqs,
 520         .main_clk       = "l3_gclk",
 521         .prcm           = {
 522                 .omap4  = {
 523                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
 524                         .modulemode     = MODULEMODE_SWCTRL,
 525                 },
 526         },
 527 };
 528
 529 /* sha0 */
 530 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 531         .name           = "sha0",
 532 };
 533
 534 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
 535         { .irq = 108 + OMAP_INTC_START, },
 536         { .irq = -1 },
 537 };
 538
 539 static struct omap_hwmod am33xx_sha0_hwmod = {
 540         .name           = "sha0",
 541         .class          = &am33xx_sha0_hwmod_class,
 542         .clkdm_name     = "l3_clkdm",
 543         .mpu_irqs       = am33xx_sha0_irqs,
 544         .main_clk       = "l3_gclk",
 545         .prcm           = {
 546                 .omap4  = {
 547                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
 548                         .modulemode     = MODULEMODE_SWCTRL,
 549                 },
 550         },
 551 };
 552
 553 #endif
 554
 555 /* ocmcram */
 556 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 557         .name = "ocmcram",
 558 };
 559
 560 static struct omap_hwmod am33xx_ocmcram_hwmod = {
 561         .name           = "ocmcram",
 562         .class          = &am33xx_ocmcram_hwmod_class,
 563         .clkdm_name     = "l3_clkdm",
 564         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 565         .main_clk       = "l3_gclk",
 566         .prcm           = {
 567                 .omap4  = {
 568                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
 569                         .modulemode     = MODULEMODE_SWCTRL,
 570                 },
 571         },
 572 };
 573
 574 /* 'smartreflex' class */
 575 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 576         .name           = "smartreflex",
 577 };
 578
 579 /* smartreflex0 */
 580 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
 581         { .irq = 120 + OMAP_INTC_START, },
 582         { .irq = -1 },
 583 };
 584
 585 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 586         .name           = "smartreflex0",
 587         .class          = &am33xx_smartreflex_hwmod_class,
 588         .clkdm_name     = "l4_wkup_clkdm",
 589         .mpu_irqs       = am33xx_smartreflex0_irqs,
 590         .main_clk       = "smartreflex0_fck",
 591         .prcm           = {
 592                 .omap4  = {
 593                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
 594                         .modulemode     = MODULEMODE_SWCTRL,
 595                 },
 596         },
 597 };
 598
 599 /* smartreflex1 */
 600 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
 601         { .irq = 121 + OMAP_INTC_START, },
 602         { .irq = -1 },
 603 };
 604
 605 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
 606         .name           = "smartreflex1",
 607         .class          = &am33xx_smartreflex_hwmod_class,
 608         .clkdm_name     = "l4_wkup_clkdm",
 609         .mpu_irqs       = am33xx_smartreflex1_irqs,
 610         .main_clk       = "smartreflex1_fck",
 611         .prcm           = {
 612                 .omap4  = {
 613                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
 614                         .modulemode     = MODULEMODE_SWCTRL,
 615                 },
 616         },
 617 };
 618
 619 /*
 620  * 'control' module class
 621  */
 622 static struct omap_hwmod_class am33xx_control_hwmod_class = {
 623         .name           = "control",
 624 };
 625
 626 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
 627         { .irq = 8 + OMAP_INTC_START, },
 628         { .irq = -1 },
 629 };
 630
 631 static struct omap_hwmod am33xx_control_hwmod = {
 632         .name           = "control",
 633         .class          = &am33xx_control_hwmod_class,
 634         .clkdm_name     = "l4_wkup_clkdm",
 635         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 636         .mpu_irqs       = am33xx_control_irqs,
 637         .main_clk       = "dpll_core_m4_div2_ck",
 638         .prcm           = {
 639                 .omap4  = {
 640                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 641                         .modulemode     = MODULEMODE_SWCTRL,
 642                 },
 643         },
 644 };
 645
 646 /*
 647  * 'cpgmac' class
 648  * cpsw/cpgmac sub system
 649  */
 650 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 651         .rev_offs       = 0x0,
 652         .sysc_offs      = 0x8,
 653         .syss_offs      = 0x4,
 654         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 655                            SYSS_HAS_RESET_STATUS),
 656         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 657                            MSTANDBY_NO),
 658         .sysc_fields    = &omap_hwmod_sysc_type3,
 659 };
 660
 661 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 662         .name           = "cpgmac0",
 663         .sysc           = &am33xx_cpgmac_sysc,
 664 };
 665
 666 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
 667         { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
 668         { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
 669         { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
 670         { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
 671         { .irq = -1 },
 672 };
 673
 674 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 675         .name           = "cpgmac0",
 676         .class          = &am33xx_cpgmac0_hwmod_class,
 677         .clkdm_name     = "cpsw_125mhz_clkdm",
 678         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 679         .mpu_irqs       = am33xx_cpgmac0_irqs,
 680         .main_clk       = "cpsw_125mhz_gclk",
 681         .prcm           = {
 682                 .omap4  = {
 683                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
 684                         .modulemode     = MODULEMODE_SWCTRL,
 685                 },
 686         },
 687 };
 688
 689 /*
 690  * mdio class
 691  */
 692 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 693         .name           = "davinci_mdio",
 694 };
 695
 696 static struct omap_hwmod am33xx_mdio_hwmod = {
 697         .name           = "davinci_mdio",
 698         .class          = &am33xx_mdio_hwmod_class,
 699         .clkdm_name     = "cpsw_125mhz_clkdm",
 700         .main_clk       = "cpsw_125mhz_gclk",
 701 };
 702
 703 /*
 704  * dcan class
 705  */
 706 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 707         .name = "d_can",
 708 };
 709
 710 /* dcan0 */
 711 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
 712         { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
 713         { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
 714         { .irq = -1 },
 715 };
 716
 717 static struct omap_hwmod am33xx_dcan0_hwmod = {
 718         .name           = "d_can0",
 719         .class          = &am33xx_dcan_hwmod_class,
 720         .clkdm_name     = "l4ls_clkdm",
 721         .mpu_irqs       = am33xx_dcan0_irqs,
 722         .main_clk       = "dcan0_fck",
 723         .prcm           = {
 724                 .omap4  = {
 725                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
 726                         .modulemode     = MODULEMODE_SWCTRL,
 727                 },
 728         },
 729 };
 730
 731 /* dcan1 */
 732 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
 733         { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
 734         { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
 735         { .irq = -1 },
 736 };
 737 static struct omap_hwmod am33xx_dcan1_hwmod = {
 738         .name           = "d_can1",
 739         .class          = &am33xx_dcan_hwmod_class,
 740         .clkdm_name     = "l4ls_clkdm",
 741         .mpu_irqs       = am33xx_dcan1_irqs,
 742         .main_clk       = "dcan1_fck",
 743         .prcm           = {
 744                 .omap4  = {
 745                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
 746                         .modulemode     = MODULEMODE_SWCTRL,
 747                 },
 748         },
 749 };
 750
 751 /* elm */
 752 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 753         .rev_offs       = 0x0000,
 754         .sysc_offs      = 0x0010,
 755         .syss_offs      = 0x0014,
 756         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 757                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 758                         SYSS_HAS_RESET_STATUS),
 759         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 760         .sysc_fields    = &omap_hwmod_sysc_type1,
 761 };
 762
 763 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 764         .name           = "elm",
 765         .sysc           = &am33xx_elm_sysc,
 766 };
 767
 768 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
 769         { .irq = 4 + OMAP_INTC_START, },
 770         { .irq = -1 },
 771 };
 772
 773 static struct omap_hwmod am33xx_elm_hwmod = {
 774         .name           = "elm",
 775         .class          = &am33xx_elm_hwmod_class,
 776         .clkdm_name     = "l4ls_clkdm",
 777         .mpu_irqs       = am33xx_elm_irqs,
 778         .main_clk       = "l4ls_gclk",
 779         .prcm           = {
 780                 .omap4  = {
 781                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
 782                         .modulemode     = MODULEMODE_SWCTRL,
 783                 },
 784         },
 785 };
 786
 787 /* pwmss  */
 788 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 789         .rev_offs       = 0x0,
 790         .sysc_offs      = 0x4,
 791         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 792         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 793                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 794                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 795         .sysc_fields    = &omap_hwmod_sysc_type2,
 796 };
 797
 798 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 799         .name           = "epwmss",
 800         .sysc           = &am33xx_epwmss_sysc,
 801 };
 802
 803 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 804         .name           = "ecap",
 805 };
 806
 807 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 808         .name           = "eqep",
 809 };
 810
 811 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 812         .name           = "ehrpwm",
 813 };
 814
 815 /* epwmss0 */
 816 static struct omap_hwmod am33xx_epwmss0_hwmod = {
 817         .name           = "epwmss0",
 818         .class          = &am33xx_epwmss_hwmod_class,
 819         .clkdm_name     = "l4ls_clkdm",
 820         .main_clk       = "l4ls_gclk",
 821         .prcm           = {
 822                 .omap4  = {
 823                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
 824                         .modulemode     = MODULEMODE_SWCTRL,
 825                 },
 826         },
 827 };
 828
 829 /* ecap0 */
 830 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
 831         { .irq = 31 + OMAP_INTC_START, },
 832         { .irq = -1 },
 833 };
 834
 835 static struct omap_hwmod am33xx_ecap0_hwmod = {
 836         .name           = "ecap0",
 837         .class          = &am33xx_ecap_hwmod_class,
 838         .clkdm_name     = "l4ls_clkdm",
 839         .mpu_irqs       = am33xx_ecap0_irqs,
 840         .main_clk       = "l4ls_gclk",
 841 };
 842
 843 /* eqep0 */
 844 static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
 845         { .irq = 79 + OMAP_INTC_START, },
 846         { .irq = -1 },
 847 };
 848
 849 static struct omap_hwmod am33xx_eqep0_hwmod = {
 850         .name           = "eqep0",
 851         .class          = &am33xx_eqep_hwmod_class,
 852         .clkdm_name     = "l4ls_clkdm",
 853         .mpu_irqs       = am33xx_eqep0_irqs,
 854         .main_clk       = "l4ls_gclk",
 855 };
 856
 857 /* ehrpwm0 */
 858 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
 859         { .name = "int", .irq = 86 + OMAP_INTC_START, },
 860         { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
 861         { .irq = -1 },
 862 };
 863
 864 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 865         .name           = "ehrpwm0",
 866         .class          = &am33xx_ehrpwm_hwmod_class,
 867         .clkdm_name     = "l4ls_clkdm",
 868         .mpu_irqs       = am33xx_ehrpwm0_irqs,
 869         .main_clk       = "l4ls_gclk",
 870 };
 871
 872 /* epwmss1 */
 873 static struct omap_hwmod am33xx_epwmss1_hwmod = {
 874         .name           = "epwmss1",
 875         .class          = &am33xx_epwmss_hwmod_class,
 876         .clkdm_name     = "l4ls_clkdm",
 877         .main_clk       = "l4ls_gclk",
 878         .prcm           = {
 879                 .omap4  = {
 880                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
 881                         .modulemode     = MODULEMODE_SWCTRL,
 882                 },
 883         },
 884 };
 885
 886 /* ecap1 */
 887 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
 888         { .irq = 47 + OMAP_INTC_START, },
 889         { .irq = -1 },
 890 };
 891
 892 static struct omap_hwmod am33xx_ecap1_hwmod = {
 893         .name           = "ecap1",
 894         .class          = &am33xx_ecap_hwmod_class,
 895         .clkdm_name     = "l4ls_clkdm",
 896         .mpu_irqs       = am33xx_ecap1_irqs,
 897         .main_clk       = "l4ls_gclk",
 898 };
 899
 900 /* eqep1 */
 901 static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
 902         { .irq = 88 + OMAP_INTC_START, },
 903         { .irq = -1 },
 904 };
 905
 906 static struct omap_hwmod am33xx_eqep1_hwmod = {
 907         .name           = "eqep1",
 908         .class          = &am33xx_eqep_hwmod_class,
 909         .clkdm_name     = "l4ls_clkdm",
 910         .mpu_irqs       = am33xx_eqep1_irqs,
 911         .main_clk       = "l4ls_gclk",
 912 };
 913
 914 /* ehrpwm1 */
 915 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
 916         { .name = "int", .irq = 87 + OMAP_INTC_START, },
 917         { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
 918         { .irq = -1 },
 919 };
 920
 921 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 922         .name           = "ehrpwm1",
 923         .class          = &am33xx_ehrpwm_hwmod_class,
 924         .clkdm_name     = "l4ls_clkdm",
 925         .mpu_irqs       = am33xx_ehrpwm1_irqs,
 926         .main_clk       = "l4ls_gclk",
 927 };
 928
 929 /* epwmss2 */
 930 static struct omap_hwmod am33xx_epwmss2_hwmod = {
 931         .name           = "epwmss2",
 932         .class          = &am33xx_epwmss_hwmod_class,
 933         .clkdm_name     = "l4ls_clkdm",
 934         .main_clk       = "l4ls_gclk",
 935         .prcm           = {
 936                 .omap4  = {
 937                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
 938                         .modulemode     = MODULEMODE_SWCTRL,
 939                 },
 940         },
 941 };
 942
 943 /* ecap2 */
 944 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
 945         { .irq = 61 + OMAP_INTC_START, },
 946         { .irq = -1 },
 947 };
 948
 949 static struct omap_hwmod am33xx_ecap2_hwmod = {
 950         .name           = "ecap2",
 951         .class          = &am33xx_ecap_hwmod_class,
 952         .clkdm_name     = "l4ls_clkdm",
 953         .mpu_irqs       = am33xx_ecap2_irqs,
 954         .main_clk       = "l4ls_gclk",
 955 };
 956
 957 /* eqep2 */
 958 static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
 959         { .irq = 89 + OMAP_INTC_START, },
 960         { .irq = -1 },
 961 };
 962
 963 static struct omap_hwmod am33xx_eqep2_hwmod = {
 964         .name           = "eqep2",
 965         .class          = &am33xx_eqep_hwmod_class,
 966         .clkdm_name     = "l4ls_clkdm",
 967         .mpu_irqs       = am33xx_eqep2_irqs,
 968         .main_clk       = "l4ls_gclk",
 969 };
 970
 971 /* ehrpwm2 */
 972 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
 973         { .name = "int", .irq = 39 + OMAP_INTC_START, },
 974         { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
 975         { .irq = -1 },
 976 };
 977
 978 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 979         .name           = "ehrpwm2",
 980         .class          = &am33xx_ehrpwm_hwmod_class,
 981         .clkdm_name     = "l4ls_clkdm",
 982         .mpu_irqs       = am33xx_ehrpwm2_irqs,
 983         .main_clk       = "l4ls_gclk",
 984 };
 985
 986 /*
 987  * 'gpio' class: for gpio 0,1,2,3
 988  */
 989 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 990         .rev_offs       = 0x0000,
 991         .sysc_offs      = 0x0010,
 992         .syss_offs      = 0x0114,
 993         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 994                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 995                           SYSS_HAS_RESET_STATUS),
 996         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 997                           SIDLE_SMART_WKUP),
 998         .sysc_fields    = &omap_hwmod_sysc_type1,
 999 };
1000
1001 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1002         .name           = "gpio",
1003         .sysc           = &am33xx_gpio_sysc,
1004         .rev            = 2,
1005 };
1006
1007 static struct omap_gpio_dev_attr gpio_dev_attr = {
1008         .bank_width     = 32,
1009         .dbck_flag      = true,
1010 };
1011
1012 /* gpio0 */
1013 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1014         { .role = "dbclk", .clk = "gpio0_dbclk" },
1015 };
1016
1017 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1018         { .irq = 96 + OMAP_INTC_START, },
1019         { .irq = -1 },
1020 };
1021
1022 static struct omap_hwmod am33xx_gpio0_hwmod = {
1023         .name           = "gpio1",
1024         .class          = &am33xx_gpio_hwmod_class,
1025         .clkdm_name     = "l4_wkup_clkdm",
1026         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1027         .mpu_irqs       = am33xx_gpio0_irqs,
1028         .main_clk       = "dpll_core_m4_div2_ck",
1029         .prcm           = {
1030                 .omap4  = {
1031                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1032                         .modulemode     = MODULEMODE_SWCTRL,
1033                 },
1034         },
1035         .opt_clks       = gpio0_opt_clks,
1036         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
1037         .dev_attr       = &gpio_dev_attr,
1038 };
1039
1040 /* gpio1 */
1041 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1042         { .irq = 98 + OMAP_INTC_START, },
1043         { .irq = -1 },
1044 };
1045
1046 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1047         { .role = "dbclk", .clk = "gpio1_dbclk" },
1048 };
1049
1050 static struct omap_hwmod am33xx_gpio1_hwmod = {
1051         .name           = "gpio2",
1052         .class          = &am33xx_gpio_hwmod_class,
1053         .clkdm_name     = "l4ls_clkdm",
1054         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1055         .mpu_irqs       = am33xx_gpio1_irqs,
1056         .main_clk       = "l4ls_gclk",
1057         .prcm           = {
1058                 .omap4  = {
1059                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1060                         .modulemode     = MODULEMODE_SWCTRL,
1061                 },
1062         },
1063         .opt_clks       = gpio1_opt_clks,
1064         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1065         .dev_attr       = &gpio_dev_attr,
1066 };
1067
1068 /* gpio2 */
1069 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1070         { .irq = 32 + OMAP_INTC_START, },
1071         { .irq = -1 },
1072 };
1073
1074 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1075         { .role = "dbclk", .clk = "gpio2_dbclk" },
1076 };
1077
1078 static struct omap_hwmod am33xx_gpio2_hwmod = {
1079         .name           = "gpio3",
1080         .class          = &am33xx_gpio_hwmod_class,
1081         .clkdm_name     = "l4ls_clkdm",
1082         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1083         .mpu_irqs       = am33xx_gpio2_irqs,
1084         .main_clk       = "l4ls_gclk",
1085         .prcm           = {
1086                 .omap4  = {
1087                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1088                         .modulemode     = MODULEMODE_SWCTRL,
1089                 },
1090         },
1091         .opt_clks       = gpio2_opt_clks,
1092         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1093         .dev_attr       = &gpio_dev_attr,
1094 };
1095
1096 /* gpio3 */
1097 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1098         { .irq = 62 + OMAP_INTC_START, },
1099         { .irq = -1 },
1100 };
1101
1102 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1103         { .role = "dbclk", .clk = "gpio3_dbclk" },
1104 };
1105
1106 static struct omap_hwmod am33xx_gpio3_hwmod = {
1107         .name           = "gpio4",
1108         .class          = &am33xx_gpio_hwmod_class,
1109         .clkdm_name     = "l4ls_clkdm",
1110         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1111         .mpu_irqs       = am33xx_gpio3_irqs,
1112         .main_clk       = "l4ls_gclk",
1113         .prcm           = {
1114                 .omap4  = {
1115                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1116                         .modulemode     = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119         .opt_clks       = gpio3_opt_clks,
1120         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1121         .dev_attr       = &gpio_dev_attr,
1122 };
1123
1124 /* gpmc */
1125 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1126         .rev_offs       = 0x0,
1127         .sysc_offs      = 0x10,
1128         .syss_offs      = 0x14,
1129         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1130                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1132         .sysc_fields    = &omap_hwmod_sysc_type1,
1133 };
1134
1135 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1136         .name           = "gpmc",
1137         .sysc           = &gpmc_sysc,
1138 };
1139
1140 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1141         { .irq = 100 + OMAP_INTC_START, },
1142         { .irq = -1 },
1143 };
1144
1145 static struct omap_hwmod am33xx_gpmc_hwmod = {
1146         .name           = "gpmc",
1147         .class          = &am33xx_gpmc_hwmod_class,
1148         .clkdm_name     = "l3s_clkdm",
1149         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1150         .mpu_irqs       = am33xx_gpmc_irqs,
1151         .main_clk       = "l3s_gclk",
1152         .prcm           = {
1153                 .omap4  = {
1154                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1155                         .modulemode     = MODULEMODE_SWCTRL,
1156                 },
1157         },
1158 };
1159
1160 /* 'i2c' class */
1161 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1162         .sysc_offs      = 0x0010,
1163         .syss_offs      = 0x0090,
1164         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1165                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1166                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1167         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1168                           SIDLE_SMART_WKUP),
1169         .sysc_fields    = &omap_hwmod_sysc_type1,
1170 };
1171
1172 static struct omap_hwmod_class i2c_class = {
1173         .name           = "i2c",
1174         .sysc           = &am33xx_i2c_sysc,
1175         .rev            = OMAP_I2C_IP_VERSION_2,
1176         .reset          = &omap_i2c_reset,
1177 };
1178
1179 static struct omap_i2c_dev_attr i2c_dev_attr = {
1180         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1181 };
1182
1183 /* i2c1 */
1184 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1185         { .irq = 70 + OMAP_INTC_START, },
1186         { .irq = -1 },
1187 };
1188
1189 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1190         { .name = "tx", .dma_req = 0, },
1191         { .name = "rx", .dma_req = 0, },
1192         { .dma_req = -1 }
1193 };
1194
1195 static struct omap_hwmod am33xx_i2c1_hwmod = {
1196         .name           = "i2c1",
1197         .class          = &i2c_class,
1198         .clkdm_name     = "l4_wkup_clkdm",
1199         .mpu_irqs       = i2c1_mpu_irqs,
1200         .sdma_reqs      = i2c1_edma_reqs,
1201         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1202         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1203         .prcm           = {
1204                 .omap4  = {
1205                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1206                         .modulemode     = MODULEMODE_SWCTRL,
1207                 },
1208         },
1209         .dev_attr       = &i2c_dev_attr,
1210 };
1211
1212 /* i2c1 */
1213 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1214         { .irq = 71 + OMAP_INTC_START, },
1215         { .irq = -1 },
1216 };
1217
1218 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1219         { .name = "tx", .dma_req = 0, },
1220         { .name = "rx", .dma_req = 0, },
1221         { .dma_req = -1 }
1222 };
1223
1224 static struct omap_hwmod am33xx_i2c2_hwmod = {
1225         .name           = "i2c2",
1226         .class          = &i2c_class,
1227         .clkdm_name     = "l4ls_clkdm",
1228         .mpu_irqs       = i2c2_mpu_irqs,
1229         .sdma_reqs      = i2c2_edma_reqs,
1230         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1231         .main_clk       = "dpll_per_m2_div4_ck",
1232         .prcm           = {
1233                 .omap4 = {
1234                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1235                         .modulemode     = MODULEMODE_SWCTRL,
1236                 },
1237         },
1238         .dev_attr       = &i2c_dev_attr,
1239 };
1240
1241 /* i2c3 */
1242 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1243         { .name = "tx", .dma_req = 0, },
1244         { .name = "rx", .dma_req = 0, },
1245         { .dma_req = -1 }
1246 };
1247
1248 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1249         { .irq = 30 + OMAP_INTC_START, },
1250         { .irq = -1 },
1251 };
1252
1253 static struct omap_hwmod am33xx_i2c3_hwmod = {
1254         .name           = "i2c3",
1255         .class          = &i2c_class,
1256         .clkdm_name     = "l4ls_clkdm",
1257         .mpu_irqs       = i2c3_mpu_irqs,
1258         .sdma_reqs      = i2c3_edma_reqs,
1259         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1260         .main_clk       = "dpll_per_m2_div4_ck",
1261         .prcm           = {
1262                 .omap4  = {
1263                         .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1264                         .modulemode     = MODULEMODE_SWCTRL,
1265                 },
1266         },
1267         .dev_attr       = &i2c_dev_attr,
1268 };
1269
1270
1271 /* lcdc */
1272 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1273         .rev_offs       = 0x0,
1274         .sysc_offs      = 0x54,
1275         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1276         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1277         .sysc_fields    = &omap_hwmod_sysc_type2,
1278 };
1279
1280 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1281         .name           = "lcdc",
1282         .sysc           = &lcdc_sysc,
1283 };
1284
1285 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1286         { .irq = 36 + OMAP_INTC_START, },
1287         { .irq = -1 },
1288 };
1289
1290 static struct omap_hwmod am33xx_lcdc_hwmod = {
1291         .name           = "lcdc",
1292         .class          = &am33xx_lcdc_hwmod_class,
1293         .clkdm_name     = "lcdc_clkdm",
1294         .mpu_irqs       = am33xx_lcdc_irqs,
1295         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1296         .main_clk       = "lcd_gclk",
1297         .prcm           = {
1298                 .omap4  = {
1299                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1300                         .modulemode     = MODULEMODE_SWCTRL,
1301                 },
1302         },
1303 };
1304
1305 /*
1306  * 'mailbox' class
1307  * mailbox module allowing communication between the on-chip processors using a
1308  * queued mailbox-interrupt mechanism.
1309  */
1310 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1311         .rev_offs       = 0x0000,
1312         .sysc_offs      = 0x0010,
1313         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1314                           SYSC_HAS_SOFTRESET),
1315         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1316         .sysc_fields    = &omap_hwmod_sysc_type2,
1317 };
1318
1319 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1320         .name   = "mailbox",
1321         .sysc   = &am33xx_mailbox_sysc,
1322 };
1323
1324 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1325         { .irq = 77 + OMAP_INTC_START, },
1326         { .irq = -1 },
1327 };
1328
1329 static struct omap_hwmod am33xx_mailbox_hwmod = {
1330         .name           = "mailbox",
1331         .class          = &am33xx_mailbox_hwmod_class,
1332         .clkdm_name     = "l4ls_clkdm",
1333         .mpu_irqs       = am33xx_mailbox_irqs,
1334         .main_clk       = "l4ls_gclk",
1335         .prcm = {
1336                 .omap4 = {
1337                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1338                         .modulemode     = MODULEMODE_SWCTRL,
1339                 },
1340         },
1341 };
1342
1343 /*
1344  * 'mcasp' class
1345  */
1346 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1347         .rev_offs       = 0x0,
1348         .sysc_offs      = 0x4,
1349         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1350         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1351         .sysc_fields    = &omap_hwmod_sysc_type3,
1352 };
1353
1354 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1355         .name           = "mcasp",
1356         .sysc           = &am33xx_mcasp_sysc,
1357 };
1358
1359 /* mcasp0 */
1360 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1361         { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1362         { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1363         { .irq = -1 },
1364 };
1365
1366 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1367         { .name = "tx", .dma_req = 8, },
1368         { .name = "rx", .dma_req = 9, },
1369         { .dma_req = -1 }
1370 };
1371
1372 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1373         .name           = "mcasp0",
1374         .class          = &am33xx_mcasp_hwmod_class,
1375         .clkdm_name     = "l3s_clkdm",
1376         .mpu_irqs       = am33xx_mcasp0_irqs,
1377         .sdma_reqs      = am33xx_mcasp0_edma_reqs,
1378         .main_clk       = "mcasp0_fck",
1379         .prcm           = {
1380                 .omap4  = {
1381                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1382                         .modulemode     = MODULEMODE_SWCTRL,
1383                 },
1384         },
1385 };
1386
1387 /* mcasp1 */
1388 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1389         { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1390         { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1391         { .irq = -1 },
1392 };
1393
1394 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1395         { .name = "tx", .dma_req = 10, },
1396         { .name = "rx", .dma_req = 11, },
1397         { .dma_req = -1 }
1398 };
1399
1400 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1401         .name           = "mcasp1",
1402         .class          = &am33xx_mcasp_hwmod_class,
1403         .clkdm_name     = "l3s_clkdm",
1404         .mpu_irqs       = am33xx_mcasp1_irqs,
1405         .sdma_reqs      = am33xx_mcasp1_edma_reqs,
1406         .main_clk       = "mcasp1_fck",
1407         .prcm           = {
1408                 .omap4  = {
1409                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1410                         .modulemode     = MODULEMODE_SWCTRL,
1411                 },
1412         },
1413 };
1414
1415 /* 'mmc' class */
1416 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1417         .rev_offs       = 0x1fc,
1418         .sysc_offs      = 0x10,
1419         .syss_offs      = 0x14,
1420         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1421                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1422                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1423         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1424         .sysc_fields    = &omap_hwmod_sysc_type1,
1425 };
1426
1427 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1428         .name           = "mmc",
1429         .sysc           = &am33xx_mmc_sysc,
1430 };
1431
1432 /* mmc0 */
1433 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1434         { .irq = 64 + OMAP_INTC_START, },
1435         { .irq = -1 },
1436 };
1437
1438 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1439         { .name = "tx", .dma_req = 24, },
1440         { .name = "rx", .dma_req = 25, },
1441         { .dma_req = -1 }
1442 };
1443
1444 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1445         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1446 };
1447
1448 static struct omap_hwmod am33xx_mmc0_hwmod = {
1449         .name           = "mmc1",
1450         .class          = &am33xx_mmc_hwmod_class,
1451         .clkdm_name     = "l4ls_clkdm",
1452         .mpu_irqs       = am33xx_mmc0_irqs,
1453         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1454         .main_clk       = "mmc_clk",
1455         .prcm           = {
1456                 .omap4  = {
1457                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1458                         .modulemode     = MODULEMODE_SWCTRL,
1459                 },
1460         },
1461         .dev_attr       = &am33xx_mmc0_dev_attr,
1462 };
1463
1464 /* mmc1 */
1465 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1466         { .irq = 28 + OMAP_INTC_START, },
1467         { .irq = -1 },
1468 };
1469
1470 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1471         { .name = "tx", .dma_req = 2, },
1472         { .name = "rx", .dma_req = 3, },
1473         { .dma_req = -1 }
1474 };
1475
1476 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1477         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1478 };
1479
1480 static struct omap_hwmod am33xx_mmc1_hwmod = {
1481         .name           = "mmc2",
1482         .class          = &am33xx_mmc_hwmod_class,
1483         .clkdm_name     = "l4ls_clkdm",
1484         .mpu_irqs       = am33xx_mmc1_irqs,
1485         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1486         .main_clk       = "mmc_clk",
1487         .prcm           = {
1488                 .omap4  = {
1489                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1490                         .modulemode     = MODULEMODE_SWCTRL,
1491                 },
1492         },
1493         .dev_attr       = &am33xx_mmc1_dev_attr,
1494 };
1495
1496 /* mmc2 */
1497 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1498         { .irq = 29 + OMAP_INTC_START, },
1499         { .irq = -1 },
1500 };
1501
1502 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1503         { .name = "tx", .dma_req = 64, },
1504         { .name = "rx", .dma_req = 65, },
1505         { .dma_req = -1 }
1506 };
1507
1508 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1509         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1510 };
1511 static struct omap_hwmod am33xx_mmc2_hwmod = {
1512         .name           = "mmc3",
1513         .class          = &am33xx_mmc_hwmod_class,
1514         .clkdm_name     = "l3s_clkdm",
1515         .mpu_irqs       = am33xx_mmc2_irqs,
1516         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1517         .main_clk       = "mmc_clk",
1518         .prcm           = {
1519                 .omap4  = {
1520                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1521                         .modulemode     = MODULEMODE_SWCTRL,
1522                 },
1523         },
1524         .dev_attr       = &am33xx_mmc2_dev_attr,
1525 };
1526
1527 /*
1528  * 'rtc' class
1529  * rtc subsystem
1530  */
1531 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1532         .rev_offs       = 0x0074,
1533         .sysc_offs      = 0x0078,
1534         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1535         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
1536                           SIDLE_SMART | SIDLE_SMART_WKUP),
1537         .sysc_fields    = &omap_hwmod_sysc_type3,
1538 };
1539
1540 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1541         .name           = "rtc",
1542         .sysc           = &am33xx_rtc_sysc,
1543 };
1544
1545 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1546         { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1547         { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1548         { .irq = -1 },
1549 };
1550
1551 static struct omap_hwmod am33xx_rtc_hwmod = {
1552         .name           = "rtc",
1553         .class          = &am33xx_rtc_hwmod_class,
1554         .clkdm_name     = "l4_rtc_clkdm",
1555         .mpu_irqs       = am33xx_rtc_irqs,
1556         .main_clk       = "clk_32768_ck",
1557         .prcm           = {
1558                 .omap4  = {
1559                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1560                         .modulemode     = MODULEMODE_SWCTRL,
1561                 },
1562         },
1563 };
1564
1565 /* 'spi' class */
1566 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1567         .rev_offs       = 0x0000,
1568         .sysc_offs      = 0x0110,
1569         .syss_offs      = 0x0114,
1570         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1571                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1572                           SYSS_HAS_RESET_STATUS),
1573         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1574         .sysc_fields    = &omap_hwmod_sysc_type1,
1575 };
1576
1577 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1578         .name           = "mcspi",
1579         .sysc           = &am33xx_mcspi_sysc,
1580         .rev            = OMAP4_MCSPI_REV,
1581 };
1582
1583 /* spi0 */
1584 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1585         { .irq = 65 + OMAP_INTC_START, },
1586         { .irq = -1 },
1587 };
1588
1589 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1590         { .name = "rx0", .dma_req = 17 },
1591         { .name = "tx0", .dma_req = 16 },
1592         { .name = "rx1", .dma_req = 19 },
1593         { .name = "tx1", .dma_req = 18 },
1594         { .dma_req = -1 }
1595 };
1596
1597 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1598         .num_chipselect = 2,
1599 };
1600 static struct omap_hwmod am33xx_spi0_hwmod = {
1601         .name           = "spi0",
1602         .class          = &am33xx_spi_hwmod_class,
1603         .clkdm_name     = "l4ls_clkdm",
1604         .mpu_irqs       = am33xx_spi0_irqs,
1605         .sdma_reqs      = am33xx_mcspi0_edma_reqs,
1606         .main_clk       = "dpll_per_m2_div4_ck",
1607         .prcm           = {
1608                 .omap4  = {
1609                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1610                         .modulemode     = MODULEMODE_SWCTRL,
1611                 },
1612         },
1613         .dev_attr       = &mcspi_attrib,
1614 };
1615
1616 /* spi1 */
1617 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1618         { .irq = 125 + OMAP_INTC_START, },
1619         { .irq = -1 },
1620 };
1621
1622 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1623         { .name = "rx0", .dma_req = 43 },
1624         { .name = "tx0", .dma_req = 42 },
1625         { .name = "rx1", .dma_req = 45 },
1626         { .name = "tx1", .dma_req = 44 },
1627         { .dma_req = -1 }
1628 };
1629
1630 static struct omap_hwmod am33xx_spi1_hwmod = {
1631         .name           = "spi1",
1632         .class          = &am33xx_spi_hwmod_class,
1633         .clkdm_name     = "l4ls_clkdm",
1634         .mpu_irqs       = am33xx_spi1_irqs,
1635         .sdma_reqs      = am33xx_mcspi1_edma_reqs,
1636         .main_clk       = "dpll_per_m2_div4_ck",
1637         .prcm           = {
1638                 .omap4  = {
1639                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1640                         .modulemode     = MODULEMODE_SWCTRL,
1641                 },
1642         },
1643         .dev_attr       = &mcspi_attrib,
1644 };
1645
1646 /*
1647  * 'spinlock' class
1648  * spinlock provides hardware assistance for synchronizing the
1649  * processes running on multiple processors
1650  */
1651 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1652         .name           = "spinlock",
1653 };
1654
1655 static struct omap_hwmod am33xx_spinlock_hwmod = {
1656         .name           = "spinlock",
1657         .class          = &am33xx_spinlock_hwmod_class,
1658         .clkdm_name     = "l4ls_clkdm",
1659         .main_clk       = "l4ls_gclk",
1660         .prcm           = {
1661                 .omap4  = {
1662                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1663                         .modulemode     = MODULEMODE_SWCTRL,
1664                 },
1665         },
1666 };
1667
1668 /* 'timer 2-7' class */
1669 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1670         .rev_offs       = 0x0000,
1671         .sysc_offs      = 0x0010,
1672         .syss_offs      = 0x0014,
1673         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1674         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1675                           SIDLE_SMART_WKUP),
1676         .sysc_fields    = &omap_hwmod_sysc_type2,
1677 };
1678
1679 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1680         .name           = "timer",
1681         .sysc           = &am33xx_timer_sysc,
1682 };
1683
1684 /* timer1 1ms */
1685 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1686         .rev_offs       = 0x0000,
1687         .sysc_offs      = 0x0010,
1688         .syss_offs      = 0x0014,
1689         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1690                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1691                         SYSS_HAS_RESET_STATUS),
1692         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1693         .sysc_fields    = &omap_hwmod_sysc_type1,
1694 };
1695
1696 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1697         .name           = "timer",
1698         .sysc           = &am33xx_timer1ms_sysc,
1699 };
1700
1701 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1702         { .irq = 67 + OMAP_INTC_START, },
1703         { .irq = -1 },
1704 };
1705
1706 static struct omap_hwmod am33xx_timer1_hwmod = {
1707         .name           = "timer1",
1708         .class          = &am33xx_timer1ms_hwmod_class,
1709         .clkdm_name     = "l4_wkup_clkdm",
1710         .mpu_irqs       = am33xx_timer1_irqs,
1711         .main_clk       = "timer1_fck",
1712         .prcm           = {
1713                 .omap4  = {
1714                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1715                         .modulemode     = MODULEMODE_SWCTRL,
1716                 },
1717         },
1718 };
1719
1720 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1721         { .irq = 68 + OMAP_INTC_START, },
1722         { .irq = -1 },
1723 };
1724
1725 static struct omap_hwmod am33xx_timer2_hwmod = {
1726         .name           = "timer2",
1727         .class          = &am33xx_timer_hwmod_class,
1728         .clkdm_name     = "l4ls_clkdm",
1729         .mpu_irqs       = am33xx_timer2_irqs,
1730         .main_clk       = "timer2_fck",
1731         .prcm           = {
1732                 .omap4  = {
1733                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1734                         .modulemode     = MODULEMODE_SWCTRL,
1735                 },
1736         },
1737 };
1738
1739 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1740         { .irq = 69 + OMAP_INTC_START, },
1741         { .irq = -1 },
1742 };
1743
1744 static struct omap_hwmod am33xx_timer3_hwmod = {
1745         .name           = "timer3",
1746         .class          = &am33xx_timer_hwmod_class,
1747         .clkdm_name     = "l4ls_clkdm",
1748         .mpu_irqs       = am33xx_timer3_irqs,
1749         .main_clk       = "timer3_fck",
1750         .prcm           = {
1751                 .omap4  = {
1752                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1753                         .modulemode     = MODULEMODE_SWCTRL,
1754                 },
1755         },
1756 };
1757
1758 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1759         { .irq = 92 + OMAP_INTC_START, },
1760         { .irq = -1 },
1761 };
1762
1763 static struct omap_hwmod am33xx_timer4_hwmod = {
1764         .name           = "timer4",
1765         .class          = &am33xx_timer_hwmod_class,
1766         .clkdm_name     = "l4ls_clkdm",
1767         .mpu_irqs       = am33xx_timer4_irqs,
1768         .main_clk       = "timer4_fck",
1769         .prcm           = {
1770                 .omap4  = {
1771                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1772                         .modulemode     = MODULEMODE_SWCTRL,
1773                 },
1774         },
1775 };
1776
1777 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1778         { .irq = 93 + OMAP_INTC_START, },
1779         { .irq = -1 },
1780 };
1781
1782 static struct omap_hwmod am33xx_timer5_hwmod = {
1783         .name           = "timer5",
1784         .class          = &am33xx_timer_hwmod_class,
1785         .clkdm_name     = "l4ls_clkdm",
1786         .mpu_irqs       = am33xx_timer5_irqs,
1787         .main_clk       = "timer5_fck",
1788         .prcm           = {
1789                 .omap4  = {
1790                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1791                         .modulemode     = MODULEMODE_SWCTRL,
1792                 },
1793         },
1794 };
1795
1796 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1797         { .irq = 94 + OMAP_INTC_START, },
1798         { .irq = -1 },
1799 };
1800
1801 static struct omap_hwmod am33xx_timer6_hwmod = {
1802         .name           = "timer6",
1803         .class          = &am33xx_timer_hwmod_class,
1804         .clkdm_name     = "l4ls_clkdm",
1805         .mpu_irqs       = am33xx_timer6_irqs,
1806         .main_clk       = "timer6_fck",
1807         .prcm           = {
1808                 .omap4  = {
1809                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1810                         .modulemode     = MODULEMODE_SWCTRL,
1811                 },
1812         },
1813 };
1814
1815 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1816         { .irq = 95 + OMAP_INTC_START, },
1817         { .irq = -1 },
1818 };
1819
1820 static struct omap_hwmod am33xx_timer7_hwmod = {
1821         .name           = "timer7",
1822         .class          = &am33xx_timer_hwmod_class,
1823         .clkdm_name     = "l4ls_clkdm",
1824         .mpu_irqs       = am33xx_timer7_irqs,
1825         .main_clk       = "timer7_fck",
1826         .prcm           = {
1827                 .omap4  = {
1828                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1829                         .modulemode     = MODULEMODE_SWCTRL,
1830                 },
1831         },
1832 };
1833
1834 /* tpcc */
1835 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1836         .name           = "tpcc",
1837 };
1838
1839 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1840         { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1841         { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1842         { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1843         { .irq = -1 },
1844 };
1845
1846 static struct omap_hwmod am33xx_tpcc_hwmod = {
1847         .name           = "tpcc",
1848         .class          = &am33xx_tpcc_hwmod_class,
1849         .clkdm_name     = "l3_clkdm",
1850         .mpu_irqs       = am33xx_tpcc_irqs,
1851         .main_clk       = "l3_gclk",
1852         .prcm           = {
1853                 .omap4  = {
1854                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1855                         .modulemode     = MODULEMODE_SWCTRL,
1856                 },
1857         },
1858 };
1859
1860 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1861         .rev_offs       = 0x0,
1862         .sysc_offs      = 0x10,
1863         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1864                           SYSC_HAS_MIDLEMODE),
1865         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1866         .sysc_fields    = &omap_hwmod_sysc_type2,
1867 };
1868
1869 /* 'tptc' class */
1870 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1871         .name           = "tptc",
1872         .sysc           = &am33xx_tptc_sysc,
1873 };
1874
1875 /* tptc0 */
1876 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1877         { .irq = 112 + OMAP_INTC_START, },
1878         { .irq = -1 },
1879 };
1880
1881 static struct omap_hwmod am33xx_tptc0_hwmod = {
1882         .name           = "tptc0",
1883         .class          = &am33xx_tptc_hwmod_class,
1884         .clkdm_name     = "l3_clkdm",
1885         .mpu_irqs       = am33xx_tptc0_irqs,
1886         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1887         .main_clk       = "l3_gclk",
1888         .prcm           = {
1889                 .omap4  = {
1890                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1891                         .modulemode     = MODULEMODE_SWCTRL,
1892                 },
1893         },
1894 };
1895
1896 /* tptc1 */
1897 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1898         { .irq = 113 + OMAP_INTC_START, },
1899         { .irq = -1 },
1900 };
1901
1902 static struct omap_hwmod am33xx_tptc1_hwmod = {
1903         .name           = "tptc1",
1904         .class          = &am33xx_tptc_hwmod_class,
1905         .clkdm_name     = "l3_clkdm",
1906         .mpu_irqs       = am33xx_tptc1_irqs,
1907         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1908         .main_clk       = "l3_gclk",
1909         .prcm           = {
1910                 .omap4  = {
1911                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1912                         .modulemode     = MODULEMODE_SWCTRL,
1913                 },
1914         },
1915 };
1916
1917 /* tptc2 */
1918 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1919         { .irq = 114 + OMAP_INTC_START, },
1920         { .irq = -1 },
1921 };
1922
1923 static struct omap_hwmod am33xx_tptc2_hwmod = {
1924         .name           = "tptc2",
1925         .class          = &am33xx_tptc_hwmod_class,
1926         .clkdm_name     = "l3_clkdm",
1927         .mpu_irqs       = am33xx_tptc2_irqs,
1928         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1929         .main_clk       = "l3_gclk",
1930         .prcm           = {
1931                 .omap4  = {
1932                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1933                         .modulemode     = MODULEMODE_SWCTRL,
1934                 },
1935         },
1936 };
1937
1938 /* 'uart' class */
1939 static struct omap_hwmod_class_sysconfig uart_sysc = {
1940         .rev_offs       = 0x50,
1941         .sysc_offs      = 0x54,
1942         .syss_offs      = 0x58,
1943         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1944                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1945         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1946                           SIDLE_SMART_WKUP),
1947         .sysc_fields    = &omap_hwmod_sysc_type1,
1948 };
1949
1950 static struct omap_hwmod_class uart_class = {
1951         .name           = "uart",
1952         .sysc           = &uart_sysc,
1953 };
1954
1955 /* uart1 */
1956 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1957         { .name = "tx", .dma_req = 26, },
1958         { .name = "rx", .dma_req = 27, },
1959         { .dma_req = -1 }
1960 };
1961
1962 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1963         { .irq = 72 + OMAP_INTC_START, },
1964         { .irq = -1 },
1965 };
1966
1967 static struct omap_hwmod am33xx_uart1_hwmod = {
1968         .name           = "uart1",
1969         .class          = &uart_class,
1970         .clkdm_name     = "l4_wkup_clkdm",
1971         .mpu_irqs       = am33xx_uart1_irqs,
1972         .sdma_reqs      = uart1_edma_reqs,
1973         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1974         .prcm           = {
1975                 .omap4  = {
1976                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1977                         .modulemode     = MODULEMODE_SWCTRL,
1978                 },
1979         },
1980 };
1981
1982 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1983         { .irq = 73 + OMAP_INTC_START, },
1984         { .irq = -1 },
1985 };
1986
1987 static struct omap_hwmod am33xx_uart2_hwmod = {
1988         .name           = "uart2",
1989         .class          = &uart_class,
1990         .clkdm_name     = "l4ls_clkdm",
1991         .mpu_irqs       = am33xx_uart2_irqs,
1992         .sdma_reqs      = uart1_edma_reqs,
1993         .main_clk       = "dpll_per_m2_div4_ck",
1994         .prcm           = {
1995                 .omap4  = {
1996                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1997                         .modulemode     = MODULEMODE_SWCTRL,
1998                 },
1999         },
2000 };
2001
2002 /* uart3 */
2003 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2004         { .name = "tx", .dma_req = 30, },
2005         { .name = "rx", .dma_req = 31, },
2006         { .dma_req = -1 }
2007 };
2008
2009 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2010         { .irq = 74 + OMAP_INTC_START, },
2011         { .irq = -1 },
2012 };
2013
2014 static struct omap_hwmod am33xx_uart3_hwmod = {
2015         .name           = "uart3",
2016         .class          = &uart_class,
2017         .clkdm_name     = "l4ls_clkdm",
2018         .mpu_irqs       = am33xx_uart3_irqs,
2019         .sdma_reqs      = uart3_edma_reqs,
2020         .main_clk       = "dpll_per_m2_div4_ck",
2021         .prcm           = {
2022                 .omap4  = {
2023                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2024                         .modulemode     = MODULEMODE_SWCTRL,
2025                 },
2026         },
2027 };
2028
2029 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2030         { .irq = 44 + OMAP_INTC_START, },
2031         { .irq = -1 },
2032 };
2033
2034 static struct omap_hwmod am33xx_uart4_hwmod = {
2035         .name           = "uart4",
2036         .class          = &uart_class,
2037         .clkdm_name     = "l4ls_clkdm",
2038         .mpu_irqs       = am33xx_uart4_irqs,
2039         .sdma_reqs      = uart1_edma_reqs,
2040         .main_clk       = "dpll_per_m2_div4_ck",
2041         .prcm           = {
2042                 .omap4  = {
2043                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2044                         .modulemode     = MODULEMODE_SWCTRL,
2045                 },
2046         },
2047 };
2048
2049 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2050         { .irq = 45 + OMAP_INTC_START, },
2051         { .irq = -1 },
2052 };
2053
2054 static struct omap_hwmod am33xx_uart5_hwmod = {
2055         .name           = "uart5",
2056         .class          = &uart_class,
2057         .clkdm_name     = "l4ls_clkdm",
2058         .mpu_irqs       = am33xx_uart5_irqs,
2059         .sdma_reqs      = uart1_edma_reqs,
2060         .main_clk       = "dpll_per_m2_div4_ck",
2061         .prcm           = {
2062                 .omap4  = {
2063                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2064                         .modulemode     = MODULEMODE_SWCTRL,
2065                 },
2066         },
2067 };
2068
2069 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2070         { .irq = 46 + OMAP_INTC_START, },
2071         { .irq = -1 },
2072 };
2073
2074 static struct omap_hwmod am33xx_uart6_hwmod = {
2075         .name           = "uart6",
2076         .class          = &uart_class,
2077         .clkdm_name     = "l4ls_clkdm",
2078         .mpu_irqs       = am33xx_uart6_irqs,
2079         .sdma_reqs      = uart1_edma_reqs,
2080         .main_clk       = "dpll_per_m2_div4_ck",
2081         .prcm           = {
2082                 .omap4  = {
2083                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2084                         .modulemode     = MODULEMODE_SWCTRL,
2085                 },
2086         },
2087 };
2088
2089 /* 'wd_timer' class */
2090 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2091         .name           = "wd_timer",
2092 };
2093
2094 /*
2095  * XXX: device.c file uses hardcoded name for watchdog timer
2096  * driver "wd_timer2, so we are also using same name as of now...
2097  */
2098 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2099         .name           = "wd_timer2",
2100         .class          = &am33xx_wd_timer_hwmod_class,
2101         .clkdm_name     = "l4_wkup_clkdm",
2102         .main_clk       = "wdt1_fck",
2103         .prcm           = {
2104                 .omap4  = {
2105                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2106                         .modulemode     = MODULEMODE_SWCTRL,
2107                 },
2108         },
2109 };
2110
2111 /*
2112  * 'usb_otg' class
2113  * high-speed on-the-go universal serial bus (usb_otg) controller
2114  */
2115 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2116         .rev_offs       = 0x0,
2117         .sysc_offs      = 0x10,
2118         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2119         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2120                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2121         .sysc_fields    = &omap_hwmod_sysc_type2,
2122 };
2123
2124 static struct omap_hwmod_class am33xx_usbotg_class = {
2125         .name           = "usbotg",
2126         .sysc           = &am33xx_usbhsotg_sysc,
2127 };
2128
2129 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2130         { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2131         { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2132         { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2133         { .irq = -1, },
2134 };
2135
2136 static struct omap_hwmod am33xx_usbss_hwmod = {
2137         .name           = "usb_otg_hs",
2138         .class          = &am33xx_usbotg_class,
2139         .clkdm_name     = "l3s_clkdm",
2140         .mpu_irqs       = am33xx_usbss_mpu_irqs,
2141         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2142         .main_clk       = "usbotg_fck",
2143         .prcm           = {
2144                 .omap4  = {
2145                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2146                         .modulemode     = MODULEMODE_SWCTRL,
2147                 },
2148         },
2149 };
2150
2151
2152 /*
2153  * Interfaces
2154  */
2155
2156 /* l4 fw -> emif fw */
2157 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2158         .master         = &am33xx_l4_fw_hwmod,
2159         .slave          = &am33xx_emif_fw_hwmod,
2160         .clk            = "l4fw_gclk",
2161         .user           = OCP_USER_MPU,
2162 };
2163
2164 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2165         {
2166                 .pa_start       = 0x4c000000,
2167                 .pa_end         = 0x4c000fff,
2168                 .flags          = ADDR_TYPE_RT
2169         },
2170         { }
2171 };
2172 /* l3 main -> emif */
2173 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2174         .master         = &am33xx_l3_main_hwmod,
2175         .slave          = &am33xx_emif_hwmod,
2176         .clk            = "dpll_core_m4_ck",
2177         .addr           = am33xx_emif_addrs,
2178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2179 };
2180
2181 /* mpu -> l3 main */
2182 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2183         .master         = &am33xx_mpu_hwmod,
2184         .slave          = &am33xx_l3_main_hwmod,
2185         .clk            = "dpll_mpu_m2_ck",
2186         .user           = OCP_USER_MPU,
2187 };
2188
2189 /* l3 main -> l4 hs */
2190 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2191         .master         = &am33xx_l3_main_hwmod,
2192         .slave          = &am33xx_l4_hs_hwmod,
2193         .clk            = "l3s_gclk",
2194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2195 };
2196
2197 /* l3 main -> l3 s */
2198 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2199         .master         = &am33xx_l3_main_hwmod,
2200         .slave          = &am33xx_l3_s_hwmod,
2201         .clk            = "l3s_gclk",
2202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2203 };
2204
2205 /* l3 s -> l4 per/ls */
2206 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2207         .master         = &am33xx_l3_s_hwmod,
2208         .slave          = &am33xx_l4_ls_hwmod,
2209         .clk            = "l3s_gclk",
2210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212
2213 /* l3 s -> l4 wkup */
2214 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2215         .master         = &am33xx_l3_s_hwmod,
2216         .slave          = &am33xx_l4_wkup_hwmod,
2217         .clk            = "l3s_gclk",
2218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2219 };
2220
2221 /* l3 s -> l4 fw */
2222 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2223         .master         = &am33xx_l3_s_hwmod,
2224         .slave          = &am33xx_l4_fw_hwmod,
2225         .clk            = "l3s_gclk",
2226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2227 };
2228
2229 /* l3 main -> l3 instr */
2230 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2231         .master         = &am33xx_l3_main_hwmod,
2232         .slave          = &am33xx_l3_instr_hwmod,
2233         .clk            = "l3s_gclk",
2234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236
2237 /* mpu -> prcm */
2238 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2239         .master         = &am33xx_mpu_hwmod,
2240         .slave          = &am33xx_prcm_hwmod,
2241         .clk            = "dpll_mpu_m2_ck",
2242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2243 };
2244
2245 /* l3 s -> l3 main*/
2246 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2247         .master         = &am33xx_l3_s_hwmod,
2248         .slave          = &am33xx_l3_main_hwmod,
2249         .clk            = "l3s_gclk",
2250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2251 };
2252
2253 /* pru-icss -> l3 main */
2254 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2255         .master         = &am33xx_pruss_hwmod,
2256         .slave          = &am33xx_l3_main_hwmod,
2257         .clk            = "l3_gclk",
2258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261 /* wkup m3 -> l4 wkup */
2262 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2263         .master         = &am33xx_wkup_m3_hwmod,
2264         .slave          = &am33xx_l4_wkup_hwmod,
2265         .clk            = "dpll_core_m4_div2_ck",
2266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2267 };
2268
2269 /* gfx -> l3 main */
2270 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2271         .master         = &am33xx_gfx_hwmod,
2272         .slave          = &am33xx_l3_main_hwmod,
2273         .clk            = "dpll_core_m4_ck",
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276
2277 /* l4 wkup -> wkup m3 */
2278 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2279         {
2280                 .name           = "umem",
2281                 .pa_start       = 0x44d00000,
2282                 .pa_end         = 0x44d00000 + SZ_16K - 1,
2283                 .flags          = ADDR_TYPE_RT
2284         },
2285         {
2286                 .name           = "dmem",
2287                 .pa_start       = 0x44d80000,
2288                 .pa_end         = 0x44d80000 + SZ_8K - 1,
2289                 .flags          = ADDR_TYPE_RT
2290         },
2291         { }
2292 };
2293
2294 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2295         .master         = &am33xx_l4_wkup_hwmod,
2296         .slave          = &am33xx_wkup_m3_hwmod,
2297         .clk            = "dpll_core_m4_div2_ck",
2298         .addr           = am33xx_wkup_m3_addrs,
2299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2300 };
2301
2302 /* l4 hs -> pru-icss */
2303 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2304         {
2305                 .pa_start       = 0x4a300000,
2306                 .pa_end         = 0x4a300000 + SZ_512K - 1,
2307                 .flags          = ADDR_TYPE_RT
2308         },
2309         { }
2310 };
2311
2312 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2313         .master         = &am33xx_l4_hs_hwmod,
2314         .slave          = &am33xx_pruss_hwmod,
2315         .clk            = "dpll_core_m4_ck",
2316         .addr           = am33xx_pruss_addrs,
2317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2318 };
2319
2320 /* l3 main -> gfx */
2321 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2322         {
2323                 .pa_start       = 0x56000000,
2324                 .pa_end         = 0x56000000 + SZ_16M - 1,
2325                 .flags          = ADDR_TYPE_RT
2326         },
2327         { }
2328 };
2329
2330 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2331         .master         = &am33xx_l3_main_hwmod,
2332         .slave          = &am33xx_gfx_hwmod,
2333         .clk            = "dpll_core_m4_ck",
2334         .addr           = am33xx_gfx_addrs,
2335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2336 };
2337
2338 /* l4 wkup -> smartreflex0 */
2339 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2340         {
2341                 .pa_start       = 0x44e37000,
2342                 .pa_end         = 0x44e37000 + SZ_4K - 1,
2343                 .flags          = ADDR_TYPE_RT
2344         },
2345         { }
2346 };
2347
2348 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2349         .master         = &am33xx_l4_wkup_hwmod,
2350         .slave          = &am33xx_smartreflex0_hwmod,
2351         .clk            = "dpll_core_m4_div2_ck",
2352         .addr           = am33xx_smartreflex0_addrs,
2353         .user           = OCP_USER_MPU,
2354 };
2355
2356 /* l4 wkup -> smartreflex1 */
2357 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2358         {
2359                 .pa_start       = 0x44e39000,
2360                 .pa_end         = 0x44e39000 + SZ_4K - 1,
2361                 .flags          = ADDR_TYPE_RT
2362         },
2363         { }
2364 };
2365
2366 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2367         .master         = &am33xx_l4_wkup_hwmod,
2368         .slave          = &am33xx_smartreflex1_hwmod,
2369         .clk            = "dpll_core_m4_div2_ck",
2370         .addr           = am33xx_smartreflex1_addrs,
2371         .user           = OCP_USER_MPU,
2372 };
2373
2374 /* l4 wkup -> control */
2375 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2376         {
2377                 .pa_start       = 0x44e10000,
2378                 .pa_end         = 0x44e10000 + SZ_8K - 1,
2379                 .flags          = ADDR_TYPE_RT
2380         },
2381         { }
2382 };
2383
2384 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2385         .master         = &am33xx_l4_wkup_hwmod,
2386         .slave          = &am33xx_control_hwmod,
2387         .clk            = "dpll_core_m4_div2_ck",
2388         .addr           = am33xx_control_addrs,
2389         .user           = OCP_USER_MPU,
2390 };
2391
2392 /* l4 wkup -> rtc */
2393 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2394         {
2395                 .pa_start       = 0x44e3e000,
2396                 .pa_end         = 0x44e3e000 + SZ_4K - 1,
2397                 .flags          = ADDR_TYPE_RT
2398         },
2399         { }
2400 };
2401
2402 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2403         .master         = &am33xx_l4_wkup_hwmod,
2404         .slave          = &am33xx_rtc_hwmod,
2405         .clk            = "clkdiv32k_ick",
2406         .addr           = am33xx_rtc_addrs,
2407         .user           = OCP_USER_MPU,
2408 };
2409
2410 /* l4 per/ls -> DCAN0 */
2411 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2412         {
2413                 .pa_start       = 0x481CC000,
2414                 .pa_end         = 0x481CC000 + SZ_4K - 1,
2415                 .flags          = ADDR_TYPE_RT
2416         },
2417         { }
2418 };
2419
2420 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2421         .master         = &am33xx_l4_ls_hwmod,
2422         .slave          = &am33xx_dcan0_hwmod,
2423         .clk            = "l4ls_gclk",
2424         .addr           = am33xx_dcan0_addrs,
2425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2426 };
2427
2428 /* l4 per/ls -> DCAN1 */
2429 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2430         {
2431                 .pa_start       = 0x481D0000,
2432                 .pa_end         = 0x481D0000 + SZ_4K - 1,
2433                 .flags          = ADDR_TYPE_RT
2434         },
2435         { }
2436 };
2437
2438 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2439         .master         = &am33xx_l4_ls_hwmod,
2440         .slave          = &am33xx_dcan1_hwmod,
2441         .clk            = "l4ls_gclk",
2442         .addr           = am33xx_dcan1_addrs,
2443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 /* l4 per/ls -> GPIO2 */
2447 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2448         {
2449                 .pa_start       = 0x4804C000,
2450                 .pa_end         = 0x4804C000 + SZ_4K - 1,
2451                 .flags          = ADDR_TYPE_RT,
2452         },
2453         { }
2454 };
2455
2456 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2457         .master         = &am33xx_l4_ls_hwmod,
2458         .slave          = &am33xx_gpio1_hwmod,
2459         .clk            = "l4ls_gclk",
2460         .addr           = am33xx_gpio1_addrs,
2461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2462 };
2463
2464 /* l4 per/ls -> gpio3 */
2465 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2466         {
2467                 .pa_start       = 0x481AC000,
2468                 .pa_end         = 0x481AC000 + SZ_4K - 1,
2469                 .flags          = ADDR_TYPE_RT,
2470         },
2471         { }
2472 };
2473
2474 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2475         .master         = &am33xx_l4_ls_hwmod,
2476         .slave          = &am33xx_gpio2_hwmod,
2477         .clk            = "l4ls_gclk",
2478         .addr           = am33xx_gpio2_addrs,
2479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 /* l4 per/ls -> gpio4 */
2483 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2484         {
2485                 .pa_start       = 0x481AE000,
2486                 .pa_end         = 0x481AE000 + SZ_4K - 1,
2487                 .flags          = ADDR_TYPE_RT,
2488         },
2489         { }
2490 };
2491
2492 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2493         .master         = &am33xx_l4_ls_hwmod,
2494         .slave          = &am33xx_gpio3_hwmod,
2495         .clk            = "l4ls_gclk",
2496         .addr           = am33xx_gpio3_addrs,
2497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2498 };
2499
2500 /* L4 WKUP -> I2C1 */
2501 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2502         {
2503                 .pa_start       = 0x44E0B000,
2504                 .pa_end         = 0x44E0B000 + SZ_4K - 1,
2505                 .flags          = ADDR_TYPE_RT,
2506         },
2507         { }
2508 };
2509
2510 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2511         .master         = &am33xx_l4_wkup_hwmod,
2512         .slave          = &am33xx_i2c1_hwmod,
2513         .clk            = "dpll_core_m4_div2_ck",
2514         .addr           = am33xx_i2c1_addr_space,
2515         .user           = OCP_USER_MPU,
2516 };
2517
2518 /* L4 WKUP -> GPIO1 */
2519 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2520         {
2521                 .pa_start       = 0x44E07000,
2522                 .pa_end         = 0x44E07000 + SZ_4K - 1,
2523                 .flags          = ADDR_TYPE_RT,
2524         },
2525         { }
2526 };
2527
2528 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2529         .master         = &am33xx_l4_wkup_hwmod,
2530         .slave          = &am33xx_gpio0_hwmod,
2531         .clk            = "dpll_core_m4_div2_ck",
2532         .addr           = am33xx_gpio0_addrs,
2533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2535
2536 /* L4 WKUP -> ADC_TSC */
2537 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2538         {
2539                 .pa_start       = 0x44E0D000,
2540                 .pa_end         = 0x44E0D000 + SZ_8K - 1,
2541                 .flags          = ADDR_TYPE_RT
2542         },
2543         { }
2544 };
2545
2546 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2547         .master         = &am33xx_l4_wkup_hwmod,
2548         .slave          = &am33xx_adc_tsc_hwmod,
2549         .clk            = "dpll_core_m4_div2_ck",
2550         .addr           = am33xx_adc_tsc_addrs,
2551         .user           = OCP_USER_MPU,
2552 };
2553
2554 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2555         /* cpsw ss */
2556         {
2557                 .pa_start       = 0x4a100000,
2558                 .pa_end         = 0x4a100000 + SZ_2K - 1,
2559         },
2560         /* cpsw wr */
2561         {
2562                 .pa_start       = 0x4a101200,
2563                 .pa_end         = 0x4a101200 + SZ_256 - 1,
2564                 .flags          = ADDR_TYPE_RT,
2565         },
2566         { }
2567 };
2568
2569 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2570         .master         = &am33xx_l4_hs_hwmod,
2571         .slave          = &am33xx_cpgmac0_hwmod,
2572         .clk            = "cpsw_125mhz_gclk",
2573         .addr           = am33xx_cpgmac0_addr_space,
2574         .user           = OCP_USER_MPU,
2575 };
2576
2577 static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2578         {
2579                 .pa_start       = 0x4A101000,
2580                 .pa_end         = 0x4A101000 + SZ_256 - 1,
2581         },
2582         { }
2583 };
2584
2585 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2586         .master         = &am33xx_cpgmac0_hwmod,
2587         .slave          = &am33xx_mdio_hwmod,
2588         .addr           = am33xx_mdio_addr_space,
2589         .user           = OCP_USER_MPU,
2590 };
2591
2592 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2593         {
2594                 .pa_start       = 0x48080000,
2595                 .pa_end         = 0x48080000 + SZ_8K - 1,
2596                 .flags          = ADDR_TYPE_RT
2597         },
2598         { }
2599 };
2600
2601 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2602         .master         = &am33xx_l4_ls_hwmod,
2603         .slave          = &am33xx_elm_hwmod,
2604         .clk            = "l4ls_gclk",
2605         .addr           = am33xx_elm_addr_space,
2606         .user           = OCP_USER_MPU,
2607 };
2608
2609 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2610         {
2611                 .pa_start       = 0x48300000,
2612                 .pa_end         = 0x48300000 + SZ_16 - 1,
2613                 .flags          = ADDR_TYPE_RT
2614         },
2615         { }
2616 };
2617
2618 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2619         .master         = &am33xx_l4_ls_hwmod,
2620         .slave          = &am33xx_epwmss0_hwmod,
2621         .clk            = "l4ls_gclk",
2622         .addr           = am33xx_epwmss0_addr_space,
2623         .user           = OCP_USER_MPU,
2624 };
2625
2626 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2627         {
2628                 .pa_start       = 0x48300100,
2629                 .pa_end         = 0x48300100 + SZ_128 - 1,
2630         },
2631         { }
2632 };
2633
2634 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2635         .master         = &am33xx_epwmss0_hwmod,
2636         .slave          = &am33xx_ecap0_hwmod,
2637         .clk            = "l4ls_gclk",
2638         .addr           = am33xx_ecap0_addr_space,
2639         .user           = OCP_USER_MPU,
2640 };
2641
2642 static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2643         {
2644                 .pa_start       = 0x48300180,
2645                 .pa_end         = 0x48300180 + SZ_128 - 1,
2646         },
2647         { }
2648 };
2649
2650 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2651         .master         = &am33xx_epwmss0_hwmod,
2652         .slave          = &am33xx_eqep0_hwmod,
2653         .clk            = "l4ls_gclk",
2654         .addr           = am33xx_eqep0_addr_space,
2655         .user           = OCP_USER_MPU,
2656 };
2657
2658 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2659         {
2660                 .pa_start       = 0x48300200,
2661                 .pa_end         = 0x48300200 + SZ_128 - 1,
2662         },
2663         { }
2664 };
2665
2666 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2667         .master         = &am33xx_epwmss0_hwmod,
2668         .slave          = &am33xx_ehrpwm0_hwmod,
2669         .clk            = "l4ls_gclk",
2670         .addr           = am33xx_ehrpwm0_addr_space,
2671         .user           = OCP_USER_MPU,
2672 };
2673
2674
2675 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2676         {
2677                 .pa_start       = 0x48302000,
2678                 .pa_end         = 0x48302000 + SZ_16 - 1,
2679                 .flags          = ADDR_TYPE_RT
2680         },
2681         { }
2682 };
2683
2684 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2685         .master         = &am33xx_l4_ls_hwmod,
2686         .slave          = &am33xx_epwmss1_hwmod,
2687         .clk            = "l4ls_gclk",
2688         .addr           = am33xx_epwmss1_addr_space,
2689         .user           = OCP_USER_MPU,
2690 };
2691
2692 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2693         {
2694                 .pa_start       = 0x48302100,
2695                 .pa_end         = 0x48302100 + SZ_128 - 1,
2696         },
2697         { }
2698 };
2699
2700 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2701         .master         = &am33xx_epwmss1_hwmod,
2702         .slave          = &am33xx_ecap1_hwmod,
2703         .clk            = "l4ls_gclk",
2704         .addr           = am33xx_ecap1_addr_space,
2705         .user           = OCP_USER_MPU,
2706 };
2707
2708 static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2709         {
2710                 .pa_start       = 0x48302180,
2711                 .pa_end         = 0x48302180 + SZ_128 - 1,
2712         },
2713         { }
2714 };
2715
2716 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2717         .master         = &am33xx_epwmss1_hwmod,
2718         .slave          = &am33xx_eqep1_hwmod,
2719         .clk            = "l4ls_gclk",
2720         .addr           = am33xx_eqep1_addr_space,
2721         .user           = OCP_USER_MPU,
2722 };
2723
2724 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2725         {
2726                 .pa_start       = 0x48302200,
2727                 .pa_end         = 0x48302200 + SZ_128 - 1,
2728         },
2729         { }
2730 };
2731
2732 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2733         .master         = &am33xx_epwmss1_hwmod,
2734         .slave          = &am33xx_ehrpwm1_hwmod,
2735         .clk            = "l4ls_gclk",
2736         .addr           = am33xx_ehrpwm1_addr_space,
2737         .user           = OCP_USER_MPU,
2738 };
2739
2740 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2741         {
2742                 .pa_start       = 0x48304000,
2743                 .pa_end         = 0x48304000 + SZ_16 - 1,
2744                 .flags          = ADDR_TYPE_RT
2745         },
2746         { }
2747 };
2748
2749 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2750         .master         = &am33xx_l4_ls_hwmod,
2751         .slave          = &am33xx_epwmss2_hwmod,
2752         .clk            = "l4ls_gclk",
2753         .addr           = am33xx_epwmss2_addr_space,
2754         .user           = OCP_USER_MPU,
2755 };
2756
2757 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2758         {
2759                 .pa_start       = 0x48304100,
2760                 .pa_end         = 0x48304100 + SZ_128 - 1,
2761         },
2762         { }
2763 };
2764
2765 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2766         .master         = &am33xx_epwmss2_hwmod,
2767         .slave          = &am33xx_ecap2_hwmod,
2768         .clk            = "l4ls_gclk",
2769         .addr           = am33xx_ecap2_addr_space,
2770         .user           = OCP_USER_MPU,
2771 };
2772
2773 static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2774         {
2775                 .pa_start       = 0x48304180,
2776                 .pa_end         = 0x48304180 + SZ_128 - 1,
2777         },
2778         { }
2779 };
2780
2781 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2782         .master         = &am33xx_epwmss2_hwmod,
2783         .slave          = &am33xx_eqep2_hwmod,
2784         .clk            = "l4ls_gclk",
2785         .addr           = am33xx_eqep2_addr_space,
2786         .user           = OCP_USER_MPU,
2787 };
2788
2789 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2790         {
2791                 .pa_start       = 0x48304200,
2792                 .pa_end         = 0x48304200 + SZ_128 - 1,
2793         },
2794         { }
2795 };
2796
2797 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2798         .master         = &am33xx_epwmss2_hwmod,
2799         .slave          = &am33xx_ehrpwm2_hwmod,
2800         .clk            = "l4ls_gclk",
2801         .addr           = am33xx_ehrpwm2_addr_space,
2802         .user           = OCP_USER_MPU,
2803 };
2804
2805 /* l3s cfg -> gpmc */
2806 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2807         {
2808                 .pa_start       = 0x50000000,
2809                 .pa_end         = 0x50000000 + SZ_8K - 1,
2810                 .flags          = ADDR_TYPE_RT,
2811         },
2812         { }
2813 };
2814
2815 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2816         .master         = &am33xx_l3_s_hwmod,
2817         .slave          = &am33xx_gpmc_hwmod,
2818         .clk            = "l3s_gclk",
2819         .addr           = am33xx_gpmc_addr_space,
2820         .user           = OCP_USER_MPU,
2821 };
2822
2823 /* i2c2 */
2824 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2825         {
2826                 .pa_start       = 0x4802A000,
2827                 .pa_end         = 0x4802A000 + SZ_4K - 1,
2828                 .flags          = ADDR_TYPE_RT,
2829         },
2830         { }
2831 };
2832
2833 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2834         .master         = &am33xx_l4_ls_hwmod,
2835         .slave          = &am33xx_i2c2_hwmod,
2836         .clk            = "l4ls_gclk",
2837         .addr           = am33xx_i2c2_addr_space,
2838         .user           = OCP_USER_MPU,
2839 };
2840
2841 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2842         {
2843                 .pa_start       = 0x4819C000,
2844                 .pa_end         = 0x4819C000 + SZ_4K - 1,
2845                 .flags          = ADDR_TYPE_RT
2846         },
2847         { }
2848 };
2849
2850 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2851         .master         = &am33xx_l4_ls_hwmod,
2852         .slave          = &am33xx_i2c3_hwmod,
2853         .clk            = "l4ls_gclk",
2854         .addr           = am33xx_i2c3_addr_space,
2855         .user           = OCP_USER_MPU,
2856 };
2857
2858 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2859         {
2860                 .pa_start       = 0x4830E000,
2861                 .pa_end         = 0x4830E000 + SZ_8K - 1,
2862                 .flags          = ADDR_TYPE_RT,
2863         },
2864         { }
2865 };
2866
2867 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2868         .master         = &am33xx_l3_main_hwmod,
2869         .slave          = &am33xx_lcdc_hwmod,
2870         .clk            = "dpll_core_m4_ck",
2871         .addr           = am33xx_lcdc_addr_space,
2872         .user           = OCP_USER_MPU,
2873 };
2874
2875 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2876         {
2877                 .pa_start       = 0x480C8000,
2878                 .pa_end         = 0x480C8000 + (SZ_4K - 1),
2879                 .flags          = ADDR_TYPE_RT
2880         },
2881         { }
2882 };
2883
2884 /* l4 ls -> mailbox */
2885 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2886         .master         = &am33xx_l4_ls_hwmod,
2887         .slave          = &am33xx_mailbox_hwmod,
2888         .clk            = "l4ls_gclk",
2889         .addr           = am33xx_mailbox_addrs,
2890         .user           = OCP_USER_MPU,
2891 };
2892
2893 /* l4 ls -> spinlock */
2894 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2895         {
2896                 .pa_start       = 0x480Ca000,
2897                 .pa_end         = 0x480Ca000 + SZ_4K - 1,
2898                 .flags          = ADDR_TYPE_RT
2899         },
2900         { }
2901 };
2902
2903 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2904         .master         = &am33xx_l4_ls_hwmod,
2905         .slave          = &am33xx_spinlock_hwmod,
2906         .clk            = "l4ls_gclk",
2907         .addr           = am33xx_spinlock_addrs,
2908         .user           = OCP_USER_MPU,
2909 };
2910
2911 /* l4 ls -> mcasp0 */
2912 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2913         {
2914                 .pa_start       = 0x48038000,
2915                 .pa_end         = 0x48038000 + SZ_8K - 1,
2916                 .flags          = ADDR_TYPE_RT
2917         },
2918         { }
2919 };
2920
2921 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2922         .master         = &am33xx_l4_ls_hwmod,
2923         .slave          = &am33xx_mcasp0_hwmod,
2924         .clk            = "l4ls_gclk",
2925         .addr           = am33xx_mcasp0_addr_space,
2926         .user           = OCP_USER_MPU,
2927 };
2928
2929 /* l3 s -> mcasp0 data */
2930 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2931         {
2932                 .pa_start       = 0x46000000,
2933                 .pa_end         = 0x46000000 + SZ_4M - 1,
2934                 .flags          = ADDR_TYPE_RT
2935         },
2936         { }
2937 };
2938
2939 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2940         .master         = &am33xx_l3_s_hwmod,
2941         .slave          = &am33xx_mcasp0_hwmod,
2942         .clk            = "l3s_gclk",
2943         .addr           = am33xx_mcasp0_data_addr_space,
2944         .user           = OCP_USER_SDMA,
2945 };
2946
2947 /* l4 ls -> mcasp1 */
2948 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2949         {
2950                 .pa_start       = 0x4803C000,
2951                 .pa_end         = 0x4803C000 + SZ_8K - 1,
2952                 .flags          = ADDR_TYPE_RT
2953         },
2954         { }
2955 };
2956
2957 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2958         .master         = &am33xx_l4_ls_hwmod,
2959         .slave          = &am33xx_mcasp1_hwmod,
2960         .clk            = "l4ls_gclk",
2961         .addr           = am33xx_mcasp1_addr_space,
2962         .user           = OCP_USER_MPU,
2963 };
2964
2965 /* l3 s -> mcasp1 data */
2966 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2967         {
2968                 .pa_start       = 0x46400000,
2969                 .pa_end         = 0x46400000 + SZ_4M - 1,
2970                 .flags          = ADDR_TYPE_RT
2971         },
2972         { }
2973 };
2974
2975 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
2976         .master         = &am33xx_l3_s_hwmod,
2977         .slave          = &am33xx_mcasp1_hwmod,
2978         .clk            = "l3s_gclk",
2979         .addr           = am33xx_mcasp1_data_addr_space,
2980         .user           = OCP_USER_SDMA,
2981 };
2982
2983 /* l4 ls -> mmc0 */
2984 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2985         {
2986                 .pa_start       = 0x48060100,
2987                 .pa_end         = 0x48060100 + SZ_4K - 1,
2988                 .flags          = ADDR_TYPE_RT,
2989         },
2990         { }
2991 };
2992
2993 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2994         .master         = &am33xx_l4_ls_hwmod,
2995         .slave          = &am33xx_mmc0_hwmod,
2996         .clk            = "l4ls_gclk",
2997         .addr           = am33xx_mmc0_addr_space,
2998         .user           = OCP_USER_MPU,
2999 };
3000
3001 /* l4 ls -> mmc1 */
3002 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
3003         {
3004                 .pa_start       = 0x481d8100,
3005                 .pa_end         = 0x481d8100 + SZ_4K - 1,
3006                 .flags          = ADDR_TYPE_RT,
3007         },
3008         { }
3009 };
3010
3011 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
3012         .master         = &am33xx_l4_ls_hwmod,
3013         .slave          = &am33xx_mmc1_hwmod,
3014         .clk            = "l4ls_gclk",
3015         .addr           = am33xx_mmc1_addr_space,
3016         .user           = OCP_USER_MPU,
3017 };
3018
3019 /* l3 s -> mmc2 */
3020 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
3021         {
3022                 .pa_start       = 0x47810100,
3023                 .pa_end         = 0x47810100 + SZ_64K - 1,
3024                 .flags          = ADDR_TYPE_RT,
3025         },
3026         { }
3027 };
3028
3029 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3030         .master         = &am33xx_l3_s_hwmod,
3031         .slave          = &am33xx_mmc2_hwmod,
3032         .clk            = "l3s_gclk",
3033         .addr           = am33xx_mmc2_addr_space,
3034         .user           = OCP_USER_MPU,
3035 };
3036
3037 /* l4 ls -> mcspi0 */
3038 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3039         {
3040                 .pa_start       = 0x48030000,
3041                 .pa_end         = 0x48030000 + SZ_1K - 1,
3042                 .flags          = ADDR_TYPE_RT,
3043         },
3044         { }
3045 };
3046
3047 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3048         .master         = &am33xx_l4_ls_hwmod,
3049         .slave          = &am33xx_spi0_hwmod,
3050         .clk            = "l4ls_gclk",
3051         .addr           = am33xx_mcspi0_addr_space,
3052         .user           = OCP_USER_MPU,
3053 };
3054
3055 /* l4 ls -> mcspi1 */
3056 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3057         {
3058                 .pa_start       = 0x481A0000,
3059                 .pa_end         = 0x481A0000 + SZ_1K - 1,
3060                 .flags          = ADDR_TYPE_RT,
3061         },
3062         { }
3063 };
3064
3065 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3066         .master         = &am33xx_l4_ls_hwmod,
3067         .slave          = &am33xx_spi1_hwmod,
3068         .clk            = "l4ls_gclk",
3069         .addr           = am33xx_mcspi1_addr_space,
3070         .user           = OCP_USER_MPU,
3071 };
3072
3073 /* l4 wkup -> timer1 */
3074 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3075         {
3076                 .pa_start       = 0x44E31000,
3077                 .pa_end         = 0x44E31000 + SZ_1K - 1,
3078                 .flags          = ADDR_TYPE_RT
3079         },
3080         { }
3081 };
3082
3083 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3084         .master         = &am33xx_l4_wkup_hwmod,
3085         .slave          = &am33xx_timer1_hwmod,
3086         .clk            = "dpll_core_m4_div2_ck",
3087         .addr           = am33xx_timer1_addr_space,
3088         .user           = OCP_USER_MPU,
3089 };
3090
3091 /* l4 per -> timer2 */
3092 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3093         {
3094                 .pa_start       = 0x48040000,
3095                 .pa_end         = 0x48040000 + SZ_1K - 1,
3096                 .flags          = ADDR_TYPE_RT
3097         },
3098         { }
3099 };
3100
3101 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3102         .master         = &am33xx_l4_ls_hwmod,
3103         .slave          = &am33xx_timer2_hwmod,
3104         .clk            = "l4ls_gclk",
3105         .addr           = am33xx_timer2_addr_space,
3106         .user           = OCP_USER_MPU,
3107 };
3108
3109 /* l4 per -> timer3 */
3110 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3111         {
3112                 .pa_start       = 0x48042000,
3113                 .pa_end         = 0x48042000 + SZ_1K - 1,
3114                 .flags          = ADDR_TYPE_RT
3115         },
3116         { }
3117 };
3118
3119 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3120         .master         = &am33xx_l4_ls_hwmod,
3121         .slave          = &am33xx_timer3_hwmod,
3122         .clk            = "l4ls_gclk",
3123         .addr           = am33xx_timer3_addr_space,
3124         .user           = OCP_USER_MPU,
3125 };
3126
3127 /* l4 per -> timer4 */
3128 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3129         {
3130                 .pa_start       = 0x48044000,
3131                 .pa_end         = 0x48044000 + SZ_1K - 1,
3132                 .flags          = ADDR_TYPE_RT
3133         },
3134         { }
3135 };
3136
3137 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3138         .master         = &am33xx_l4_ls_hwmod,
3139         .slave          = &am33xx_timer4_hwmod,
3140         .clk            = "l4ls_gclk",
3141         .addr           = am33xx_timer4_addr_space,
3142         .user           = OCP_USER_MPU,
3143 };
3144
3145 /* l4 per -> timer5 */
3146 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3147         {
3148                 .pa_start       = 0x48046000,
3149                 .pa_end         = 0x48046000 + SZ_1K - 1,
3150                 .flags          = ADDR_TYPE_RT
3151         },
3152         { }
3153 };
3154
3155 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3156         .master         = &am33xx_l4_ls_hwmod,
3157         .slave          = &am33xx_timer5_hwmod,
3158         .clk            = "l4ls_gclk",
3159         .addr           = am33xx_timer5_addr_space,
3160         .user           = OCP_USER_MPU,
3161 };
3162
3163 /* l4 per -> timer6 */
3164 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3165         {
3166                 .pa_start       = 0x48048000,
3167                 .pa_end         = 0x48048000 + SZ_1K - 1,
3168                 .flags          = ADDR_TYPE_RT
3169         },
3170         { }
3171 };
3172
3173 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3174         .master         = &am33xx_l4_ls_hwmod,
3175         .slave          = &am33xx_timer6_hwmod,
3176         .clk            = "l4ls_gclk",
3177         .addr           = am33xx_timer6_addr_space,
3178         .user           = OCP_USER_MPU,
3179 };
3180
3181 /* l4 per -> timer7 */
3182 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3183         {
3184                 .pa_start       = 0x4804A000,
3185                 .pa_end         = 0x4804A000 + SZ_1K - 1,
3186                 .flags          = ADDR_TYPE_RT
3187         },
3188         { }
3189 };
3190
3191 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3192         .master         = &am33xx_l4_ls_hwmod,
3193         .slave          = &am33xx_timer7_hwmod,
3194         .clk            = "l4ls_gclk",
3195         .addr           = am33xx_timer7_addr_space,
3196         .user           = OCP_USER_MPU,
3197 };
3198
3199 /* l3 main -> tpcc */
3200 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3201         {
3202                 .pa_start       = 0x49000000,
3203                 .pa_end         = 0x49000000 + SZ_32K - 1,
3204                 .flags          = ADDR_TYPE_RT
3205         },
3206         { }
3207 };
3208
3209 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3210         .master         = &am33xx_l3_main_hwmod,
3211         .slave          = &am33xx_tpcc_hwmod,
3212         .clk            = "l3_gclk",
3213         .addr           = am33xx_tpcc_addr_space,
3214         .user           = OCP_USER_MPU,
3215 };
3216
3217 /* l3 main -> tpcc0 */
3218 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3219         {
3220                 .pa_start       = 0x49800000,
3221                 .pa_end         = 0x49800000 + SZ_8K - 1,
3222                 .flags          = ADDR_TYPE_RT,
3223         },
3224         { }
3225 };
3226
3227 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3228         .master         = &am33xx_l3_main_hwmod,
3229         .slave          = &am33xx_tptc0_hwmod,
3230         .clk            = "l3_gclk",
3231         .addr           = am33xx_tptc0_addr_space,
3232         .user           = OCP_USER_MPU,
3233 };
3234
3235 /* l3 main -> tpcc1 */
3236 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3237         {
3238                 .pa_start       = 0x49900000,
3239                 .pa_end         = 0x49900000 + SZ_8K - 1,
3240                 .flags          = ADDR_TYPE_RT,
3241         },
3242         { }
3243 };
3244
3245 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3246         .master         = &am33xx_l3_main_hwmod,
3247         .slave          = &am33xx_tptc1_hwmod,
3248         .clk            = "l3_gclk",
3249         .addr           = am33xx_tptc1_addr_space,
3250         .user           = OCP_USER_MPU,
3251 };
3252
3253 /* l3 main -> tpcc2 */
3254 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3255         {
3256                 .pa_start       = 0x49a00000,
3257                 .pa_end         = 0x49a00000 + SZ_8K - 1,
3258                 .flags          = ADDR_TYPE_RT,
3259         },
3260         { }
3261 };
3262
3263 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3264         .master         = &am33xx_l3_main_hwmod,
3265         .slave          = &am33xx_tptc2_hwmod,
3266         .clk            = "l3_gclk",
3267         .addr           = am33xx_tptc2_addr_space,
3268         .user           = OCP_USER_MPU,
3269 };
3270
3271 /* l4 wkup -> uart1 */
3272 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3273         {
3274                 .pa_start       = 0x44E09000,
3275                 .pa_end         = 0x44E09000 + SZ_8K - 1,
3276                 .flags          = ADDR_TYPE_RT,
3277         },
3278         { }
3279 };
3280
3281 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3282         .master         = &am33xx_l4_wkup_hwmod,
3283         .slave          = &am33xx_uart1_hwmod,
3284         .clk            = "dpll_core_m4_div2_ck",
3285         .addr           = am33xx_uart1_addr_space,
3286         .user           = OCP_USER_MPU,
3287 };
3288
3289 /* l4 ls -> uart2 */
3290 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3291         {
3292                 .pa_start       = 0x48022000,
3293                 .pa_end         = 0x48022000 + SZ_8K - 1,
3294                 .flags          = ADDR_TYPE_RT,
3295         },
3296         { }
3297 };
3298
3299 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3300         .master         = &am33xx_l4_ls_hwmod,
3301         .slave          = &am33xx_uart2_hwmod,
3302         .clk            = "l4ls_gclk",
3303         .addr           = am33xx_uart2_addr_space,
3304         .user           = OCP_USER_MPU,
3305 };
3306
3307 /* l4 ls -> uart3 */
3308 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3309         {
3310                 .pa_start       = 0x48024000,
3311                 .pa_end         = 0x48024000 + SZ_8K - 1,
3312                 .flags          = ADDR_TYPE_RT,
3313         },
3314         { }
3315 };
3316
3317 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3318         .master         = &am33xx_l4_ls_hwmod,
3319         .slave          = &am33xx_uart3_hwmod,
3320         .clk            = "l4ls_gclk",
3321         .addr           = am33xx_uart3_addr_space,
3322         .user           = OCP_USER_MPU,
3323 };
3324
3325 /* l4 ls -> uart4 */
3326 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3327         {
3328                 .pa_start       = 0x481A6000,
3329                 .pa_end         = 0x481A6000 + SZ_8K - 1,
3330                 .flags          = ADDR_TYPE_RT,
3331         },
3332         { }
3333 };
3334
3335 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3336         .master         = &am33xx_l4_ls_hwmod,
3337         .slave          = &am33xx_uart4_hwmod,
3338         .clk            = "l4ls_gclk",
3339         .addr           = am33xx_uart4_addr_space,
3340         .user           = OCP_USER_MPU,
3341 };
3342
3343 /* l4 ls -> uart5 */
3344 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3345         {
3346                 .pa_start       = 0x481A8000,
3347                 .pa_end         = 0x481A8000 + SZ_8K - 1,
3348                 .flags          = ADDR_TYPE_RT,
3349         },
3350         { }
3351 };
3352
3353 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3354         .master         = &am33xx_l4_ls_hwmod,
3355         .slave          = &am33xx_uart5_hwmod,
3356         .clk            = "l4ls_gclk",
3357         .addr           = am33xx_uart5_addr_space,
3358         .user           = OCP_USER_MPU,
3359 };
3360
3361 /* l4 ls -> uart6 */
3362 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3363         {
3364                 .pa_start       = 0x481aa000,
3365                 .pa_end         = 0x481aa000 + SZ_8K - 1,
3366                 .flags          = ADDR_TYPE_RT,
3367         },
3368         { }
3369 };
3370
3371 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3372         .master         = &am33xx_l4_ls_hwmod,
3373         .slave          = &am33xx_uart6_hwmod,
3374         .clk            = "l4ls_gclk",
3375         .addr           = am33xx_uart6_addr_space,
3376         .user           = OCP_USER_MPU,
3377 };
3378
3379 /* l4 wkup -> wd_timer1 */
3380 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3381         {
3382                 .pa_start       = 0x44e35000,
3383                 .pa_end         = 0x44e35000 + SZ_4K - 1,
3384                 .flags          = ADDR_TYPE_RT
3385         },
3386         { }
3387 };
3388
3389 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3390         .master         = &am33xx_l4_wkup_hwmod,
3391         .slave          = &am33xx_wd_timer1_hwmod,
3392         .clk            = "dpll_core_m4_div2_ck",
3393         .addr           = am33xx_wd_timer1_addrs,
3394         .user           = OCP_USER_MPU,
3395 };
3396
3397 /* usbss */
3398 /* l3 s -> USBSS interface */
3399 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3400         {
3401                 .name           = "usbss",
3402                 .pa_start       = 0x47400000,
3403                 .pa_end         = 0x47400000 + SZ_4K - 1,
3404                 .flags          = ADDR_TYPE_RT
3405         },
3406         {
3407                 .name           = "musb0",
3408                 .pa_start       = 0x47401000,
3409                 .pa_end         = 0x47401000 + SZ_2K - 1,
3410                 .flags          = ADDR_TYPE_RT
3411         },
3412         {
3413                 .name           = "musb1",
3414                 .pa_start       = 0x47401800,
3415                 .pa_end         = 0x47401800 + SZ_2K - 1,
3416                 .flags          = ADDR_TYPE_RT
3417         },
3418         { }
3419 };
3420
3421 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3422         .master         = &am33xx_l3_s_hwmod,
3423         .slave          = &am33xx_usbss_hwmod,
3424         .clk            = "l3s_gclk",
3425         .addr           = am33xx_usbss_addr_space,
3426         .user           = OCP_USER_MPU,
3427         .flags          = OCPIF_SWSUP_IDLE,
3428 };
3429
3430 /* l3 main -> ocmc */
3431 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3432         .master         = &am33xx_l3_main_hwmod,
3433         .slave          = &am33xx_ocmcram_hwmod,
3434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3435 };
3436
3437 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3438         &am33xx_l4_fw__emif_fw,
3439         &am33xx_l3_main__emif,
3440         &am33xx_mpu__l3_main,
3441         &am33xx_mpu__prcm,
3442         &am33xx_l3_s__l4_ls,
3443         &am33xx_l3_s__l4_wkup,
3444         &am33xx_l3_s__l4_fw,
3445         &am33xx_l3_main__l4_hs,
3446         &am33xx_l3_main__l3_s,
3447         &am33xx_l3_main__l3_instr,
3448         &am33xx_l3_main__gfx,
3449         &am33xx_l3_s__l3_main,
3450         &am33xx_pruss__l3_main,
3451         &am33xx_wkup_m3__l4_wkup,
3452         &am33xx_gfx__l3_main,
3453         &am33xx_l4_wkup__wkup_m3,
3454         &am33xx_l4_wkup__control,
3455         &am33xx_l4_wkup__smartreflex0,
3456         &am33xx_l4_wkup__smartreflex1,
3457         &am33xx_l4_wkup__uart1,
3458         &am33xx_l4_wkup__timer1,
3459         &am33xx_l4_wkup__rtc,
3460         &am33xx_l4_wkup__i2c1,
3461         &am33xx_l4_wkup__gpio0,
3462         &am33xx_l4_wkup__adc_tsc,
3463         &am33xx_l4_wkup__wd_timer1,
3464         &am33xx_l4_hs__pruss,
3465         &am33xx_l4_per__dcan0,
3466         &am33xx_l4_per__dcan1,
3467         &am33xx_l4_per__gpio1,
3468         &am33xx_l4_per__gpio2,
3469         &am33xx_l4_per__gpio3,
3470         &am33xx_l4_per__i2c2,
3471         &am33xx_l4_per__i2c3,
3472         &am33xx_l4_per__mailbox,
3473         &am33xx_l4_ls__mcasp0,
3474         &am33xx_l3_s__mcasp0_data,
3475         &am33xx_l4_ls__mcasp1,
3476         &am33xx_l3_s__mcasp1_data,
3477         &am33xx_l4_ls__mmc0,
3478         &am33xx_l4_ls__mmc1,
3479         &am33xx_l3_s__mmc2,
3480         &am33xx_l4_ls__timer2,
3481         &am33xx_l4_ls__timer3,
3482         &am33xx_l4_ls__timer4,
3483         &am33xx_l4_ls__timer5,
3484         &am33xx_l4_ls__timer6,
3485         &am33xx_l4_ls__timer7,
3486         &am33xx_l3_main__tpcc,
3487         &am33xx_l4_ls__uart2,
3488         &am33xx_l4_ls__uart3,
3489         &am33xx_l4_ls__uart4,
3490         &am33xx_l4_ls__uart5,
3491         &am33xx_l4_ls__uart6,
3492         &am33xx_l4_ls__spinlock,
3493         &am33xx_l4_ls__elm,
3494         &am33xx_l4_ls__epwmss0,
3495         &am33xx_epwmss0__ecap0,
3496         &am33xx_epwmss0__eqep0,
3497         &am33xx_epwmss0__ehrpwm0,
3498         &am33xx_l4_ls__epwmss1,
3499         &am33xx_epwmss1__ecap1,
3500         &am33xx_epwmss1__eqep1,
3501         &am33xx_epwmss1__ehrpwm1,
3502         &am33xx_l4_ls__epwmss2,
3503         &am33xx_epwmss2__ecap2,
3504         &am33xx_epwmss2__eqep2,
3505         &am33xx_epwmss2__ehrpwm2,
3506         &am33xx_l3_s__gpmc,
3507         &am33xx_l3_main__lcdc,
3508         &am33xx_l4_ls__mcspi0,
3509         &am33xx_l4_ls__mcspi1,
3510         &am33xx_l3_main__tptc0,
3511         &am33xx_l3_main__tptc1,
3512         &am33xx_l3_main__tptc2,
3513         &am33xx_l3_main__ocmc,
3514         &am33xx_l3_s__usbss,
3515         &am33xx_l4_hs__cpgmac0,
3516         &am33xx_cpgmac0__mdio,
3517         NULL,
3518 };
3519
3520 int __init am33xx_hwmod_init(void)
3521 {
3522         omap_hwmod_init();
3523         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3524 }