2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/i2c-omap.h>
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
23 #include "omap_hwmod_common_data.h"
28 #include "prm-regbits-33xx.h"
38 * instance(s): emif_fw
40 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
45 static struct omap_hwmod am33xx_emif_fw_hwmod = {
47 .class = &am33xx_emif_fw_hwmod_class,
48 .clkdm_name = "l4fw_clkdm",
49 .main_clk = "l4fw_gclk",
50 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
53 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
63 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
67 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
69 .sysc = &am33xx_emif_sysc,
72 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
73 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
78 static struct omap_hwmod am33xx_emif_hwmod = {
80 .class = &am33xx_emif_hwmod_class,
81 .clkdm_name = "l3_clkdm",
82 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
83 .mpu_irqs = am33xx_emif_irqs,
84 .main_clk = "dpll_ddr_m2_div2_ck",
87 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
95 * instance(s): l3_main, l3_s, l3_instr
97 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
101 /* l3_main (l3_fast) */
102 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
103 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
104 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
108 static struct omap_hwmod am33xx_l3_main_hwmod = {
110 .class = &am33xx_l3_hwmod_class,
111 .clkdm_name = "l3_clkdm",
112 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
113 .mpu_irqs = am33xx_l3_main_irqs,
114 .main_clk = "l3_gclk",
117 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
124 static struct omap_hwmod am33xx_l3_s_hwmod = {
126 .class = &am33xx_l3_hwmod_class,
127 .clkdm_name = "l3s_clkdm",
131 static struct omap_hwmod am33xx_l3_instr_hwmod = {
133 .class = &am33xx_l3_hwmod_class,
134 .clkdm_name = "l3_clkdm",
135 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
136 .main_clk = "l3_gclk",
139 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
140 .modulemode = MODULEMODE_SWCTRL,
147 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
149 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
154 static struct omap_hwmod am33xx_l4_ls_hwmod = {
156 .class = &am33xx_l4_hwmod_class,
157 .clkdm_name = "l4ls_clkdm",
158 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
159 .main_clk = "l4ls_gclk",
162 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
163 .modulemode = MODULEMODE_SWCTRL,
169 static struct omap_hwmod am33xx_l4_hs_hwmod = {
171 .class = &am33xx_l4_hwmod_class,
172 .clkdm_name = "l4hs_clkdm",
173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
174 .main_clk = "l4hs_gclk",
177 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
185 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
187 .class = &am33xx_l4_hwmod_class,
188 .clkdm_name = "l4_wkup_clkdm",
189 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
192 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
193 .modulemode = MODULEMODE_SWCTRL,
199 static struct omap_hwmod am33xx_l4_fw_hwmod = {
201 .class = &am33xx_l4_hwmod_class,
202 .clkdm_name = "l4fw_clkdm",
203 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
206 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
207 .modulemode = MODULEMODE_SWCTRL,
215 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
220 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
221 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
222 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
223 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
224 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
228 static struct omap_hwmod am33xx_mpu_hwmod = {
230 .class = &am33xx_mpu_hwmod_class,
231 .clkdm_name = "mpu_clkdm",
232 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
233 .mpu_irqs = am33xx_mpu_irqs,
234 .main_clk = "dpll_mpu_m2_ck",
237 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
238 .modulemode = MODULEMODE_SWCTRL,
245 * Wakeup controller sub-system under wakeup domain
247 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
251 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
252 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
255 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
256 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
261 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
263 .class = &am33xx_wkup_m3_hwmod_class,
264 .clkdm_name = "l4_wkup_aon_clkdm",
265 /* Keep hardreset asserted */
266 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
267 .mpu_irqs = am33xx_wkup_m3_irqs,
268 .main_clk = "dpll_core_m4_div2_ck",
271 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
272 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
273 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
274 .modulemode = MODULEMODE_SWCTRL,
277 .rst_lines = am33xx_wkup_m3_resets,
278 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
283 * Programmable Real-Time Unit and Industrial Communication Subsystem
285 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
289 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
290 { .name = "pruss", .rst_shift = 1 },
293 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
294 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
295 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
296 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
297 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
298 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
299 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
300 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
301 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
306 /* Pseudo hwmod for reset control purpose only */
307 static struct omap_hwmod am33xx_pruss_hwmod = {
309 .class = &am33xx_pruss_hwmod_class,
310 .clkdm_name = "pruss_ocp_clkdm",
311 .mpu_irqs = am33xx_pruss_irqs,
312 .main_clk = "pruss_ocp_gclk",
315 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
316 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
317 .modulemode = MODULEMODE_SWCTRL,
320 .rst_lines = am33xx_pruss_resets,
321 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
325 /* Pseudo hwmod for reset control purpose only */
326 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
330 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
331 { .name = "gfx", .rst_shift = 0 },
334 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
335 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
339 static struct omap_hwmod am33xx_gfx_hwmod = {
341 .class = &am33xx_gfx_hwmod_class,
342 .clkdm_name = "gfx_l3_clkdm",
343 .mpu_irqs = am33xx_gfx_irqs,
344 .main_clk = "gfx_fck_div_ck",
347 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
348 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
349 .modulemode = MODULEMODE_SWCTRL,
352 .rst_lines = am33xx_gfx_resets,
353 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
358 * power and reset manager (whole prcm infrastructure)
360 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
365 static struct omap_hwmod am33xx_prcm_hwmod = {
367 .class = &am33xx_prcm_hwmod_class,
368 .clkdm_name = "l4_wkup_clkdm",
373 * TouchScreen Controller (Anolog-To-Digital Converter)
375 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
378 .sysc_flags = SYSC_HAS_SIDLEMODE,
379 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
381 .sysc_fields = &omap_hwmod_sysc_type2,
384 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
386 .sysc = &am33xx_adc_tsc_sysc,
389 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
390 { .irq = 16 + OMAP_INTC_START, },
394 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
396 .class = &am33xx_adc_tsc_hwmod_class,
397 .clkdm_name = "l4_wkup_clkdm",
398 .mpu_irqs = am33xx_adc_tsc_irqs,
399 .main_clk = "adc_tsc_fck",
402 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
403 .modulemode = MODULEMODE_SWCTRL,
409 * Modules omap_hwmod structures
411 * The following IPs are excluded for the moment because:
412 * - They do not need an explicit SW control using omap_hwmod API.
413 * - They still need to be validated with the driver
414 * properly adapted to omap_hwmod / omap_device
416 * - cEFUSE (doesn't fall under any ocp_if)
426 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
430 static struct omap_hwmod am33xx_cefuse_hwmod = {
432 .class = &am33xx_cefuse_hwmod_class,
433 .clkdm_name = "l4_cefuse_clkdm",
434 .main_clk = "cefuse_fck",
437 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
438 .modulemode = MODULEMODE_SWCTRL,
446 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
450 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
452 .class = &am33xx_clkdiv32k_hwmod_class,
453 .clkdm_name = "clk_24mhz_clkdm",
454 .main_clk = "clkdiv32k_ick",
457 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
467 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
471 static struct omap_hwmod am33xx_debugss_hwmod = {
473 .class = &am33xx_debugss_hwmod_class,
474 .clkdm_name = "l3_aon_clkdm",
475 .main_clk = "debugss_ick",
478 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
479 .modulemode = MODULEMODE_SWCTRL,
485 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
489 static struct omap_hwmod am33xx_ocpwp_hwmod = {
491 .class = &am33xx_ocpwp_hwmod_class,
492 .clkdm_name = "l4ls_clkdm",
493 .main_clk = "l4ls_gclk",
496 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
497 .modulemode = MODULEMODE_SWCTRL,
505 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
509 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
510 { .irq = 102 + OMAP_INTC_START, },
514 static struct omap_hwmod am33xx_aes0_hwmod = {
516 .class = &am33xx_aes_hwmod_class,
517 .clkdm_name = "l3_clkdm",
518 .mpu_irqs = am33xx_aes0_irqs,
519 .main_clk = "l3_gclk",
522 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
523 .modulemode = MODULEMODE_SWCTRL,
529 /* sha0 HIB2 (the 'P' (public) device) */
530 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
534 .sysc_flags = SYSS_HAS_RESET_STATUS,
537 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
539 .sysc = &am33xx_sha0_sysc,
542 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
543 { .irq = 109 + OMAP_INTC_START, },
547 static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
548 { .name = "rx", .dma_req = 36, },
552 static struct omap_hwmod am33xx_sha0_hwmod = {
554 .class = &am33xx_sha0_hwmod_class,
555 .clkdm_name = "l3_clkdm",
556 .mpu_irqs = am33xx_sha0_irqs,
557 .sdma_reqs = am33xx_sha0_edma_reqs,
558 .main_clk = "l3_gclk",
561 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
562 .modulemode = MODULEMODE_SWCTRL,
568 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
572 static struct omap_hwmod am33xx_ocmcram_hwmod = {
574 .class = &am33xx_ocmcram_hwmod_class,
575 .clkdm_name = "l3_clkdm",
576 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
577 .main_clk = "l3_gclk",
580 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
581 .modulemode = MODULEMODE_SWCTRL,
586 /* 'smartreflex' class */
587 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
588 .name = "smartreflex",
592 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
593 { .irq = 120 + OMAP_INTC_START, },
597 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
598 .name = "smartreflex0",
599 .class = &am33xx_smartreflex_hwmod_class,
600 .clkdm_name = "l4_wkup_clkdm",
601 .mpu_irqs = am33xx_smartreflex0_irqs,
602 .main_clk = "smartreflex0_fck",
605 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
606 .modulemode = MODULEMODE_SWCTRL,
612 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
613 { .irq = 121 + OMAP_INTC_START, },
617 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
618 .name = "smartreflex1",
619 .class = &am33xx_smartreflex_hwmod_class,
620 .clkdm_name = "l4_wkup_clkdm",
621 .mpu_irqs = am33xx_smartreflex1_irqs,
622 .main_clk = "smartreflex1_fck",
625 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
626 .modulemode = MODULEMODE_SWCTRL,
632 * 'control' module class
634 static struct omap_hwmod_class am33xx_control_hwmod_class = {
638 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
639 { .irq = 8 + OMAP_INTC_START, },
643 static struct omap_hwmod am33xx_control_hwmod = {
645 .class = &am33xx_control_hwmod_class,
646 .clkdm_name = "l4_wkup_clkdm",
647 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
648 .mpu_irqs = am33xx_control_irqs,
649 .main_clk = "dpll_core_m4_div2_ck",
652 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
653 .modulemode = MODULEMODE_SWCTRL,
660 * cpsw/cpgmac sub system
662 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
666 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
667 SYSS_HAS_RESET_STATUS),
668 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
670 .sysc_fields = &omap_hwmod_sysc_type3,
673 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
675 .sysc = &am33xx_cpgmac_sysc,
678 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
679 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
680 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
681 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
682 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
686 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
688 .class = &am33xx_cpgmac0_hwmod_class,
689 .clkdm_name = "cpsw_125mhz_clkdm",
690 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
691 .mpu_irqs = am33xx_cpgmac0_irqs,
692 .main_clk = "cpsw_125mhz_gclk",
695 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
696 .modulemode = MODULEMODE_SWCTRL,
704 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
705 .name = "davinci_mdio",
708 static struct omap_hwmod am33xx_mdio_hwmod = {
709 .name = "davinci_mdio",
710 .class = &am33xx_mdio_hwmod_class,
711 .clkdm_name = "cpsw_125mhz_clkdm",
712 .main_clk = "cpsw_125mhz_gclk",
718 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
723 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
724 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
725 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
729 static struct omap_hwmod am33xx_dcan0_hwmod = {
731 .class = &am33xx_dcan_hwmod_class,
732 .clkdm_name = "l4ls_clkdm",
733 .mpu_irqs = am33xx_dcan0_irqs,
734 .main_clk = "dcan0_fck",
737 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
738 .modulemode = MODULEMODE_SWCTRL,
744 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
745 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
746 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
749 static struct omap_hwmod am33xx_dcan1_hwmod = {
751 .class = &am33xx_dcan_hwmod_class,
752 .clkdm_name = "l4ls_clkdm",
753 .mpu_irqs = am33xx_dcan1_irqs,
754 .main_clk = "dcan1_fck",
757 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
758 .modulemode = MODULEMODE_SWCTRL,
764 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
768 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
769 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
770 SYSS_HAS_RESET_STATUS),
771 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
772 .sysc_fields = &omap_hwmod_sysc_type1,
775 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
777 .sysc = &am33xx_elm_sysc,
780 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
781 { .irq = 4 + OMAP_INTC_START, },
785 static struct omap_hwmod am33xx_elm_hwmod = {
787 .class = &am33xx_elm_hwmod_class,
788 .clkdm_name = "l4ls_clkdm",
789 .mpu_irqs = am33xx_elm_irqs,
790 .main_clk = "l4ls_gclk",
793 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
794 .modulemode = MODULEMODE_SWCTRL,
800 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
803 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
804 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
805 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
806 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
807 .sysc_fields = &omap_hwmod_sysc_type2,
810 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
812 .sysc = &am33xx_epwmss_sysc,
815 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
819 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
823 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
828 static struct omap_hwmod am33xx_epwmss0_hwmod = {
830 .class = &am33xx_epwmss_hwmod_class,
831 .clkdm_name = "l4ls_clkdm",
832 .main_clk = "l4ls_gclk",
835 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
836 .modulemode = MODULEMODE_SWCTRL,
842 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
843 { .irq = 31 + OMAP_INTC_START, },
847 static struct omap_hwmod am33xx_ecap0_hwmod = {
849 .class = &am33xx_ecap_hwmod_class,
850 .clkdm_name = "l4ls_clkdm",
851 .mpu_irqs = am33xx_ecap0_irqs,
852 .main_clk = "l4ls_gclk",
856 static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
857 { .irq = 79 + OMAP_INTC_START, },
861 static struct omap_hwmod am33xx_eqep0_hwmod = {
863 .class = &am33xx_eqep_hwmod_class,
864 .clkdm_name = "l4ls_clkdm",
865 .mpu_irqs = am33xx_eqep0_irqs,
866 .main_clk = "l4ls_gclk",
870 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
871 { .name = "int", .irq = 86 + OMAP_INTC_START, },
872 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
876 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
878 .class = &am33xx_ehrpwm_hwmod_class,
879 .clkdm_name = "l4ls_clkdm",
880 .mpu_irqs = am33xx_ehrpwm0_irqs,
881 .main_clk = "l4ls_gclk",
885 static struct omap_hwmod am33xx_epwmss1_hwmod = {
887 .class = &am33xx_epwmss_hwmod_class,
888 .clkdm_name = "l4ls_clkdm",
889 .main_clk = "l4ls_gclk",
892 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
893 .modulemode = MODULEMODE_SWCTRL,
899 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
900 { .irq = 47 + OMAP_INTC_START, },
904 static struct omap_hwmod am33xx_ecap1_hwmod = {
906 .class = &am33xx_ecap_hwmod_class,
907 .clkdm_name = "l4ls_clkdm",
908 .mpu_irqs = am33xx_ecap1_irqs,
909 .main_clk = "l4ls_gclk",
913 static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
914 { .irq = 88 + OMAP_INTC_START, },
918 static struct omap_hwmod am33xx_eqep1_hwmod = {
920 .class = &am33xx_eqep_hwmod_class,
921 .clkdm_name = "l4ls_clkdm",
922 .mpu_irqs = am33xx_eqep1_irqs,
923 .main_clk = "l4ls_gclk",
927 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
928 { .name = "int", .irq = 87 + OMAP_INTC_START, },
929 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
933 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
935 .class = &am33xx_ehrpwm_hwmod_class,
936 .clkdm_name = "l4ls_clkdm",
937 .mpu_irqs = am33xx_ehrpwm1_irqs,
938 .main_clk = "l4ls_gclk",
942 static struct omap_hwmod am33xx_epwmss2_hwmod = {
944 .class = &am33xx_epwmss_hwmod_class,
945 .clkdm_name = "l4ls_clkdm",
946 .main_clk = "l4ls_gclk",
949 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
956 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
957 { .irq = 61 + OMAP_INTC_START, },
961 static struct omap_hwmod am33xx_ecap2_hwmod = {
963 .class = &am33xx_ecap_hwmod_class,
964 .clkdm_name = "l4ls_clkdm",
965 .mpu_irqs = am33xx_ecap2_irqs,
966 .main_clk = "l4ls_gclk",
970 static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
971 { .irq = 89 + OMAP_INTC_START, },
975 static struct omap_hwmod am33xx_eqep2_hwmod = {
977 .class = &am33xx_eqep_hwmod_class,
978 .clkdm_name = "l4ls_clkdm",
979 .mpu_irqs = am33xx_eqep2_irqs,
980 .main_clk = "l4ls_gclk",
984 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
985 { .name = "int", .irq = 39 + OMAP_INTC_START, },
986 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
990 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
992 .class = &am33xx_ehrpwm_hwmod_class,
993 .clkdm_name = "l4ls_clkdm",
994 .mpu_irqs = am33xx_ehrpwm2_irqs,
995 .main_clk = "l4ls_gclk",
999 * 'gpio' class: for gpio 0,1,2,3
1001 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
1003 .sysc_offs = 0x0010,
1004 .syss_offs = 0x0114,
1005 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1006 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1007 SYSS_HAS_RESET_STATUS),
1008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1010 .sysc_fields = &omap_hwmod_sysc_type1,
1013 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1015 .sysc = &am33xx_gpio_sysc,
1019 static struct omap_gpio_dev_attr gpio_dev_attr = {
1025 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1026 { .role = "dbclk", .clk = "gpio0_dbclk" },
1029 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1030 { .irq = 96 + OMAP_INTC_START, },
1034 static struct omap_hwmod am33xx_gpio0_hwmod = {
1036 .class = &am33xx_gpio_hwmod_class,
1037 .clkdm_name = "l4_wkup_clkdm",
1038 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1039 .mpu_irqs = am33xx_gpio0_irqs,
1040 .main_clk = "dpll_core_m4_div2_ck",
1043 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1044 .modulemode = MODULEMODE_SWCTRL,
1047 .opt_clks = gpio0_opt_clks,
1048 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
1049 .dev_attr = &gpio_dev_attr,
1053 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1054 { .irq = 98 + OMAP_INTC_START, },
1058 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1059 { .role = "dbclk", .clk = "gpio1_dbclk" },
1062 static struct omap_hwmod am33xx_gpio1_hwmod = {
1064 .class = &am33xx_gpio_hwmod_class,
1065 .clkdm_name = "l4ls_clkdm",
1066 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1067 .mpu_irqs = am33xx_gpio1_irqs,
1068 .main_clk = "l4ls_gclk",
1071 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1072 .modulemode = MODULEMODE_SWCTRL,
1075 .opt_clks = gpio1_opt_clks,
1076 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1077 .dev_attr = &gpio_dev_attr,
1081 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1082 { .irq = 32 + OMAP_INTC_START, },
1086 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1087 { .role = "dbclk", .clk = "gpio2_dbclk" },
1090 static struct omap_hwmod am33xx_gpio2_hwmod = {
1092 .class = &am33xx_gpio_hwmod_class,
1093 .clkdm_name = "l4ls_clkdm",
1094 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1095 .mpu_irqs = am33xx_gpio2_irqs,
1096 .main_clk = "l4ls_gclk",
1099 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1100 .modulemode = MODULEMODE_SWCTRL,
1103 .opt_clks = gpio2_opt_clks,
1104 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1105 .dev_attr = &gpio_dev_attr,
1109 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1110 { .irq = 62 + OMAP_INTC_START, },
1114 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1115 { .role = "dbclk", .clk = "gpio3_dbclk" },
1118 static struct omap_hwmod am33xx_gpio3_hwmod = {
1120 .class = &am33xx_gpio_hwmod_class,
1121 .clkdm_name = "l4ls_clkdm",
1122 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1123 .mpu_irqs = am33xx_gpio3_irqs,
1124 .main_clk = "l4ls_gclk",
1127 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1128 .modulemode = MODULEMODE_SWCTRL,
1131 .opt_clks = gpio3_opt_clks,
1132 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1133 .dev_attr = &gpio_dev_attr,
1137 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1141 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1142 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144 .sysc_fields = &omap_hwmod_sysc_type1,
1147 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1152 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1153 { .irq = 100 + OMAP_INTC_START, },
1157 static struct omap_hwmod am33xx_gpmc_hwmod = {
1159 .class = &am33xx_gpmc_hwmod_class,
1160 .clkdm_name = "l3s_clkdm",
1161 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1162 .mpu_irqs = am33xx_gpmc_irqs,
1163 .main_clk = "l3s_gclk",
1166 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1167 .modulemode = MODULEMODE_SWCTRL,
1173 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1174 .sysc_offs = 0x0010,
1175 .syss_offs = 0x0090,
1176 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1177 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1178 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1179 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1181 .sysc_fields = &omap_hwmod_sysc_type1,
1184 static struct omap_hwmod_class i2c_class = {
1186 .sysc = &am33xx_i2c_sysc,
1187 .rev = OMAP_I2C_IP_VERSION_2,
1188 .reset = &omap_i2c_reset,
1191 static struct omap_i2c_dev_attr i2c_dev_attr = {
1192 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1196 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1197 { .irq = 70 + OMAP_INTC_START, },
1201 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1202 { .name = "tx", .dma_req = 0, },
1203 { .name = "rx", .dma_req = 0, },
1207 static struct omap_hwmod am33xx_i2c1_hwmod = {
1209 .class = &i2c_class,
1210 .clkdm_name = "l4_wkup_clkdm",
1211 .mpu_irqs = i2c1_mpu_irqs,
1212 .sdma_reqs = i2c1_edma_reqs,
1213 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1214 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1217 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1218 .modulemode = MODULEMODE_SWCTRL,
1221 .dev_attr = &i2c_dev_attr,
1225 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1226 { .irq = 71 + OMAP_INTC_START, },
1230 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1231 { .name = "tx", .dma_req = 0, },
1232 { .name = "rx", .dma_req = 0, },
1236 static struct omap_hwmod am33xx_i2c2_hwmod = {
1238 .class = &i2c_class,
1239 .clkdm_name = "l4ls_clkdm",
1240 .mpu_irqs = i2c2_mpu_irqs,
1241 .sdma_reqs = i2c2_edma_reqs,
1242 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1243 .main_clk = "dpll_per_m2_div4_ck",
1246 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1247 .modulemode = MODULEMODE_SWCTRL,
1250 .dev_attr = &i2c_dev_attr,
1254 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1255 { .name = "tx", .dma_req = 0, },
1256 { .name = "rx", .dma_req = 0, },
1260 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1261 { .irq = 30 + OMAP_INTC_START, },
1265 static struct omap_hwmod am33xx_i2c3_hwmod = {
1267 .class = &i2c_class,
1268 .clkdm_name = "l4ls_clkdm",
1269 .mpu_irqs = i2c3_mpu_irqs,
1270 .sdma_reqs = i2c3_edma_reqs,
1271 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1272 .main_clk = "dpll_per_m2_div4_ck",
1275 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1276 .modulemode = MODULEMODE_SWCTRL,
1279 .dev_attr = &i2c_dev_attr,
1284 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1287 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1288 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1289 .sysc_fields = &omap_hwmod_sysc_type2,
1292 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1297 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1298 { .irq = 36 + OMAP_INTC_START, },
1302 static struct omap_hwmod am33xx_lcdc_hwmod = {
1304 .class = &am33xx_lcdc_hwmod_class,
1305 .clkdm_name = "lcdc_clkdm",
1306 .mpu_irqs = am33xx_lcdc_irqs,
1307 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1308 .main_clk = "lcd_gclk",
1311 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1312 .modulemode = MODULEMODE_SWCTRL,
1319 * mailbox module allowing communication between the on-chip processors using a
1320 * queued mailbox-interrupt mechanism.
1322 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1324 .sysc_offs = 0x0010,
1325 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1326 SYSC_HAS_SOFTRESET),
1327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1328 .sysc_fields = &omap_hwmod_sysc_type2,
1331 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1333 .sysc = &am33xx_mailbox_sysc,
1336 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1337 { .irq = 77 + OMAP_INTC_START, },
1341 static struct omap_hwmod am33xx_mailbox_hwmod = {
1343 .class = &am33xx_mailbox_hwmod_class,
1344 .clkdm_name = "l4ls_clkdm",
1345 .mpu_irqs = am33xx_mailbox_irqs,
1346 .main_clk = "l4ls_gclk",
1349 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1350 .modulemode = MODULEMODE_SWCTRL,
1358 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1361 .sysc_flags = SYSC_HAS_SIDLEMODE,
1362 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1363 .sysc_fields = &omap_hwmod_sysc_type3,
1366 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1368 .sysc = &am33xx_mcasp_sysc,
1372 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1373 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1374 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1378 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1379 { .name = "tx", .dma_req = 8, },
1380 { .name = "rx", .dma_req = 9, },
1384 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1386 .class = &am33xx_mcasp_hwmod_class,
1387 .clkdm_name = "l3s_clkdm",
1388 .mpu_irqs = am33xx_mcasp0_irqs,
1389 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1390 .main_clk = "mcasp0_fck",
1393 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1394 .modulemode = MODULEMODE_SWCTRL,
1400 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1401 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1402 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1406 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1407 { .name = "tx", .dma_req = 10, },
1408 { .name = "rx", .dma_req = 11, },
1412 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1414 .class = &am33xx_mcasp_hwmod_class,
1415 .clkdm_name = "l3s_clkdm",
1416 .mpu_irqs = am33xx_mcasp1_irqs,
1417 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1418 .main_clk = "mcasp1_fck",
1421 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1422 .modulemode = MODULEMODE_SWCTRL,
1428 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1432 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1433 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1434 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1435 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1436 .sysc_fields = &omap_hwmod_sysc_type1,
1439 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1441 .sysc = &am33xx_mmc_sysc,
1445 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1446 { .irq = 64 + OMAP_INTC_START, },
1450 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1451 { .name = "tx", .dma_req = 24, },
1452 { .name = "rx", .dma_req = 25, },
1456 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1457 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1460 static struct omap_hwmod am33xx_mmc0_hwmod = {
1462 .class = &am33xx_mmc_hwmod_class,
1463 .clkdm_name = "l4ls_clkdm",
1464 .mpu_irqs = am33xx_mmc0_irqs,
1465 .sdma_reqs = am33xx_mmc0_edma_reqs,
1466 .main_clk = "mmc_clk",
1469 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1470 .modulemode = MODULEMODE_SWCTRL,
1473 .dev_attr = &am33xx_mmc0_dev_attr,
1477 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1478 { .irq = 28 + OMAP_INTC_START, },
1482 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1483 { .name = "tx", .dma_req = 2, },
1484 { .name = "rx", .dma_req = 3, },
1488 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1489 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1492 static struct omap_hwmod am33xx_mmc1_hwmod = {
1494 .class = &am33xx_mmc_hwmod_class,
1495 .clkdm_name = "l4ls_clkdm",
1496 .mpu_irqs = am33xx_mmc1_irqs,
1497 .sdma_reqs = am33xx_mmc1_edma_reqs,
1498 .main_clk = "mmc_clk",
1501 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1502 .modulemode = MODULEMODE_SWCTRL,
1505 .dev_attr = &am33xx_mmc1_dev_attr,
1509 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1510 { .irq = 29 + OMAP_INTC_START, },
1514 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1515 { .name = "tx", .dma_req = 64, },
1516 { .name = "rx", .dma_req = 65, },
1520 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1521 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1523 static struct omap_hwmod am33xx_mmc2_hwmod = {
1525 .class = &am33xx_mmc_hwmod_class,
1526 .clkdm_name = "l3s_clkdm",
1527 .mpu_irqs = am33xx_mmc2_irqs,
1528 .sdma_reqs = am33xx_mmc2_edma_reqs,
1529 .main_clk = "mmc_clk",
1532 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1533 .modulemode = MODULEMODE_SWCTRL,
1536 .dev_attr = &am33xx_mmc2_dev_attr,
1543 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1545 .sysc_offs = 0x0078,
1546 .sysc_flags = SYSC_HAS_SIDLEMODE,
1547 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1548 SIDLE_SMART | SIDLE_SMART_WKUP),
1549 .sysc_fields = &omap_hwmod_sysc_type3,
1552 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1554 .sysc = &am33xx_rtc_sysc,
1557 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1558 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1559 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1563 static struct omap_hwmod am33xx_rtc_hwmod = {
1565 .class = &am33xx_rtc_hwmod_class,
1566 .clkdm_name = "l4_rtc_clkdm",
1567 .mpu_irqs = am33xx_rtc_irqs,
1568 .main_clk = "clk_32768_ck",
1571 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1572 .modulemode = MODULEMODE_SWCTRL,
1578 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1580 .sysc_offs = 0x0110,
1581 .syss_offs = 0x0114,
1582 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1583 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1584 SYSS_HAS_RESET_STATUS),
1585 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1586 .sysc_fields = &omap_hwmod_sysc_type1,
1589 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1591 .sysc = &am33xx_mcspi_sysc,
1592 .rev = OMAP4_MCSPI_REV,
1596 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1597 { .irq = 65 + OMAP_INTC_START, },
1601 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1602 { .name = "rx0", .dma_req = 17 },
1603 { .name = "tx0", .dma_req = 16 },
1604 { .name = "rx1", .dma_req = 19 },
1605 { .name = "tx1", .dma_req = 18 },
1609 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1610 .num_chipselect = 2,
1612 static struct omap_hwmod am33xx_spi0_hwmod = {
1614 .class = &am33xx_spi_hwmod_class,
1615 .clkdm_name = "l4ls_clkdm",
1616 .mpu_irqs = am33xx_spi0_irqs,
1617 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1618 .main_clk = "dpll_per_m2_div4_ck",
1621 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1622 .modulemode = MODULEMODE_SWCTRL,
1625 .dev_attr = &mcspi_attrib,
1629 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1630 { .irq = 125 + OMAP_INTC_START, },
1634 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1635 { .name = "rx0", .dma_req = 43 },
1636 { .name = "tx0", .dma_req = 42 },
1637 { .name = "rx1", .dma_req = 45 },
1638 { .name = "tx1", .dma_req = 44 },
1642 static struct omap_hwmod am33xx_spi1_hwmod = {
1644 .class = &am33xx_spi_hwmod_class,
1645 .clkdm_name = "l4ls_clkdm",
1646 .mpu_irqs = am33xx_spi1_irqs,
1647 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1648 .main_clk = "dpll_per_m2_div4_ck",
1651 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1652 .modulemode = MODULEMODE_SWCTRL,
1655 .dev_attr = &mcspi_attrib,
1660 * spinlock provides hardware assistance for synchronizing the
1661 * processes running on multiple processors
1663 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1667 static struct omap_hwmod am33xx_spinlock_hwmod = {
1669 .class = &am33xx_spinlock_hwmod_class,
1670 .clkdm_name = "l4ls_clkdm",
1671 .main_clk = "l4ls_gclk",
1674 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1675 .modulemode = MODULEMODE_SWCTRL,
1680 /* 'timer 2-7' class */
1681 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1683 .sysc_offs = 0x0010,
1684 .syss_offs = 0x0014,
1685 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1686 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1688 .sysc_fields = &omap_hwmod_sysc_type2,
1691 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1693 .sysc = &am33xx_timer_sysc,
1697 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1699 .sysc_offs = 0x0010,
1700 .syss_offs = 0x0014,
1701 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1702 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1703 SYSS_HAS_RESET_STATUS),
1704 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1705 .sysc_fields = &omap_hwmod_sysc_type1,
1708 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1710 .sysc = &am33xx_timer1ms_sysc,
1713 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1714 { .irq = 67 + OMAP_INTC_START, },
1718 static struct omap_hwmod am33xx_timer1_hwmod = {
1720 .class = &am33xx_timer1ms_hwmod_class,
1721 .clkdm_name = "l4_wkup_clkdm",
1722 .mpu_irqs = am33xx_timer1_irqs,
1723 .main_clk = "timer1_fck",
1726 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1727 .modulemode = MODULEMODE_SWCTRL,
1732 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1733 { .irq = 68 + OMAP_INTC_START, },
1737 static struct omap_hwmod am33xx_timer2_hwmod = {
1739 .class = &am33xx_timer_hwmod_class,
1740 .clkdm_name = "l4ls_clkdm",
1741 .mpu_irqs = am33xx_timer2_irqs,
1742 .main_clk = "timer2_fck",
1745 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1746 .modulemode = MODULEMODE_SWCTRL,
1751 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1752 { .irq = 69 + OMAP_INTC_START, },
1756 static struct omap_hwmod am33xx_timer3_hwmod = {
1758 .class = &am33xx_timer_hwmod_class,
1759 .clkdm_name = "l4ls_clkdm",
1760 .mpu_irqs = am33xx_timer3_irqs,
1761 .main_clk = "timer3_fck",
1764 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1765 .modulemode = MODULEMODE_SWCTRL,
1770 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1771 { .irq = 92 + OMAP_INTC_START, },
1775 static struct omap_hwmod am33xx_timer4_hwmod = {
1777 .class = &am33xx_timer_hwmod_class,
1778 .clkdm_name = "l4ls_clkdm",
1779 .mpu_irqs = am33xx_timer4_irqs,
1780 .main_clk = "timer4_fck",
1783 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1784 .modulemode = MODULEMODE_SWCTRL,
1789 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1790 { .irq = 93 + OMAP_INTC_START, },
1794 static struct omap_hwmod am33xx_timer5_hwmod = {
1796 .class = &am33xx_timer_hwmod_class,
1797 .clkdm_name = "l4ls_clkdm",
1798 .mpu_irqs = am33xx_timer5_irqs,
1799 .main_clk = "timer5_fck",
1802 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1803 .modulemode = MODULEMODE_SWCTRL,
1808 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1809 { .irq = 94 + OMAP_INTC_START, },
1813 static struct omap_hwmod am33xx_timer6_hwmod = {
1815 .class = &am33xx_timer_hwmod_class,
1816 .clkdm_name = "l4ls_clkdm",
1817 .mpu_irqs = am33xx_timer6_irqs,
1818 .main_clk = "timer6_fck",
1821 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1822 .modulemode = MODULEMODE_SWCTRL,
1827 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1828 { .irq = 95 + OMAP_INTC_START, },
1832 static struct omap_hwmod am33xx_timer7_hwmod = {
1834 .class = &am33xx_timer_hwmod_class,
1835 .clkdm_name = "l4ls_clkdm",
1836 .mpu_irqs = am33xx_timer7_irqs,
1837 .main_clk = "timer7_fck",
1840 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1841 .modulemode = MODULEMODE_SWCTRL,
1847 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1851 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1852 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1853 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1854 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1858 static struct omap_hwmod am33xx_tpcc_hwmod = {
1860 .class = &am33xx_tpcc_hwmod_class,
1861 .clkdm_name = "l3_clkdm",
1862 .mpu_irqs = am33xx_tpcc_irqs,
1863 .main_clk = "l3_gclk",
1866 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1867 .modulemode = MODULEMODE_SWCTRL,
1872 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1875 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1876 SYSC_HAS_MIDLEMODE),
1877 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1878 .sysc_fields = &omap_hwmod_sysc_type2,
1882 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1884 .sysc = &am33xx_tptc_sysc,
1888 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1889 { .irq = 112 + OMAP_INTC_START, },
1893 static struct omap_hwmod am33xx_tptc0_hwmod = {
1895 .class = &am33xx_tptc_hwmod_class,
1896 .clkdm_name = "l3_clkdm",
1897 .mpu_irqs = am33xx_tptc0_irqs,
1898 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1899 .main_clk = "l3_gclk",
1902 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1903 .modulemode = MODULEMODE_SWCTRL,
1909 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1910 { .irq = 113 + OMAP_INTC_START, },
1914 static struct omap_hwmod am33xx_tptc1_hwmod = {
1916 .class = &am33xx_tptc_hwmod_class,
1917 .clkdm_name = "l3_clkdm",
1918 .mpu_irqs = am33xx_tptc1_irqs,
1919 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1920 .main_clk = "l3_gclk",
1923 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1924 .modulemode = MODULEMODE_SWCTRL,
1930 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1931 { .irq = 114 + OMAP_INTC_START, },
1935 static struct omap_hwmod am33xx_tptc2_hwmod = {
1937 .class = &am33xx_tptc_hwmod_class,
1938 .clkdm_name = "l3_clkdm",
1939 .mpu_irqs = am33xx_tptc2_irqs,
1940 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1941 .main_clk = "l3_gclk",
1944 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1945 .modulemode = MODULEMODE_SWCTRL,
1951 static struct omap_hwmod_class_sysconfig uart_sysc = {
1955 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1956 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1957 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1959 .sysc_fields = &omap_hwmod_sysc_type1,
1962 static struct omap_hwmod_class uart_class = {
1968 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1969 { .name = "tx", .dma_req = 26, },
1970 { .name = "rx", .dma_req = 27, },
1974 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1975 { .irq = 72 + OMAP_INTC_START, },
1979 static struct omap_hwmod am33xx_uart1_hwmod = {
1981 .class = &uart_class,
1982 .clkdm_name = "l4_wkup_clkdm",
1983 .mpu_irqs = am33xx_uart1_irqs,
1984 .sdma_reqs = uart1_edma_reqs,
1985 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1988 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1989 .modulemode = MODULEMODE_SWCTRL,
1994 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1995 { .irq = 73 + OMAP_INTC_START, },
1999 static struct omap_hwmod am33xx_uart2_hwmod = {
2001 .class = &uart_class,
2002 .clkdm_name = "l4ls_clkdm",
2003 .mpu_irqs = am33xx_uart2_irqs,
2004 .sdma_reqs = uart1_edma_reqs,
2005 .main_clk = "dpll_per_m2_div4_ck",
2008 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2009 .modulemode = MODULEMODE_SWCTRL,
2015 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2016 { .name = "tx", .dma_req = 30, },
2017 { .name = "rx", .dma_req = 31, },
2021 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2022 { .irq = 74 + OMAP_INTC_START, },
2026 static struct omap_hwmod am33xx_uart3_hwmod = {
2028 .class = &uart_class,
2029 .clkdm_name = "l4ls_clkdm",
2030 .mpu_irqs = am33xx_uart3_irqs,
2031 .sdma_reqs = uart3_edma_reqs,
2032 .main_clk = "dpll_per_m2_div4_ck",
2035 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2036 .modulemode = MODULEMODE_SWCTRL,
2041 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2042 { .irq = 44 + OMAP_INTC_START, },
2046 static struct omap_hwmod am33xx_uart4_hwmod = {
2048 .class = &uart_class,
2049 .clkdm_name = "l4ls_clkdm",
2050 .mpu_irqs = am33xx_uart4_irqs,
2051 .sdma_reqs = uart1_edma_reqs,
2052 .main_clk = "dpll_per_m2_div4_ck",
2055 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2056 .modulemode = MODULEMODE_SWCTRL,
2061 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2062 { .irq = 45 + OMAP_INTC_START, },
2066 static struct omap_hwmod am33xx_uart5_hwmod = {
2068 .class = &uart_class,
2069 .clkdm_name = "l4ls_clkdm",
2070 .mpu_irqs = am33xx_uart5_irqs,
2071 .sdma_reqs = uart1_edma_reqs,
2072 .main_clk = "dpll_per_m2_div4_ck",
2075 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2076 .modulemode = MODULEMODE_SWCTRL,
2081 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2082 { .irq = 46 + OMAP_INTC_START, },
2086 static struct omap_hwmod am33xx_uart6_hwmod = {
2088 .class = &uart_class,
2089 .clkdm_name = "l4ls_clkdm",
2090 .mpu_irqs = am33xx_uart6_irqs,
2091 .sdma_reqs = uart1_edma_reqs,
2092 .main_clk = "dpll_per_m2_div4_ck",
2095 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2096 .modulemode = MODULEMODE_SWCTRL,
2101 /* 'wd_timer' class */
2102 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2107 * XXX: device.c file uses hardcoded name for watchdog timer
2108 * driver "wd_timer2, so we are also using same name as of now...
2110 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2111 .name = "wd_timer2",
2112 .class = &am33xx_wd_timer_hwmod_class,
2113 .clkdm_name = "l4_wkup_clkdm",
2114 .main_clk = "wdt1_fck",
2117 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2118 .modulemode = MODULEMODE_SWCTRL,
2125 * high-speed on-the-go universal serial bus (usb_otg) controller
2127 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2130 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2132 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2133 .sysc_fields = &omap_hwmod_sysc_type2,
2136 static struct omap_hwmod_class am33xx_usbotg_class = {
2138 .sysc = &am33xx_usbhsotg_sysc,
2141 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2142 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2143 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2144 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2148 static struct omap_hwmod am33xx_usbss_hwmod = {
2149 .name = "usb_otg_hs",
2150 .class = &am33xx_usbotg_class,
2151 .clkdm_name = "l3s_clkdm",
2152 .mpu_irqs = am33xx_usbss_mpu_irqs,
2153 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2154 .main_clk = "usbotg_fck",
2157 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2158 .modulemode = MODULEMODE_SWCTRL,
2168 /* l4 fw -> emif fw */
2169 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2170 .master = &am33xx_l4_fw_hwmod,
2171 .slave = &am33xx_emif_fw_hwmod,
2173 .user = OCP_USER_MPU,
2176 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2178 .pa_start = 0x4c000000,
2179 .pa_end = 0x4c000fff,
2180 .flags = ADDR_TYPE_RT
2184 /* l3 main -> emif */
2185 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2186 .master = &am33xx_l3_main_hwmod,
2187 .slave = &am33xx_emif_hwmod,
2188 .clk = "dpll_core_m4_ck",
2189 .addr = am33xx_emif_addrs,
2190 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193 /* mpu -> l3 main */
2194 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2195 .master = &am33xx_mpu_hwmod,
2196 .slave = &am33xx_l3_main_hwmod,
2197 .clk = "dpll_mpu_m2_ck",
2198 .user = OCP_USER_MPU,
2201 /* l3 main -> l4 hs */
2202 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2203 .master = &am33xx_l3_main_hwmod,
2204 .slave = &am33xx_l4_hs_hwmod,
2206 .user = OCP_USER_MPU | OCP_USER_SDMA,
2209 /* l3 main -> l3 s */
2210 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2211 .master = &am33xx_l3_main_hwmod,
2212 .slave = &am33xx_l3_s_hwmod,
2214 .user = OCP_USER_MPU | OCP_USER_SDMA,
2217 /* l3 s -> l4 per/ls */
2218 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2219 .master = &am33xx_l3_s_hwmod,
2220 .slave = &am33xx_l4_ls_hwmod,
2222 .user = OCP_USER_MPU | OCP_USER_SDMA,
2225 /* l3 s -> l4 wkup */
2226 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2227 .master = &am33xx_l3_s_hwmod,
2228 .slave = &am33xx_l4_wkup_hwmod,
2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2234 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2235 .master = &am33xx_l3_s_hwmod,
2236 .slave = &am33xx_l4_fw_hwmod,
2238 .user = OCP_USER_MPU | OCP_USER_SDMA,
2241 /* l3 main -> l3 instr */
2242 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2243 .master = &am33xx_l3_main_hwmod,
2244 .slave = &am33xx_l3_instr_hwmod,
2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2250 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2251 .master = &am33xx_mpu_hwmod,
2252 .slave = &am33xx_prcm_hwmod,
2253 .clk = "dpll_mpu_m2_ck",
2254 .user = OCP_USER_MPU | OCP_USER_SDMA,
2257 /* l3 s -> l3 main*/
2258 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2259 .master = &am33xx_l3_s_hwmod,
2260 .slave = &am33xx_l3_main_hwmod,
2262 .user = OCP_USER_MPU | OCP_USER_SDMA,
2265 /* pru-icss -> l3 main */
2266 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2267 .master = &am33xx_pruss_hwmod,
2268 .slave = &am33xx_l3_main_hwmod,
2270 .user = OCP_USER_MPU | OCP_USER_SDMA,
2273 /* wkup m3 -> l4 wkup */
2274 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2275 .master = &am33xx_wkup_m3_hwmod,
2276 .slave = &am33xx_l4_wkup_hwmod,
2277 .clk = "dpll_core_m4_div2_ck",
2278 .user = OCP_USER_MPU | OCP_USER_SDMA,
2281 /* gfx -> l3 main */
2282 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2283 .master = &am33xx_gfx_hwmod,
2284 .slave = &am33xx_l3_main_hwmod,
2285 .clk = "dpll_core_m4_ck",
2286 .user = OCP_USER_MPU | OCP_USER_SDMA,
2289 /* l4 wkup -> wkup m3 */
2290 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2293 .pa_start = 0x44d00000,
2294 .pa_end = 0x44d00000 + SZ_16K - 1,
2295 .flags = ADDR_TYPE_RT
2299 .pa_start = 0x44d80000,
2300 .pa_end = 0x44d80000 + SZ_8K - 1,
2301 .flags = ADDR_TYPE_RT
2306 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2307 .master = &am33xx_l4_wkup_hwmod,
2308 .slave = &am33xx_wkup_m3_hwmod,
2309 .clk = "dpll_core_m4_div2_ck",
2310 .addr = am33xx_wkup_m3_addrs,
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2314 /* l4 hs -> pru-icss */
2315 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2317 .pa_start = 0x4a300000,
2318 .pa_end = 0x4a300000 + SZ_512K - 1,
2319 .flags = ADDR_TYPE_RT
2324 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2325 .master = &am33xx_l4_hs_hwmod,
2326 .slave = &am33xx_pruss_hwmod,
2327 .clk = "dpll_core_m4_ck",
2328 .addr = am33xx_pruss_addrs,
2329 .user = OCP_USER_MPU | OCP_USER_SDMA,
2332 /* l3 main -> gfx */
2333 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2335 .pa_start = 0x56000000,
2336 .pa_end = 0x56000000 + SZ_16M - 1,
2337 .flags = ADDR_TYPE_RT
2342 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2343 .master = &am33xx_l3_main_hwmod,
2344 .slave = &am33xx_gfx_hwmod,
2345 .clk = "dpll_core_m4_ck",
2346 .addr = am33xx_gfx_addrs,
2347 .user = OCP_USER_MPU | OCP_USER_SDMA,
2350 /* l4 wkup -> smartreflex0 */
2351 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2353 .pa_start = 0x44e37000,
2354 .pa_end = 0x44e37000 + SZ_4K - 1,
2355 .flags = ADDR_TYPE_RT
2360 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2361 .master = &am33xx_l4_wkup_hwmod,
2362 .slave = &am33xx_smartreflex0_hwmod,
2363 .clk = "dpll_core_m4_div2_ck",
2364 .addr = am33xx_smartreflex0_addrs,
2365 .user = OCP_USER_MPU,
2368 /* l4 wkup -> smartreflex1 */
2369 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2371 .pa_start = 0x44e39000,
2372 .pa_end = 0x44e39000 + SZ_4K - 1,
2373 .flags = ADDR_TYPE_RT
2378 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2379 .master = &am33xx_l4_wkup_hwmod,
2380 .slave = &am33xx_smartreflex1_hwmod,
2381 .clk = "dpll_core_m4_div2_ck",
2382 .addr = am33xx_smartreflex1_addrs,
2383 .user = OCP_USER_MPU,
2386 /* l4 wkup -> control */
2387 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2389 .pa_start = 0x44e10000,
2390 .pa_end = 0x44e10000 + SZ_8K - 1,
2391 .flags = ADDR_TYPE_RT
2396 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2397 .master = &am33xx_l4_wkup_hwmod,
2398 .slave = &am33xx_control_hwmod,
2399 .clk = "dpll_core_m4_div2_ck",
2400 .addr = am33xx_control_addrs,
2401 .user = OCP_USER_MPU,
2404 /* l4 wkup -> rtc */
2405 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2407 .pa_start = 0x44e3e000,
2408 .pa_end = 0x44e3e000 + SZ_4K - 1,
2409 .flags = ADDR_TYPE_RT
2414 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2415 .master = &am33xx_l4_wkup_hwmod,
2416 .slave = &am33xx_rtc_hwmod,
2417 .clk = "clkdiv32k_ick",
2418 .addr = am33xx_rtc_addrs,
2419 .user = OCP_USER_MPU,
2422 /* l4 per/ls -> DCAN0 */
2423 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2425 .pa_start = 0x481CC000,
2426 .pa_end = 0x481CC000 + SZ_4K - 1,
2427 .flags = ADDR_TYPE_RT
2432 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2433 .master = &am33xx_l4_ls_hwmod,
2434 .slave = &am33xx_dcan0_hwmod,
2436 .addr = am33xx_dcan0_addrs,
2437 .user = OCP_USER_MPU | OCP_USER_SDMA,
2440 /* l4 per/ls -> DCAN1 */
2441 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2443 .pa_start = 0x481D0000,
2444 .pa_end = 0x481D0000 + SZ_4K - 1,
2445 .flags = ADDR_TYPE_RT
2450 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2451 .master = &am33xx_l4_ls_hwmod,
2452 .slave = &am33xx_dcan1_hwmod,
2454 .addr = am33xx_dcan1_addrs,
2455 .user = OCP_USER_MPU | OCP_USER_SDMA,
2458 /* l4 per/ls -> GPIO2 */
2459 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2461 .pa_start = 0x4804C000,
2462 .pa_end = 0x4804C000 + SZ_4K - 1,
2463 .flags = ADDR_TYPE_RT,
2468 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2469 .master = &am33xx_l4_ls_hwmod,
2470 .slave = &am33xx_gpio1_hwmod,
2472 .addr = am33xx_gpio1_addrs,
2473 .user = OCP_USER_MPU | OCP_USER_SDMA,
2476 /* l4 per/ls -> gpio3 */
2477 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2479 .pa_start = 0x481AC000,
2480 .pa_end = 0x481AC000 + SZ_4K - 1,
2481 .flags = ADDR_TYPE_RT,
2486 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2487 .master = &am33xx_l4_ls_hwmod,
2488 .slave = &am33xx_gpio2_hwmod,
2490 .addr = am33xx_gpio2_addrs,
2491 .user = OCP_USER_MPU | OCP_USER_SDMA,
2494 /* l4 per/ls -> gpio4 */
2495 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2497 .pa_start = 0x481AE000,
2498 .pa_end = 0x481AE000 + SZ_4K - 1,
2499 .flags = ADDR_TYPE_RT,
2504 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2505 .master = &am33xx_l4_ls_hwmod,
2506 .slave = &am33xx_gpio3_hwmod,
2508 .addr = am33xx_gpio3_addrs,
2509 .user = OCP_USER_MPU | OCP_USER_SDMA,
2512 /* L4 WKUP -> I2C1 */
2513 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2515 .pa_start = 0x44E0B000,
2516 .pa_end = 0x44E0B000 + SZ_4K - 1,
2517 .flags = ADDR_TYPE_RT,
2522 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2523 .master = &am33xx_l4_wkup_hwmod,
2524 .slave = &am33xx_i2c1_hwmod,
2525 .clk = "dpll_core_m4_div2_ck",
2526 .addr = am33xx_i2c1_addr_space,
2527 .user = OCP_USER_MPU,
2530 /* L4 WKUP -> GPIO1 */
2531 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2533 .pa_start = 0x44E07000,
2534 .pa_end = 0x44E07000 + SZ_4K - 1,
2535 .flags = ADDR_TYPE_RT,
2540 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2541 .master = &am33xx_l4_wkup_hwmod,
2542 .slave = &am33xx_gpio0_hwmod,
2543 .clk = "dpll_core_m4_div2_ck",
2544 .addr = am33xx_gpio0_addrs,
2545 .user = OCP_USER_MPU | OCP_USER_SDMA,
2548 /* L4 WKUP -> ADC_TSC */
2549 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2551 .pa_start = 0x44E0D000,
2552 .pa_end = 0x44E0D000 + SZ_8K - 1,
2553 .flags = ADDR_TYPE_RT
2558 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2559 .master = &am33xx_l4_wkup_hwmod,
2560 .slave = &am33xx_adc_tsc_hwmod,
2561 .clk = "dpll_core_m4_div2_ck",
2562 .addr = am33xx_adc_tsc_addrs,
2563 .user = OCP_USER_MPU,
2566 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2569 .pa_start = 0x4a100000,
2570 .pa_end = 0x4a100000 + SZ_2K - 1,
2574 .pa_start = 0x4a101200,
2575 .pa_end = 0x4a101200 + SZ_256 - 1,
2576 .flags = ADDR_TYPE_RT,
2581 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2582 .master = &am33xx_l4_hs_hwmod,
2583 .slave = &am33xx_cpgmac0_hwmod,
2584 .clk = "cpsw_125mhz_gclk",
2585 .addr = am33xx_cpgmac0_addr_space,
2586 .user = OCP_USER_MPU,
2589 static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2591 .pa_start = 0x4A101000,
2592 .pa_end = 0x4A101000 + SZ_256 - 1,
2597 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2598 .master = &am33xx_cpgmac0_hwmod,
2599 .slave = &am33xx_mdio_hwmod,
2600 .addr = am33xx_mdio_addr_space,
2601 .user = OCP_USER_MPU,
2604 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2606 .pa_start = 0x48080000,
2607 .pa_end = 0x48080000 + SZ_8K - 1,
2608 .flags = ADDR_TYPE_RT
2613 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2614 .master = &am33xx_l4_ls_hwmod,
2615 .slave = &am33xx_elm_hwmod,
2617 .addr = am33xx_elm_addr_space,
2618 .user = OCP_USER_MPU,
2621 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2623 .pa_start = 0x48300000,
2624 .pa_end = 0x48300000 + SZ_16 - 1,
2625 .flags = ADDR_TYPE_RT
2630 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2631 .master = &am33xx_l4_ls_hwmod,
2632 .slave = &am33xx_epwmss0_hwmod,
2634 .addr = am33xx_epwmss0_addr_space,
2635 .user = OCP_USER_MPU,
2638 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2640 .pa_start = 0x48300100,
2641 .pa_end = 0x48300100 + SZ_128 - 1,
2646 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2647 .master = &am33xx_epwmss0_hwmod,
2648 .slave = &am33xx_ecap0_hwmod,
2650 .addr = am33xx_ecap0_addr_space,
2651 .user = OCP_USER_MPU,
2654 static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2656 .pa_start = 0x48300180,
2657 .pa_end = 0x48300180 + SZ_128 - 1,
2662 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2663 .master = &am33xx_epwmss0_hwmod,
2664 .slave = &am33xx_eqep0_hwmod,
2666 .addr = am33xx_eqep0_addr_space,
2667 .user = OCP_USER_MPU,
2670 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2672 .pa_start = 0x48300200,
2673 .pa_end = 0x48300200 + SZ_128 - 1,
2678 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2679 .master = &am33xx_epwmss0_hwmod,
2680 .slave = &am33xx_ehrpwm0_hwmod,
2682 .addr = am33xx_ehrpwm0_addr_space,
2683 .user = OCP_USER_MPU,
2687 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2689 .pa_start = 0x48302000,
2690 .pa_end = 0x48302000 + SZ_16 - 1,
2691 .flags = ADDR_TYPE_RT
2696 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2697 .master = &am33xx_l4_ls_hwmod,
2698 .slave = &am33xx_epwmss1_hwmod,
2700 .addr = am33xx_epwmss1_addr_space,
2701 .user = OCP_USER_MPU,
2704 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2706 .pa_start = 0x48302100,
2707 .pa_end = 0x48302100 + SZ_128 - 1,
2712 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2713 .master = &am33xx_epwmss1_hwmod,
2714 .slave = &am33xx_ecap1_hwmod,
2716 .addr = am33xx_ecap1_addr_space,
2717 .user = OCP_USER_MPU,
2720 static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2722 .pa_start = 0x48302180,
2723 .pa_end = 0x48302180 + SZ_128 - 1,
2728 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2729 .master = &am33xx_epwmss1_hwmod,
2730 .slave = &am33xx_eqep1_hwmod,
2732 .addr = am33xx_eqep1_addr_space,
2733 .user = OCP_USER_MPU,
2736 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2738 .pa_start = 0x48302200,
2739 .pa_end = 0x48302200 + SZ_128 - 1,
2744 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2745 .master = &am33xx_epwmss1_hwmod,
2746 .slave = &am33xx_ehrpwm1_hwmod,
2748 .addr = am33xx_ehrpwm1_addr_space,
2749 .user = OCP_USER_MPU,
2752 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2754 .pa_start = 0x48304000,
2755 .pa_end = 0x48304000 + SZ_16 - 1,
2756 .flags = ADDR_TYPE_RT
2761 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2762 .master = &am33xx_l4_ls_hwmod,
2763 .slave = &am33xx_epwmss2_hwmod,
2765 .addr = am33xx_epwmss2_addr_space,
2766 .user = OCP_USER_MPU,
2769 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2771 .pa_start = 0x48304100,
2772 .pa_end = 0x48304100 + SZ_128 - 1,
2777 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2778 .master = &am33xx_epwmss2_hwmod,
2779 .slave = &am33xx_ecap2_hwmod,
2781 .addr = am33xx_ecap2_addr_space,
2782 .user = OCP_USER_MPU,
2785 static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2787 .pa_start = 0x48304180,
2788 .pa_end = 0x48304180 + SZ_128 - 1,
2793 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2794 .master = &am33xx_epwmss2_hwmod,
2795 .slave = &am33xx_eqep2_hwmod,
2797 .addr = am33xx_eqep2_addr_space,
2798 .user = OCP_USER_MPU,
2801 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2803 .pa_start = 0x48304200,
2804 .pa_end = 0x48304200 + SZ_128 - 1,
2809 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2810 .master = &am33xx_epwmss2_hwmod,
2811 .slave = &am33xx_ehrpwm2_hwmod,
2813 .addr = am33xx_ehrpwm2_addr_space,
2814 .user = OCP_USER_MPU,
2817 /* l3s cfg -> gpmc */
2818 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2820 .pa_start = 0x50000000,
2821 .pa_end = 0x50000000 + SZ_8K - 1,
2822 .flags = ADDR_TYPE_RT,
2827 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2828 .master = &am33xx_l3_s_hwmod,
2829 .slave = &am33xx_gpmc_hwmod,
2831 .addr = am33xx_gpmc_addr_space,
2832 .user = OCP_USER_MPU,
2836 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2838 .pa_start = 0x4802A000,
2839 .pa_end = 0x4802A000 + SZ_4K - 1,
2840 .flags = ADDR_TYPE_RT,
2845 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2846 .master = &am33xx_l4_ls_hwmod,
2847 .slave = &am33xx_i2c2_hwmod,
2849 .addr = am33xx_i2c2_addr_space,
2850 .user = OCP_USER_MPU,
2853 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2855 .pa_start = 0x4819C000,
2856 .pa_end = 0x4819C000 + SZ_4K - 1,
2857 .flags = ADDR_TYPE_RT
2862 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2863 .master = &am33xx_l4_ls_hwmod,
2864 .slave = &am33xx_i2c3_hwmod,
2866 .addr = am33xx_i2c3_addr_space,
2867 .user = OCP_USER_MPU,
2870 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2872 .pa_start = 0x4830E000,
2873 .pa_end = 0x4830E000 + SZ_8K - 1,
2874 .flags = ADDR_TYPE_RT,
2879 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2880 .master = &am33xx_l3_main_hwmod,
2881 .slave = &am33xx_lcdc_hwmod,
2882 .clk = "dpll_core_m4_ck",
2883 .addr = am33xx_lcdc_addr_space,
2884 .user = OCP_USER_MPU,
2887 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2889 .pa_start = 0x480C8000,
2890 .pa_end = 0x480C8000 + (SZ_4K - 1),
2891 .flags = ADDR_TYPE_RT
2896 /* l4 ls -> mailbox */
2897 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2898 .master = &am33xx_l4_ls_hwmod,
2899 .slave = &am33xx_mailbox_hwmod,
2901 .addr = am33xx_mailbox_addrs,
2902 .user = OCP_USER_MPU,
2905 /* l4 ls -> spinlock */
2906 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2908 .pa_start = 0x480Ca000,
2909 .pa_end = 0x480Ca000 + SZ_4K - 1,
2910 .flags = ADDR_TYPE_RT
2915 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2916 .master = &am33xx_l4_ls_hwmod,
2917 .slave = &am33xx_spinlock_hwmod,
2919 .addr = am33xx_spinlock_addrs,
2920 .user = OCP_USER_MPU,
2923 /* l4 ls -> mcasp0 */
2924 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2926 .pa_start = 0x48038000,
2927 .pa_end = 0x48038000 + SZ_8K - 1,
2928 .flags = ADDR_TYPE_RT
2933 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2934 .master = &am33xx_l4_ls_hwmod,
2935 .slave = &am33xx_mcasp0_hwmod,
2937 .addr = am33xx_mcasp0_addr_space,
2938 .user = OCP_USER_MPU,
2941 /* l3 s -> mcasp0 data */
2942 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2944 .pa_start = 0x46000000,
2945 .pa_end = 0x46000000 + SZ_4M - 1,
2946 .flags = ADDR_TYPE_RT
2951 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2952 .master = &am33xx_l3_s_hwmod,
2953 .slave = &am33xx_mcasp0_hwmod,
2955 .addr = am33xx_mcasp0_data_addr_space,
2956 .user = OCP_USER_SDMA,
2959 /* l4 ls -> mcasp1 */
2960 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2962 .pa_start = 0x4803C000,
2963 .pa_end = 0x4803C000 + SZ_8K - 1,
2964 .flags = ADDR_TYPE_RT
2969 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2970 .master = &am33xx_l4_ls_hwmod,
2971 .slave = &am33xx_mcasp1_hwmod,
2973 .addr = am33xx_mcasp1_addr_space,
2974 .user = OCP_USER_MPU,
2977 /* l3 s -> mcasp1 data */
2978 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2980 .pa_start = 0x46400000,
2981 .pa_end = 0x46400000 + SZ_4M - 1,
2982 .flags = ADDR_TYPE_RT
2987 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
2988 .master = &am33xx_l3_s_hwmod,
2989 .slave = &am33xx_mcasp1_hwmod,
2991 .addr = am33xx_mcasp1_data_addr_space,
2992 .user = OCP_USER_SDMA,
2996 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2998 .pa_start = 0x48060100,
2999 .pa_end = 0x48060100 + SZ_4K - 1,
3000 .flags = ADDR_TYPE_RT,
3005 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
3006 .master = &am33xx_l4_ls_hwmod,
3007 .slave = &am33xx_mmc0_hwmod,
3009 .addr = am33xx_mmc0_addr_space,
3010 .user = OCP_USER_MPU,
3014 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
3016 .pa_start = 0x481d8100,
3017 .pa_end = 0x481d8100 + SZ_4K - 1,
3018 .flags = ADDR_TYPE_RT,
3023 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
3024 .master = &am33xx_l4_ls_hwmod,
3025 .slave = &am33xx_mmc1_hwmod,
3027 .addr = am33xx_mmc1_addr_space,
3028 .user = OCP_USER_MPU,
3032 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
3034 .pa_start = 0x47810100,
3035 .pa_end = 0x47810100 + SZ_64K - 1,
3036 .flags = ADDR_TYPE_RT,
3041 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3042 .master = &am33xx_l3_s_hwmod,
3043 .slave = &am33xx_mmc2_hwmod,
3045 .addr = am33xx_mmc2_addr_space,
3046 .user = OCP_USER_MPU,
3049 /* l4 ls -> mcspi0 */
3050 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3052 .pa_start = 0x48030000,
3053 .pa_end = 0x48030000 + SZ_1K - 1,
3054 .flags = ADDR_TYPE_RT,
3059 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3060 .master = &am33xx_l4_ls_hwmod,
3061 .slave = &am33xx_spi0_hwmod,
3063 .addr = am33xx_mcspi0_addr_space,
3064 .user = OCP_USER_MPU,
3067 /* l4 ls -> mcspi1 */
3068 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3070 .pa_start = 0x481A0000,
3071 .pa_end = 0x481A0000 + SZ_1K - 1,
3072 .flags = ADDR_TYPE_RT,
3077 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3078 .master = &am33xx_l4_ls_hwmod,
3079 .slave = &am33xx_spi1_hwmod,
3081 .addr = am33xx_mcspi1_addr_space,
3082 .user = OCP_USER_MPU,
3085 /* l4 wkup -> timer1 */
3086 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3088 .pa_start = 0x44E31000,
3089 .pa_end = 0x44E31000 + SZ_1K - 1,
3090 .flags = ADDR_TYPE_RT
3095 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3096 .master = &am33xx_l4_wkup_hwmod,
3097 .slave = &am33xx_timer1_hwmod,
3098 .clk = "dpll_core_m4_div2_ck",
3099 .addr = am33xx_timer1_addr_space,
3100 .user = OCP_USER_MPU,
3103 /* l4 per -> timer2 */
3104 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3106 .pa_start = 0x48040000,
3107 .pa_end = 0x48040000 + SZ_1K - 1,
3108 .flags = ADDR_TYPE_RT
3113 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3114 .master = &am33xx_l4_ls_hwmod,
3115 .slave = &am33xx_timer2_hwmod,
3117 .addr = am33xx_timer2_addr_space,
3118 .user = OCP_USER_MPU,
3121 /* l4 per -> timer3 */
3122 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3124 .pa_start = 0x48042000,
3125 .pa_end = 0x48042000 + SZ_1K - 1,
3126 .flags = ADDR_TYPE_RT
3131 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3132 .master = &am33xx_l4_ls_hwmod,
3133 .slave = &am33xx_timer3_hwmod,
3135 .addr = am33xx_timer3_addr_space,
3136 .user = OCP_USER_MPU,
3139 /* l4 per -> timer4 */
3140 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3142 .pa_start = 0x48044000,
3143 .pa_end = 0x48044000 + SZ_1K - 1,
3144 .flags = ADDR_TYPE_RT
3149 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3150 .master = &am33xx_l4_ls_hwmod,
3151 .slave = &am33xx_timer4_hwmod,
3153 .addr = am33xx_timer4_addr_space,
3154 .user = OCP_USER_MPU,
3157 /* l4 per -> timer5 */
3158 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3160 .pa_start = 0x48046000,
3161 .pa_end = 0x48046000 + SZ_1K - 1,
3162 .flags = ADDR_TYPE_RT
3167 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3168 .master = &am33xx_l4_ls_hwmod,
3169 .slave = &am33xx_timer5_hwmod,
3171 .addr = am33xx_timer5_addr_space,
3172 .user = OCP_USER_MPU,
3175 /* l4 per -> timer6 */
3176 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3178 .pa_start = 0x48048000,
3179 .pa_end = 0x48048000 + SZ_1K - 1,
3180 .flags = ADDR_TYPE_RT
3185 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3186 .master = &am33xx_l4_ls_hwmod,
3187 .slave = &am33xx_timer6_hwmod,
3189 .addr = am33xx_timer6_addr_space,
3190 .user = OCP_USER_MPU,
3193 /* l4 per -> timer7 */
3194 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3196 .pa_start = 0x4804A000,
3197 .pa_end = 0x4804A000 + SZ_1K - 1,
3198 .flags = ADDR_TYPE_RT
3203 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3204 .master = &am33xx_l4_ls_hwmod,
3205 .slave = &am33xx_timer7_hwmod,
3207 .addr = am33xx_timer7_addr_space,
3208 .user = OCP_USER_MPU,
3211 /* l3 main -> tpcc */
3212 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3214 .pa_start = 0x49000000,
3215 .pa_end = 0x49000000 + SZ_32K - 1,
3216 .flags = ADDR_TYPE_RT
3221 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3222 .master = &am33xx_l3_main_hwmod,
3223 .slave = &am33xx_tpcc_hwmod,
3225 .addr = am33xx_tpcc_addr_space,
3226 .user = OCP_USER_MPU,
3229 /* l3 main -> tpcc0 */
3230 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3232 .pa_start = 0x49800000,
3233 .pa_end = 0x49800000 + SZ_8K - 1,
3234 .flags = ADDR_TYPE_RT,
3239 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3240 .master = &am33xx_l3_main_hwmod,
3241 .slave = &am33xx_tptc0_hwmod,
3243 .addr = am33xx_tptc0_addr_space,
3244 .user = OCP_USER_MPU,
3247 /* l3 main -> tpcc1 */
3248 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3250 .pa_start = 0x49900000,
3251 .pa_end = 0x49900000 + SZ_8K - 1,
3252 .flags = ADDR_TYPE_RT,
3257 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3258 .master = &am33xx_l3_main_hwmod,
3259 .slave = &am33xx_tptc1_hwmod,
3261 .addr = am33xx_tptc1_addr_space,
3262 .user = OCP_USER_MPU,
3265 /* l3 main -> tpcc2 */
3266 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3268 .pa_start = 0x49a00000,
3269 .pa_end = 0x49a00000 + SZ_8K - 1,
3270 .flags = ADDR_TYPE_RT,
3275 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3276 .master = &am33xx_l3_main_hwmod,
3277 .slave = &am33xx_tptc2_hwmod,
3279 .addr = am33xx_tptc2_addr_space,
3280 .user = OCP_USER_MPU,
3283 /* l4 wkup -> uart1 */
3284 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3286 .pa_start = 0x44E09000,
3287 .pa_end = 0x44E09000 + SZ_8K - 1,
3288 .flags = ADDR_TYPE_RT,
3293 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3294 .master = &am33xx_l4_wkup_hwmod,
3295 .slave = &am33xx_uart1_hwmod,
3296 .clk = "dpll_core_m4_div2_ck",
3297 .addr = am33xx_uart1_addr_space,
3298 .user = OCP_USER_MPU,
3301 /* l4 ls -> uart2 */
3302 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3304 .pa_start = 0x48022000,
3305 .pa_end = 0x48022000 + SZ_8K - 1,
3306 .flags = ADDR_TYPE_RT,
3311 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3312 .master = &am33xx_l4_ls_hwmod,
3313 .slave = &am33xx_uart2_hwmod,
3315 .addr = am33xx_uart2_addr_space,
3316 .user = OCP_USER_MPU,
3319 /* l4 ls -> uart3 */
3320 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3322 .pa_start = 0x48024000,
3323 .pa_end = 0x48024000 + SZ_8K - 1,
3324 .flags = ADDR_TYPE_RT,
3329 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3330 .master = &am33xx_l4_ls_hwmod,
3331 .slave = &am33xx_uart3_hwmod,
3333 .addr = am33xx_uart3_addr_space,
3334 .user = OCP_USER_MPU,
3337 /* l4 ls -> uart4 */
3338 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3340 .pa_start = 0x481A6000,
3341 .pa_end = 0x481A6000 + SZ_8K - 1,
3342 .flags = ADDR_TYPE_RT,
3347 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3348 .master = &am33xx_l4_ls_hwmod,
3349 .slave = &am33xx_uart4_hwmod,
3351 .addr = am33xx_uart4_addr_space,
3352 .user = OCP_USER_MPU,
3355 /* l4 ls -> uart5 */
3356 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3358 .pa_start = 0x481A8000,
3359 .pa_end = 0x481A8000 + SZ_8K - 1,
3360 .flags = ADDR_TYPE_RT,
3365 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3366 .master = &am33xx_l4_ls_hwmod,
3367 .slave = &am33xx_uart5_hwmod,
3369 .addr = am33xx_uart5_addr_space,
3370 .user = OCP_USER_MPU,
3373 /* l4 ls -> uart6 */
3374 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3376 .pa_start = 0x481aa000,
3377 .pa_end = 0x481aa000 + SZ_8K - 1,
3378 .flags = ADDR_TYPE_RT,
3383 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3384 .master = &am33xx_l4_ls_hwmod,
3385 .slave = &am33xx_uart6_hwmod,
3387 .addr = am33xx_uart6_addr_space,
3388 .user = OCP_USER_MPU,
3391 /* l4 wkup -> wd_timer1 */
3392 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3394 .pa_start = 0x44e35000,
3395 .pa_end = 0x44e35000 + SZ_4K - 1,
3396 .flags = ADDR_TYPE_RT
3401 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3402 .master = &am33xx_l4_wkup_hwmod,
3403 .slave = &am33xx_wd_timer1_hwmod,
3404 .clk = "dpll_core_m4_div2_ck",
3405 .addr = am33xx_wd_timer1_addrs,
3406 .user = OCP_USER_MPU,
3410 /* l3 s -> USBSS interface */
3411 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3414 .pa_start = 0x47400000,
3415 .pa_end = 0x47400000 + SZ_4K - 1,
3416 .flags = ADDR_TYPE_RT
3420 .pa_start = 0x47401000,
3421 .pa_end = 0x47401000 + SZ_2K - 1,
3422 .flags = ADDR_TYPE_RT
3426 .pa_start = 0x47401800,
3427 .pa_end = 0x47401800 + SZ_2K - 1,
3428 .flags = ADDR_TYPE_RT
3433 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3434 .master = &am33xx_l3_s_hwmod,
3435 .slave = &am33xx_usbss_hwmod,
3437 .addr = am33xx_usbss_addr_space,
3438 .user = OCP_USER_MPU,
3439 .flags = OCPIF_SWSUP_IDLE,
3442 /* l3 main -> ocmc */
3443 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3444 .master = &am33xx_l3_main_hwmod,
3445 .slave = &am33xx_ocmcram_hwmod,
3446 .user = OCP_USER_MPU | OCP_USER_SDMA,
3449 /* l3 main -> sha0 HIB2 */
3450 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
3452 .pa_start = 0x53100000,
3453 .pa_end = 0x53100000 + SZ_512 - 1,
3454 .flags = ADDR_TYPE_RT
3459 static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
3460 .master = &am33xx_l3_main_hwmod,
3461 .slave = &am33xx_sha0_hwmod,
3463 .addr = am33xx_sha0_addrs,
3464 .user = OCP_USER_MPU | OCP_USER_SDMA,
3467 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3468 &am33xx_l4_fw__emif_fw,
3469 &am33xx_l3_main__emif,
3470 &am33xx_mpu__l3_main,
3472 &am33xx_l3_s__l4_ls,
3473 &am33xx_l3_s__l4_wkup,
3474 &am33xx_l3_s__l4_fw,
3475 &am33xx_l3_main__l4_hs,
3476 &am33xx_l3_main__l3_s,
3477 &am33xx_l3_main__l3_instr,
3478 &am33xx_l3_main__gfx,
3479 &am33xx_l3_s__l3_main,
3480 &am33xx_pruss__l3_main,
3481 &am33xx_wkup_m3__l4_wkup,
3482 &am33xx_gfx__l3_main,
3483 &am33xx_l4_wkup__wkup_m3,
3484 &am33xx_l4_wkup__control,
3485 &am33xx_l4_wkup__smartreflex0,
3486 &am33xx_l4_wkup__smartreflex1,
3487 &am33xx_l4_wkup__uart1,
3488 &am33xx_l4_wkup__timer1,
3489 &am33xx_l4_wkup__rtc,
3490 &am33xx_l4_wkup__i2c1,
3491 &am33xx_l4_wkup__gpio0,
3492 &am33xx_l4_wkup__adc_tsc,
3493 &am33xx_l4_wkup__wd_timer1,
3494 &am33xx_l4_hs__pruss,
3495 &am33xx_l4_per__dcan0,
3496 &am33xx_l4_per__dcan1,
3497 &am33xx_l4_per__gpio1,
3498 &am33xx_l4_per__gpio2,
3499 &am33xx_l4_per__gpio3,
3500 &am33xx_l4_per__i2c2,
3501 &am33xx_l4_per__i2c3,
3502 &am33xx_l4_per__mailbox,
3503 &am33xx_l4_ls__mcasp0,
3504 &am33xx_l3_s__mcasp0_data,
3505 &am33xx_l4_ls__mcasp1,
3506 &am33xx_l3_s__mcasp1_data,
3507 &am33xx_l4_ls__mmc0,
3508 &am33xx_l4_ls__mmc1,
3510 &am33xx_l4_ls__timer2,
3511 &am33xx_l4_ls__timer3,
3512 &am33xx_l4_ls__timer4,
3513 &am33xx_l4_ls__timer5,
3514 &am33xx_l4_ls__timer6,
3515 &am33xx_l4_ls__timer7,
3516 &am33xx_l3_main__tpcc,
3517 &am33xx_l4_ls__uart2,
3518 &am33xx_l4_ls__uart3,
3519 &am33xx_l4_ls__uart4,
3520 &am33xx_l4_ls__uart5,
3521 &am33xx_l4_ls__uart6,
3522 &am33xx_l4_ls__spinlock,
3524 &am33xx_l4_ls__epwmss0,
3525 &am33xx_epwmss0__ecap0,
3526 &am33xx_epwmss0__eqep0,
3527 &am33xx_epwmss0__ehrpwm0,
3528 &am33xx_l4_ls__epwmss1,
3529 &am33xx_epwmss1__ecap1,
3530 &am33xx_epwmss1__eqep1,
3531 &am33xx_epwmss1__ehrpwm1,
3532 &am33xx_l4_ls__epwmss2,
3533 &am33xx_epwmss2__ecap2,
3534 &am33xx_epwmss2__eqep2,
3535 &am33xx_epwmss2__ehrpwm2,
3537 &am33xx_l3_main__lcdc,
3538 &am33xx_l4_ls__mcspi0,
3539 &am33xx_l4_ls__mcspi1,
3540 &am33xx_l3_main__tptc0,
3541 &am33xx_l3_main__tptc1,
3542 &am33xx_l3_main__tptc2,
3543 &am33xx_l3_main__ocmc,
3544 &am33xx_l3_s__usbss,
3545 &am33xx_l4_hs__cpgmac0,
3546 &am33xx_cpgmac0__mdio,
3547 &am33xx_l3_main__sha0,
3551 int __init am33xx_hwmod_init(void)
3554 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);