arch/arm/mach-omap2/omap_hwmod_33xx_data.c

   1 /*
   2  * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
   3  *
   4  * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is automatically generated from the AM33XX hardware databases.
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/i2c-omap.h>
  18
  19 #include "omap_hwmod.h"
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/spi-omap2-mcspi.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24
  25 #include "control.h"
  26 #include "cm33xx.h"
  27 #include "prm33xx.h"
  28 #include "prm-regbits-33xx.h"
  29 #include "i2c.h"
  30 #include "mmc.h"
  31
  32 /*
  33  * IP blocks
  34  */
  35
  36 /*
  37  * 'emif_fw' class
  38  * instance(s): emif_fw
  39  */
  40 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
  41         .name           = "emif_fw",
  42 };
  43
  44 /* emif_fw */
  45 static struct omap_hwmod am33xx_emif_fw_hwmod = {
  46         .name           = "emif_fw",
  47         .class          = &am33xx_emif_fw_hwmod_class,
  48         .clkdm_name     = "l4fw_clkdm",
  49         .main_clk       = "l4fw_gclk",
  50         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  51         .prcm           = {
  52                 .omap4  = {
  53                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
  54                         .modulemode     = MODULEMODE_SWCTRL,
  55                 },
  56         },
  57 };
  58
  59 /*
  60  * 'emif' class
  61  * instance(s): emif
  62  */
  63 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
  64         .rev_offs       = 0x0000,
  65 };
  66
  67 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
  68         .name           = "emif",
  69         .sysc           = &am33xx_emif_sysc,
  70 };
  71
  72 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
  73         { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
  74         { .irq = -1 },
  75 };
  76
  77 /* emif */
  78 static struct omap_hwmod am33xx_emif_hwmod = {
  79         .name           = "emif",
  80         .class          = &am33xx_emif_hwmod_class,
  81         .clkdm_name     = "l3_clkdm",
  82         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  83         .mpu_irqs       = am33xx_emif_irqs,
  84         .main_clk       = "dpll_ddr_m2_div2_ck",
  85         .prcm           = {
  86                 .omap4  = {
  87                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
  88                         .modulemode     = MODULEMODE_SWCTRL,
  89                 },
  90         },
  91 };
  92
  93 /*
  94  * 'l3' class
  95  * instance(s): l3_main, l3_s, l3_instr
  96  */
  97 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  98         .name           = "l3",
  99 };
 100
 101 /* l3_main (l3_fast) */
 102 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
 103         { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
 104         { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
 105         { .irq = -1 },
 106 };
 107
 108 static struct omap_hwmod am33xx_l3_main_hwmod = {
 109         .name           = "l3_main",
 110         .class          = &am33xx_l3_hwmod_class,
 111         .clkdm_name     = "l3_clkdm",
 112         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 113         .mpu_irqs       = am33xx_l3_main_irqs,
 114         .main_clk       = "l3_gclk",
 115         .prcm           = {
 116                 .omap4  = {
 117                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
 118                         .modulemode     = MODULEMODE_SWCTRL,
 119                 },
 120         },
 121 };
 122
 123 /* l3_s */
 124 static struct omap_hwmod am33xx_l3_s_hwmod = {
 125         .name           = "l3_s",
 126         .class          = &am33xx_l3_hwmod_class,
 127         .clkdm_name     = "l3s_clkdm",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod am33xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &am33xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_clkdm",
 135         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 136         .main_clk       = "l3_gclk",
 137         .prcm           = {
 138                 .omap4  = {
 139                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
 140                         .modulemode     = MODULEMODE_SWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /*
 146  * 'l4' class
 147  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
 148  */
 149 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
 150         .name           = "l4",
 151 };
 152
 153 /* l4_ls */
 154 static struct omap_hwmod am33xx_l4_ls_hwmod = {
 155         .name           = "l4_ls",
 156         .class          = &am33xx_l4_hwmod_class,
 157         .clkdm_name     = "l4ls_clkdm",
 158         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 159         .main_clk       = "l4ls_gclk",
 160         .prcm           = {
 161                 .omap4  = {
 162                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
 163                         .modulemode     = MODULEMODE_SWCTRL,
 164                 },
 165         },
 166 };
 167
 168 /* l4_hs */
 169 static struct omap_hwmod am33xx_l4_hs_hwmod = {
 170         .name           = "l4_hs",
 171         .class          = &am33xx_l4_hwmod_class,
 172         .clkdm_name     = "l4hs_clkdm",
 173         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 174         .main_clk       = "l4hs_gclk",
 175         .prcm           = {
 176                 .omap4  = {
 177                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
 178                         .modulemode     = MODULEMODE_SWCTRL,
 179                 },
 180         },
 181 };
 182
 183
 184 /* l4_wkup */
 185 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
 186         .name           = "l4_wkup",
 187         .class          = &am33xx_l4_hwmod_class,
 188         .clkdm_name     = "l4_wkup_clkdm",
 189         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 190         .prcm           = {
 191                 .omap4  = {
 192                         .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 193                         .modulemode     = MODULEMODE_SWCTRL,
 194                 },
 195         },
 196 };
 197
 198 /* l4_fw */
 199 static struct omap_hwmod am33xx_l4_fw_hwmod = {
 200         .name           = "l4_fw",
 201         .class          = &am33xx_l4_hwmod_class,
 202         .clkdm_name     = "l4fw_clkdm",
 203         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 204         .prcm           = {
 205                 .omap4  = {
 206                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
 207                         .modulemode     = MODULEMODE_SWCTRL,
 208                 },
 209         },
 210 };
 211
 212 /*
 213  * 'mpu' class
 214  */
 215 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 216         .name   = "mpu",
 217 };
 218
 219 /* mpu */
 220 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
 221         { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
 222         { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
 223         { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
 224         { .name = "bench", .irq = 3 + OMAP_INTC_START, },
 225         { .irq = -1 },
 226 };
 227
 228 static struct omap_hwmod am33xx_mpu_hwmod = {
 229         .name           = "mpu",
 230         .class          = &am33xx_mpu_hwmod_class,
 231         .clkdm_name     = "mpu_clkdm",
 232         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 233         .mpu_irqs       = am33xx_mpu_irqs,
 234         .main_clk       = "dpll_mpu_m2_ck",
 235         .prcm           = {
 236                 .omap4  = {
 237                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 238                         .modulemode     = MODULEMODE_SWCTRL,
 239                 },
 240         },
 241 };
 242
 243 /*
 244  * 'wakeup m3' class
 245  * Wakeup controller sub-system under wakeup domain
 246  */
 247 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 248         .name           = "wkup_m3",
 249 };
 250
 251 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
 252         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 253 };
 254
 255 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
 256         { .name = "txev", .irq = 78 + OMAP_INTC_START, },
 257         { .irq = -1 },
 258 };
 259
 260 /* wkup_m3  */
 261 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
 262         .name           = "wkup_m3",
 263         .class          = &am33xx_wkup_m3_hwmod_class,
 264         .clkdm_name     = "l4_wkup_aon_clkdm",
 265         /* Keep hardreset asserted */
 266         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
 267         .mpu_irqs       = am33xx_wkup_m3_irqs,
 268         .main_clk       = "dpll_core_m4_div2_ck",
 269         .prcm           = {
 270                 .omap4  = {
 271                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
 272                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
 273                         .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
 274                         .modulemode     = MODULEMODE_SWCTRL,
 275                 },
 276         },
 277         .rst_lines      = am33xx_wkup_m3_resets,
 278         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
 279 };
 280
 281 /*
 282  * 'pru-icss' class
 283  * Programmable Real-Time Unit and Industrial Communication Subsystem
 284  */
 285 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 286         .name   = "pruss",
 287 };
 288
 289 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 290         { .name = "pruss", .rst_shift = 1 },
 291 };
 292
 293 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
 294         { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
 295         { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
 296         { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
 297         { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
 298         { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
 299         { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
 300         { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
 301         { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
 302         { .irq = -1 },
 303 };
 304
 305 /* pru-icss */
 306 /* Pseudo hwmod for reset control purpose only */
 307 static struct omap_hwmod am33xx_pruss_hwmod = {
 308         .name           = "pruss",
 309         .class          = &am33xx_pruss_hwmod_class,
 310         .clkdm_name     = "pruss_ocp_clkdm",
 311         .mpu_irqs       = am33xx_pruss_irqs,
 312         .main_clk       = "pruss_ocp_gclk",
 313         .prcm           = {
 314                 .omap4  = {
 315                         .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
 316                         .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
 317                         .modulemode     = MODULEMODE_SWCTRL,
 318                 },
 319         },
 320         .rst_lines      = am33xx_pruss_resets,
 321         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 322 };
 323
 324 /* gfx */
 325 /* Pseudo hwmod for reset control purpose only */
 326 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 327         .name   = "gfx",
 328 };
 329
 330 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 331         { .name = "gfx", .rst_shift = 0 },
 332 };
 333
 334 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
 335         { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
 336         { .irq = -1 },
 337 };
 338
 339 static struct omap_hwmod am33xx_gfx_hwmod = {
 340         .name           = "gfx",
 341         .class          = &am33xx_gfx_hwmod_class,
 342         .clkdm_name     = "gfx_l3_clkdm",
 343         .mpu_irqs       = am33xx_gfx_irqs,
 344         .main_clk       = "gfx_fck_div_ck",
 345         .prcm           = {
 346                 .omap4  = {
 347                         .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
 348                         .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
 349                         .modulemode     = MODULEMODE_SWCTRL,
 350                 },
 351         },
 352         .rst_lines      = am33xx_gfx_resets,
 353         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 354 };
 355
 356 /*
 357  * 'prcm' class
 358  * power and reset manager (whole prcm infrastructure)
 359  */
 360 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 361         .name   = "prcm",
 362 };
 363
 364 /* prcm */
 365 static struct omap_hwmod am33xx_prcm_hwmod = {
 366         .name           = "prcm",
 367         .class          = &am33xx_prcm_hwmod_class,
 368         .clkdm_name     = "l4_wkup_clkdm",
 369 };
 370
 371 /*
 372  * 'adc/tsc' class
 373  * TouchScreen Controller (Anolog-To-Digital Converter)
 374  */
 375 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
 376         .rev_offs       = 0x00,
 377         .sysc_offs      = 0x10,
 378         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 379         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 380                         SIDLE_SMART_WKUP),
 381         .sysc_fields    = &omap_hwmod_sysc_type2,
 382 };
 383
 384 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
 385         .name           = "adc_tsc",
 386         .sysc           = &am33xx_adc_tsc_sysc,
 387 };
 388
 389 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
 390         { .irq = 16 + OMAP_INTC_START, },
 391         { .irq = -1 },
 392 };
 393
 394 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
 395         .name           = "adc_tsc",
 396         .class          = &am33xx_adc_tsc_hwmod_class,
 397         .clkdm_name     = "l4_wkup_clkdm",
 398         .mpu_irqs       = am33xx_adc_tsc_irqs,
 399         .main_clk       = "adc_tsc_fck",
 400         .prcm           = {
 401                 .omap4  = {
 402                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
 403                         .modulemode     = MODULEMODE_SWCTRL,
 404                 },
 405         },
 406 };
 407
 408 /*
 409  * Modules omap_hwmod structures
 410  *
 411  * The following IPs are excluded for the moment because:
 412  * - They do not need an explicit SW control using omap_hwmod API.
 413  * - They still need to be validated with the driver
 414  *   properly adapted to omap_hwmod / omap_device
 415  *
 416  *    - cEFUSE (doesn't fall under any ocp_if)
 417  *    - clkdiv32k
 418  *    - debugss
 419  *    - ocp watch point
 420  *    - aes0
 421  */
 422 #if 0
 423 /*
 424  * 'cefuse' class
 425  */
 426 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
 427         .name           = "cefuse",
 428 };
 429
 430 static struct omap_hwmod am33xx_cefuse_hwmod = {
 431         .name           = "cefuse",
 432         .class          = &am33xx_cefuse_hwmod_class,
 433         .clkdm_name     = "l4_cefuse_clkdm",
 434         .main_clk       = "cefuse_fck",
 435         .prcm           = {
 436                 .omap4  = {
 437                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
 438                         .modulemode     = MODULEMODE_SWCTRL,
 439                 },
 440         },
 441 };
 442
 443 /*
 444  * 'clkdiv32k' class
 445  */
 446 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
 447         .name           = "clkdiv32k",
 448 };
 449
 450 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
 451         .name           = "clkdiv32k",
 452         .class          = &am33xx_clkdiv32k_hwmod_class,
 453         .clkdm_name     = "clk_24mhz_clkdm",
 454         .main_clk       = "clkdiv32k_ick",
 455         .prcm           = {
 456                 .omap4  = {
 457                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
 458                         .modulemode     = MODULEMODE_SWCTRL,
 459                 },
 460         },
 461 };
 462
 463 /*
 464  * 'debugss' class
 465  * debug sub system
 466  */
 467 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
 468         .name           = "debugss",
 469 };
 470
 471 static struct omap_hwmod am33xx_debugss_hwmod = {
 472         .name           = "debugss",
 473         .class          = &am33xx_debugss_hwmod_class,
 474         .clkdm_name     = "l3_aon_clkdm",
 475         .main_clk       = "debugss_ick",
 476         .prcm           = {
 477                 .omap4  = {
 478                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
 479                         .modulemode     = MODULEMODE_SWCTRL,
 480                 },
 481         },
 482 };
 483
 484 /* ocpwp */
 485 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
 486         .name           = "ocpwp",
 487 };
 488
 489 static struct omap_hwmod am33xx_ocpwp_hwmod = {
 490         .name           = "ocpwp",
 491         .class          = &am33xx_ocpwp_hwmod_class,
 492         .clkdm_name     = "l4ls_clkdm",
 493         .main_clk       = "l4ls_gclk",
 494         .prcm           = {
 495                 .omap4  = {
 496                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
 497                         .modulemode     = MODULEMODE_SWCTRL,
 498                 },
 499         },
 500 };
 501
 502 /*
 503  * 'aes' class
 504  */
 505 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
 506         .name           = "aes",
 507 };
 508
 509 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
 510         { .irq = 102 + OMAP_INTC_START, },
 511         { .irq = -1 },
 512 };
 513
 514 static struct omap_hwmod am33xx_aes0_hwmod = {
 515         .name           = "aes0",
 516         .class          = &am33xx_aes_hwmod_class,
 517         .clkdm_name     = "l3_clkdm",
 518         .mpu_irqs       = am33xx_aes0_irqs,
 519         .main_clk       = "l3_gclk",
 520         .prcm           = {
 521                 .omap4  = {
 522                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
 523                         .modulemode     = MODULEMODE_SWCTRL,
 524                 },
 525         },
 526 };
 527 #endif
 528
 529 /* sha0 HIB2 (the 'P' (public) device) */
 530 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 531         .rev_offs       = 0x100,
 532         .sysc_offs      = 0x110,
 533         .syss_offs      = 0x114,
 534         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 535 };
 536
 537 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 538         .name           = "sha0",
 539         .sysc           = &am33xx_sha0_sysc,
 540 };
 541
 542 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
 543         { .irq = 109 + OMAP_INTC_START, },
 544         { .irq = -1 },
 545 };
 546
 547 static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
 548         { .name = "rx", .dma_req = 36, },
 549         { .dma_req = -1 }
 550 };
 551
 552 static struct omap_hwmod am33xx_sha0_hwmod = {
 553         .name           = "sham",
 554         .class          = &am33xx_sha0_hwmod_class,
 555         .clkdm_name     = "l3_clkdm",
 556         .mpu_irqs       = am33xx_sha0_irqs,
 557         .sdma_reqs      = am33xx_sha0_edma_reqs,
 558         .main_clk       = "l3_gclk",
 559         .prcm           = {
 560                 .omap4  = {
 561                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
 562                         .modulemode     = MODULEMODE_SWCTRL,
 563                 },
 564         },
 565 };
 566
 567 /* ocmcram */
 568 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 569         .name = "ocmcram",
 570 };
 571
 572 static struct omap_hwmod am33xx_ocmcram_hwmod = {
 573         .name           = "ocmcram",
 574         .class          = &am33xx_ocmcram_hwmod_class,
 575         .clkdm_name     = "l3_clkdm",
 576         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 577         .main_clk       = "l3_gclk",
 578         .prcm           = {
 579                 .omap4  = {
 580                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
 581                         .modulemode     = MODULEMODE_SWCTRL,
 582                 },
 583         },
 584 };
 585
 586 /* 'smartreflex' class */
 587 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 588         .name           = "smartreflex",
 589 };
 590
 591 /* smartreflex0 */
 592 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
 593         { .irq = 120 + OMAP_INTC_START, },
 594         { .irq = -1 },
 595 };
 596
 597 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 598         .name           = "smartreflex0",
 599         .class          = &am33xx_smartreflex_hwmod_class,
 600         .clkdm_name     = "l4_wkup_clkdm",
 601         .mpu_irqs       = am33xx_smartreflex0_irqs,
 602         .main_clk       = "smartreflex0_fck",
 603         .prcm           = {
 604                 .omap4  = {
 605                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
 606                         .modulemode     = MODULEMODE_SWCTRL,
 607                 },
 608         },
 609 };
 610
 611 /* smartreflex1 */
 612 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
 613         { .irq = 121 + OMAP_INTC_START, },
 614         { .irq = -1 },
 615 };
 616
 617 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
 618         .name           = "smartreflex1",
 619         .class          = &am33xx_smartreflex_hwmod_class,
 620         .clkdm_name     = "l4_wkup_clkdm",
 621         .mpu_irqs       = am33xx_smartreflex1_irqs,
 622         .main_clk       = "smartreflex1_fck",
 623         .prcm           = {
 624                 .omap4  = {
 625                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
 626                         .modulemode     = MODULEMODE_SWCTRL,
 627                 },
 628         },
 629 };
 630
 631 /*
 632  * 'control' module class
 633  */
 634 static struct omap_hwmod_class am33xx_control_hwmod_class = {
 635         .name           = "control",
 636 };
 637
 638 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
 639         { .irq = 8 + OMAP_INTC_START, },
 640         { .irq = -1 },
 641 };
 642
 643 static struct omap_hwmod am33xx_control_hwmod = {
 644         .name           = "control",
 645         .class          = &am33xx_control_hwmod_class,
 646         .clkdm_name     = "l4_wkup_clkdm",
 647         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 648         .mpu_irqs       = am33xx_control_irqs,
 649         .main_clk       = "dpll_core_m4_div2_ck",
 650         .prcm           = {
 651                 .omap4  = {
 652                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
 653                         .modulemode     = MODULEMODE_SWCTRL,
 654                 },
 655         },
 656 };
 657
 658 /*
 659  * 'cpgmac' class
 660  * cpsw/cpgmac sub system
 661  */
 662 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 663         .rev_offs       = 0x0,
 664         .sysc_offs      = 0x8,
 665         .syss_offs      = 0x4,
 666         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 667                            SYSS_HAS_RESET_STATUS),
 668         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 669                            MSTANDBY_NO),
 670         .sysc_fields    = &omap_hwmod_sysc_type3,
 671 };
 672
 673 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 674         .name           = "cpgmac0",
 675         .sysc           = &am33xx_cpgmac_sysc,
 676 };
 677
 678 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
 679         { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
 680         { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
 681         { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
 682         { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
 683         { .irq = -1 },
 684 };
 685
 686 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
 687         .name           = "cpgmac0",
 688         .class          = &am33xx_cpgmac0_hwmod_class,
 689         .clkdm_name     = "cpsw_125mhz_clkdm",
 690         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 691         .mpu_irqs       = am33xx_cpgmac0_irqs,
 692         .main_clk       = "cpsw_125mhz_gclk",
 693         .prcm           = {
 694                 .omap4  = {
 695                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
 696                         .modulemode     = MODULEMODE_SWCTRL,
 697                 },
 698         },
 699 };
 700
 701 /*
 702  * mdio class
 703  */
 704 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 705         .name           = "davinci_mdio",
 706 };
 707
 708 static struct omap_hwmod am33xx_mdio_hwmod = {
 709         .name           = "davinci_mdio",
 710         .class          = &am33xx_mdio_hwmod_class,
 711         .clkdm_name     = "cpsw_125mhz_clkdm",
 712         .main_clk       = "cpsw_125mhz_gclk",
 713 };
 714
 715 /*
 716  * dcan class
 717  */
 718 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 719         .name = "d_can",
 720 };
 721
 722 /* dcan0 */
 723 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
 724         { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
 725         { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
 726         { .irq = -1 },
 727 };
 728
 729 static struct omap_hwmod am33xx_dcan0_hwmod = {
 730         .name           = "d_can0",
 731         .class          = &am33xx_dcan_hwmod_class,
 732         .clkdm_name     = "l4ls_clkdm",
 733         .mpu_irqs       = am33xx_dcan0_irqs,
 734         .main_clk       = "dcan0_fck",
 735         .prcm           = {
 736                 .omap4  = {
 737                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
 738                         .modulemode     = MODULEMODE_SWCTRL,
 739                 },
 740         },
 741 };
 742
 743 /* dcan1 */
 744 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
 745         { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
 746         { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
 747         { .irq = -1 },
 748 };
 749 static struct omap_hwmod am33xx_dcan1_hwmod = {
 750         .name           = "d_can1",
 751         .class          = &am33xx_dcan_hwmod_class,
 752         .clkdm_name     = "l4ls_clkdm",
 753         .mpu_irqs       = am33xx_dcan1_irqs,
 754         .main_clk       = "dcan1_fck",
 755         .prcm           = {
 756                 .omap4  = {
 757                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
 758                         .modulemode     = MODULEMODE_SWCTRL,
 759                 },
 760         },
 761 };
 762
 763 /* elm */
 764 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 765         .rev_offs       = 0x0000,
 766         .sysc_offs      = 0x0010,
 767         .syss_offs      = 0x0014,
 768         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 769                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 770                         SYSS_HAS_RESET_STATUS),
 771         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 772         .sysc_fields    = &omap_hwmod_sysc_type1,
 773 };
 774
 775 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 776         .name           = "elm",
 777         .sysc           = &am33xx_elm_sysc,
 778 };
 779
 780 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
 781         { .irq = 4 + OMAP_INTC_START, },
 782         { .irq = -1 },
 783 };
 784
 785 static struct omap_hwmod am33xx_elm_hwmod = {
 786         .name           = "elm",
 787         .class          = &am33xx_elm_hwmod_class,
 788         .clkdm_name     = "l4ls_clkdm",
 789         .mpu_irqs       = am33xx_elm_irqs,
 790         .main_clk       = "l4ls_gclk",
 791         .prcm           = {
 792                 .omap4  = {
 793                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
 794                         .modulemode     = MODULEMODE_SWCTRL,
 795                 },
 796         },
 797 };
 798
 799 /* pwmss  */
 800 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 801         .rev_offs       = 0x0,
 802         .sysc_offs      = 0x4,
 803         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 804         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 805                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 806                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 807         .sysc_fields    = &omap_hwmod_sysc_type2,
 808 };
 809
 810 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 811         .name           = "epwmss",
 812         .sysc           = &am33xx_epwmss_sysc,
 813 };
 814
 815 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 816         .name           = "ecap",
 817 };
 818
 819 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 820         .name           = "eqep",
 821 };
 822
 823 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 824         .name           = "ehrpwm",
 825 };
 826
 827 /* epwmss0 */
 828 static struct omap_hwmod am33xx_epwmss0_hwmod = {
 829         .name           = "epwmss0",
 830         .class          = &am33xx_epwmss_hwmod_class,
 831         .clkdm_name     = "l4ls_clkdm",
 832         .main_clk       = "l4ls_gclk",
 833         .prcm           = {
 834                 .omap4  = {
 835                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
 836                         .modulemode     = MODULEMODE_SWCTRL,
 837                 },
 838         },
 839 };
 840
 841 /* ecap0 */
 842 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
 843         { .irq = 31 + OMAP_INTC_START, },
 844         { .irq = -1 },
 845 };
 846
 847 static struct omap_hwmod am33xx_ecap0_hwmod = {
 848         .name           = "ecap0",
 849         .class          = &am33xx_ecap_hwmod_class,
 850         .clkdm_name     = "l4ls_clkdm",
 851         .mpu_irqs       = am33xx_ecap0_irqs,
 852         .main_clk       = "l4ls_gclk",
 853 };
 854
 855 /* eqep0 */
 856 static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
 857         { .irq = 79 + OMAP_INTC_START, },
 858         { .irq = -1 },
 859 };
 860
 861 static struct omap_hwmod am33xx_eqep0_hwmod = {
 862         .name           = "eqep0",
 863         .class          = &am33xx_eqep_hwmod_class,
 864         .clkdm_name     = "l4ls_clkdm",
 865         .mpu_irqs       = am33xx_eqep0_irqs,
 866         .main_clk       = "l4ls_gclk",
 867 };
 868
 869 /* ehrpwm0 */
 870 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
 871         { .name = "int", .irq = 86 + OMAP_INTC_START, },
 872         { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
 873         { .irq = -1 },
 874 };
 875
 876 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 877         .name           = "ehrpwm0",
 878         .class          = &am33xx_ehrpwm_hwmod_class,
 879         .clkdm_name     = "l4ls_clkdm",
 880         .mpu_irqs       = am33xx_ehrpwm0_irqs,
 881         .main_clk       = "l4ls_gclk",
 882 };
 883
 884 /* epwmss1 */
 885 static struct omap_hwmod am33xx_epwmss1_hwmod = {
 886         .name           = "epwmss1",
 887         .class          = &am33xx_epwmss_hwmod_class,
 888         .clkdm_name     = "l4ls_clkdm",
 889         .main_clk       = "l4ls_gclk",
 890         .prcm           = {
 891                 .omap4  = {
 892                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
 893                         .modulemode     = MODULEMODE_SWCTRL,
 894                 },
 895         },
 896 };
 897
 898 /* ecap1 */
 899 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
 900         { .irq = 47 + OMAP_INTC_START, },
 901         { .irq = -1 },
 902 };
 903
 904 static struct omap_hwmod am33xx_ecap1_hwmod = {
 905         .name           = "ecap1",
 906         .class          = &am33xx_ecap_hwmod_class,
 907         .clkdm_name     = "l4ls_clkdm",
 908         .mpu_irqs       = am33xx_ecap1_irqs,
 909         .main_clk       = "l4ls_gclk",
 910 };
 911
 912 /* eqep1 */
 913 static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
 914         { .irq = 88 + OMAP_INTC_START, },
 915         { .irq = -1 },
 916 };
 917
 918 static struct omap_hwmod am33xx_eqep1_hwmod = {
 919         .name           = "eqep1",
 920         .class          = &am33xx_eqep_hwmod_class,
 921         .clkdm_name     = "l4ls_clkdm",
 922         .mpu_irqs       = am33xx_eqep1_irqs,
 923         .main_clk       = "l4ls_gclk",
 924 };
 925
 926 /* ehrpwm1 */
 927 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
 928         { .name = "int", .irq = 87 + OMAP_INTC_START, },
 929         { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
 930         { .irq = -1 },
 931 };
 932
 933 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 934         .name           = "ehrpwm1",
 935         .class          = &am33xx_ehrpwm_hwmod_class,
 936         .clkdm_name     = "l4ls_clkdm",
 937         .mpu_irqs       = am33xx_ehrpwm1_irqs,
 938         .main_clk       = "l4ls_gclk",
 939 };
 940
 941 /* epwmss2 */
 942 static struct omap_hwmod am33xx_epwmss2_hwmod = {
 943         .name           = "epwmss2",
 944         .class          = &am33xx_epwmss_hwmod_class,
 945         .clkdm_name     = "l4ls_clkdm",
 946         .main_clk       = "l4ls_gclk",
 947         .prcm           = {
 948                 .omap4  = {
 949                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
 950                         .modulemode     = MODULEMODE_SWCTRL,
 951                 },
 952         },
 953 };
 954
 955 /* ecap2 */
 956 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
 957         { .irq = 61 + OMAP_INTC_START, },
 958         { .irq = -1 },
 959 };
 960
 961 static struct omap_hwmod am33xx_ecap2_hwmod = {
 962         .name           = "ecap2",
 963         .class          = &am33xx_ecap_hwmod_class,
 964         .clkdm_name     = "l4ls_clkdm",
 965         .mpu_irqs       = am33xx_ecap2_irqs,
 966         .main_clk       = "l4ls_gclk",
 967 };
 968
 969 /* eqep2 */
 970 static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
 971         { .irq = 89 + OMAP_INTC_START, },
 972         { .irq = -1 },
 973 };
 974
 975 static struct omap_hwmod am33xx_eqep2_hwmod = {
 976         .name           = "eqep2",
 977         .class          = &am33xx_eqep_hwmod_class,
 978         .clkdm_name     = "l4ls_clkdm",
 979         .mpu_irqs       = am33xx_eqep2_irqs,
 980         .main_clk       = "l4ls_gclk",
 981 };
 982
 983 /* ehrpwm2 */
 984 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
 985         { .name = "int", .irq = 39 + OMAP_INTC_START, },
 986         { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
 987         { .irq = -1 },
 988 };
 989
 990 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 991         .name           = "ehrpwm2",
 992         .class          = &am33xx_ehrpwm_hwmod_class,
 993         .clkdm_name     = "l4ls_clkdm",
 994         .mpu_irqs       = am33xx_ehrpwm2_irqs,
 995         .main_clk       = "l4ls_gclk",
 996 };
 997
 998 /*
 999  * 'gpio' class: for gpio 0,1,2,3
1000  */
1001 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
1002         .rev_offs       = 0x0000,
1003         .sysc_offs      = 0x0010,
1004         .syss_offs      = 0x0114,
1005         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1006                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1007                           SYSS_HAS_RESET_STATUS),
1008         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1009                           SIDLE_SMART_WKUP),
1010         .sysc_fields    = &omap_hwmod_sysc_type1,
1011 };
1012
1013 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1014         .name           = "gpio",
1015         .sysc           = &am33xx_gpio_sysc,
1016         .rev            = 2,
1017 };
1018
1019 static struct omap_gpio_dev_attr gpio_dev_attr = {
1020         .bank_width     = 32,
1021         .dbck_flag      = true,
1022 };
1023
1024 /* gpio0 */
1025 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1026         { .role = "dbclk", .clk = "gpio0_dbclk" },
1027 };
1028
1029 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1030         { .irq = 96 + OMAP_INTC_START, },
1031         { .irq = -1 },
1032 };
1033
1034 static struct omap_hwmod am33xx_gpio0_hwmod = {
1035         .name           = "gpio1",
1036         .class          = &am33xx_gpio_hwmod_class,
1037         .clkdm_name     = "l4_wkup_clkdm",
1038         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1039         .mpu_irqs       = am33xx_gpio0_irqs,
1040         .main_clk       = "dpll_core_m4_div2_ck",
1041         .prcm           = {
1042                 .omap4  = {
1043                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1044                         .modulemode     = MODULEMODE_SWCTRL,
1045                 },
1046         },
1047         .opt_clks       = gpio0_opt_clks,
1048         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
1049         .dev_attr       = &gpio_dev_attr,
1050 };
1051
1052 /* gpio1 */
1053 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1054         { .irq = 98 + OMAP_INTC_START, },
1055         { .irq = -1 },
1056 };
1057
1058 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1059         { .role = "dbclk", .clk = "gpio1_dbclk" },
1060 };
1061
1062 static struct omap_hwmod am33xx_gpio1_hwmod = {
1063         .name           = "gpio2",
1064         .class          = &am33xx_gpio_hwmod_class,
1065         .clkdm_name     = "l4ls_clkdm",
1066         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1067         .mpu_irqs       = am33xx_gpio1_irqs,
1068         .main_clk       = "l4ls_gclk",
1069         .prcm           = {
1070                 .omap4  = {
1071                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1072                         .modulemode     = MODULEMODE_SWCTRL,
1073                 },
1074         },
1075         .opt_clks       = gpio1_opt_clks,
1076         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1077         .dev_attr       = &gpio_dev_attr,
1078 };
1079
1080 /* gpio2 */
1081 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1082         { .irq = 32 + OMAP_INTC_START, },
1083         { .irq = -1 },
1084 };
1085
1086 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1087         { .role = "dbclk", .clk = "gpio2_dbclk" },
1088 };
1089
1090 static struct omap_hwmod am33xx_gpio2_hwmod = {
1091         .name           = "gpio3",
1092         .class          = &am33xx_gpio_hwmod_class,
1093         .clkdm_name     = "l4ls_clkdm",
1094         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1095         .mpu_irqs       = am33xx_gpio2_irqs,
1096         .main_clk       = "l4ls_gclk",
1097         .prcm           = {
1098                 .omap4  = {
1099                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1100                         .modulemode     = MODULEMODE_SWCTRL,
1101                 },
1102         },
1103         .opt_clks       = gpio2_opt_clks,
1104         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1105         .dev_attr       = &gpio_dev_attr,
1106 };
1107
1108 /* gpio3 */
1109 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1110         { .irq = 62 + OMAP_INTC_START, },
1111         { .irq = -1 },
1112 };
1113
1114 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1115         { .role = "dbclk", .clk = "gpio3_dbclk" },
1116 };
1117
1118 static struct omap_hwmod am33xx_gpio3_hwmod = {
1119         .name           = "gpio4",
1120         .class          = &am33xx_gpio_hwmod_class,
1121         .clkdm_name     = "l4ls_clkdm",
1122         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1123         .mpu_irqs       = am33xx_gpio3_irqs,
1124         .main_clk       = "l4ls_gclk",
1125         .prcm           = {
1126                 .omap4  = {
1127                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1128                         .modulemode     = MODULEMODE_SWCTRL,
1129                 },
1130         },
1131         .opt_clks       = gpio3_opt_clks,
1132         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1133         .dev_attr       = &gpio_dev_attr,
1134 };
1135
1136 /* gpmc */
1137 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1138         .rev_offs       = 0x0,
1139         .sysc_offs      = 0x10,
1140         .syss_offs      = 0x14,
1141         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1142                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144         .sysc_fields    = &omap_hwmod_sysc_type1,
1145 };
1146
1147 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1148         .name           = "gpmc",
1149         .sysc           = &gpmc_sysc,
1150 };
1151
1152 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1153         { .irq = 100 + OMAP_INTC_START, },
1154         { .irq = -1 },
1155 };
1156
1157 static struct omap_hwmod am33xx_gpmc_hwmod = {
1158         .name           = "gpmc",
1159         .class          = &am33xx_gpmc_hwmod_class,
1160         .clkdm_name     = "l3s_clkdm",
1161         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1162         .mpu_irqs       = am33xx_gpmc_irqs,
1163         .main_clk       = "l3s_gclk",
1164         .prcm           = {
1165                 .omap4  = {
1166                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1167                         .modulemode     = MODULEMODE_SWCTRL,
1168                 },
1169         },
1170 };
1171
1172 /* 'i2c' class */
1173 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1174         .sysc_offs      = 0x0010,
1175         .syss_offs      = 0x0090,
1176         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1177                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1178                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1179         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1180                           SIDLE_SMART_WKUP),
1181         .sysc_fields    = &omap_hwmod_sysc_type1,
1182 };
1183
1184 static struct omap_hwmod_class i2c_class = {
1185         .name           = "i2c",
1186         .sysc           = &am33xx_i2c_sysc,
1187         .rev            = OMAP_I2C_IP_VERSION_2,
1188         .reset          = &omap_i2c_reset,
1189 };
1190
1191 static struct omap_i2c_dev_attr i2c_dev_attr = {
1192         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1193 };
1194
1195 /* i2c1 */
1196 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1197         { .irq = 70 + OMAP_INTC_START, },
1198         { .irq = -1 },
1199 };
1200
1201 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1202         { .name = "tx", .dma_req = 0, },
1203         { .name = "rx", .dma_req = 0, },
1204         { .dma_req = -1 }
1205 };
1206
1207 static struct omap_hwmod am33xx_i2c1_hwmod = {
1208         .name           = "i2c1",
1209         .class          = &i2c_class,
1210         .clkdm_name     = "l4_wkup_clkdm",
1211         .mpu_irqs       = i2c1_mpu_irqs,
1212         .sdma_reqs      = i2c1_edma_reqs,
1213         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1214         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1215         .prcm           = {
1216                 .omap4  = {
1217                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1218                         .modulemode     = MODULEMODE_SWCTRL,
1219                 },
1220         },
1221         .dev_attr       = &i2c_dev_attr,
1222 };
1223
1224 /* i2c1 */
1225 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1226         { .irq = 71 + OMAP_INTC_START, },
1227         { .irq = -1 },
1228 };
1229
1230 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1231         { .name = "tx", .dma_req = 0, },
1232         { .name = "rx", .dma_req = 0, },
1233         { .dma_req = -1 }
1234 };
1235
1236 static struct omap_hwmod am33xx_i2c2_hwmod = {
1237         .name           = "i2c2",
1238         .class          = &i2c_class,
1239         .clkdm_name     = "l4ls_clkdm",
1240         .mpu_irqs       = i2c2_mpu_irqs,
1241         .sdma_reqs      = i2c2_edma_reqs,
1242         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1243         .main_clk       = "dpll_per_m2_div4_ck",
1244         .prcm           = {
1245                 .omap4 = {
1246                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1247                         .modulemode     = MODULEMODE_SWCTRL,
1248                 },
1249         },
1250         .dev_attr       = &i2c_dev_attr,
1251 };
1252
1253 /* i2c3 */
1254 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1255         { .name = "tx", .dma_req = 0, },
1256         { .name = "rx", .dma_req = 0, },
1257         { .dma_req = -1 }
1258 };
1259
1260 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1261         { .irq = 30 + OMAP_INTC_START, },
1262         { .irq = -1 },
1263 };
1264
1265 static struct omap_hwmod am33xx_i2c3_hwmod = {
1266         .name           = "i2c3",
1267         .class          = &i2c_class,
1268         .clkdm_name     = "l4ls_clkdm",
1269         .mpu_irqs       = i2c3_mpu_irqs,
1270         .sdma_reqs      = i2c3_edma_reqs,
1271         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1272         .main_clk       = "dpll_per_m2_div4_ck",
1273         .prcm           = {
1274                 .omap4  = {
1275                         .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1276                         .modulemode     = MODULEMODE_SWCTRL,
1277                 },
1278         },
1279         .dev_attr       = &i2c_dev_attr,
1280 };
1281
1282
1283 /* lcdc */
1284 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1285         .rev_offs       = 0x0,
1286         .sysc_offs      = 0x54,
1287         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1288         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1289         .sysc_fields    = &omap_hwmod_sysc_type2,
1290 };
1291
1292 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1293         .name           = "lcdc",
1294         .sysc           = &lcdc_sysc,
1295 };
1296
1297 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1298         { .irq = 36 + OMAP_INTC_START, },
1299         { .irq = -1 },
1300 };
1301
1302 static struct omap_hwmod am33xx_lcdc_hwmod = {
1303         .name           = "lcdc",
1304         .class          = &am33xx_lcdc_hwmod_class,
1305         .clkdm_name     = "lcdc_clkdm",
1306         .mpu_irqs       = am33xx_lcdc_irqs,
1307         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1308         .main_clk       = "lcd_gclk",
1309         .prcm           = {
1310                 .omap4  = {
1311                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1312                         .modulemode     = MODULEMODE_SWCTRL,
1313                 },
1314         },
1315 };
1316
1317 /*
1318  * 'mailbox' class
1319  * mailbox module allowing communication between the on-chip processors using a
1320  * queued mailbox-interrupt mechanism.
1321  */
1322 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1323         .rev_offs       = 0x0000,
1324         .sysc_offs      = 0x0010,
1325         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1326                           SYSC_HAS_SOFTRESET),
1327         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1328         .sysc_fields    = &omap_hwmod_sysc_type2,
1329 };
1330
1331 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1332         .name   = "mailbox",
1333         .sysc   = &am33xx_mailbox_sysc,
1334 };
1335
1336 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1337         { .irq = 77 + OMAP_INTC_START, },
1338         { .irq = -1 },
1339 };
1340
1341 static struct omap_hwmod am33xx_mailbox_hwmod = {
1342         .name           = "mailbox",
1343         .class          = &am33xx_mailbox_hwmod_class,
1344         .clkdm_name     = "l4ls_clkdm",
1345         .mpu_irqs       = am33xx_mailbox_irqs,
1346         .main_clk       = "l4ls_gclk",
1347         .prcm = {
1348                 .omap4 = {
1349                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1350                         .modulemode     = MODULEMODE_SWCTRL,
1351                 },
1352         },
1353 };
1354
1355 /*
1356  * 'mcasp' class
1357  */
1358 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1359         .rev_offs       = 0x0,
1360         .sysc_offs      = 0x4,
1361         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1362         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1363         .sysc_fields    = &omap_hwmod_sysc_type3,
1364 };
1365
1366 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1367         .name           = "mcasp",
1368         .sysc           = &am33xx_mcasp_sysc,
1369 };
1370
1371 /* mcasp0 */
1372 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1373         { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1374         { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1375         { .irq = -1 },
1376 };
1377
1378 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1379         { .name = "tx", .dma_req = 8, },
1380         { .name = "rx", .dma_req = 9, },
1381         { .dma_req = -1 }
1382 };
1383
1384 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1385         .name           = "mcasp0",
1386         .class          = &am33xx_mcasp_hwmod_class,
1387         .clkdm_name     = "l3s_clkdm",
1388         .mpu_irqs       = am33xx_mcasp0_irqs,
1389         .sdma_reqs      = am33xx_mcasp0_edma_reqs,
1390         .main_clk       = "mcasp0_fck",
1391         .prcm           = {
1392                 .omap4  = {
1393                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1394                         .modulemode     = MODULEMODE_SWCTRL,
1395                 },
1396         },
1397 };
1398
1399 /* mcasp1 */
1400 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1401         { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1402         { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1403         { .irq = -1 },
1404 };
1405
1406 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1407         { .name = "tx", .dma_req = 10, },
1408         { .name = "rx", .dma_req = 11, },
1409         { .dma_req = -1 }
1410 };
1411
1412 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1413         .name           = "mcasp1",
1414         .class          = &am33xx_mcasp_hwmod_class,
1415         .clkdm_name     = "l3s_clkdm",
1416         .mpu_irqs       = am33xx_mcasp1_irqs,
1417         .sdma_reqs      = am33xx_mcasp1_edma_reqs,
1418         .main_clk       = "mcasp1_fck",
1419         .prcm           = {
1420                 .omap4  = {
1421                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1422                         .modulemode     = MODULEMODE_SWCTRL,
1423                 },
1424         },
1425 };
1426
1427 /* 'mmc' class */
1428 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1429         .rev_offs       = 0x1fc,
1430         .sysc_offs      = 0x10,
1431         .syss_offs      = 0x14,
1432         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1433                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1434                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1435         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1436         .sysc_fields    = &omap_hwmod_sysc_type1,
1437 };
1438
1439 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1440         .name           = "mmc",
1441         .sysc           = &am33xx_mmc_sysc,
1442 };
1443
1444 /* mmc0 */
1445 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1446         { .irq = 64 + OMAP_INTC_START, },
1447         { .irq = -1 },
1448 };
1449
1450 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1451         { .name = "tx", .dma_req = 24, },
1452         { .name = "rx", .dma_req = 25, },
1453         { .dma_req = -1 }
1454 };
1455
1456 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1457         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1458 };
1459
1460 static struct omap_hwmod am33xx_mmc0_hwmod = {
1461         .name           = "mmc1",
1462         .class          = &am33xx_mmc_hwmod_class,
1463         .clkdm_name     = "l4ls_clkdm",
1464         .mpu_irqs       = am33xx_mmc0_irqs,
1465         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1466         .main_clk       = "mmc_clk",
1467         .prcm           = {
1468                 .omap4  = {
1469                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1470                         .modulemode     = MODULEMODE_SWCTRL,
1471                 },
1472         },
1473         .dev_attr       = &am33xx_mmc0_dev_attr,
1474 };
1475
1476 /* mmc1 */
1477 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1478         { .irq = 28 + OMAP_INTC_START, },
1479         { .irq = -1 },
1480 };
1481
1482 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1483         { .name = "tx", .dma_req = 2, },
1484         { .name = "rx", .dma_req = 3, },
1485         { .dma_req = -1 }
1486 };
1487
1488 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1489         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1490 };
1491
1492 static struct omap_hwmod am33xx_mmc1_hwmod = {
1493         .name           = "mmc2",
1494         .class          = &am33xx_mmc_hwmod_class,
1495         .clkdm_name     = "l4ls_clkdm",
1496         .mpu_irqs       = am33xx_mmc1_irqs,
1497         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1498         .main_clk       = "mmc_clk",
1499         .prcm           = {
1500                 .omap4  = {
1501                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1502                         .modulemode     = MODULEMODE_SWCTRL,
1503                 },
1504         },
1505         .dev_attr       = &am33xx_mmc1_dev_attr,
1506 };
1507
1508 /* mmc2 */
1509 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1510         { .irq = 29 + OMAP_INTC_START, },
1511         { .irq = -1 },
1512 };
1513
1514 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1515         { .name = "tx", .dma_req = 64, },
1516         { .name = "rx", .dma_req = 65, },
1517         { .dma_req = -1 }
1518 };
1519
1520 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1521         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1522 };
1523 static struct omap_hwmod am33xx_mmc2_hwmod = {
1524         .name           = "mmc3",
1525         .class          = &am33xx_mmc_hwmod_class,
1526         .clkdm_name     = "l3s_clkdm",
1527         .mpu_irqs       = am33xx_mmc2_irqs,
1528         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1529         .main_clk       = "mmc_clk",
1530         .prcm           = {
1531                 .omap4  = {
1532                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1533                         .modulemode     = MODULEMODE_SWCTRL,
1534                 },
1535         },
1536         .dev_attr       = &am33xx_mmc2_dev_attr,
1537 };
1538
1539 /*
1540  * 'rtc' class
1541  * rtc subsystem
1542  */
1543 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1544         .rev_offs       = 0x0074,
1545         .sysc_offs      = 0x0078,
1546         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
1548                           SIDLE_SMART | SIDLE_SMART_WKUP),
1549         .sysc_fields    = &omap_hwmod_sysc_type3,
1550 };
1551
1552 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1553         .name           = "rtc",
1554         .sysc           = &am33xx_rtc_sysc,
1555 };
1556
1557 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1558         { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1559         { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1560         { .irq = -1 },
1561 };
1562
1563 static struct omap_hwmod am33xx_rtc_hwmod = {
1564         .name           = "rtc",
1565         .class          = &am33xx_rtc_hwmod_class,
1566         .clkdm_name     = "l4_rtc_clkdm",
1567         .mpu_irqs       = am33xx_rtc_irqs,
1568         .main_clk       = "clk_32768_ck",
1569         .prcm           = {
1570                 .omap4  = {
1571                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1572                         .modulemode     = MODULEMODE_SWCTRL,
1573                 },
1574         },
1575 };
1576
1577 /* 'spi' class */
1578 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1579         .rev_offs       = 0x0000,
1580         .sysc_offs      = 0x0110,
1581         .syss_offs      = 0x0114,
1582         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1583                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1584                           SYSS_HAS_RESET_STATUS),
1585         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1586         .sysc_fields    = &omap_hwmod_sysc_type1,
1587 };
1588
1589 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1590         .name           = "mcspi",
1591         .sysc           = &am33xx_mcspi_sysc,
1592         .rev            = OMAP4_MCSPI_REV,
1593 };
1594
1595 /* spi0 */
1596 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1597         { .irq = 65 + OMAP_INTC_START, },
1598         { .irq = -1 },
1599 };
1600
1601 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1602         { .name = "rx0", .dma_req = 17 },
1603         { .name = "tx0", .dma_req = 16 },
1604         { .name = "rx1", .dma_req = 19 },
1605         { .name = "tx1", .dma_req = 18 },
1606         { .dma_req = -1 }
1607 };
1608
1609 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1610         .num_chipselect = 2,
1611 };
1612 static struct omap_hwmod am33xx_spi0_hwmod = {
1613         .name           = "spi0",
1614         .class          = &am33xx_spi_hwmod_class,
1615         .clkdm_name     = "l4ls_clkdm",
1616         .mpu_irqs       = am33xx_spi0_irqs,
1617         .sdma_reqs      = am33xx_mcspi0_edma_reqs,
1618         .main_clk       = "dpll_per_m2_div4_ck",
1619         .prcm           = {
1620                 .omap4  = {
1621                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1622                         .modulemode     = MODULEMODE_SWCTRL,
1623                 },
1624         },
1625         .dev_attr       = &mcspi_attrib,
1626 };
1627
1628 /* spi1 */
1629 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1630         { .irq = 125 + OMAP_INTC_START, },
1631         { .irq = -1 },
1632 };
1633
1634 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1635         { .name = "rx0", .dma_req = 43 },
1636         { .name = "tx0", .dma_req = 42 },
1637         { .name = "rx1", .dma_req = 45 },
1638         { .name = "tx1", .dma_req = 44 },
1639         { .dma_req = -1 }
1640 };
1641
1642 static struct omap_hwmod am33xx_spi1_hwmod = {
1643         .name           = "spi1",
1644         .class          = &am33xx_spi_hwmod_class,
1645         .clkdm_name     = "l4ls_clkdm",
1646         .mpu_irqs       = am33xx_spi1_irqs,
1647         .sdma_reqs      = am33xx_mcspi1_edma_reqs,
1648         .main_clk       = "dpll_per_m2_div4_ck",
1649         .prcm           = {
1650                 .omap4  = {
1651                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1652                         .modulemode     = MODULEMODE_SWCTRL,
1653                 },
1654         },
1655         .dev_attr       = &mcspi_attrib,
1656 };
1657
1658 /*
1659  * 'spinlock' class
1660  * spinlock provides hardware assistance for synchronizing the
1661  * processes running on multiple processors
1662  */
1663 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1664         .name           = "spinlock",
1665 };
1666
1667 static struct omap_hwmod am33xx_spinlock_hwmod = {
1668         .name           = "spinlock",
1669         .class          = &am33xx_spinlock_hwmod_class,
1670         .clkdm_name     = "l4ls_clkdm",
1671         .main_clk       = "l4ls_gclk",
1672         .prcm           = {
1673                 .omap4  = {
1674                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1675                         .modulemode     = MODULEMODE_SWCTRL,
1676                 },
1677         },
1678 };
1679
1680 /* 'timer 2-7' class */
1681 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1682         .rev_offs       = 0x0000,
1683         .sysc_offs      = 0x0010,
1684         .syss_offs      = 0x0014,
1685         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1686         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1687                           SIDLE_SMART_WKUP),
1688         .sysc_fields    = &omap_hwmod_sysc_type2,
1689 };
1690
1691 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1692         .name           = "timer",
1693         .sysc           = &am33xx_timer_sysc,
1694 };
1695
1696 /* timer1 1ms */
1697 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         .syss_offs      = 0x0014,
1701         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1702                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1703                         SYSS_HAS_RESET_STATUS),
1704         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1705         .sysc_fields    = &omap_hwmod_sysc_type1,
1706 };
1707
1708 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1709         .name           = "timer",
1710         .sysc           = &am33xx_timer1ms_sysc,
1711 };
1712
1713 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1714         { .irq = 67 + OMAP_INTC_START, },
1715         { .irq = -1 },
1716 };
1717
1718 static struct omap_hwmod am33xx_timer1_hwmod = {
1719         .name           = "timer1",
1720         .class          = &am33xx_timer1ms_hwmod_class,
1721         .clkdm_name     = "l4_wkup_clkdm",
1722         .mpu_irqs       = am33xx_timer1_irqs,
1723         .main_clk       = "timer1_fck",
1724         .prcm           = {
1725                 .omap4  = {
1726                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1727                         .modulemode     = MODULEMODE_SWCTRL,
1728                 },
1729         },
1730 };
1731
1732 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1733         { .irq = 68 + OMAP_INTC_START, },
1734         { .irq = -1 },
1735 };
1736
1737 static struct omap_hwmod am33xx_timer2_hwmod = {
1738         .name           = "timer2",
1739         .class          = &am33xx_timer_hwmod_class,
1740         .clkdm_name     = "l4ls_clkdm",
1741         .mpu_irqs       = am33xx_timer2_irqs,
1742         .main_clk       = "timer2_fck",
1743         .prcm           = {
1744                 .omap4  = {
1745                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1746                         .modulemode     = MODULEMODE_SWCTRL,
1747                 },
1748         },
1749 };
1750
1751 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1752         { .irq = 69 + OMAP_INTC_START, },
1753         { .irq = -1 },
1754 };
1755
1756 static struct omap_hwmod am33xx_timer3_hwmod = {
1757         .name           = "timer3",
1758         .class          = &am33xx_timer_hwmod_class,
1759         .clkdm_name     = "l4ls_clkdm",
1760         .mpu_irqs       = am33xx_timer3_irqs,
1761         .main_clk       = "timer3_fck",
1762         .prcm           = {
1763                 .omap4  = {
1764                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1765                         .modulemode     = MODULEMODE_SWCTRL,
1766                 },
1767         },
1768 };
1769
1770 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1771         { .irq = 92 + OMAP_INTC_START, },
1772         { .irq = -1 },
1773 };
1774
1775 static struct omap_hwmod am33xx_timer4_hwmod = {
1776         .name           = "timer4",
1777         .class          = &am33xx_timer_hwmod_class,
1778         .clkdm_name     = "l4ls_clkdm",
1779         .mpu_irqs       = am33xx_timer4_irqs,
1780         .main_clk       = "timer4_fck",
1781         .prcm           = {
1782                 .omap4  = {
1783                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1784                         .modulemode     = MODULEMODE_SWCTRL,
1785                 },
1786         },
1787 };
1788
1789 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1790         { .irq = 93 + OMAP_INTC_START, },
1791         { .irq = -1 },
1792 };
1793
1794 static struct omap_hwmod am33xx_timer5_hwmod = {
1795         .name           = "timer5",
1796         .class          = &am33xx_timer_hwmod_class,
1797         .clkdm_name     = "l4ls_clkdm",
1798         .mpu_irqs       = am33xx_timer5_irqs,
1799         .main_clk       = "timer5_fck",
1800         .prcm           = {
1801                 .omap4  = {
1802                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1803                         .modulemode     = MODULEMODE_SWCTRL,
1804                 },
1805         },
1806 };
1807
1808 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1809         { .irq = 94 + OMAP_INTC_START, },
1810         { .irq = -1 },
1811 };
1812
1813 static struct omap_hwmod am33xx_timer6_hwmod = {
1814         .name           = "timer6",
1815         .class          = &am33xx_timer_hwmod_class,
1816         .clkdm_name     = "l4ls_clkdm",
1817         .mpu_irqs       = am33xx_timer6_irqs,
1818         .main_clk       = "timer6_fck",
1819         .prcm           = {
1820                 .omap4  = {
1821                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1822                         .modulemode     = MODULEMODE_SWCTRL,
1823                 },
1824         },
1825 };
1826
1827 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1828         { .irq = 95 + OMAP_INTC_START, },
1829         { .irq = -1 },
1830 };
1831
1832 static struct omap_hwmod am33xx_timer7_hwmod = {
1833         .name           = "timer7",
1834         .class          = &am33xx_timer_hwmod_class,
1835         .clkdm_name     = "l4ls_clkdm",
1836         .mpu_irqs       = am33xx_timer7_irqs,
1837         .main_clk       = "timer7_fck",
1838         .prcm           = {
1839                 .omap4  = {
1840                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1841                         .modulemode     = MODULEMODE_SWCTRL,
1842                 },
1843         },
1844 };
1845
1846 /* tpcc */
1847 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1848         .name           = "tpcc",
1849 };
1850
1851 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1852         { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1853         { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1854         { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1855         { .irq = -1 },
1856 };
1857
1858 static struct omap_hwmod am33xx_tpcc_hwmod = {
1859         .name           = "tpcc",
1860         .class          = &am33xx_tpcc_hwmod_class,
1861         .clkdm_name     = "l3_clkdm",
1862         .mpu_irqs       = am33xx_tpcc_irqs,
1863         .main_clk       = "l3_gclk",
1864         .prcm           = {
1865                 .omap4  = {
1866                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1867                         .modulemode     = MODULEMODE_SWCTRL,
1868                 },
1869         },
1870 };
1871
1872 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1873         .rev_offs       = 0x0,
1874         .sysc_offs      = 0x10,
1875         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1876                           SYSC_HAS_MIDLEMODE),
1877         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1878         .sysc_fields    = &omap_hwmod_sysc_type2,
1879 };
1880
1881 /* 'tptc' class */
1882 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1883         .name           = "tptc",
1884         .sysc           = &am33xx_tptc_sysc,
1885 };
1886
1887 /* tptc0 */
1888 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1889         { .irq = 112 + OMAP_INTC_START, },
1890         { .irq = -1 },
1891 };
1892
1893 static struct omap_hwmod am33xx_tptc0_hwmod = {
1894         .name           = "tptc0",
1895         .class          = &am33xx_tptc_hwmod_class,
1896         .clkdm_name     = "l3_clkdm",
1897         .mpu_irqs       = am33xx_tptc0_irqs,
1898         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1899         .main_clk       = "l3_gclk",
1900         .prcm           = {
1901                 .omap4  = {
1902                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1903                         .modulemode     = MODULEMODE_SWCTRL,
1904                 },
1905         },
1906 };
1907
1908 /* tptc1 */
1909 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1910         { .irq = 113 + OMAP_INTC_START, },
1911         { .irq = -1 },
1912 };
1913
1914 static struct omap_hwmod am33xx_tptc1_hwmod = {
1915         .name           = "tptc1",
1916         .class          = &am33xx_tptc_hwmod_class,
1917         .clkdm_name     = "l3_clkdm",
1918         .mpu_irqs       = am33xx_tptc1_irqs,
1919         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1920         .main_clk       = "l3_gclk",
1921         .prcm           = {
1922                 .omap4  = {
1923                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1924                         .modulemode     = MODULEMODE_SWCTRL,
1925                 },
1926         },
1927 };
1928
1929 /* tptc2 */
1930 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1931         { .irq = 114 + OMAP_INTC_START, },
1932         { .irq = -1 },
1933 };
1934
1935 static struct omap_hwmod am33xx_tptc2_hwmod = {
1936         .name           = "tptc2",
1937         .class          = &am33xx_tptc_hwmod_class,
1938         .clkdm_name     = "l3_clkdm",
1939         .mpu_irqs       = am33xx_tptc2_irqs,
1940         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1941         .main_clk       = "l3_gclk",
1942         .prcm           = {
1943                 .omap4  = {
1944                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1945                         .modulemode     = MODULEMODE_SWCTRL,
1946                 },
1947         },
1948 };
1949
1950 /* 'uart' class */
1951 static struct omap_hwmod_class_sysconfig uart_sysc = {
1952         .rev_offs       = 0x50,
1953         .sysc_offs      = 0x54,
1954         .syss_offs      = 0x58,
1955         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1956                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1957         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1958                           SIDLE_SMART_WKUP),
1959         .sysc_fields    = &omap_hwmod_sysc_type1,
1960 };
1961
1962 static struct omap_hwmod_class uart_class = {
1963         .name           = "uart",
1964         .sysc           = &uart_sysc,
1965 };
1966
1967 /* uart1 */
1968 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1969         { .name = "tx", .dma_req = 26, },
1970         { .name = "rx", .dma_req = 27, },
1971         { .dma_req = -1 }
1972 };
1973
1974 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1975         { .irq = 72 + OMAP_INTC_START, },
1976         { .irq = -1 },
1977 };
1978
1979 static struct omap_hwmod am33xx_uart1_hwmod = {
1980         .name           = "uart1",
1981         .class          = &uart_class,
1982         .clkdm_name     = "l4_wkup_clkdm",
1983         .mpu_irqs       = am33xx_uart1_irqs,
1984         .sdma_reqs      = uart1_edma_reqs,
1985         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1986         .prcm           = {
1987                 .omap4  = {
1988                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1989                         .modulemode     = MODULEMODE_SWCTRL,
1990                 },
1991         },
1992 };
1993
1994 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1995         { .irq = 73 + OMAP_INTC_START, },
1996         { .irq = -1 },
1997 };
1998
1999 static struct omap_hwmod am33xx_uart2_hwmod = {
2000         .name           = "uart2",
2001         .class          = &uart_class,
2002         .clkdm_name     = "l4ls_clkdm",
2003         .mpu_irqs       = am33xx_uart2_irqs,
2004         .sdma_reqs      = uart1_edma_reqs,
2005         .main_clk       = "dpll_per_m2_div4_ck",
2006         .prcm           = {
2007                 .omap4  = {
2008                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2009                         .modulemode     = MODULEMODE_SWCTRL,
2010                 },
2011         },
2012 };
2013
2014 /* uart3 */
2015 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2016         { .name = "tx", .dma_req = 30, },
2017         { .name = "rx", .dma_req = 31, },
2018         { .dma_req = -1 }
2019 };
2020
2021 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2022         { .irq = 74 + OMAP_INTC_START, },
2023         { .irq = -1 },
2024 };
2025
2026 static struct omap_hwmod am33xx_uart3_hwmod = {
2027         .name           = "uart3",
2028         .class          = &uart_class,
2029         .clkdm_name     = "l4ls_clkdm",
2030         .mpu_irqs       = am33xx_uart3_irqs,
2031         .sdma_reqs      = uart3_edma_reqs,
2032         .main_clk       = "dpll_per_m2_div4_ck",
2033         .prcm           = {
2034                 .omap4  = {
2035                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2036                         .modulemode     = MODULEMODE_SWCTRL,
2037                 },
2038         },
2039 };
2040
2041 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2042         { .irq = 44 + OMAP_INTC_START, },
2043         { .irq = -1 },
2044 };
2045
2046 static struct omap_hwmod am33xx_uart4_hwmod = {
2047         .name           = "uart4",
2048         .class          = &uart_class,
2049         .clkdm_name     = "l4ls_clkdm",
2050         .mpu_irqs       = am33xx_uart4_irqs,
2051         .sdma_reqs      = uart1_edma_reqs,
2052         .main_clk       = "dpll_per_m2_div4_ck",
2053         .prcm           = {
2054                 .omap4  = {
2055                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2056                         .modulemode     = MODULEMODE_SWCTRL,
2057                 },
2058         },
2059 };
2060
2061 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2062         { .irq = 45 + OMAP_INTC_START, },
2063         { .irq = -1 },
2064 };
2065
2066 static struct omap_hwmod am33xx_uart5_hwmod = {
2067         .name           = "uart5",
2068         .class          = &uart_class,
2069         .clkdm_name     = "l4ls_clkdm",
2070         .mpu_irqs       = am33xx_uart5_irqs,
2071         .sdma_reqs      = uart1_edma_reqs,
2072         .main_clk       = "dpll_per_m2_div4_ck",
2073         .prcm           = {
2074                 .omap4  = {
2075                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2076                         .modulemode     = MODULEMODE_SWCTRL,
2077                 },
2078         },
2079 };
2080
2081 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2082         { .irq = 46 + OMAP_INTC_START, },
2083         { .irq = -1 },
2084 };
2085
2086 static struct omap_hwmod am33xx_uart6_hwmod = {
2087         .name           = "uart6",
2088         .class          = &uart_class,
2089         .clkdm_name     = "l4ls_clkdm",
2090         .mpu_irqs       = am33xx_uart6_irqs,
2091         .sdma_reqs      = uart1_edma_reqs,
2092         .main_clk       = "dpll_per_m2_div4_ck",
2093         .prcm           = {
2094                 .omap4  = {
2095                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2096                         .modulemode     = MODULEMODE_SWCTRL,
2097                 },
2098         },
2099 };
2100
2101 /* 'wd_timer' class */
2102 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2103         .name           = "wd_timer",
2104 };
2105
2106 /*
2107  * XXX: device.c file uses hardcoded name for watchdog timer
2108  * driver "wd_timer2, so we are also using same name as of now...
2109  */
2110 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2111         .name           = "wd_timer2",
2112         .class          = &am33xx_wd_timer_hwmod_class,
2113         .clkdm_name     = "l4_wkup_clkdm",
2114         .main_clk       = "wdt1_fck",
2115         .prcm           = {
2116                 .omap4  = {
2117                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2118                         .modulemode     = MODULEMODE_SWCTRL,
2119                 },
2120         },
2121 };
2122
2123 /*
2124  * 'usb_otg' class
2125  * high-speed on-the-go universal serial bus (usb_otg) controller
2126  */
2127 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2128         .rev_offs       = 0x0,
2129         .sysc_offs      = 0x10,
2130         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2132                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2133         .sysc_fields    = &omap_hwmod_sysc_type2,
2134 };
2135
2136 static struct omap_hwmod_class am33xx_usbotg_class = {
2137         .name           = "usbotg",
2138         .sysc           = &am33xx_usbhsotg_sysc,
2139 };
2140
2141 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2142         { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2143         { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2144         { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2145         { .irq = -1, },
2146 };
2147
2148 static struct omap_hwmod am33xx_usbss_hwmod = {
2149         .name           = "usb_otg_hs",
2150         .class          = &am33xx_usbotg_class,
2151         .clkdm_name     = "l3s_clkdm",
2152         .mpu_irqs       = am33xx_usbss_mpu_irqs,
2153         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2154         .main_clk       = "usbotg_fck",
2155         .prcm           = {
2156                 .omap4  = {
2157                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2158                         .modulemode     = MODULEMODE_SWCTRL,
2159                 },
2160         },
2161 };
2162
2163
2164 /*
2165  * Interfaces
2166  */
2167
2168 /* l4 fw -> emif fw */
2169 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2170         .master         = &am33xx_l4_fw_hwmod,
2171         .slave          = &am33xx_emif_fw_hwmod,
2172         .clk            = "l4fw_gclk",
2173         .user           = OCP_USER_MPU,
2174 };
2175
2176 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2177         {
2178                 .pa_start       = 0x4c000000,
2179                 .pa_end         = 0x4c000fff,
2180                 .flags          = ADDR_TYPE_RT
2181         },
2182         { }
2183 };
2184 /* l3 main -> emif */
2185 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2186         .master         = &am33xx_l3_main_hwmod,
2187         .slave          = &am33xx_emif_hwmod,
2188         .clk            = "dpll_core_m4_ck",
2189         .addr           = am33xx_emif_addrs,
2190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2191 };
2192
2193 /* mpu -> l3 main */
2194 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2195         .master         = &am33xx_mpu_hwmod,
2196         .slave          = &am33xx_l3_main_hwmod,
2197         .clk            = "dpll_mpu_m2_ck",
2198         .user           = OCP_USER_MPU,
2199 };
2200
2201 /* l3 main -> l4 hs */
2202 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2203         .master         = &am33xx_l3_main_hwmod,
2204         .slave          = &am33xx_l4_hs_hwmod,
2205         .clk            = "l3s_gclk",
2206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2207 };
2208
2209 /* l3 main -> l3 s */
2210 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2211         .master         = &am33xx_l3_main_hwmod,
2212         .slave          = &am33xx_l3_s_hwmod,
2213         .clk            = "l3s_gclk",
2214         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2215 };
2216
2217 /* l3 s -> l4 per/ls */
2218 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2219         .master         = &am33xx_l3_s_hwmod,
2220         .slave          = &am33xx_l4_ls_hwmod,
2221         .clk            = "l3s_gclk",
2222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2223 };
2224
2225 /* l3 s -> l4 wkup */
2226 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2227         .master         = &am33xx_l3_s_hwmod,
2228         .slave          = &am33xx_l4_wkup_hwmod,
2229         .clk            = "l3s_gclk",
2230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2231 };
2232
2233 /* l3 s -> l4 fw */
2234 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2235         .master         = &am33xx_l3_s_hwmod,
2236         .slave          = &am33xx_l4_fw_hwmod,
2237         .clk            = "l3s_gclk",
2238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2239 };
2240
2241 /* l3 main -> l3 instr */
2242 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2243         .master         = &am33xx_l3_main_hwmod,
2244         .slave          = &am33xx_l3_instr_hwmod,
2245         .clk            = "l3s_gclk",
2246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2247 };
2248
2249 /* mpu -> prcm */
2250 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2251         .master         = &am33xx_mpu_hwmod,
2252         .slave          = &am33xx_prcm_hwmod,
2253         .clk            = "dpll_mpu_m2_ck",
2254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2255 };
2256
2257 /* l3 s -> l3 main*/
2258 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2259         .master         = &am33xx_l3_s_hwmod,
2260         .slave          = &am33xx_l3_main_hwmod,
2261         .clk            = "l3s_gclk",
2262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2263 };
2264
2265 /* pru-icss -> l3 main */
2266 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2267         .master         = &am33xx_pruss_hwmod,
2268         .slave          = &am33xx_l3_main_hwmod,
2269         .clk            = "l3_gclk",
2270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2271 };
2272
2273 /* wkup m3 -> l4 wkup */
2274 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2275         .master         = &am33xx_wkup_m3_hwmod,
2276         .slave          = &am33xx_l4_wkup_hwmod,
2277         .clk            = "dpll_core_m4_div2_ck",
2278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2279 };
2280
2281 /* gfx -> l3 main */
2282 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2283         .master         = &am33xx_gfx_hwmod,
2284         .slave          = &am33xx_l3_main_hwmod,
2285         .clk            = "dpll_core_m4_ck",
2286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2287 };
2288
2289 /* l4 wkup -> wkup m3 */
2290 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2291         {
2292                 .name           = "umem",
2293                 .pa_start       = 0x44d00000,
2294                 .pa_end         = 0x44d00000 + SZ_16K - 1,
2295                 .flags          = ADDR_TYPE_RT
2296         },
2297         {
2298                 .name           = "dmem",
2299                 .pa_start       = 0x44d80000,
2300                 .pa_end         = 0x44d80000 + SZ_8K - 1,
2301                 .flags          = ADDR_TYPE_RT
2302         },
2303         { }
2304 };
2305
2306 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2307         .master         = &am33xx_l4_wkup_hwmod,
2308         .slave          = &am33xx_wkup_m3_hwmod,
2309         .clk            = "dpll_core_m4_div2_ck",
2310         .addr           = am33xx_wkup_m3_addrs,
2311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2312 };
2313
2314 /* l4 hs -> pru-icss */
2315 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2316         {
2317                 .pa_start       = 0x4a300000,
2318                 .pa_end         = 0x4a300000 + SZ_512K - 1,
2319                 .flags          = ADDR_TYPE_RT
2320         },
2321         { }
2322 };
2323
2324 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2325         .master         = &am33xx_l4_hs_hwmod,
2326         .slave          = &am33xx_pruss_hwmod,
2327         .clk            = "dpll_core_m4_ck",
2328         .addr           = am33xx_pruss_addrs,
2329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2330 };
2331
2332 /* l3 main -> gfx */
2333 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2334         {
2335                 .pa_start       = 0x56000000,
2336                 .pa_end         = 0x56000000 + SZ_16M - 1,
2337                 .flags          = ADDR_TYPE_RT
2338         },
2339         { }
2340 };
2341
2342 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2343         .master         = &am33xx_l3_main_hwmod,
2344         .slave          = &am33xx_gfx_hwmod,
2345         .clk            = "dpll_core_m4_ck",
2346         .addr           = am33xx_gfx_addrs,
2347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2348 };
2349
2350 /* l4 wkup -> smartreflex0 */
2351 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2352         {
2353                 .pa_start       = 0x44e37000,
2354                 .pa_end         = 0x44e37000 + SZ_4K - 1,
2355                 .flags          = ADDR_TYPE_RT
2356         },
2357         { }
2358 };
2359
2360 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2361         .master         = &am33xx_l4_wkup_hwmod,
2362         .slave          = &am33xx_smartreflex0_hwmod,
2363         .clk            = "dpll_core_m4_div2_ck",
2364         .addr           = am33xx_smartreflex0_addrs,
2365         .user           = OCP_USER_MPU,
2366 };
2367
2368 /* l4 wkup -> smartreflex1 */
2369 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2370         {
2371                 .pa_start       = 0x44e39000,
2372                 .pa_end         = 0x44e39000 + SZ_4K - 1,
2373                 .flags          = ADDR_TYPE_RT
2374         },
2375         { }
2376 };
2377
2378 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2379         .master         = &am33xx_l4_wkup_hwmod,
2380         .slave          = &am33xx_smartreflex1_hwmod,
2381         .clk            = "dpll_core_m4_div2_ck",
2382         .addr           = am33xx_smartreflex1_addrs,
2383         .user           = OCP_USER_MPU,
2384 };
2385
2386 /* l4 wkup -> control */
2387 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2388         {
2389                 .pa_start       = 0x44e10000,
2390                 .pa_end         = 0x44e10000 + SZ_8K - 1,
2391                 .flags          = ADDR_TYPE_RT
2392         },
2393         { }
2394 };
2395
2396 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2397         .master         = &am33xx_l4_wkup_hwmod,
2398         .slave          = &am33xx_control_hwmod,
2399         .clk            = "dpll_core_m4_div2_ck",
2400         .addr           = am33xx_control_addrs,
2401         .user           = OCP_USER_MPU,
2402 };
2403
2404 /* l4 wkup -> rtc */
2405 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2406         {
2407                 .pa_start       = 0x44e3e000,
2408                 .pa_end         = 0x44e3e000 + SZ_4K - 1,
2409                 .flags          = ADDR_TYPE_RT
2410         },
2411         { }
2412 };
2413
2414 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2415         .master         = &am33xx_l4_wkup_hwmod,
2416         .slave          = &am33xx_rtc_hwmod,
2417         .clk            = "clkdiv32k_ick",
2418         .addr           = am33xx_rtc_addrs,
2419         .user           = OCP_USER_MPU,
2420 };
2421
2422 /* l4 per/ls -> DCAN0 */
2423 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2424         {
2425                 .pa_start       = 0x481CC000,
2426                 .pa_end         = 0x481CC000 + SZ_4K - 1,
2427                 .flags          = ADDR_TYPE_RT
2428         },
2429         { }
2430 };
2431
2432 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2433         .master         = &am33xx_l4_ls_hwmod,
2434         .slave          = &am33xx_dcan0_hwmod,
2435         .clk            = "l4ls_gclk",
2436         .addr           = am33xx_dcan0_addrs,
2437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2438 };
2439
2440 /* l4 per/ls -> DCAN1 */
2441 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2442         {
2443                 .pa_start       = 0x481D0000,
2444                 .pa_end         = 0x481D0000 + SZ_4K - 1,
2445                 .flags          = ADDR_TYPE_RT
2446         },
2447         { }
2448 };
2449
2450 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2451         .master         = &am33xx_l4_ls_hwmod,
2452         .slave          = &am33xx_dcan1_hwmod,
2453         .clk            = "l4ls_gclk",
2454         .addr           = am33xx_dcan1_addrs,
2455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2456 };
2457
2458 /* l4 per/ls -> GPIO2 */
2459 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2460         {
2461                 .pa_start       = 0x4804C000,
2462                 .pa_end         = 0x4804C000 + SZ_4K - 1,
2463                 .flags          = ADDR_TYPE_RT,
2464         },
2465         { }
2466 };
2467
2468 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2469         .master         = &am33xx_l4_ls_hwmod,
2470         .slave          = &am33xx_gpio1_hwmod,
2471         .clk            = "l4ls_gclk",
2472         .addr           = am33xx_gpio1_addrs,
2473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2474 };
2475
2476 /* l4 per/ls -> gpio3 */
2477 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2478         {
2479                 .pa_start       = 0x481AC000,
2480                 .pa_end         = 0x481AC000 + SZ_4K - 1,
2481                 .flags          = ADDR_TYPE_RT,
2482         },
2483         { }
2484 };
2485
2486 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2487         .master         = &am33xx_l4_ls_hwmod,
2488         .slave          = &am33xx_gpio2_hwmod,
2489         .clk            = "l4ls_gclk",
2490         .addr           = am33xx_gpio2_addrs,
2491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2492 };
2493
2494 /* l4 per/ls -> gpio4 */
2495 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2496         {
2497                 .pa_start       = 0x481AE000,
2498                 .pa_end         = 0x481AE000 + SZ_4K - 1,
2499                 .flags          = ADDR_TYPE_RT,
2500         },
2501         { }
2502 };
2503
2504 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2505         .master         = &am33xx_l4_ls_hwmod,
2506         .slave          = &am33xx_gpio3_hwmod,
2507         .clk            = "l4ls_gclk",
2508         .addr           = am33xx_gpio3_addrs,
2509         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2510 };
2511
2512 /* L4 WKUP -> I2C1 */
2513 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2514         {
2515                 .pa_start       = 0x44E0B000,
2516                 .pa_end         = 0x44E0B000 + SZ_4K - 1,
2517                 .flags          = ADDR_TYPE_RT,
2518         },
2519         { }
2520 };
2521
2522 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2523         .master         = &am33xx_l4_wkup_hwmod,
2524         .slave          = &am33xx_i2c1_hwmod,
2525         .clk            = "dpll_core_m4_div2_ck",
2526         .addr           = am33xx_i2c1_addr_space,
2527         .user           = OCP_USER_MPU,
2528 };
2529
2530 /* L4 WKUP -> GPIO1 */
2531 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2532         {
2533                 .pa_start       = 0x44E07000,
2534                 .pa_end         = 0x44E07000 + SZ_4K - 1,
2535                 .flags          = ADDR_TYPE_RT,
2536         },
2537         { }
2538 };
2539
2540 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2541         .master         = &am33xx_l4_wkup_hwmod,
2542         .slave          = &am33xx_gpio0_hwmod,
2543         .clk            = "dpll_core_m4_div2_ck",
2544         .addr           = am33xx_gpio0_addrs,
2545         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2546 };
2547
2548 /* L4 WKUP -> ADC_TSC */
2549 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2550         {
2551                 .pa_start       = 0x44E0D000,
2552                 .pa_end         = 0x44E0D000 + SZ_8K - 1,
2553                 .flags          = ADDR_TYPE_RT
2554         },
2555         { }
2556 };
2557
2558 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2559         .master         = &am33xx_l4_wkup_hwmod,
2560         .slave          = &am33xx_adc_tsc_hwmod,
2561         .clk            = "dpll_core_m4_div2_ck",
2562         .addr           = am33xx_adc_tsc_addrs,
2563         .user           = OCP_USER_MPU,
2564 };
2565
2566 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2567         /* cpsw ss */
2568         {
2569                 .pa_start       = 0x4a100000,
2570                 .pa_end         = 0x4a100000 + SZ_2K - 1,
2571         },
2572         /* cpsw wr */
2573         {
2574                 .pa_start       = 0x4a101200,
2575                 .pa_end         = 0x4a101200 + SZ_256 - 1,
2576                 .flags          = ADDR_TYPE_RT,
2577         },
2578         { }
2579 };
2580
2581 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2582         .master         = &am33xx_l4_hs_hwmod,
2583         .slave          = &am33xx_cpgmac0_hwmod,
2584         .clk            = "cpsw_125mhz_gclk",
2585         .addr           = am33xx_cpgmac0_addr_space,
2586         .user           = OCP_USER_MPU,
2587 };
2588
2589 static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2590         {
2591                 .pa_start       = 0x4A101000,
2592                 .pa_end         = 0x4A101000 + SZ_256 - 1,
2593         },
2594         { }
2595 };
2596
2597 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2598         .master         = &am33xx_cpgmac0_hwmod,
2599         .slave          = &am33xx_mdio_hwmod,
2600         .addr           = am33xx_mdio_addr_space,
2601         .user           = OCP_USER_MPU,
2602 };
2603
2604 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2605         {
2606                 .pa_start       = 0x48080000,
2607                 .pa_end         = 0x48080000 + SZ_8K - 1,
2608                 .flags          = ADDR_TYPE_RT
2609         },
2610         { }
2611 };
2612
2613 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2614         .master         = &am33xx_l4_ls_hwmod,
2615         .slave          = &am33xx_elm_hwmod,
2616         .clk            = "l4ls_gclk",
2617         .addr           = am33xx_elm_addr_space,
2618         .user           = OCP_USER_MPU,
2619 };
2620
2621 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2622         {
2623                 .pa_start       = 0x48300000,
2624                 .pa_end         = 0x48300000 + SZ_16 - 1,
2625                 .flags          = ADDR_TYPE_RT
2626         },
2627         { }
2628 };
2629
2630 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2631         .master         = &am33xx_l4_ls_hwmod,
2632         .slave          = &am33xx_epwmss0_hwmod,
2633         .clk            = "l4ls_gclk",
2634         .addr           = am33xx_epwmss0_addr_space,
2635         .user           = OCP_USER_MPU,
2636 };
2637
2638 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2639         {
2640                 .pa_start       = 0x48300100,
2641                 .pa_end         = 0x48300100 + SZ_128 - 1,
2642         },
2643         { }
2644 };
2645
2646 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2647         .master         = &am33xx_epwmss0_hwmod,
2648         .slave          = &am33xx_ecap0_hwmod,
2649         .clk            = "l4ls_gclk",
2650         .addr           = am33xx_ecap0_addr_space,
2651         .user           = OCP_USER_MPU,
2652 };
2653
2654 static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2655         {
2656                 .pa_start       = 0x48300180,
2657                 .pa_end         = 0x48300180 + SZ_128 - 1,
2658         },
2659         { }
2660 };
2661
2662 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2663         .master         = &am33xx_epwmss0_hwmod,
2664         .slave          = &am33xx_eqep0_hwmod,
2665         .clk            = "l4ls_gclk",
2666         .addr           = am33xx_eqep0_addr_space,
2667         .user           = OCP_USER_MPU,
2668 };
2669
2670 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2671         {
2672                 .pa_start       = 0x48300200,
2673                 .pa_end         = 0x48300200 + SZ_128 - 1,
2674         },
2675         { }
2676 };
2677
2678 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2679         .master         = &am33xx_epwmss0_hwmod,
2680         .slave          = &am33xx_ehrpwm0_hwmod,
2681         .clk            = "l4ls_gclk",
2682         .addr           = am33xx_ehrpwm0_addr_space,
2683         .user           = OCP_USER_MPU,
2684 };
2685
2686
2687 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2688         {
2689                 .pa_start       = 0x48302000,
2690                 .pa_end         = 0x48302000 + SZ_16 - 1,
2691                 .flags          = ADDR_TYPE_RT
2692         },
2693         { }
2694 };
2695
2696 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2697         .master         = &am33xx_l4_ls_hwmod,
2698         .slave          = &am33xx_epwmss1_hwmod,
2699         .clk            = "l4ls_gclk",
2700         .addr           = am33xx_epwmss1_addr_space,
2701         .user           = OCP_USER_MPU,
2702 };
2703
2704 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2705         {
2706                 .pa_start       = 0x48302100,
2707                 .pa_end         = 0x48302100 + SZ_128 - 1,
2708         },
2709         { }
2710 };
2711
2712 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2713         .master         = &am33xx_epwmss1_hwmod,
2714         .slave          = &am33xx_ecap1_hwmod,
2715         .clk            = "l4ls_gclk",
2716         .addr           = am33xx_ecap1_addr_space,
2717         .user           = OCP_USER_MPU,
2718 };
2719
2720 static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2721         {
2722                 .pa_start       = 0x48302180,
2723                 .pa_end         = 0x48302180 + SZ_128 - 1,
2724         },
2725         { }
2726 };
2727
2728 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2729         .master         = &am33xx_epwmss1_hwmod,
2730         .slave          = &am33xx_eqep1_hwmod,
2731         .clk            = "l4ls_gclk",
2732         .addr           = am33xx_eqep1_addr_space,
2733         .user           = OCP_USER_MPU,
2734 };
2735
2736 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2737         {
2738                 .pa_start       = 0x48302200,
2739                 .pa_end         = 0x48302200 + SZ_128 - 1,
2740         },
2741         { }
2742 };
2743
2744 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2745         .master         = &am33xx_epwmss1_hwmod,
2746         .slave          = &am33xx_ehrpwm1_hwmod,
2747         .clk            = "l4ls_gclk",
2748         .addr           = am33xx_ehrpwm1_addr_space,
2749         .user           = OCP_USER_MPU,
2750 };
2751
2752 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2753         {
2754                 .pa_start       = 0x48304000,
2755                 .pa_end         = 0x48304000 + SZ_16 - 1,
2756                 .flags          = ADDR_TYPE_RT
2757         },
2758         { }
2759 };
2760
2761 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2762         .master         = &am33xx_l4_ls_hwmod,
2763         .slave          = &am33xx_epwmss2_hwmod,
2764         .clk            = "l4ls_gclk",
2765         .addr           = am33xx_epwmss2_addr_space,
2766         .user           = OCP_USER_MPU,
2767 };
2768
2769 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2770         {
2771                 .pa_start       = 0x48304100,
2772                 .pa_end         = 0x48304100 + SZ_128 - 1,
2773         },
2774         { }
2775 };
2776
2777 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2778         .master         = &am33xx_epwmss2_hwmod,
2779         .slave          = &am33xx_ecap2_hwmod,
2780         .clk            = "l4ls_gclk",
2781         .addr           = am33xx_ecap2_addr_space,
2782         .user           = OCP_USER_MPU,
2783 };
2784
2785 static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2786         {
2787                 .pa_start       = 0x48304180,
2788                 .pa_end         = 0x48304180 + SZ_128 - 1,
2789         },
2790         { }
2791 };
2792
2793 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2794         .master         = &am33xx_epwmss2_hwmod,
2795         .slave          = &am33xx_eqep2_hwmod,
2796         .clk            = "l4ls_gclk",
2797         .addr           = am33xx_eqep2_addr_space,
2798         .user           = OCP_USER_MPU,
2799 };
2800
2801 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2802         {
2803                 .pa_start       = 0x48304200,
2804                 .pa_end         = 0x48304200 + SZ_128 - 1,
2805         },
2806         { }
2807 };
2808
2809 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2810         .master         = &am33xx_epwmss2_hwmod,
2811         .slave          = &am33xx_ehrpwm2_hwmod,
2812         .clk            = "l4ls_gclk",
2813         .addr           = am33xx_ehrpwm2_addr_space,
2814         .user           = OCP_USER_MPU,
2815 };
2816
2817 /* l3s cfg -> gpmc */
2818 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2819         {
2820                 .pa_start       = 0x50000000,
2821                 .pa_end         = 0x50000000 + SZ_8K - 1,
2822                 .flags          = ADDR_TYPE_RT,
2823         },
2824         { }
2825 };
2826
2827 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2828         .master         = &am33xx_l3_s_hwmod,
2829         .slave          = &am33xx_gpmc_hwmod,
2830         .clk            = "l3s_gclk",
2831         .addr           = am33xx_gpmc_addr_space,
2832         .user           = OCP_USER_MPU,
2833 };
2834
2835 /* i2c2 */
2836 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2837         {
2838                 .pa_start       = 0x4802A000,
2839                 .pa_end         = 0x4802A000 + SZ_4K - 1,
2840                 .flags          = ADDR_TYPE_RT,
2841         },
2842         { }
2843 };
2844
2845 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2846         .master         = &am33xx_l4_ls_hwmod,
2847         .slave          = &am33xx_i2c2_hwmod,
2848         .clk            = "l4ls_gclk",
2849         .addr           = am33xx_i2c2_addr_space,
2850         .user           = OCP_USER_MPU,
2851 };
2852
2853 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2854         {
2855                 .pa_start       = 0x4819C000,
2856                 .pa_end         = 0x4819C000 + SZ_4K - 1,
2857                 .flags          = ADDR_TYPE_RT
2858         },
2859         { }
2860 };
2861
2862 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2863         .master         = &am33xx_l4_ls_hwmod,
2864         .slave          = &am33xx_i2c3_hwmod,
2865         .clk            = "l4ls_gclk",
2866         .addr           = am33xx_i2c3_addr_space,
2867         .user           = OCP_USER_MPU,
2868 };
2869
2870 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2871         {
2872                 .pa_start       = 0x4830E000,
2873                 .pa_end         = 0x4830E000 + SZ_8K - 1,
2874                 .flags          = ADDR_TYPE_RT,
2875         },
2876         { }
2877 };
2878
2879 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2880         .master         = &am33xx_l3_main_hwmod,
2881         .slave          = &am33xx_lcdc_hwmod,
2882         .clk            = "dpll_core_m4_ck",
2883         .addr           = am33xx_lcdc_addr_space,
2884         .user           = OCP_USER_MPU,
2885 };
2886
2887 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2888         {
2889                 .pa_start       = 0x480C8000,
2890                 .pa_end         = 0x480C8000 + (SZ_4K - 1),
2891                 .flags          = ADDR_TYPE_RT
2892         },
2893         { }
2894 };
2895
2896 /* l4 ls -> mailbox */
2897 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2898         .master         = &am33xx_l4_ls_hwmod,
2899         .slave          = &am33xx_mailbox_hwmod,
2900         .clk            = "l4ls_gclk",
2901         .addr           = am33xx_mailbox_addrs,
2902         .user           = OCP_USER_MPU,
2903 };
2904
2905 /* l4 ls -> spinlock */
2906 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2907         {
2908                 .pa_start       = 0x480Ca000,
2909                 .pa_end         = 0x480Ca000 + SZ_4K - 1,
2910                 .flags          = ADDR_TYPE_RT
2911         },
2912         { }
2913 };
2914
2915 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2916         .master         = &am33xx_l4_ls_hwmod,
2917         .slave          = &am33xx_spinlock_hwmod,
2918         .clk            = "l4ls_gclk",
2919         .addr           = am33xx_spinlock_addrs,
2920         .user           = OCP_USER_MPU,
2921 };
2922
2923 /* l4 ls -> mcasp0 */
2924 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2925         {
2926                 .pa_start       = 0x48038000,
2927                 .pa_end         = 0x48038000 + SZ_8K - 1,
2928                 .flags          = ADDR_TYPE_RT
2929         },
2930         { }
2931 };
2932
2933 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2934         .master         = &am33xx_l4_ls_hwmod,
2935         .slave          = &am33xx_mcasp0_hwmod,
2936         .clk            = "l4ls_gclk",
2937         .addr           = am33xx_mcasp0_addr_space,
2938         .user           = OCP_USER_MPU,
2939 };
2940
2941 /* l3 s -> mcasp0 data */
2942 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2943         {
2944                 .pa_start       = 0x46000000,
2945                 .pa_end         = 0x46000000 + SZ_4M - 1,
2946                 .flags          = ADDR_TYPE_RT
2947         },
2948         { }
2949 };
2950
2951 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2952         .master         = &am33xx_l3_s_hwmod,
2953         .slave          = &am33xx_mcasp0_hwmod,
2954         .clk            = "l3s_gclk",
2955         .addr           = am33xx_mcasp0_data_addr_space,
2956         .user           = OCP_USER_SDMA,
2957 };
2958
2959 /* l4 ls -> mcasp1 */
2960 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2961         {
2962                 .pa_start       = 0x4803C000,
2963                 .pa_end         = 0x4803C000 + SZ_8K - 1,
2964                 .flags          = ADDR_TYPE_RT
2965         },
2966         { }
2967 };
2968
2969 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2970         .master         = &am33xx_l4_ls_hwmod,
2971         .slave          = &am33xx_mcasp1_hwmod,
2972         .clk            = "l4ls_gclk",
2973         .addr           = am33xx_mcasp1_addr_space,
2974         .user           = OCP_USER_MPU,
2975 };
2976
2977 /* l3 s -> mcasp1 data */
2978 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2979         {
2980                 .pa_start       = 0x46400000,
2981                 .pa_end         = 0x46400000 + SZ_4M - 1,
2982                 .flags          = ADDR_TYPE_RT
2983         },
2984         { }
2985 };
2986
2987 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
2988         .master         = &am33xx_l3_s_hwmod,
2989         .slave          = &am33xx_mcasp1_hwmod,
2990         .clk            = "l3s_gclk",
2991         .addr           = am33xx_mcasp1_data_addr_space,
2992         .user           = OCP_USER_SDMA,
2993 };
2994
2995 /* l4 ls -> mmc0 */
2996 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2997         {
2998                 .pa_start       = 0x48060100,
2999                 .pa_end         = 0x48060100 + SZ_4K - 1,
3000                 .flags          = ADDR_TYPE_RT,
3001         },
3002         { }
3003 };
3004
3005 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
3006         .master         = &am33xx_l4_ls_hwmod,
3007         .slave          = &am33xx_mmc0_hwmod,
3008         .clk            = "l4ls_gclk",
3009         .addr           = am33xx_mmc0_addr_space,
3010         .user           = OCP_USER_MPU,
3011 };
3012
3013 /* l4 ls -> mmc1 */
3014 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
3015         {
3016                 .pa_start       = 0x481d8100,
3017                 .pa_end         = 0x481d8100 + SZ_4K - 1,
3018                 .flags          = ADDR_TYPE_RT,
3019         },
3020         { }
3021 };
3022
3023 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
3024         .master         = &am33xx_l4_ls_hwmod,
3025         .slave          = &am33xx_mmc1_hwmod,
3026         .clk            = "l4ls_gclk",
3027         .addr           = am33xx_mmc1_addr_space,
3028         .user           = OCP_USER_MPU,
3029 };
3030
3031 /* l3 s -> mmc2 */
3032 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
3033         {
3034                 .pa_start       = 0x47810100,
3035                 .pa_end         = 0x47810100 + SZ_64K - 1,
3036                 .flags          = ADDR_TYPE_RT,
3037         },
3038         { }
3039 };
3040
3041 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3042         .master         = &am33xx_l3_s_hwmod,
3043         .slave          = &am33xx_mmc2_hwmod,
3044         .clk            = "l3s_gclk",
3045         .addr           = am33xx_mmc2_addr_space,
3046         .user           = OCP_USER_MPU,
3047 };
3048
3049 /* l4 ls -> mcspi0 */
3050 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3051         {
3052                 .pa_start       = 0x48030000,
3053                 .pa_end         = 0x48030000 + SZ_1K - 1,
3054                 .flags          = ADDR_TYPE_RT,
3055         },
3056         { }
3057 };
3058
3059 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3060         .master         = &am33xx_l4_ls_hwmod,
3061         .slave          = &am33xx_spi0_hwmod,
3062         .clk            = "l4ls_gclk",
3063         .addr           = am33xx_mcspi0_addr_space,
3064         .user           = OCP_USER_MPU,
3065 };
3066
3067 /* l4 ls -> mcspi1 */
3068 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3069         {
3070                 .pa_start       = 0x481A0000,
3071                 .pa_end         = 0x481A0000 + SZ_1K - 1,
3072                 .flags          = ADDR_TYPE_RT,
3073         },
3074         { }
3075 };
3076
3077 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3078         .master         = &am33xx_l4_ls_hwmod,
3079         .slave          = &am33xx_spi1_hwmod,
3080         .clk            = "l4ls_gclk",
3081         .addr           = am33xx_mcspi1_addr_space,
3082         .user           = OCP_USER_MPU,
3083 };
3084
3085 /* l4 wkup -> timer1 */
3086 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3087         {
3088                 .pa_start       = 0x44E31000,
3089                 .pa_end         = 0x44E31000 + SZ_1K - 1,
3090                 .flags          = ADDR_TYPE_RT
3091         },
3092         { }
3093 };
3094
3095 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3096         .master         = &am33xx_l4_wkup_hwmod,
3097         .slave          = &am33xx_timer1_hwmod,
3098         .clk            = "dpll_core_m4_div2_ck",
3099         .addr           = am33xx_timer1_addr_space,
3100         .user           = OCP_USER_MPU,
3101 };
3102
3103 /* l4 per -> timer2 */
3104 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3105         {
3106                 .pa_start       = 0x48040000,
3107                 .pa_end         = 0x48040000 + SZ_1K - 1,
3108                 .flags          = ADDR_TYPE_RT
3109         },
3110         { }
3111 };
3112
3113 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3114         .master         = &am33xx_l4_ls_hwmod,
3115         .slave          = &am33xx_timer2_hwmod,
3116         .clk            = "l4ls_gclk",
3117         .addr           = am33xx_timer2_addr_space,
3118         .user           = OCP_USER_MPU,
3119 };
3120
3121 /* l4 per -> timer3 */
3122 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3123         {
3124                 .pa_start       = 0x48042000,
3125                 .pa_end         = 0x48042000 + SZ_1K - 1,
3126                 .flags          = ADDR_TYPE_RT
3127         },
3128         { }
3129 };
3130
3131 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3132         .master         = &am33xx_l4_ls_hwmod,
3133         .slave          = &am33xx_timer3_hwmod,
3134         .clk            = "l4ls_gclk",
3135         .addr           = am33xx_timer3_addr_space,
3136         .user           = OCP_USER_MPU,
3137 };
3138
3139 /* l4 per -> timer4 */
3140 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3141         {
3142                 .pa_start       = 0x48044000,
3143                 .pa_end         = 0x48044000 + SZ_1K - 1,
3144                 .flags          = ADDR_TYPE_RT
3145         },
3146         { }
3147 };
3148
3149 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3150         .master         = &am33xx_l4_ls_hwmod,
3151         .slave          = &am33xx_timer4_hwmod,
3152         .clk            = "l4ls_gclk",
3153         .addr           = am33xx_timer4_addr_space,
3154         .user           = OCP_USER_MPU,
3155 };
3156
3157 /* l4 per -> timer5 */
3158 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3159         {
3160                 .pa_start       = 0x48046000,
3161                 .pa_end         = 0x48046000 + SZ_1K - 1,
3162                 .flags          = ADDR_TYPE_RT
3163         },
3164         { }
3165 };
3166
3167 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3168         .master         = &am33xx_l4_ls_hwmod,
3169         .slave          = &am33xx_timer5_hwmod,
3170         .clk            = "l4ls_gclk",
3171         .addr           = am33xx_timer5_addr_space,
3172         .user           = OCP_USER_MPU,
3173 };
3174
3175 /* l4 per -> timer6 */
3176 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3177         {
3178                 .pa_start       = 0x48048000,
3179                 .pa_end         = 0x48048000 + SZ_1K - 1,
3180                 .flags          = ADDR_TYPE_RT
3181         },
3182         { }
3183 };
3184
3185 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3186         .master         = &am33xx_l4_ls_hwmod,
3187         .slave          = &am33xx_timer6_hwmod,
3188         .clk            = "l4ls_gclk",
3189         .addr           = am33xx_timer6_addr_space,
3190         .user           = OCP_USER_MPU,
3191 };
3192
3193 /* l4 per -> timer7 */
3194 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3195         {
3196                 .pa_start       = 0x4804A000,
3197                 .pa_end         = 0x4804A000 + SZ_1K - 1,
3198                 .flags          = ADDR_TYPE_RT
3199         },
3200         { }
3201 };
3202
3203 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3204         .master         = &am33xx_l4_ls_hwmod,
3205         .slave          = &am33xx_timer7_hwmod,
3206         .clk            = "l4ls_gclk",
3207         .addr           = am33xx_timer7_addr_space,
3208         .user           = OCP_USER_MPU,
3209 };
3210
3211 /* l3 main -> tpcc */
3212 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3213         {
3214                 .pa_start       = 0x49000000,
3215                 .pa_end         = 0x49000000 + SZ_32K - 1,
3216                 .flags          = ADDR_TYPE_RT
3217         },
3218         { }
3219 };
3220
3221 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3222         .master         = &am33xx_l3_main_hwmod,
3223         .slave          = &am33xx_tpcc_hwmod,
3224         .clk            = "l3_gclk",
3225         .addr           = am33xx_tpcc_addr_space,
3226         .user           = OCP_USER_MPU,
3227 };
3228
3229 /* l3 main -> tpcc0 */
3230 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3231         {
3232                 .pa_start       = 0x49800000,
3233                 .pa_end         = 0x49800000 + SZ_8K - 1,
3234                 .flags          = ADDR_TYPE_RT,
3235         },
3236         { }
3237 };
3238
3239 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3240         .master         = &am33xx_l3_main_hwmod,
3241         .slave          = &am33xx_tptc0_hwmod,
3242         .clk            = "l3_gclk",
3243         .addr           = am33xx_tptc0_addr_space,
3244         .user           = OCP_USER_MPU,
3245 };
3246
3247 /* l3 main -> tpcc1 */
3248 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3249         {
3250                 .pa_start       = 0x49900000,
3251                 .pa_end         = 0x49900000 + SZ_8K - 1,
3252                 .flags          = ADDR_TYPE_RT,
3253         },
3254         { }
3255 };
3256
3257 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3258         .master         = &am33xx_l3_main_hwmod,
3259         .slave          = &am33xx_tptc1_hwmod,
3260         .clk            = "l3_gclk",
3261         .addr           = am33xx_tptc1_addr_space,
3262         .user           = OCP_USER_MPU,
3263 };
3264
3265 /* l3 main -> tpcc2 */
3266 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3267         {
3268                 .pa_start       = 0x49a00000,
3269                 .pa_end         = 0x49a00000 + SZ_8K - 1,
3270                 .flags          = ADDR_TYPE_RT,
3271         },
3272         { }
3273 };
3274
3275 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3276         .master         = &am33xx_l3_main_hwmod,
3277         .slave          = &am33xx_tptc2_hwmod,
3278         .clk            = "l3_gclk",
3279         .addr           = am33xx_tptc2_addr_space,
3280         .user           = OCP_USER_MPU,
3281 };
3282
3283 /* l4 wkup -> uart1 */
3284 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3285         {
3286                 .pa_start       = 0x44E09000,
3287                 .pa_end         = 0x44E09000 + SZ_8K - 1,
3288                 .flags          = ADDR_TYPE_RT,
3289         },
3290         { }
3291 };
3292
3293 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3294         .master         = &am33xx_l4_wkup_hwmod,
3295         .slave          = &am33xx_uart1_hwmod,
3296         .clk            = "dpll_core_m4_div2_ck",
3297         .addr           = am33xx_uart1_addr_space,
3298         .user           = OCP_USER_MPU,
3299 };
3300
3301 /* l4 ls -> uart2 */
3302 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3303         {
3304                 .pa_start       = 0x48022000,
3305                 .pa_end         = 0x48022000 + SZ_8K - 1,
3306                 .flags          = ADDR_TYPE_RT,
3307         },
3308         { }
3309 };
3310
3311 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3312         .master         = &am33xx_l4_ls_hwmod,
3313         .slave          = &am33xx_uart2_hwmod,
3314         .clk            = "l4ls_gclk",
3315         .addr           = am33xx_uart2_addr_space,
3316         .user           = OCP_USER_MPU,
3317 };
3318
3319 /* l4 ls -> uart3 */
3320 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3321         {
3322                 .pa_start       = 0x48024000,
3323                 .pa_end         = 0x48024000 + SZ_8K - 1,
3324                 .flags          = ADDR_TYPE_RT,
3325         },
3326         { }
3327 };
3328
3329 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3330         .master         = &am33xx_l4_ls_hwmod,
3331         .slave          = &am33xx_uart3_hwmod,
3332         .clk            = "l4ls_gclk",
3333         .addr           = am33xx_uart3_addr_space,
3334         .user           = OCP_USER_MPU,
3335 };
3336
3337 /* l4 ls -> uart4 */
3338 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3339         {
3340                 .pa_start       = 0x481A6000,
3341                 .pa_end         = 0x481A6000 + SZ_8K - 1,
3342                 .flags          = ADDR_TYPE_RT,
3343         },
3344         { }
3345 };
3346
3347 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3348         .master         = &am33xx_l4_ls_hwmod,
3349         .slave          = &am33xx_uart4_hwmod,
3350         .clk            = "l4ls_gclk",
3351         .addr           = am33xx_uart4_addr_space,
3352         .user           = OCP_USER_MPU,
3353 };
3354
3355 /* l4 ls -> uart5 */
3356 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3357         {
3358                 .pa_start       = 0x481A8000,
3359                 .pa_end         = 0x481A8000 + SZ_8K - 1,
3360                 .flags          = ADDR_TYPE_RT,
3361         },
3362         { }
3363 };
3364
3365 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3366         .master         = &am33xx_l4_ls_hwmod,
3367         .slave          = &am33xx_uart5_hwmod,
3368         .clk            = "l4ls_gclk",
3369         .addr           = am33xx_uart5_addr_space,
3370         .user           = OCP_USER_MPU,
3371 };
3372
3373 /* l4 ls -> uart6 */
3374 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3375         {
3376                 .pa_start       = 0x481aa000,
3377                 .pa_end         = 0x481aa000 + SZ_8K - 1,
3378                 .flags          = ADDR_TYPE_RT,
3379         },
3380         { }
3381 };
3382
3383 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3384         .master         = &am33xx_l4_ls_hwmod,
3385         .slave          = &am33xx_uart6_hwmod,
3386         .clk            = "l4ls_gclk",
3387         .addr           = am33xx_uart6_addr_space,
3388         .user           = OCP_USER_MPU,
3389 };
3390
3391 /* l4 wkup -> wd_timer1 */
3392 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3393         {
3394                 .pa_start       = 0x44e35000,
3395                 .pa_end         = 0x44e35000 + SZ_4K - 1,
3396                 .flags          = ADDR_TYPE_RT
3397         },
3398         { }
3399 };
3400
3401 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3402         .master         = &am33xx_l4_wkup_hwmod,
3403         .slave          = &am33xx_wd_timer1_hwmod,
3404         .clk            = "dpll_core_m4_div2_ck",
3405         .addr           = am33xx_wd_timer1_addrs,
3406         .user           = OCP_USER_MPU,
3407 };
3408
3409 /* usbss */
3410 /* l3 s -> USBSS interface */
3411 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3412         {
3413                 .name           = "usbss",
3414                 .pa_start       = 0x47400000,
3415                 .pa_end         = 0x47400000 + SZ_4K - 1,
3416                 .flags          = ADDR_TYPE_RT
3417         },
3418         {
3419                 .name           = "musb0",
3420                 .pa_start       = 0x47401000,
3421                 .pa_end         = 0x47401000 + SZ_2K - 1,
3422                 .flags          = ADDR_TYPE_RT
3423         },
3424         {
3425                 .name           = "musb1",
3426                 .pa_start       = 0x47401800,
3427                 .pa_end         = 0x47401800 + SZ_2K - 1,
3428                 .flags          = ADDR_TYPE_RT
3429         },
3430         { }
3431 };
3432
3433 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3434         .master         = &am33xx_l3_s_hwmod,
3435         .slave          = &am33xx_usbss_hwmod,
3436         .clk            = "l3s_gclk",
3437         .addr           = am33xx_usbss_addr_space,
3438         .user           = OCP_USER_MPU,
3439         .flags          = OCPIF_SWSUP_IDLE,
3440 };
3441
3442 /* l3 main -> ocmc */
3443 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3444         .master         = &am33xx_l3_main_hwmod,
3445         .slave          = &am33xx_ocmcram_hwmod,
3446         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3447 };
3448
3449 /* l3 main -> sha0 HIB2 */
3450 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
3451         {
3452                 .pa_start       = 0x53100000,
3453                 .pa_end         = 0x53100000 + SZ_512 - 1,
3454                 .flags          = ADDR_TYPE_RT
3455         },
3456         { }
3457 };
3458
3459 static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
3460         .master         = &am33xx_l3_main_hwmod,
3461         .slave          = &am33xx_sha0_hwmod,
3462         .clk            = "sha0_fck",
3463         .addr           = am33xx_sha0_addrs,
3464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3465 };
3466
3467 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3468         &am33xx_l4_fw__emif_fw,
3469         &am33xx_l3_main__emif,
3470         &am33xx_mpu__l3_main,
3471         &am33xx_mpu__prcm,
3472         &am33xx_l3_s__l4_ls,
3473         &am33xx_l3_s__l4_wkup,
3474         &am33xx_l3_s__l4_fw,
3475         &am33xx_l3_main__l4_hs,
3476         &am33xx_l3_main__l3_s,
3477         &am33xx_l3_main__l3_instr,
3478         &am33xx_l3_main__gfx,
3479         &am33xx_l3_s__l3_main,
3480         &am33xx_pruss__l3_main,
3481         &am33xx_wkup_m3__l4_wkup,
3482         &am33xx_gfx__l3_main,
3483         &am33xx_l4_wkup__wkup_m3,
3484         &am33xx_l4_wkup__control,
3485         &am33xx_l4_wkup__smartreflex0,
3486         &am33xx_l4_wkup__smartreflex1,
3487         &am33xx_l4_wkup__uart1,
3488         &am33xx_l4_wkup__timer1,
3489         &am33xx_l4_wkup__rtc,
3490         &am33xx_l4_wkup__i2c1,
3491         &am33xx_l4_wkup__gpio0,
3492         &am33xx_l4_wkup__adc_tsc,
3493         &am33xx_l4_wkup__wd_timer1,
3494         &am33xx_l4_hs__pruss,
3495         &am33xx_l4_per__dcan0,
3496         &am33xx_l4_per__dcan1,
3497         &am33xx_l4_per__gpio1,
3498         &am33xx_l4_per__gpio2,
3499         &am33xx_l4_per__gpio3,
3500         &am33xx_l4_per__i2c2,
3501         &am33xx_l4_per__i2c3,
3502         &am33xx_l4_per__mailbox,
3503         &am33xx_l4_ls__mcasp0,
3504         &am33xx_l3_s__mcasp0_data,
3505         &am33xx_l4_ls__mcasp1,
3506         &am33xx_l3_s__mcasp1_data,
3507         &am33xx_l4_ls__mmc0,
3508         &am33xx_l4_ls__mmc1,
3509         &am33xx_l3_s__mmc2,
3510         &am33xx_l4_ls__timer2,
3511         &am33xx_l4_ls__timer3,
3512         &am33xx_l4_ls__timer4,
3513         &am33xx_l4_ls__timer5,
3514         &am33xx_l4_ls__timer6,
3515         &am33xx_l4_ls__timer7,
3516         &am33xx_l3_main__tpcc,
3517         &am33xx_l4_ls__uart2,
3518         &am33xx_l4_ls__uart3,
3519         &am33xx_l4_ls__uart4,
3520         &am33xx_l4_ls__uart5,
3521         &am33xx_l4_ls__uart6,
3522         &am33xx_l4_ls__spinlock,
3523         &am33xx_l4_ls__elm,
3524         &am33xx_l4_ls__epwmss0,
3525         &am33xx_epwmss0__ecap0,
3526         &am33xx_epwmss0__eqep0,
3527         &am33xx_epwmss0__ehrpwm0,
3528         &am33xx_l4_ls__epwmss1,
3529         &am33xx_epwmss1__ecap1,
3530         &am33xx_epwmss1__eqep1,
3531         &am33xx_epwmss1__ehrpwm1,
3532         &am33xx_l4_ls__epwmss2,
3533         &am33xx_epwmss2__ecap2,
3534         &am33xx_epwmss2__eqep2,
3535         &am33xx_epwmss2__ehrpwm2,
3536         &am33xx_l3_s__gpmc,
3537         &am33xx_l3_main__lcdc,
3538         &am33xx_l4_ls__mcspi0,
3539         &am33xx_l4_ls__mcspi1,
3540         &am33xx_l3_main__tptc0,
3541         &am33xx_l3_main__tptc1,
3542         &am33xx_l3_main__tptc2,
3543         &am33xx_l3_main__ocmc,
3544         &am33xx_l3_s__usbss,
3545         &am33xx_l4_hs__cpgmac0,
3546         &am33xx_cpgmac0__mdio,
3547         &am33xx_l3_main__sha0,
3548         NULL,
3549 };
3550
3551 int __init am33xx_hwmod_init(void)
3552 {
3553         omap_hwmod_init();
3554         return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3555 }