2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/i2c-omap.h>
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
23 #include "omap_hwmod_common_data.h"
28 #include "prm-regbits-33xx.h"
41 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
45 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
47 .sysc = &am33xx_emif_sysc,
51 static struct omap_hwmod am33xx_emif_hwmod = {
53 .class = &am33xx_emif_hwmod_class,
54 .clkdm_name = "l3_clkdm",
55 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
56 .main_clk = "dpll_ddr_m2_div2_ck",
59 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
60 .modulemode = MODULEMODE_SWCTRL,
67 * instance(s): l3_main, l3_s, l3_instr
69 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
73 static struct omap_hwmod am33xx_l3_main_hwmod = {
75 .class = &am33xx_l3_hwmod_class,
76 .clkdm_name = "l3_clkdm",
77 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
78 .main_clk = "l3_gclk",
81 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
82 .modulemode = MODULEMODE_SWCTRL,
88 static struct omap_hwmod am33xx_l3_s_hwmod = {
90 .class = &am33xx_l3_hwmod_class,
91 .clkdm_name = "l3s_clkdm",
95 static struct omap_hwmod am33xx_l3_instr_hwmod = {
97 .class = &am33xx_l3_hwmod_class,
98 .clkdm_name = "l3_clkdm",
99 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
100 .main_clk = "l3_gclk",
103 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
104 .modulemode = MODULEMODE_SWCTRL,
111 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
113 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
118 static struct omap_hwmod am33xx_l4_ls_hwmod = {
120 .class = &am33xx_l4_hwmod_class,
121 .clkdm_name = "l4ls_clkdm",
122 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
123 .main_clk = "l4ls_gclk",
126 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
127 .modulemode = MODULEMODE_SWCTRL,
133 static struct omap_hwmod am33xx_l4_hs_hwmod = {
135 .class = &am33xx_l4_hwmod_class,
136 .clkdm_name = "l4hs_clkdm",
137 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
138 .main_clk = "l4hs_gclk",
141 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
142 .modulemode = MODULEMODE_SWCTRL,
149 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
151 .class = &am33xx_l4_hwmod_class,
152 .clkdm_name = "l4_wkup_clkdm",
153 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
156 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
157 .modulemode = MODULEMODE_SWCTRL,
165 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
169 static struct omap_hwmod am33xx_mpu_hwmod = {
171 .class = &am33xx_mpu_hwmod_class,
172 .clkdm_name = "mpu_clkdm",
173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
174 .main_clk = "dpll_mpu_m2_ck",
177 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
185 * Wakeup controller sub-system under wakeup domain
187 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
191 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
192 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
196 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
198 .class = &am33xx_wkup_m3_hwmod_class,
199 .clkdm_name = "l4_wkup_aon_clkdm",
200 /* Keep hardreset asserted */
201 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
202 .main_clk = "dpll_core_m4_div2_ck",
205 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
206 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
207 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
208 .modulemode = MODULEMODE_SWCTRL,
211 .rst_lines = am33xx_wkup_m3_resets,
212 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
217 * Programmable Real-Time Unit and Industrial Communication Subsystem
219 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
223 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
224 { .name = "pruss", .rst_shift = 1 },
228 /* Pseudo hwmod for reset control purpose only */
229 static struct omap_hwmod am33xx_pruss_hwmod = {
231 .class = &am33xx_pruss_hwmod_class,
232 .clkdm_name = "pruss_ocp_clkdm",
233 .main_clk = "pruss_ocp_gclk",
236 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
237 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
238 .modulemode = MODULEMODE_SWCTRL,
241 .rst_lines = am33xx_pruss_resets,
242 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
246 /* Pseudo hwmod for reset control purpose only */
247 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
251 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
252 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
255 static struct omap_hwmod am33xx_gfx_hwmod = {
257 .class = &am33xx_gfx_hwmod_class,
258 .clkdm_name = "gfx_l3_clkdm",
259 .main_clk = "gfx_fck_div_ck",
262 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
263 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
264 .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
265 .modulemode = MODULEMODE_SWCTRL,
268 .rst_lines = am33xx_gfx_resets,
269 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
274 * power and reset manager (whole prcm infrastructure)
276 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
281 static struct omap_hwmod am33xx_prcm_hwmod = {
283 .class = &am33xx_prcm_hwmod_class,
284 .clkdm_name = "l4_wkup_clkdm",
289 * TouchScreen Controller (Anolog-To-Digital Converter)
291 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
294 .sysc_flags = SYSC_HAS_SIDLEMODE,
295 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
297 .sysc_fields = &omap_hwmod_sysc_type2,
300 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
302 .sysc = &am33xx_adc_tsc_sysc,
305 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
307 .class = &am33xx_adc_tsc_hwmod_class,
308 .clkdm_name = "l4_wkup_clkdm",
309 .main_clk = "adc_tsc_fck",
312 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
313 .modulemode = MODULEMODE_SWCTRL,
319 * Modules omap_hwmod structures
321 * The following IPs are excluded for the moment because:
322 * - They do not need an explicit SW control using omap_hwmod API.
323 * - They still need to be validated with the driver
324 * properly adapted to omap_hwmod / omap_device
326 * - cEFUSE (doesn't fall under any ocp_if)
335 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
339 static struct omap_hwmod am33xx_cefuse_hwmod = {
341 .class = &am33xx_cefuse_hwmod_class,
342 .clkdm_name = "l4_cefuse_clkdm",
343 .main_clk = "cefuse_fck",
346 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
347 .modulemode = MODULEMODE_SWCTRL,
355 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
359 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
361 .class = &am33xx_clkdiv32k_hwmod_class,
362 .clkdm_name = "clk_24mhz_clkdm",
363 .main_clk = "clkdiv32k_ick",
366 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
367 .modulemode = MODULEMODE_SWCTRL,
376 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
380 static struct omap_hwmod am33xx_debugss_hwmod = {
382 .class = &am33xx_debugss_hwmod_class,
383 .clkdm_name = "l3_aon_clkdm",
384 .main_clk = "debugss_ick",
387 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
388 .modulemode = MODULEMODE_SWCTRL,
394 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
398 static struct omap_hwmod am33xx_ocpwp_hwmod = {
400 .class = &am33xx_ocpwp_hwmod_class,
401 .clkdm_name = "l4ls_clkdm",
402 .main_clk = "l4ls_gclk",
405 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
406 .modulemode = MODULEMODE_SWCTRL,
415 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
419 .sysc_flags = SYSS_HAS_RESET_STATUS,
422 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
424 .sysc = &am33xx_aes0_sysc,
427 static struct omap_hwmod am33xx_aes0_hwmod = {
429 .class = &am33xx_aes0_hwmod_class,
430 .clkdm_name = "l3_clkdm",
431 .main_clk = "aes0_fck",
434 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
435 .modulemode = MODULEMODE_SWCTRL,
440 /* sha0 HIB2 (the 'P' (public) device) */
441 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
445 .sysc_flags = SYSS_HAS_RESET_STATUS,
448 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
450 .sysc = &am33xx_sha0_sysc,
453 static struct omap_hwmod am33xx_sha0_hwmod = {
455 .class = &am33xx_sha0_hwmod_class,
456 .clkdm_name = "l3_clkdm",
457 .main_clk = "l3_gclk",
460 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
461 .modulemode = MODULEMODE_SWCTRL,
467 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
471 static struct omap_hwmod am33xx_ocmcram_hwmod = {
473 .class = &am33xx_ocmcram_hwmod_class,
474 .clkdm_name = "l3_clkdm",
475 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
476 .main_clk = "l3_gclk",
479 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
480 .modulemode = MODULEMODE_SWCTRL,
485 /* 'smartreflex' class */
486 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
487 .name = "smartreflex",
491 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
492 .name = "smartreflex0",
493 .class = &am33xx_smartreflex_hwmod_class,
494 .clkdm_name = "l4_wkup_clkdm",
495 .main_clk = "smartreflex0_fck",
498 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
499 .modulemode = MODULEMODE_SWCTRL,
505 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
506 .name = "smartreflex1",
507 .class = &am33xx_smartreflex_hwmod_class,
508 .clkdm_name = "l4_wkup_clkdm",
509 .main_clk = "smartreflex1_fck",
512 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
513 .modulemode = MODULEMODE_SWCTRL,
519 * 'control' module class
521 static struct omap_hwmod_class am33xx_control_hwmod_class = {
525 static struct omap_hwmod am33xx_control_hwmod = {
527 .class = &am33xx_control_hwmod_class,
528 .clkdm_name = "l4_wkup_clkdm",
529 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
530 .main_clk = "dpll_core_m4_div2_ck",
533 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
534 .modulemode = MODULEMODE_SWCTRL,
541 * cpsw/cpgmac sub system
543 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
547 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
548 SYSS_HAS_RESET_STATUS),
549 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
551 .sysc_fields = &omap_hwmod_sysc_type3,
554 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
556 .sysc = &am33xx_cpgmac_sysc,
559 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
561 .class = &am33xx_cpgmac0_hwmod_class,
562 .clkdm_name = "cpsw_125mhz_clkdm",
563 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
564 .main_clk = "cpsw_125mhz_gclk",
568 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
569 .modulemode = MODULEMODE_SWCTRL,
577 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
578 .name = "davinci_mdio",
581 static struct omap_hwmod am33xx_mdio_hwmod = {
582 .name = "davinci_mdio",
583 .class = &am33xx_mdio_hwmod_class,
584 .clkdm_name = "cpsw_125mhz_clkdm",
585 .main_clk = "cpsw_125mhz_gclk",
591 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
596 static struct omap_hwmod am33xx_dcan0_hwmod = {
598 .class = &am33xx_dcan_hwmod_class,
599 .clkdm_name = "l4ls_clkdm",
600 .main_clk = "dcan0_fck",
603 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
604 .modulemode = MODULEMODE_SWCTRL,
610 static struct omap_hwmod am33xx_dcan1_hwmod = {
612 .class = &am33xx_dcan_hwmod_class,
613 .clkdm_name = "l4ls_clkdm",
614 .main_clk = "dcan1_fck",
617 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
618 .modulemode = MODULEMODE_SWCTRL,
624 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
628 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
629 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
630 SYSS_HAS_RESET_STATUS),
631 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
632 .sysc_fields = &omap_hwmod_sysc_type1,
635 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
637 .sysc = &am33xx_elm_sysc,
640 static struct omap_hwmod am33xx_elm_hwmod = {
642 .class = &am33xx_elm_hwmod_class,
643 .clkdm_name = "l4ls_clkdm",
644 .main_clk = "l4ls_gclk",
647 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
648 .modulemode = MODULEMODE_SWCTRL,
654 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
657 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
658 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
659 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
660 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
661 .sysc_fields = &omap_hwmod_sysc_type2,
664 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
666 .sysc = &am33xx_epwmss_sysc,
669 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
673 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
677 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
682 static struct omap_hwmod am33xx_epwmss0_hwmod = {
684 .class = &am33xx_epwmss_hwmod_class,
685 .clkdm_name = "l4ls_clkdm",
686 .main_clk = "l4ls_gclk",
689 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
690 .modulemode = MODULEMODE_SWCTRL,
696 static struct omap_hwmod am33xx_ecap0_hwmod = {
698 .class = &am33xx_ecap_hwmod_class,
699 .clkdm_name = "l4ls_clkdm",
700 .main_clk = "l4ls_gclk",
704 static struct omap_hwmod am33xx_eqep0_hwmod = {
706 .class = &am33xx_eqep_hwmod_class,
707 .clkdm_name = "l4ls_clkdm",
708 .main_clk = "l4ls_gclk",
712 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
714 .class = &am33xx_ehrpwm_hwmod_class,
715 .clkdm_name = "l4ls_clkdm",
716 .main_clk = "l4ls_gclk",
720 static struct omap_hwmod am33xx_epwmss1_hwmod = {
722 .class = &am33xx_epwmss_hwmod_class,
723 .clkdm_name = "l4ls_clkdm",
724 .main_clk = "l4ls_gclk",
727 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
728 .modulemode = MODULEMODE_SWCTRL,
734 static struct omap_hwmod am33xx_ecap1_hwmod = {
736 .class = &am33xx_ecap_hwmod_class,
737 .clkdm_name = "l4ls_clkdm",
738 .main_clk = "l4ls_gclk",
742 static struct omap_hwmod am33xx_eqep1_hwmod = {
744 .class = &am33xx_eqep_hwmod_class,
745 .clkdm_name = "l4ls_clkdm",
746 .main_clk = "l4ls_gclk",
750 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
752 .class = &am33xx_ehrpwm_hwmod_class,
753 .clkdm_name = "l4ls_clkdm",
754 .main_clk = "l4ls_gclk",
758 static struct omap_hwmod am33xx_epwmss2_hwmod = {
760 .class = &am33xx_epwmss_hwmod_class,
761 .clkdm_name = "l4ls_clkdm",
762 .main_clk = "l4ls_gclk",
765 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
766 .modulemode = MODULEMODE_SWCTRL,
772 static struct omap_hwmod am33xx_ecap2_hwmod = {
774 .class = &am33xx_ecap_hwmod_class,
775 .clkdm_name = "l4ls_clkdm",
776 .main_clk = "l4ls_gclk",
780 static struct omap_hwmod am33xx_eqep2_hwmod = {
782 .class = &am33xx_eqep_hwmod_class,
783 .clkdm_name = "l4ls_clkdm",
784 .main_clk = "l4ls_gclk",
788 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
790 .class = &am33xx_ehrpwm_hwmod_class,
791 .clkdm_name = "l4ls_clkdm",
792 .main_clk = "l4ls_gclk",
796 * 'gpio' class: for gpio 0,1,2,3
798 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
802 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
803 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
804 SYSS_HAS_RESET_STATUS),
805 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
807 .sysc_fields = &omap_hwmod_sysc_type1,
810 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
812 .sysc = &am33xx_gpio_sysc,
816 static struct omap_gpio_dev_attr gpio_dev_attr = {
822 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
823 { .role = "dbclk", .clk = "gpio0_dbclk" },
826 static struct omap_hwmod am33xx_gpio0_hwmod = {
828 .class = &am33xx_gpio_hwmod_class,
829 .clkdm_name = "l4_wkup_clkdm",
830 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
831 .main_clk = "dpll_core_m4_div2_ck",
834 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
835 .modulemode = MODULEMODE_SWCTRL,
838 .opt_clks = gpio0_opt_clks,
839 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
840 .dev_attr = &gpio_dev_attr,
844 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
845 { .role = "dbclk", .clk = "gpio1_dbclk" },
848 static struct omap_hwmod am33xx_gpio1_hwmod = {
850 .class = &am33xx_gpio_hwmod_class,
851 .clkdm_name = "l4ls_clkdm",
852 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
853 .main_clk = "l4ls_gclk",
856 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
857 .modulemode = MODULEMODE_SWCTRL,
860 .opt_clks = gpio1_opt_clks,
861 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
862 .dev_attr = &gpio_dev_attr,
866 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
867 { .role = "dbclk", .clk = "gpio2_dbclk" },
870 static struct omap_hwmod am33xx_gpio2_hwmod = {
872 .class = &am33xx_gpio_hwmod_class,
873 .clkdm_name = "l4ls_clkdm",
874 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
875 .main_clk = "l4ls_gclk",
878 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
879 .modulemode = MODULEMODE_SWCTRL,
882 .opt_clks = gpio2_opt_clks,
883 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
884 .dev_attr = &gpio_dev_attr,
888 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
889 { .role = "dbclk", .clk = "gpio3_dbclk" },
892 static struct omap_hwmod am33xx_gpio3_hwmod = {
894 .class = &am33xx_gpio_hwmod_class,
895 .clkdm_name = "l4ls_clkdm",
896 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
897 .main_clk = "l4ls_gclk",
900 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
904 .opt_clks = gpio3_opt_clks,
905 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
906 .dev_attr = &gpio_dev_attr,
910 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
914 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
915 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
916 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
917 .sysc_fields = &omap_hwmod_sysc_type1,
920 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
925 static struct omap_hwmod am33xx_gpmc_hwmod = {
927 .class = &am33xx_gpmc_hwmod_class,
928 .clkdm_name = "l3s_clkdm",
929 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
930 .main_clk = "l3s_gclk",
933 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
934 .modulemode = MODULEMODE_SWCTRL,
940 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
943 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
944 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
945 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
946 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
948 .sysc_fields = &omap_hwmod_sysc_type1,
951 static struct omap_hwmod_class i2c_class = {
953 .sysc = &am33xx_i2c_sysc,
954 .rev = OMAP_I2C_IP_VERSION_2,
955 .reset = &omap_i2c_reset,
958 static struct omap_i2c_dev_attr i2c_dev_attr = {
959 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
963 static struct omap_hwmod am33xx_i2c1_hwmod = {
966 .clkdm_name = "l4_wkup_clkdm",
967 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
968 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
971 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
972 .modulemode = MODULEMODE_SWCTRL,
975 .dev_attr = &i2c_dev_attr,
979 static struct omap_hwmod am33xx_i2c2_hwmod = {
982 .clkdm_name = "l4ls_clkdm",
983 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
984 .main_clk = "dpll_per_m2_div4_ck",
987 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
988 .modulemode = MODULEMODE_SWCTRL,
991 .dev_attr = &i2c_dev_attr,
995 static struct omap_hwmod am33xx_i2c3_hwmod = {
998 .clkdm_name = "l4ls_clkdm",
999 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1000 .main_clk = "dpll_per_m2_div4_ck",
1003 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1004 .modulemode = MODULEMODE_SWCTRL,
1007 .dev_attr = &i2c_dev_attr,
1012 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1015 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1016 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1017 .sysc_fields = &omap_hwmod_sysc_type2,
1020 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1025 static struct omap_hwmod am33xx_lcdc_hwmod = {
1027 .class = &am33xx_lcdc_hwmod_class,
1028 .clkdm_name = "lcdc_clkdm",
1029 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1030 .main_clk = "lcd_gclk",
1033 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1034 .modulemode = MODULEMODE_SWCTRL,
1041 * mailbox module allowing communication between the on-chip processors using a
1042 * queued mailbox-interrupt mechanism.
1044 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1046 .sysc_offs = 0x0010,
1047 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1048 SYSC_HAS_SOFTRESET),
1049 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1050 .sysc_fields = &omap_hwmod_sysc_type2,
1053 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1055 .sysc = &am33xx_mailbox_sysc,
1058 static struct omap_hwmod am33xx_mailbox_hwmod = {
1060 .class = &am33xx_mailbox_hwmod_class,
1061 .clkdm_name = "l4ls_clkdm",
1062 .main_clk = "l4ls_gclk",
1065 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1066 .modulemode = MODULEMODE_SWCTRL,
1074 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1077 .sysc_flags = SYSC_HAS_SIDLEMODE,
1078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1079 .sysc_fields = &omap_hwmod_sysc_type3,
1082 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1084 .sysc = &am33xx_mcasp_sysc,
1088 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1090 .class = &am33xx_mcasp_hwmod_class,
1091 .clkdm_name = "l3s_clkdm",
1092 .main_clk = "mcasp0_fck",
1095 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1096 .modulemode = MODULEMODE_SWCTRL,
1102 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1104 .class = &am33xx_mcasp_hwmod_class,
1105 .clkdm_name = "l3s_clkdm",
1106 .main_clk = "mcasp1_fck",
1109 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1110 .modulemode = MODULEMODE_SWCTRL,
1116 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1120 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1121 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1122 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1123 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1124 .sysc_fields = &omap_hwmod_sysc_type1,
1127 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1129 .sysc = &am33xx_mmc_sysc,
1133 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1134 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1137 static struct omap_hwmod am33xx_mmc0_hwmod = {
1139 .class = &am33xx_mmc_hwmod_class,
1140 .clkdm_name = "l4ls_clkdm",
1141 .main_clk = "mmc_clk",
1144 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1145 .modulemode = MODULEMODE_SWCTRL,
1148 .dev_attr = &am33xx_mmc0_dev_attr,
1152 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1153 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1156 static struct omap_hwmod am33xx_mmc1_hwmod = {
1158 .class = &am33xx_mmc_hwmod_class,
1159 .clkdm_name = "l4ls_clkdm",
1160 .main_clk = "mmc_clk",
1163 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1164 .modulemode = MODULEMODE_SWCTRL,
1167 .dev_attr = &am33xx_mmc1_dev_attr,
1171 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1172 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1174 static struct omap_hwmod am33xx_mmc2_hwmod = {
1176 .class = &am33xx_mmc_hwmod_class,
1177 .clkdm_name = "l3s_clkdm",
1178 .main_clk = "mmc_clk",
1181 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1182 .modulemode = MODULEMODE_SWCTRL,
1185 .dev_attr = &am33xx_mmc2_dev_attr,
1192 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1194 .sysc_offs = 0x0078,
1195 .sysc_flags = SYSC_HAS_SIDLEMODE,
1196 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1197 SIDLE_SMART | SIDLE_SMART_WKUP),
1198 .sysc_fields = &omap_hwmod_sysc_type3,
1201 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1203 .sysc = &am33xx_rtc_sysc,
1206 static struct omap_hwmod am33xx_rtc_hwmod = {
1208 .class = &am33xx_rtc_hwmod_class,
1209 .clkdm_name = "l4_rtc_clkdm",
1210 .main_clk = "clk_32768_ck",
1213 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1214 .modulemode = MODULEMODE_SWCTRL,
1220 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1222 .sysc_offs = 0x0110,
1223 .syss_offs = 0x0114,
1224 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1225 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1226 SYSS_HAS_RESET_STATUS),
1227 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1228 .sysc_fields = &omap_hwmod_sysc_type1,
1231 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1233 .sysc = &am33xx_mcspi_sysc,
1234 .rev = OMAP4_MCSPI_REV,
1238 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1239 .num_chipselect = 2,
1241 static struct omap_hwmod am33xx_spi0_hwmod = {
1243 .class = &am33xx_spi_hwmod_class,
1244 .clkdm_name = "l4ls_clkdm",
1245 .main_clk = "dpll_per_m2_div4_ck",
1248 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1249 .modulemode = MODULEMODE_SWCTRL,
1252 .dev_attr = &mcspi_attrib,
1256 static struct omap_hwmod am33xx_spi1_hwmod = {
1258 .class = &am33xx_spi_hwmod_class,
1259 .clkdm_name = "l4ls_clkdm",
1260 .main_clk = "dpll_per_m2_div4_ck",
1263 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1264 .modulemode = MODULEMODE_SWCTRL,
1267 .dev_attr = &mcspi_attrib,
1272 * spinlock provides hardware assistance for synchronizing the
1273 * processes running on multiple processors
1275 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1279 static struct omap_hwmod am33xx_spinlock_hwmod = {
1281 .class = &am33xx_spinlock_hwmod_class,
1282 .clkdm_name = "l4ls_clkdm",
1283 .main_clk = "l4ls_gclk",
1286 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1287 .modulemode = MODULEMODE_SWCTRL,
1292 /* 'timer 2-7' class */
1293 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1295 .sysc_offs = 0x0010,
1296 .syss_offs = 0x0014,
1297 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1298 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1300 .sysc_fields = &omap_hwmod_sysc_type2,
1303 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1305 .sysc = &am33xx_timer_sysc,
1309 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1311 .sysc_offs = 0x0010,
1312 .syss_offs = 0x0014,
1313 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1314 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1315 SYSS_HAS_RESET_STATUS),
1316 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1317 .sysc_fields = &omap_hwmod_sysc_type1,
1320 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1322 .sysc = &am33xx_timer1ms_sysc,
1325 static struct omap_hwmod am33xx_timer1_hwmod = {
1327 .class = &am33xx_timer1ms_hwmod_class,
1328 .clkdm_name = "l4_wkup_clkdm",
1329 .main_clk = "timer1_fck",
1332 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1333 .modulemode = MODULEMODE_SWCTRL,
1338 static struct omap_hwmod am33xx_timer2_hwmod = {
1340 .class = &am33xx_timer_hwmod_class,
1341 .clkdm_name = "l4ls_clkdm",
1342 .main_clk = "timer2_fck",
1345 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1346 .modulemode = MODULEMODE_SWCTRL,
1351 static struct omap_hwmod am33xx_timer3_hwmod = {
1353 .class = &am33xx_timer_hwmod_class,
1354 .clkdm_name = "l4ls_clkdm",
1355 .main_clk = "timer3_fck",
1358 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1359 .modulemode = MODULEMODE_SWCTRL,
1364 static struct omap_hwmod am33xx_timer4_hwmod = {
1366 .class = &am33xx_timer_hwmod_class,
1367 .clkdm_name = "l4ls_clkdm",
1368 .main_clk = "timer4_fck",
1371 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1372 .modulemode = MODULEMODE_SWCTRL,
1377 static struct omap_hwmod am33xx_timer5_hwmod = {
1379 .class = &am33xx_timer_hwmod_class,
1380 .clkdm_name = "l4ls_clkdm",
1381 .main_clk = "timer5_fck",
1384 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1385 .modulemode = MODULEMODE_SWCTRL,
1390 static struct omap_hwmod am33xx_timer6_hwmod = {
1392 .class = &am33xx_timer_hwmod_class,
1393 .clkdm_name = "l4ls_clkdm",
1394 .main_clk = "timer6_fck",
1397 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1398 .modulemode = MODULEMODE_SWCTRL,
1403 static struct omap_hwmod am33xx_timer7_hwmod = {
1405 .class = &am33xx_timer_hwmod_class,
1406 .clkdm_name = "l4ls_clkdm",
1407 .main_clk = "timer7_fck",
1410 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1411 .modulemode = MODULEMODE_SWCTRL,
1417 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1421 static struct omap_hwmod am33xx_tpcc_hwmod = {
1423 .class = &am33xx_tpcc_hwmod_class,
1424 .clkdm_name = "l3_clkdm",
1425 .main_clk = "l3_gclk",
1428 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1429 .modulemode = MODULEMODE_SWCTRL,
1434 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1437 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1438 SYSC_HAS_MIDLEMODE),
1439 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1440 .sysc_fields = &omap_hwmod_sysc_type2,
1444 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1446 .sysc = &am33xx_tptc_sysc,
1450 static struct omap_hwmod am33xx_tptc0_hwmod = {
1452 .class = &am33xx_tptc_hwmod_class,
1453 .clkdm_name = "l3_clkdm",
1454 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1455 .main_clk = "l3_gclk",
1458 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1459 .modulemode = MODULEMODE_SWCTRL,
1465 static struct omap_hwmod am33xx_tptc1_hwmod = {
1467 .class = &am33xx_tptc_hwmod_class,
1468 .clkdm_name = "l3_clkdm",
1469 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1470 .main_clk = "l3_gclk",
1473 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1474 .modulemode = MODULEMODE_SWCTRL,
1480 static struct omap_hwmod am33xx_tptc2_hwmod = {
1482 .class = &am33xx_tptc_hwmod_class,
1483 .clkdm_name = "l3_clkdm",
1484 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1485 .main_clk = "l3_gclk",
1488 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1489 .modulemode = MODULEMODE_SWCTRL,
1495 static struct omap_hwmod_class_sysconfig uart_sysc = {
1499 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1500 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1501 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1503 .sysc_fields = &omap_hwmod_sysc_type1,
1506 static struct omap_hwmod_class uart_class = {
1512 static struct omap_hwmod am33xx_uart1_hwmod = {
1514 .class = &uart_class,
1515 .clkdm_name = "l4_wkup_clkdm",
1516 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1517 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1520 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1521 .modulemode = MODULEMODE_SWCTRL,
1526 static struct omap_hwmod am33xx_uart2_hwmod = {
1528 .class = &uart_class,
1529 .clkdm_name = "l4ls_clkdm",
1530 .flags = HWMOD_SWSUP_SIDLE_ACT,
1531 .main_clk = "dpll_per_m2_div4_ck",
1534 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1535 .modulemode = MODULEMODE_SWCTRL,
1541 static struct omap_hwmod am33xx_uart3_hwmod = {
1543 .class = &uart_class,
1544 .clkdm_name = "l4ls_clkdm",
1545 .flags = HWMOD_SWSUP_SIDLE_ACT,
1546 .main_clk = "dpll_per_m2_div4_ck",
1549 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1550 .modulemode = MODULEMODE_SWCTRL,
1555 static struct omap_hwmod am33xx_uart4_hwmod = {
1557 .class = &uart_class,
1558 .clkdm_name = "l4ls_clkdm",
1559 .flags = HWMOD_SWSUP_SIDLE_ACT,
1560 .main_clk = "dpll_per_m2_div4_ck",
1563 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1564 .modulemode = MODULEMODE_SWCTRL,
1569 static struct omap_hwmod am33xx_uart5_hwmod = {
1571 .class = &uart_class,
1572 .clkdm_name = "l4ls_clkdm",
1573 .flags = HWMOD_SWSUP_SIDLE_ACT,
1574 .main_clk = "dpll_per_m2_div4_ck",
1577 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
1578 .modulemode = MODULEMODE_SWCTRL,
1583 static struct omap_hwmod am33xx_uart6_hwmod = {
1585 .class = &uart_class,
1586 .clkdm_name = "l4ls_clkdm",
1587 .flags = HWMOD_SWSUP_SIDLE_ACT,
1588 .main_clk = "dpll_per_m2_div4_ck",
1591 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
1592 .modulemode = MODULEMODE_SWCTRL,
1597 /* 'wd_timer' class */
1598 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1602 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1603 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1604 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1606 .sysc_fields = &omap_hwmod_sysc_type1,
1609 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1612 .pre_shutdown = &omap2_wd_timer_disable,
1616 * XXX: device.c file uses hardcoded name for watchdog timer
1617 * driver "wd_timer2, so we are also using same name as of now...
1619 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
1620 .name = "wd_timer2",
1621 .class = &am33xx_wd_timer_hwmod_class,
1622 .clkdm_name = "l4_wkup_clkdm",
1623 .flags = HWMOD_SWSUP_SIDLE,
1624 .main_clk = "wdt1_fck",
1627 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
1628 .modulemode = MODULEMODE_SWCTRL,
1635 * high-speed on-the-go universal serial bus (usb_otg) controller
1637 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
1640 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1641 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1642 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1643 .sysc_fields = &omap_hwmod_sysc_type2,
1646 static struct omap_hwmod_class am33xx_usbotg_class = {
1648 .sysc = &am33xx_usbhsotg_sysc,
1651 static struct omap_hwmod am33xx_usbss_hwmod = {
1652 .name = "usb_otg_hs",
1653 .class = &am33xx_usbotg_class,
1654 .clkdm_name = "l3s_clkdm",
1655 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1656 .main_clk = "usbotg_fck",
1659 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1670 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
1672 .pa_start = 0x4c000000,
1673 .pa_end = 0x4c000fff,
1674 .flags = ADDR_TYPE_RT
1678 /* l3 main -> emif */
1679 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
1680 .master = &am33xx_l3_main_hwmod,
1681 .slave = &am33xx_emif_hwmod,
1682 .clk = "dpll_core_m4_ck",
1683 .addr = am33xx_emif_addrs,
1684 .user = OCP_USER_MPU | OCP_USER_SDMA,
1687 /* mpu -> l3 main */
1688 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
1689 .master = &am33xx_mpu_hwmod,
1690 .slave = &am33xx_l3_main_hwmod,
1691 .clk = "dpll_mpu_m2_ck",
1692 .user = OCP_USER_MPU,
1695 /* l3 main -> l4 hs */
1696 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
1697 .master = &am33xx_l3_main_hwmod,
1698 .slave = &am33xx_l4_hs_hwmod,
1700 .user = OCP_USER_MPU | OCP_USER_SDMA,
1703 /* l3 main -> l3 s */
1704 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
1705 .master = &am33xx_l3_main_hwmod,
1706 .slave = &am33xx_l3_s_hwmod,
1708 .user = OCP_USER_MPU | OCP_USER_SDMA,
1711 /* l3 s -> l4 per/ls */
1712 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
1713 .master = &am33xx_l3_s_hwmod,
1714 .slave = &am33xx_l4_ls_hwmod,
1716 .user = OCP_USER_MPU | OCP_USER_SDMA,
1719 /* l3 s -> l4 wkup */
1720 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
1721 .master = &am33xx_l3_s_hwmod,
1722 .slave = &am33xx_l4_wkup_hwmod,
1724 .user = OCP_USER_MPU | OCP_USER_SDMA,
1727 /* l3 main -> l3 instr */
1728 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
1729 .master = &am33xx_l3_main_hwmod,
1730 .slave = &am33xx_l3_instr_hwmod,
1732 .user = OCP_USER_MPU | OCP_USER_SDMA,
1736 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
1737 .master = &am33xx_mpu_hwmod,
1738 .slave = &am33xx_prcm_hwmod,
1739 .clk = "dpll_mpu_m2_ck",
1740 .user = OCP_USER_MPU | OCP_USER_SDMA,
1743 /* l3 s -> l3 main*/
1744 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
1745 .master = &am33xx_l3_s_hwmod,
1746 .slave = &am33xx_l3_main_hwmod,
1748 .user = OCP_USER_MPU | OCP_USER_SDMA,
1751 /* pru-icss -> l3 main */
1752 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
1753 .master = &am33xx_pruss_hwmod,
1754 .slave = &am33xx_l3_main_hwmod,
1756 .user = OCP_USER_MPU | OCP_USER_SDMA,
1759 /* wkup m3 -> l4 wkup */
1760 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
1761 .master = &am33xx_wkup_m3_hwmod,
1762 .slave = &am33xx_l4_wkup_hwmod,
1763 .clk = "dpll_core_m4_div2_ck",
1764 .user = OCP_USER_MPU | OCP_USER_SDMA,
1767 /* gfx -> l3 main */
1768 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
1769 .master = &am33xx_gfx_hwmod,
1770 .slave = &am33xx_l3_main_hwmod,
1771 .clk = "dpll_core_m4_ck",
1772 .user = OCP_USER_MPU | OCP_USER_SDMA,
1775 /* l4 wkup -> wkup m3 */
1776 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
1777 .master = &am33xx_l4_wkup_hwmod,
1778 .slave = &am33xx_wkup_m3_hwmod,
1779 .clk = "dpll_core_m4_div2_ck",
1780 .user = OCP_USER_MPU | OCP_USER_SDMA,
1783 /* l4 hs -> pru-icss */
1784 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
1785 .master = &am33xx_l4_hs_hwmod,
1786 .slave = &am33xx_pruss_hwmod,
1787 .clk = "dpll_core_m4_ck",
1788 .user = OCP_USER_MPU | OCP_USER_SDMA,
1791 /* l3 main -> gfx */
1792 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
1793 .master = &am33xx_l3_main_hwmod,
1794 .slave = &am33xx_gfx_hwmod,
1795 .clk = "dpll_core_m4_ck",
1796 .user = OCP_USER_MPU | OCP_USER_SDMA,
1799 /* l4 wkup -> smartreflex0 */
1800 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
1801 .master = &am33xx_l4_wkup_hwmod,
1802 .slave = &am33xx_smartreflex0_hwmod,
1803 .clk = "dpll_core_m4_div2_ck",
1804 .user = OCP_USER_MPU,
1807 /* l4 wkup -> smartreflex1 */
1808 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
1809 .master = &am33xx_l4_wkup_hwmod,
1810 .slave = &am33xx_smartreflex1_hwmod,
1811 .clk = "dpll_core_m4_div2_ck",
1812 .user = OCP_USER_MPU,
1815 /* l4 wkup -> control */
1816 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
1817 .master = &am33xx_l4_wkup_hwmod,
1818 .slave = &am33xx_control_hwmod,
1819 .clk = "dpll_core_m4_div2_ck",
1820 .user = OCP_USER_MPU,
1823 /* l4 wkup -> rtc */
1824 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
1825 .master = &am33xx_l4_wkup_hwmod,
1826 .slave = &am33xx_rtc_hwmod,
1827 .clk = "clkdiv32k_ick",
1828 .user = OCP_USER_MPU,
1831 /* l4 per/ls -> DCAN0 */
1832 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
1833 .master = &am33xx_l4_ls_hwmod,
1834 .slave = &am33xx_dcan0_hwmod,
1836 .user = OCP_USER_MPU | OCP_USER_SDMA,
1839 /* l4 per/ls -> DCAN1 */
1840 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
1841 .master = &am33xx_l4_ls_hwmod,
1842 .slave = &am33xx_dcan1_hwmod,
1844 .user = OCP_USER_MPU | OCP_USER_SDMA,
1847 /* l4 per/ls -> GPIO2 */
1848 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
1849 .master = &am33xx_l4_ls_hwmod,
1850 .slave = &am33xx_gpio1_hwmod,
1852 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855 /* l4 per/ls -> gpio3 */
1856 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
1857 .master = &am33xx_l4_ls_hwmod,
1858 .slave = &am33xx_gpio2_hwmod,
1860 .user = OCP_USER_MPU | OCP_USER_SDMA,
1863 /* l4 per/ls -> gpio4 */
1864 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
1865 .master = &am33xx_l4_ls_hwmod,
1866 .slave = &am33xx_gpio3_hwmod,
1868 .user = OCP_USER_MPU | OCP_USER_SDMA,
1871 /* L4 WKUP -> I2C1 */
1872 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
1873 .master = &am33xx_l4_wkup_hwmod,
1874 .slave = &am33xx_i2c1_hwmod,
1875 .clk = "dpll_core_m4_div2_ck",
1876 .user = OCP_USER_MPU,
1879 /* L4 WKUP -> GPIO1 */
1880 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
1881 .master = &am33xx_l4_wkup_hwmod,
1882 .slave = &am33xx_gpio0_hwmod,
1883 .clk = "dpll_core_m4_div2_ck",
1884 .user = OCP_USER_MPU | OCP_USER_SDMA,
1887 /* L4 WKUP -> ADC_TSC */
1888 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
1890 .pa_start = 0x44E0D000,
1891 .pa_end = 0x44E0D000 + SZ_8K - 1,
1892 .flags = ADDR_TYPE_RT
1897 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
1898 .master = &am33xx_l4_wkup_hwmod,
1899 .slave = &am33xx_adc_tsc_hwmod,
1900 .clk = "dpll_core_m4_div2_ck",
1901 .addr = am33xx_adc_tsc_addrs,
1902 .user = OCP_USER_MPU,
1905 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
1906 .master = &am33xx_l4_hs_hwmod,
1907 .slave = &am33xx_cpgmac0_hwmod,
1908 .clk = "cpsw_125mhz_gclk",
1909 .user = OCP_USER_MPU,
1912 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
1913 .master = &am33xx_cpgmac0_hwmod,
1914 .slave = &am33xx_mdio_hwmod,
1915 .user = OCP_USER_MPU,
1918 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
1920 .pa_start = 0x48080000,
1921 .pa_end = 0x48080000 + SZ_8K - 1,
1922 .flags = ADDR_TYPE_RT
1927 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
1928 .master = &am33xx_l4_ls_hwmod,
1929 .slave = &am33xx_elm_hwmod,
1931 .addr = am33xx_elm_addr_space,
1932 .user = OCP_USER_MPU,
1935 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
1937 .pa_start = 0x48300000,
1938 .pa_end = 0x48300000 + SZ_16 - 1,
1939 .flags = ADDR_TYPE_RT
1944 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
1945 .master = &am33xx_l4_ls_hwmod,
1946 .slave = &am33xx_epwmss0_hwmod,
1948 .addr = am33xx_epwmss0_addr_space,
1949 .user = OCP_USER_MPU,
1952 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
1953 .master = &am33xx_epwmss0_hwmod,
1954 .slave = &am33xx_ecap0_hwmod,
1956 .user = OCP_USER_MPU,
1959 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
1960 .master = &am33xx_epwmss0_hwmod,
1961 .slave = &am33xx_eqep0_hwmod,
1963 .user = OCP_USER_MPU,
1966 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
1967 .master = &am33xx_epwmss0_hwmod,
1968 .slave = &am33xx_ehrpwm0_hwmod,
1970 .user = OCP_USER_MPU,
1974 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
1976 .pa_start = 0x48302000,
1977 .pa_end = 0x48302000 + SZ_16 - 1,
1978 .flags = ADDR_TYPE_RT
1983 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
1984 .master = &am33xx_l4_ls_hwmod,
1985 .slave = &am33xx_epwmss1_hwmod,
1987 .addr = am33xx_epwmss1_addr_space,
1988 .user = OCP_USER_MPU,
1991 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
1992 .master = &am33xx_epwmss1_hwmod,
1993 .slave = &am33xx_ecap1_hwmod,
1995 .user = OCP_USER_MPU,
1998 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
1999 .master = &am33xx_epwmss1_hwmod,
2000 .slave = &am33xx_eqep1_hwmod,
2002 .user = OCP_USER_MPU,
2005 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2006 .master = &am33xx_epwmss1_hwmod,
2007 .slave = &am33xx_ehrpwm1_hwmod,
2009 .user = OCP_USER_MPU,
2012 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2014 .pa_start = 0x48304000,
2015 .pa_end = 0x48304000 + SZ_16 - 1,
2016 .flags = ADDR_TYPE_RT
2021 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2022 .master = &am33xx_l4_ls_hwmod,
2023 .slave = &am33xx_epwmss2_hwmod,
2025 .addr = am33xx_epwmss2_addr_space,
2026 .user = OCP_USER_MPU,
2029 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2030 .master = &am33xx_epwmss2_hwmod,
2031 .slave = &am33xx_ecap2_hwmod,
2033 .user = OCP_USER_MPU,
2036 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2037 .master = &am33xx_epwmss2_hwmod,
2038 .slave = &am33xx_eqep2_hwmod,
2040 .user = OCP_USER_MPU,
2043 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2044 .master = &am33xx_epwmss2_hwmod,
2045 .slave = &am33xx_ehrpwm2_hwmod,
2047 .user = OCP_USER_MPU,
2050 /* l3s cfg -> gpmc */
2051 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2053 .pa_start = 0x50000000,
2054 .pa_end = 0x50000000 + SZ_8K - 1,
2055 .flags = ADDR_TYPE_RT,
2060 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2061 .master = &am33xx_l3_s_hwmod,
2062 .slave = &am33xx_gpmc_hwmod,
2064 .addr = am33xx_gpmc_addr_space,
2065 .user = OCP_USER_MPU,
2069 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2070 .master = &am33xx_l4_ls_hwmod,
2071 .slave = &am33xx_i2c2_hwmod,
2073 .user = OCP_USER_MPU,
2076 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2077 .master = &am33xx_l4_ls_hwmod,
2078 .slave = &am33xx_i2c3_hwmod,
2080 .user = OCP_USER_MPU,
2083 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2085 .pa_start = 0x4830E000,
2086 .pa_end = 0x4830E000 + SZ_8K - 1,
2087 .flags = ADDR_TYPE_RT,
2092 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2093 .master = &am33xx_l3_main_hwmod,
2094 .slave = &am33xx_lcdc_hwmod,
2095 .clk = "dpll_core_m4_ck",
2096 .addr = am33xx_lcdc_addr_space,
2097 .user = OCP_USER_MPU,
2100 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2102 .pa_start = 0x480C8000,
2103 .pa_end = 0x480C8000 + (SZ_4K - 1),
2104 .flags = ADDR_TYPE_RT
2109 /* l4 ls -> mailbox */
2110 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2111 .master = &am33xx_l4_ls_hwmod,
2112 .slave = &am33xx_mailbox_hwmod,
2114 .addr = am33xx_mailbox_addrs,
2115 .user = OCP_USER_MPU,
2118 /* l4 ls -> spinlock */
2119 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2120 .master = &am33xx_l4_ls_hwmod,
2121 .slave = &am33xx_spinlock_hwmod,
2123 .user = OCP_USER_MPU,
2126 /* l4 ls -> mcasp0 */
2127 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2129 .pa_start = 0x48038000,
2130 .pa_end = 0x48038000 + SZ_8K - 1,
2131 .flags = ADDR_TYPE_RT
2136 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2137 .master = &am33xx_l4_ls_hwmod,
2138 .slave = &am33xx_mcasp0_hwmod,
2140 .addr = am33xx_mcasp0_addr_space,
2141 .user = OCP_USER_MPU,
2144 /* l4 ls -> mcasp1 */
2145 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2147 .pa_start = 0x4803C000,
2148 .pa_end = 0x4803C000 + SZ_8K - 1,
2149 .flags = ADDR_TYPE_RT
2154 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2155 .master = &am33xx_l4_ls_hwmod,
2156 .slave = &am33xx_mcasp1_hwmod,
2158 .addr = am33xx_mcasp1_addr_space,
2159 .user = OCP_USER_MPU,
2163 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2165 .pa_start = 0x48060100,
2166 .pa_end = 0x48060100 + SZ_4K - 1,
2167 .flags = ADDR_TYPE_RT,
2172 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2173 .master = &am33xx_l4_ls_hwmod,
2174 .slave = &am33xx_mmc0_hwmod,
2176 .addr = am33xx_mmc0_addr_space,
2177 .user = OCP_USER_MPU,
2181 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
2183 .pa_start = 0x481d8100,
2184 .pa_end = 0x481d8100 + SZ_4K - 1,
2185 .flags = ADDR_TYPE_RT,
2190 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
2191 .master = &am33xx_l4_ls_hwmod,
2192 .slave = &am33xx_mmc1_hwmod,
2194 .addr = am33xx_mmc1_addr_space,
2195 .user = OCP_USER_MPU,
2199 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2201 .pa_start = 0x47810100,
2202 .pa_end = 0x47810100 + SZ_64K - 1,
2203 .flags = ADDR_TYPE_RT,
2208 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
2209 .master = &am33xx_l3_s_hwmod,
2210 .slave = &am33xx_mmc2_hwmod,
2212 .addr = am33xx_mmc2_addr_space,
2213 .user = OCP_USER_MPU,
2216 /* l4 ls -> mcspi0 */
2217 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
2218 .master = &am33xx_l4_ls_hwmod,
2219 .slave = &am33xx_spi0_hwmod,
2221 .user = OCP_USER_MPU,
2224 /* l4 ls -> mcspi1 */
2225 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
2226 .master = &am33xx_l4_ls_hwmod,
2227 .slave = &am33xx_spi1_hwmod,
2229 .user = OCP_USER_MPU,
2232 /* l4 wkup -> timer1 */
2233 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2234 .master = &am33xx_l4_wkup_hwmod,
2235 .slave = &am33xx_timer1_hwmod,
2236 .clk = "dpll_core_m4_div2_ck",
2237 .user = OCP_USER_MPU,
2240 /* l4 per -> timer2 */
2241 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
2242 .master = &am33xx_l4_ls_hwmod,
2243 .slave = &am33xx_timer2_hwmod,
2245 .user = OCP_USER_MPU,
2248 /* l4 per -> timer3 */
2249 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
2250 .master = &am33xx_l4_ls_hwmod,
2251 .slave = &am33xx_timer3_hwmod,
2253 .user = OCP_USER_MPU,
2256 /* l4 per -> timer4 */
2257 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
2258 .master = &am33xx_l4_ls_hwmod,
2259 .slave = &am33xx_timer4_hwmod,
2261 .user = OCP_USER_MPU,
2264 /* l4 per -> timer5 */
2265 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
2266 .master = &am33xx_l4_ls_hwmod,
2267 .slave = &am33xx_timer5_hwmod,
2269 .user = OCP_USER_MPU,
2272 /* l4 per -> timer6 */
2273 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
2274 .master = &am33xx_l4_ls_hwmod,
2275 .slave = &am33xx_timer6_hwmod,
2277 .user = OCP_USER_MPU,
2280 /* l4 per -> timer7 */
2281 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
2282 .master = &am33xx_l4_ls_hwmod,
2283 .slave = &am33xx_timer7_hwmod,
2285 .user = OCP_USER_MPU,
2288 /* l3 main -> tpcc */
2289 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
2290 .master = &am33xx_l3_main_hwmod,
2291 .slave = &am33xx_tpcc_hwmod,
2293 .user = OCP_USER_MPU,
2296 /* l3 main -> tpcc0 */
2297 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2299 .pa_start = 0x49800000,
2300 .pa_end = 0x49800000 + SZ_8K - 1,
2301 .flags = ADDR_TYPE_RT,
2306 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2307 .master = &am33xx_l3_main_hwmod,
2308 .slave = &am33xx_tptc0_hwmod,
2310 .addr = am33xx_tptc0_addr_space,
2311 .user = OCP_USER_MPU,
2314 /* l3 main -> tpcc1 */
2315 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2317 .pa_start = 0x49900000,
2318 .pa_end = 0x49900000 + SZ_8K - 1,
2319 .flags = ADDR_TYPE_RT,
2324 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2325 .master = &am33xx_l3_main_hwmod,
2326 .slave = &am33xx_tptc1_hwmod,
2328 .addr = am33xx_tptc1_addr_space,
2329 .user = OCP_USER_MPU,
2332 /* l3 main -> tpcc2 */
2333 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2335 .pa_start = 0x49a00000,
2336 .pa_end = 0x49a00000 + SZ_8K - 1,
2337 .flags = ADDR_TYPE_RT,
2342 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2343 .master = &am33xx_l3_main_hwmod,
2344 .slave = &am33xx_tptc2_hwmod,
2346 .addr = am33xx_tptc2_addr_space,
2347 .user = OCP_USER_MPU,
2350 /* l4 wkup -> uart1 */
2351 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2352 .master = &am33xx_l4_wkup_hwmod,
2353 .slave = &am33xx_uart1_hwmod,
2354 .clk = "dpll_core_m4_div2_ck",
2355 .user = OCP_USER_MPU,
2358 /* l4 ls -> uart2 */
2359 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2360 .master = &am33xx_l4_ls_hwmod,
2361 .slave = &am33xx_uart2_hwmod,
2363 .user = OCP_USER_MPU,
2366 /* l4 ls -> uart3 */
2367 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2368 .master = &am33xx_l4_ls_hwmod,
2369 .slave = &am33xx_uart3_hwmod,
2371 .user = OCP_USER_MPU,
2374 /* l4 ls -> uart4 */
2375 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2376 .master = &am33xx_l4_ls_hwmod,
2377 .slave = &am33xx_uart4_hwmod,
2379 .user = OCP_USER_MPU,
2382 /* l4 ls -> uart5 */
2383 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2384 .master = &am33xx_l4_ls_hwmod,
2385 .slave = &am33xx_uart5_hwmod,
2387 .user = OCP_USER_MPU,
2390 /* l4 ls -> uart6 */
2391 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2392 .master = &am33xx_l4_ls_hwmod,
2393 .slave = &am33xx_uart6_hwmod,
2395 .user = OCP_USER_MPU,
2398 /* l4 wkup -> wd_timer1 */
2399 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
2400 .master = &am33xx_l4_wkup_hwmod,
2401 .slave = &am33xx_wd_timer1_hwmod,
2402 .clk = "dpll_core_m4_div2_ck",
2403 .user = OCP_USER_MPU,
2407 /* l3 s -> USBSS interface */
2408 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
2409 .master = &am33xx_l3_s_hwmod,
2410 .slave = &am33xx_usbss_hwmod,
2412 .user = OCP_USER_MPU,
2413 .flags = OCPIF_SWSUP_IDLE,
2416 /* l3 main -> ocmc */
2417 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
2418 .master = &am33xx_l3_main_hwmod,
2419 .slave = &am33xx_ocmcram_hwmod,
2420 .user = OCP_USER_MPU | OCP_USER_SDMA,
2423 /* l3 main -> sha0 HIB2 */
2424 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
2426 .pa_start = 0x53100000,
2427 .pa_end = 0x53100000 + SZ_512 - 1,
2428 .flags = ADDR_TYPE_RT
2433 static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
2434 .master = &am33xx_l3_main_hwmod,
2435 .slave = &am33xx_sha0_hwmod,
2437 .addr = am33xx_sha0_addrs,
2438 .user = OCP_USER_MPU | OCP_USER_SDMA,
2441 /* l3 main -> AES0 HIB2 */
2442 static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
2444 .pa_start = 0x53500000,
2445 .pa_end = 0x53500000 + SZ_1M - 1,
2446 .flags = ADDR_TYPE_RT
2451 static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
2452 .master = &am33xx_l3_main_hwmod,
2453 .slave = &am33xx_aes0_hwmod,
2455 .addr = am33xx_aes0_addrs,
2456 .user = OCP_USER_MPU | OCP_USER_SDMA,
2459 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
2460 &am33xx_l3_main__emif,
2461 &am33xx_mpu__l3_main,
2463 &am33xx_l3_s__l4_ls,
2464 &am33xx_l3_s__l4_wkup,
2465 &am33xx_l3_main__l4_hs,
2466 &am33xx_l3_main__l3_s,
2467 &am33xx_l3_main__l3_instr,
2468 &am33xx_l3_main__gfx,
2469 &am33xx_l3_s__l3_main,
2470 &am33xx_pruss__l3_main,
2471 &am33xx_wkup_m3__l4_wkup,
2472 &am33xx_gfx__l3_main,
2473 &am33xx_l4_wkup__wkup_m3,
2474 &am33xx_l4_wkup__control,
2475 &am33xx_l4_wkup__smartreflex0,
2476 &am33xx_l4_wkup__smartreflex1,
2477 &am33xx_l4_wkup__uart1,
2478 &am33xx_l4_wkup__timer1,
2479 &am33xx_l4_wkup__rtc,
2480 &am33xx_l4_wkup__i2c1,
2481 &am33xx_l4_wkup__gpio0,
2482 &am33xx_l4_wkup__adc_tsc,
2483 &am33xx_l4_wkup__wd_timer1,
2484 &am33xx_l4_hs__pruss,
2485 &am33xx_l4_per__dcan0,
2486 &am33xx_l4_per__dcan1,
2487 &am33xx_l4_per__gpio1,
2488 &am33xx_l4_per__gpio2,
2489 &am33xx_l4_per__gpio3,
2490 &am33xx_l4_per__i2c2,
2491 &am33xx_l4_per__i2c3,
2492 &am33xx_l4_per__mailbox,
2493 &am33xx_l4_ls__mcasp0,
2494 &am33xx_l4_ls__mcasp1,
2495 &am33xx_l4_ls__mmc0,
2496 &am33xx_l4_ls__mmc1,
2498 &am33xx_l4_ls__timer2,
2499 &am33xx_l4_ls__timer3,
2500 &am33xx_l4_ls__timer4,
2501 &am33xx_l4_ls__timer5,
2502 &am33xx_l4_ls__timer6,
2503 &am33xx_l4_ls__timer7,
2504 &am33xx_l3_main__tpcc,
2505 &am33xx_l4_ls__uart2,
2506 &am33xx_l4_ls__uart3,
2507 &am33xx_l4_ls__uart4,
2508 &am33xx_l4_ls__uart5,
2509 &am33xx_l4_ls__uart6,
2510 &am33xx_l4_ls__spinlock,
2512 &am33xx_l4_ls__epwmss0,
2513 &am33xx_epwmss0__ecap0,
2514 &am33xx_epwmss0__eqep0,
2515 &am33xx_epwmss0__ehrpwm0,
2516 &am33xx_l4_ls__epwmss1,
2517 &am33xx_epwmss1__ecap1,
2518 &am33xx_epwmss1__eqep1,
2519 &am33xx_epwmss1__ehrpwm1,
2520 &am33xx_l4_ls__epwmss2,
2521 &am33xx_epwmss2__ecap2,
2522 &am33xx_epwmss2__eqep2,
2523 &am33xx_epwmss2__ehrpwm2,
2525 &am33xx_l3_main__lcdc,
2526 &am33xx_l4_ls__mcspi0,
2527 &am33xx_l4_ls__mcspi1,
2528 &am33xx_l3_main__tptc0,
2529 &am33xx_l3_main__tptc1,
2530 &am33xx_l3_main__tptc2,
2531 &am33xx_l3_main__ocmc,
2532 &am33xx_l3_s__usbss,
2533 &am33xx_l4_hs__cpgmac0,
2534 &am33xx_cpgmac0__mdio,
2535 &am33xx_l3_main__sha0,
2536 &am33xx_l3_main__aes0,
2540 int __init am33xx_hwmod_init(void)
2543 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);