2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/smartreflex.h>
27 #include <plat/mcbsp.h>
28 #include <plat/mcspi.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod_common_data.h"
33 #include "prm-regbits-34xx.h"
34 #include "cm-regbits-34xx.h"
36 #include <mach/am35xx.h>
39 * OMAP3xxx hardware module integration data
41 * ALl of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs
47 static struct omap_hwmod omap3xxx_mpu_hwmod;
48 static struct omap_hwmod omap3xxx_iva_hwmod;
49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
68 static struct omap_hwmod omap34xx_sr1_hwmod;
69 static struct omap_hwmod omap34xx_sr2_hwmod;
70 static struct omap_hwmod omap34xx_mcspi1;
71 static struct omap_hwmod omap34xx_mcspi2;
72 static struct omap_hwmod omap34xx_mcspi3;
73 static struct omap_hwmod omap34xx_mcspi4;
74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
89 /* L3 -> L4_CORE interface */
90 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
91 .master = &omap3xxx_l3_main_hwmod,
92 .slave = &omap3xxx_l4_core_hwmod,
93 .user = OCP_USER_MPU | OCP_USER_SDMA,
96 /* L3 -> L4_PER interface */
97 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
98 .master = &omap3xxx_l3_main_hwmod,
99 .slave = &omap3xxx_l4_per_hwmod,
100 .user = OCP_USER_MPU | OCP_USER_SDMA,
103 /* L3 taret configuration and error log registers */
104 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
105 { .irq = INT_34XX_L3_DBG_IRQ },
106 { .irq = INT_34XX_L3_APP_IRQ },
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
117 /* MPU -> L3 interface */
118 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
119 .master = &omap3xxx_mpu_hwmod,
120 .slave = &omap3xxx_l3_main_hwmod,
121 .addr = omap3xxx_l3_main_addrs,
122 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
123 .user = OCP_USER_MPU,
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128 &omap3xxx_mpu__l3_main,
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133 .master = &omap3xxx_dss_core_hwmod,
134 .slave = &omap3xxx_l3_main_hwmod,
137 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138 .flags = OMAP_FIREWALL_L3,
141 .user = OCP_USER_MPU | OCP_USER_SDMA,
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146 &omap3xxx_l3_main__l4_core,
147 &omap3xxx_l3_main__l4_per,
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
156 .masters = omap3xxx_l3_main_masters,
157 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
158 .slaves = omap3xxx_l3_main_slaves,
159 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
161 .flags = HWMOD_NO_IDLEST,
164 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
165 static struct omap_hwmod omap3xxx_uart1_hwmod;
166 static struct omap_hwmod omap3xxx_uart2_hwmod;
167 static struct omap_hwmod omap3xxx_uart3_hwmod;
168 static struct omap_hwmod omap3xxx_uart4_hwmod;
169 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
171 /* l3_core -> usbhsotg interface */
172 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
173 .master = &omap3xxx_usbhsotg_hwmod,
174 .slave = &omap3xxx_l3_main_hwmod,
175 .clk = "core_l3_ick",
176 .user = OCP_USER_MPU,
179 /* l3_core -> am35xx_usbhsotg interface */
180 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
181 .master = &am35xx_usbhsotg_hwmod,
182 .slave = &omap3xxx_l3_main_hwmod,
183 .clk = "core_l3_ick",
184 .user = OCP_USER_MPU,
186 /* L4_CORE -> L4_WKUP interface */
187 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
188 .master = &omap3xxx_l4_core_hwmod,
189 .slave = &omap3xxx_l4_wkup_hwmod,
190 .user = OCP_USER_MPU | OCP_USER_SDMA,
193 /* L4 CORE -> MMC1 interface */
194 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
196 .pa_start = 0x4809c000,
197 .pa_end = 0x4809c1ff,
198 .flags = ADDR_TYPE_RT,
202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
203 .master = &omap3xxx_l4_core_hwmod,
204 .slave = &omap3xxx_mmc1_hwmod,
206 .addr = omap3xxx_mmc1_addr_space,
207 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 .flags = OMAP_FIREWALL_L4
212 /* L4 CORE -> MMC2 interface */
213 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
215 .pa_start = 0x480b4000,
216 .pa_end = 0x480b41ff,
217 .flags = ADDR_TYPE_RT,
221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
222 .master = &omap3xxx_l4_core_hwmod,
223 .slave = &omap3xxx_mmc2_hwmod,
225 .addr = omap3xxx_mmc2_addr_space,
226 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 .flags = OMAP_FIREWALL_L4
231 /* L4 CORE -> MMC3 interface */
232 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
234 .pa_start = 0x480ad000,
235 .pa_end = 0x480ad1ff,
236 .flags = ADDR_TYPE_RT,
240 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
241 .master = &omap3xxx_l4_core_hwmod,
242 .slave = &omap3xxx_mmc3_hwmod,
244 .addr = omap3xxx_mmc3_addr_space,
245 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247 .flags = OMAP_FIREWALL_L4
250 /* L4 CORE -> UART1 interface */
251 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
253 .pa_start = OMAP3_UART1_BASE,
254 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
255 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
260 .master = &omap3xxx_l4_core_hwmod,
261 .slave = &omap3xxx_uart1_hwmod,
263 .addr = omap3xxx_uart1_addr_space,
264 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
265 .user = OCP_USER_MPU | OCP_USER_SDMA,
268 /* L4 CORE -> UART2 interface */
269 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
271 .pa_start = OMAP3_UART2_BASE,
272 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
273 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
277 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
278 .master = &omap3xxx_l4_core_hwmod,
279 .slave = &omap3xxx_uart2_hwmod,
281 .addr = omap3xxx_uart2_addr_space,
282 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
283 .user = OCP_USER_MPU | OCP_USER_SDMA,
286 /* L4 PER -> UART3 interface */
287 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
289 .pa_start = OMAP3_UART3_BASE,
290 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
291 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
296 .master = &omap3xxx_l4_per_hwmod,
297 .slave = &omap3xxx_uart3_hwmod,
299 .addr = omap3xxx_uart3_addr_space,
300 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
301 .user = OCP_USER_MPU | OCP_USER_SDMA,
304 /* L4 PER -> UART4 interface */
305 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
307 .pa_start = OMAP3_UART4_BASE,
308 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
309 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
313 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
314 .master = &omap3xxx_l4_per_hwmod,
315 .slave = &omap3xxx_uart4_hwmod,
317 .addr = omap3xxx_uart4_addr_space,
318 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
322 /* I2C IP block address space length (in bytes) */
323 #define OMAP2_I2C_AS_LEN 128
325 /* L4 CORE -> I2C1 interface */
326 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
328 .pa_start = 0x48070000,
329 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
330 .flags = ADDR_TYPE_RT,
334 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
335 .master = &omap3xxx_l4_core_hwmod,
336 .slave = &omap3xxx_i2c1_hwmod,
338 .addr = omap3xxx_i2c1_addr_space,
339 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
342 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
344 .flags = OMAP_FIREWALL_L4,
347 .user = OCP_USER_MPU | OCP_USER_SDMA,
350 /* L4 CORE -> I2C2 interface */
351 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
353 .pa_start = 0x48072000,
354 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
355 .flags = ADDR_TYPE_RT,
359 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
360 .master = &omap3xxx_l4_core_hwmod,
361 .slave = &omap3xxx_i2c2_hwmod,
363 .addr = omap3xxx_i2c2_addr_space,
364 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
367 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
369 .flags = OMAP_FIREWALL_L4,
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
375 /* L4 CORE -> I2C3 interface */
376 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
378 .pa_start = 0x48060000,
379 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
380 .flags = ADDR_TYPE_RT,
384 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
385 .master = &omap3xxx_l4_core_hwmod,
386 .slave = &omap3xxx_i2c3_hwmod,
388 .addr = omap3xxx_i2c3_addr_space,
389 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
392 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
394 .flags = OMAP_FIREWALL_L4,
397 .user = OCP_USER_MPU | OCP_USER_SDMA,
400 /* L4 CORE -> SR1 interface */
401 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
403 .pa_start = OMAP34XX_SR1_BASE,
404 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
405 .flags = ADDR_TYPE_RT,
409 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
410 .master = &omap3xxx_l4_core_hwmod,
411 .slave = &omap34xx_sr1_hwmod,
413 .addr = omap3_sr1_addr_space,
414 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
415 .user = OCP_USER_MPU,
418 /* L4 CORE -> SR1 interface */
419 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
421 .pa_start = OMAP34XX_SR2_BASE,
422 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
423 .flags = ADDR_TYPE_RT,
427 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
428 .master = &omap3xxx_l4_core_hwmod,
429 .slave = &omap34xx_sr2_hwmod,
431 .addr = omap3_sr2_addr_space,
432 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
433 .user = OCP_USER_MPU,
437 * usbhsotg interface data
440 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
442 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
443 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
444 .flags = ADDR_TYPE_RT
448 /* l4_core -> usbhsotg */
449 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
450 .master = &omap3xxx_l4_core_hwmod,
451 .slave = &omap3xxx_usbhsotg_hwmod,
453 .addr = omap3xxx_usbhsotg_addrs,
454 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
455 .user = OCP_USER_MPU,
458 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
459 &omap3xxx_usbhsotg__l3,
462 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
463 &omap3xxx_l4_core__usbhsotg,
466 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
468 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
469 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
470 .flags = ADDR_TYPE_RT
474 /* l4_core -> usbhsotg */
475 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
476 .master = &omap3xxx_l4_core_hwmod,
477 .slave = &am35xx_usbhsotg_hwmod,
479 .addr = am35xx_usbhsotg_addrs,
480 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
481 .user = OCP_USER_MPU,
484 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
485 &am35xx_usbhsotg__l3,
488 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
489 &am35xx_l4_core__usbhsotg,
491 /* Slave interfaces on the L4_CORE interconnect */
492 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
493 &omap3xxx_l3_main__l4_core,
497 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
499 .class = &l4_hwmod_class,
500 .slaves = omap3xxx_l4_core_slaves,
501 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
502 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
503 .flags = HWMOD_NO_IDLEST,
506 /* Slave interfaces on the L4_PER interconnect */
507 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
508 &omap3xxx_l3_main__l4_per,
512 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
514 .class = &l4_hwmod_class,
515 .slaves = omap3xxx_l4_per_slaves,
516 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
518 .flags = HWMOD_NO_IDLEST,
521 /* Slave interfaces on the L4_WKUP interconnect */
522 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
523 &omap3xxx_l4_core__l4_wkup,
527 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
529 .class = &l4_hwmod_class,
530 .slaves = omap3xxx_l4_wkup_slaves,
531 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
533 .flags = HWMOD_NO_IDLEST,
536 /* Master interfaces on the MPU device */
537 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
538 &omap3xxx_mpu__l3_main,
542 static struct omap_hwmod omap3xxx_mpu_hwmod = {
544 .class = &mpu_hwmod_class,
545 .main_clk = "arm_fck",
546 .masters = omap3xxx_mpu_masters,
547 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
548 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
552 * IVA2_2 interface data
555 /* IVA2 <- L3 interface */
556 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
557 .master = &omap3xxx_l3_main_hwmod,
558 .slave = &omap3xxx_iva_hwmod,
560 .user = OCP_USER_MPU | OCP_USER_SDMA,
563 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
571 static struct omap_hwmod omap3xxx_iva_hwmod = {
573 .class = &iva_hwmod_class,
574 .masters = omap3xxx_iva_masters,
575 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
580 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
584 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
585 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
586 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
587 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
588 .sysc_fields = &omap_hwmod_sysc_type1,
591 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
593 .sysc = &omap3xxx_timer_1ms_sysc,
594 .rev = OMAP_TIMER_IP_VERSION_1,
597 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
601 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
602 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
603 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
604 .sysc_fields = &omap_hwmod_sysc_type1,
607 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
609 .sysc = &omap3xxx_timer_sysc,
610 .rev = OMAP_TIMER_IP_VERSION_1,
614 static struct omap_hwmod omap3xxx_timer1_hwmod;
615 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
619 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
621 .pa_start = 0x48318000,
622 .pa_end = 0x48318000 + SZ_1K - 1,
623 .flags = ADDR_TYPE_RT
627 /* l4_wkup -> timer1 */
628 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
629 .master = &omap3xxx_l4_wkup_hwmod,
630 .slave = &omap3xxx_timer1_hwmod,
632 .addr = omap3xxx_timer1_addrs,
633 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
634 .user = OCP_USER_MPU | OCP_USER_SDMA,
637 /* timer1 slave port */
638 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
639 &omap3xxx_l4_wkup__timer1,
643 static struct omap_hwmod omap3xxx_timer1_hwmod = {
645 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
646 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
647 .main_clk = "gpt1_fck",
651 .module_bit = OMAP3430_EN_GPT1_SHIFT,
652 .module_offs = WKUP_MOD,
654 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
657 .slaves = omap3xxx_timer1_slaves,
658 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
659 .class = &omap3xxx_timer_1ms_hwmod_class,
660 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
664 static struct omap_hwmod omap3xxx_timer2_hwmod;
665 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
669 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
671 .pa_start = 0x49032000,
672 .pa_end = 0x49032000 + SZ_1K - 1,
673 .flags = ADDR_TYPE_RT
677 /* l4_per -> timer2 */
678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
679 .master = &omap3xxx_l4_per_hwmod,
680 .slave = &omap3xxx_timer2_hwmod,
682 .addr = omap3xxx_timer2_addrs,
683 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
684 .user = OCP_USER_MPU | OCP_USER_SDMA,
687 /* timer2 slave port */
688 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
689 &omap3xxx_l4_per__timer2,
693 static struct omap_hwmod omap3xxx_timer2_hwmod = {
695 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
696 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
697 .main_clk = "gpt2_fck",
701 .module_bit = OMAP3430_EN_GPT2_SHIFT,
702 .module_offs = OMAP3430_PER_MOD,
704 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
707 .slaves = omap3xxx_timer2_slaves,
708 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
709 .class = &omap3xxx_timer_1ms_hwmod_class,
710 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
714 static struct omap_hwmod omap3xxx_timer3_hwmod;
715 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
719 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
721 .pa_start = 0x49034000,
722 .pa_end = 0x49034000 + SZ_1K - 1,
723 .flags = ADDR_TYPE_RT
727 /* l4_per -> timer3 */
728 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
729 .master = &omap3xxx_l4_per_hwmod,
730 .slave = &omap3xxx_timer3_hwmod,
732 .addr = omap3xxx_timer3_addrs,
733 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
734 .user = OCP_USER_MPU | OCP_USER_SDMA,
737 /* timer3 slave port */
738 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
739 &omap3xxx_l4_per__timer3,
743 static struct omap_hwmod omap3xxx_timer3_hwmod = {
745 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
746 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
747 .main_clk = "gpt3_fck",
751 .module_bit = OMAP3430_EN_GPT3_SHIFT,
752 .module_offs = OMAP3430_PER_MOD,
754 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
757 .slaves = omap3xxx_timer3_slaves,
758 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
759 .class = &omap3xxx_timer_hwmod_class,
760 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
764 static struct omap_hwmod omap3xxx_timer4_hwmod;
765 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
769 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
771 .pa_start = 0x49036000,
772 .pa_end = 0x49036000 + SZ_1K - 1,
773 .flags = ADDR_TYPE_RT
777 /* l4_per -> timer4 */
778 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
779 .master = &omap3xxx_l4_per_hwmod,
780 .slave = &omap3xxx_timer4_hwmod,
782 .addr = omap3xxx_timer4_addrs,
783 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
784 .user = OCP_USER_MPU | OCP_USER_SDMA,
787 /* timer4 slave port */
788 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
789 &omap3xxx_l4_per__timer4,
793 static struct omap_hwmod omap3xxx_timer4_hwmod = {
795 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
796 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
797 .main_clk = "gpt4_fck",
801 .module_bit = OMAP3430_EN_GPT4_SHIFT,
802 .module_offs = OMAP3430_PER_MOD,
804 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
807 .slaves = omap3xxx_timer4_slaves,
808 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
809 .class = &omap3xxx_timer_hwmod_class,
810 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
814 static struct omap_hwmod omap3xxx_timer5_hwmod;
815 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
819 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
821 .pa_start = 0x49038000,
822 .pa_end = 0x49038000 + SZ_1K - 1,
823 .flags = ADDR_TYPE_RT
827 /* l4_per -> timer5 */
828 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
829 .master = &omap3xxx_l4_per_hwmod,
830 .slave = &omap3xxx_timer5_hwmod,
832 .addr = omap3xxx_timer5_addrs,
833 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
834 .user = OCP_USER_MPU | OCP_USER_SDMA,
837 /* timer5 slave port */
838 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
839 &omap3xxx_l4_per__timer5,
843 static struct omap_hwmod omap3xxx_timer5_hwmod = {
845 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
846 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
847 .main_clk = "gpt5_fck",
851 .module_bit = OMAP3430_EN_GPT5_SHIFT,
852 .module_offs = OMAP3430_PER_MOD,
854 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
857 .slaves = omap3xxx_timer5_slaves,
858 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
859 .class = &omap3xxx_timer_hwmod_class,
860 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
864 static struct omap_hwmod omap3xxx_timer6_hwmod;
865 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
869 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
871 .pa_start = 0x4903A000,
872 .pa_end = 0x4903A000 + SZ_1K - 1,
873 .flags = ADDR_TYPE_RT
877 /* l4_per -> timer6 */
878 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
879 .master = &omap3xxx_l4_per_hwmod,
880 .slave = &omap3xxx_timer6_hwmod,
882 .addr = omap3xxx_timer6_addrs,
883 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
887 /* timer6 slave port */
888 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
889 &omap3xxx_l4_per__timer6,
893 static struct omap_hwmod omap3xxx_timer6_hwmod = {
895 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
896 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
897 .main_clk = "gpt6_fck",
901 .module_bit = OMAP3430_EN_GPT6_SHIFT,
902 .module_offs = OMAP3430_PER_MOD,
904 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
907 .slaves = omap3xxx_timer6_slaves,
908 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
909 .class = &omap3xxx_timer_hwmod_class,
910 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
914 static struct omap_hwmod omap3xxx_timer7_hwmod;
915 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
919 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
921 .pa_start = 0x4903C000,
922 .pa_end = 0x4903C000 + SZ_1K - 1,
923 .flags = ADDR_TYPE_RT
927 /* l4_per -> timer7 */
928 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
929 .master = &omap3xxx_l4_per_hwmod,
930 .slave = &omap3xxx_timer7_hwmod,
932 .addr = omap3xxx_timer7_addrs,
933 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
934 .user = OCP_USER_MPU | OCP_USER_SDMA,
937 /* timer7 slave port */
938 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
939 &omap3xxx_l4_per__timer7,
943 static struct omap_hwmod omap3xxx_timer7_hwmod = {
945 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
946 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
947 .main_clk = "gpt7_fck",
951 .module_bit = OMAP3430_EN_GPT7_SHIFT,
952 .module_offs = OMAP3430_PER_MOD,
954 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
957 .slaves = omap3xxx_timer7_slaves,
958 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
959 .class = &omap3xxx_timer_hwmod_class,
960 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
964 static struct omap_hwmod omap3xxx_timer8_hwmod;
965 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
969 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
971 .pa_start = 0x4903E000,
972 .pa_end = 0x4903E000 + SZ_1K - 1,
973 .flags = ADDR_TYPE_RT
977 /* l4_per -> timer8 */
978 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
979 .master = &omap3xxx_l4_per_hwmod,
980 .slave = &omap3xxx_timer8_hwmod,
982 .addr = omap3xxx_timer8_addrs,
983 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
984 .user = OCP_USER_MPU | OCP_USER_SDMA,
987 /* timer8 slave port */
988 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
989 &omap3xxx_l4_per__timer8,
993 static struct omap_hwmod omap3xxx_timer8_hwmod = {
995 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
996 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
997 .main_clk = "gpt8_fck",
1001 .module_bit = OMAP3430_EN_GPT8_SHIFT,
1002 .module_offs = OMAP3430_PER_MOD,
1004 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1007 .slaves = omap3xxx_timer8_slaves,
1008 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
1009 .class = &omap3xxx_timer_hwmod_class,
1010 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1014 static struct omap_hwmod omap3xxx_timer9_hwmod;
1015 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1019 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1021 .pa_start = 0x49040000,
1022 .pa_end = 0x49040000 + SZ_1K - 1,
1023 .flags = ADDR_TYPE_RT
1027 /* l4_per -> timer9 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1029 .master = &omap3xxx_l4_per_hwmod,
1030 .slave = &omap3xxx_timer9_hwmod,
1032 .addr = omap3xxx_timer9_addrs,
1033 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1034 .user = OCP_USER_MPU | OCP_USER_SDMA,
1037 /* timer9 slave port */
1038 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1039 &omap3xxx_l4_per__timer9,
1043 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1045 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
1046 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1047 .main_clk = "gpt9_fck",
1051 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1052 .module_offs = OMAP3430_PER_MOD,
1054 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1057 .slaves = omap3xxx_timer9_slaves,
1058 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1059 .class = &omap3xxx_timer_hwmod_class,
1060 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1064 static struct omap_hwmod omap3xxx_timer10_hwmod;
1065 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1069 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1071 .pa_start = 0x48086000,
1072 .pa_end = 0x48086000 + SZ_1K - 1,
1073 .flags = ADDR_TYPE_RT
1077 /* l4_core -> timer10 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1079 .master = &omap3xxx_l4_core_hwmod,
1080 .slave = &omap3xxx_timer10_hwmod,
1082 .addr = omap3xxx_timer10_addrs,
1083 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1084 .user = OCP_USER_MPU | OCP_USER_SDMA,
1087 /* timer10 slave port */
1088 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1089 &omap3xxx_l4_core__timer10,
1093 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1095 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1096 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1097 .main_clk = "gpt10_fck",
1101 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1102 .module_offs = CORE_MOD,
1104 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1107 .slaves = omap3xxx_timer10_slaves,
1108 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1109 .class = &omap3xxx_timer_1ms_hwmod_class,
1110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1114 static struct omap_hwmod omap3xxx_timer11_hwmod;
1115 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1119 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1121 .pa_start = 0x48088000,
1122 .pa_end = 0x48088000 + SZ_1K - 1,
1123 .flags = ADDR_TYPE_RT
1127 /* l4_core -> timer11 */
1128 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1129 .master = &omap3xxx_l4_core_hwmod,
1130 .slave = &omap3xxx_timer11_hwmod,
1132 .addr = omap3xxx_timer11_addrs,
1133 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1134 .user = OCP_USER_MPU | OCP_USER_SDMA,
1137 /* timer11 slave port */
1138 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1139 &omap3xxx_l4_core__timer11,
1143 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1145 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1146 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1147 .main_clk = "gpt11_fck",
1151 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1152 .module_offs = CORE_MOD,
1154 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1157 .slaves = omap3xxx_timer11_slaves,
1158 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1159 .class = &omap3xxx_timer_hwmod_class,
1160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1164 static struct omap_hwmod omap3xxx_timer12_hwmod;
1165 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1169 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1171 .pa_start = 0x48304000,
1172 .pa_end = 0x48304000 + SZ_1K - 1,
1173 .flags = ADDR_TYPE_RT
1177 /* l4_core -> timer12 */
1178 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1179 .master = &omap3xxx_l4_core_hwmod,
1180 .slave = &omap3xxx_timer12_hwmod,
1182 .addr = omap3xxx_timer12_addrs,
1183 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1184 .user = OCP_USER_MPU | OCP_USER_SDMA,
1187 /* timer12 slave port */
1188 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1189 &omap3xxx_l4_core__timer12,
1193 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1195 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1196 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1197 .main_clk = "gpt12_fck",
1201 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1202 .module_offs = WKUP_MOD,
1204 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1207 .slaves = omap3xxx_timer12_slaves,
1208 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1209 .class = &omap3xxx_timer_hwmod_class,
1210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1213 /* l4_wkup -> wd_timer2 */
1214 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1216 .pa_start = 0x48314000,
1217 .pa_end = 0x4831407f,
1218 .flags = ADDR_TYPE_RT
1222 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1223 .master = &omap3xxx_l4_wkup_hwmod,
1224 .slave = &omap3xxx_wd_timer2_hwmod,
1226 .addr = omap3xxx_wd_timer2_addrs,
1227 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1228 .user = OCP_USER_MPU | OCP_USER_SDMA,
1233 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1234 * overflow condition
1237 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1239 .sysc_offs = 0x0010,
1240 .syss_offs = 0x0014,
1241 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1242 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1243 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1244 SYSS_HAS_RESET_STATUS),
1245 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1246 .sysc_fields = &omap_hwmod_sysc_type1,
1250 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1254 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1255 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1256 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1257 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1258 .sysc_fields = &omap_hwmod_sysc_type1,
1261 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1263 .sysc = &omap3xxx_wd_timer_sysc,
1264 .pre_shutdown = &omap2_wd_timer_disable
1268 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1269 &omap3xxx_l4_wkup__wd_timer2,
1272 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1273 .name = "wd_timer2",
1274 .class = &omap3xxx_wd_timer_hwmod_class,
1275 .main_clk = "wdt2_fck",
1279 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1280 .module_offs = WKUP_MOD,
1282 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1285 .slaves = omap3xxx_wd_timer2_slaves,
1286 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1289 * XXX: Use software supervised mode, HW supervised smartidle seems to
1290 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1292 .flags = HWMOD_SWSUP_SIDLE,
1297 static struct omap_hwmod_class_sysconfig uart_sysc = {
1301 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1302 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1303 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1304 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1305 .sysc_fields = &omap_hwmod_sysc_type1,
1308 static struct omap_hwmod_class uart_class = {
1315 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1316 { .irq = INT_24XX_UART1_IRQ, },
1319 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1320 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1321 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1324 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1325 &omap3_l4_core__uart1,
1328 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1330 .mpu_irqs = uart1_mpu_irqs,
1331 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
1332 .sdma_reqs = uart1_sdma_reqs,
1333 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1334 .main_clk = "uart1_fck",
1337 .module_offs = CORE_MOD,
1339 .module_bit = OMAP3430_EN_UART1_SHIFT,
1341 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1344 .slaves = omap3xxx_uart1_slaves,
1345 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1346 .class = &uart_class,
1347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1352 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1353 { .irq = INT_24XX_UART2_IRQ, },
1356 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1357 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1358 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1361 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1362 &omap3_l4_core__uart2,
1365 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1367 .mpu_irqs = uart2_mpu_irqs,
1368 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
1369 .sdma_reqs = uart2_sdma_reqs,
1370 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1371 .main_clk = "uart2_fck",
1374 .module_offs = CORE_MOD,
1376 .module_bit = OMAP3430_EN_UART2_SHIFT,
1378 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1381 .slaves = omap3xxx_uart2_slaves,
1382 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1383 .class = &uart_class,
1384 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1389 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1390 { .irq = INT_24XX_UART3_IRQ, },
1393 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1394 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1395 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1398 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1399 &omap3_l4_per__uart3,
1402 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1404 .mpu_irqs = uart3_mpu_irqs,
1405 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
1406 .sdma_reqs = uart3_sdma_reqs,
1407 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1408 .main_clk = "uart3_fck",
1411 .module_offs = OMAP3430_PER_MOD,
1413 .module_bit = OMAP3430_EN_UART3_SHIFT,
1415 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1418 .slaves = omap3xxx_uart3_slaves,
1419 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1420 .class = &uart_class,
1421 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1426 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1427 { .irq = INT_36XX_UART4_IRQ, },
1430 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1431 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1432 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1435 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1436 &omap3_l4_per__uart4,
1439 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1441 .mpu_irqs = uart4_mpu_irqs,
1442 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1443 .sdma_reqs = uart4_sdma_reqs,
1444 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1445 .main_clk = "uart4_fck",
1448 .module_offs = OMAP3430_PER_MOD,
1450 .module_bit = OMAP3630_EN_UART4_SHIFT,
1452 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1455 .slaves = omap3xxx_uart4_slaves,
1456 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1457 .class = &uart_class,
1458 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1461 static struct omap_hwmod_class i2c_class = {
1468 * display sub-system
1471 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1473 .sysc_offs = 0x0010,
1474 .syss_offs = 0x0014,
1475 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1476 .sysc_fields = &omap_hwmod_sysc_type1,
1479 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1481 .sysc = &omap3xxx_dss_sysc,
1485 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
1489 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1490 { .name = "dispc", .dma_req = 5 },
1491 { .name = "dsi1", .dma_req = 74 },
1495 /* dss master ports */
1496 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1500 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1502 .pa_start = 0x48050000,
1503 .pa_end = 0x480503FF,
1504 .flags = ADDR_TYPE_RT
1508 /* l4_core -> dss */
1509 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1510 .master = &omap3xxx_l4_core_hwmod,
1511 .slave = &omap3430es1_dss_core_hwmod,
1513 .addr = omap3xxx_dss_addrs,
1514 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1517 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1518 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1519 .flags = OMAP_FIREWALL_L4,
1522 .user = OCP_USER_MPU | OCP_USER_SDMA,
1525 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1526 .master = &omap3xxx_l4_core_hwmod,
1527 .slave = &omap3xxx_dss_core_hwmod,
1529 .addr = omap3xxx_dss_addrs,
1530 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1533 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1534 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1535 .flags = OMAP_FIREWALL_L4,
1538 .user = OCP_USER_MPU | OCP_USER_SDMA,
1541 /* dss slave ports */
1542 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1543 &omap3430es1_l4_core__dss,
1546 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1547 &omap3xxx_l4_core__dss,
1550 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1551 { .role = "tv_clk", .clk = "dss_tv_fck" },
1552 { .role = "dssclk", .clk = "dss_96m_fck" },
1553 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1556 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1558 .class = &omap3xxx_dss_hwmod_class,
1559 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1560 .mpu_irqs = omap3xxx_dss_irqs,
1561 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1562 .sdma_reqs = omap3xxx_dss_sdma_chs,
1563 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1568 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1569 .module_offs = OMAP3430_DSS_MOD,
1571 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1574 .opt_clks = dss_opt_clks,
1575 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1576 .slaves = omap3430es1_dss_slaves,
1577 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1578 .masters = omap3xxx_dss_masters,
1579 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1581 .flags = HWMOD_NO_IDLEST,
1584 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1586 .class = &omap3xxx_dss_hwmod_class,
1587 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1588 .mpu_irqs = omap3xxx_dss_irqs,
1589 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
1590 .sdma_reqs = omap3xxx_dss_sdma_chs,
1591 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1596 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1597 .module_offs = OMAP3430_DSS_MOD,
1599 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1600 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1603 .opt_clks = dss_opt_clks,
1604 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1605 .slaves = omap3xxx_dss_slaves,
1606 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1607 .masters = omap3xxx_dss_masters,
1608 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1609 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1610 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1615 * display controller
1618 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1620 .sysc_offs = 0x0010,
1621 .syss_offs = 0x0014,
1622 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1623 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1624 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1625 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1626 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1627 .sysc_fields = &omap_hwmod_sysc_type1,
1630 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1632 .sysc = &omap3xxx_dispc_sysc,
1635 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1637 .pa_start = 0x48050400,
1638 .pa_end = 0x480507FF,
1639 .flags = ADDR_TYPE_RT
1643 /* l4_core -> dss_dispc */
1644 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1645 .master = &omap3xxx_l4_core_hwmod,
1646 .slave = &omap3xxx_dss_dispc_hwmod,
1648 .addr = omap3xxx_dss_dispc_addrs,
1649 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1652 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1653 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1654 .flags = OMAP_FIREWALL_L4,
1657 .user = OCP_USER_MPU | OCP_USER_SDMA,
1660 /* dss_dispc slave ports */
1661 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1662 &omap3xxx_l4_core__dss_dispc,
1665 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1666 .name = "dss_dispc",
1667 .class = &omap3xxx_dispc_hwmod_class,
1668 .main_clk = "dss1_alwon_fck",
1672 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1673 .module_offs = OMAP3430_DSS_MOD,
1676 .slaves = omap3xxx_dss_dispc_slaves,
1677 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1678 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1679 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1680 CHIP_GE_OMAP3630ES1_1),
1681 .flags = HWMOD_NO_IDLEST,
1686 * display serial interface controller
1689 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1694 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1696 .pa_start = 0x4804FC00,
1697 .pa_end = 0x4804FFFF,
1698 .flags = ADDR_TYPE_RT
1702 /* l4_core -> dss_dsi1 */
1703 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1704 .master = &omap3xxx_l4_core_hwmod,
1705 .slave = &omap3xxx_dss_dsi1_hwmod,
1706 .addr = omap3xxx_dss_dsi1_addrs,
1707 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1710 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1711 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1712 .flags = OMAP_FIREWALL_L4,
1715 .user = OCP_USER_MPU | OCP_USER_SDMA,
1718 /* dss_dsi1 slave ports */
1719 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1720 &omap3xxx_l4_core__dss_dsi1,
1723 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1725 .class = &omap3xxx_dsi_hwmod_class,
1726 .main_clk = "dss1_alwon_fck",
1730 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1731 .module_offs = OMAP3430_DSS_MOD,
1734 .slaves = omap3xxx_dss_dsi1_slaves,
1735 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1736 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1737 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1738 CHIP_GE_OMAP3630ES1_1),
1739 .flags = HWMOD_NO_IDLEST,
1744 * remote frame buffer interface
1747 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1749 .sysc_offs = 0x0010,
1750 .syss_offs = 0x0014,
1751 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1754 .sysc_fields = &omap_hwmod_sysc_type1,
1757 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1759 .sysc = &omap3xxx_rfbi_sysc,
1762 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1764 .pa_start = 0x48050800,
1765 .pa_end = 0x48050BFF,
1766 .flags = ADDR_TYPE_RT
1770 /* l4_core -> dss_rfbi */
1771 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1772 .master = &omap3xxx_l4_core_hwmod,
1773 .slave = &omap3xxx_dss_rfbi_hwmod,
1775 .addr = omap3xxx_dss_rfbi_addrs,
1776 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1779 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1780 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1781 .flags = OMAP_FIREWALL_L4,
1784 .user = OCP_USER_MPU | OCP_USER_SDMA,
1787 /* dss_rfbi slave ports */
1788 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1789 &omap3xxx_l4_core__dss_rfbi,
1792 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1794 .class = &omap3xxx_rfbi_hwmod_class,
1795 .main_clk = "dss1_alwon_fck",
1799 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1800 .module_offs = OMAP3430_DSS_MOD,
1803 .slaves = omap3xxx_dss_rfbi_slaves,
1804 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1805 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1806 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1807 CHIP_GE_OMAP3630ES1_1),
1808 .flags = HWMOD_NO_IDLEST,
1816 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1821 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1823 .pa_start = 0x48050C00,
1824 .pa_end = 0x48050FFF,
1825 .flags = ADDR_TYPE_RT
1829 /* l4_core -> dss_venc */
1830 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1831 .master = &omap3xxx_l4_core_hwmod,
1832 .slave = &omap3xxx_dss_venc_hwmod,
1833 .clk = "dss_tv_fck",
1834 .addr = omap3xxx_dss_venc_addrs,
1835 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1838 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1839 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1840 .flags = OMAP_FIREWALL_L4,
1843 .flags = OCPIF_SWSUP_IDLE,
1844 .user = OCP_USER_MPU | OCP_USER_SDMA,
1847 /* dss_venc slave ports */
1848 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1849 &omap3xxx_l4_core__dss_venc,
1852 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1854 .class = &omap3xxx_venc_hwmod_class,
1855 .main_clk = "dss1_alwon_fck",
1859 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1860 .module_offs = OMAP3430_DSS_MOD,
1863 .slaves = omap3xxx_dss_venc_slaves,
1864 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1865 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1866 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1867 CHIP_GE_OMAP3630ES1_1),
1868 .flags = HWMOD_NO_IDLEST,
1873 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1874 .fifo_depth = 8, /* bytes */
1877 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1878 { .irq = INT_24XX_I2C1_IRQ, },
1881 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1882 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1883 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1886 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1887 &omap3_l4_core__i2c1,
1890 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1892 .mpu_irqs = i2c1_mpu_irqs,
1893 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1894 .sdma_reqs = i2c1_sdma_reqs,
1895 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1896 .main_clk = "i2c1_fck",
1899 .module_offs = CORE_MOD,
1901 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1903 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1906 .slaves = omap3xxx_i2c1_slaves,
1907 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1908 .class = &i2c_class,
1909 .dev_attr = &i2c1_dev_attr,
1910 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1915 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1916 .fifo_depth = 8, /* bytes */
1919 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1920 { .irq = INT_24XX_I2C2_IRQ, },
1923 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1924 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1925 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1928 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1929 &omap3_l4_core__i2c2,
1932 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1934 .mpu_irqs = i2c2_mpu_irqs,
1935 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1936 .sdma_reqs = i2c2_sdma_reqs,
1937 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1938 .main_clk = "i2c2_fck",
1941 .module_offs = CORE_MOD,
1943 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1945 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1948 .slaves = omap3xxx_i2c2_slaves,
1949 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1950 .class = &i2c_class,
1951 .dev_attr = &i2c2_dev_attr,
1952 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1957 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1958 .fifo_depth = 64, /* bytes */
1961 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1962 { .irq = INT_34XX_I2C3_IRQ, },
1965 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1966 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1967 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1970 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1971 &omap3_l4_core__i2c3,
1974 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1976 .mpu_irqs = i2c3_mpu_irqs,
1977 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1978 .sdma_reqs = i2c3_sdma_reqs,
1979 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1980 .main_clk = "i2c3_fck",
1983 .module_offs = CORE_MOD,
1985 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1987 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1990 .slaves = omap3xxx_i2c3_slaves,
1991 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1992 .class = &i2c_class,
1993 .dev_attr = &i2c3_dev_attr,
1994 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1997 /* l4_wkup -> gpio1 */
1998 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2000 .pa_start = 0x48310000,
2001 .pa_end = 0x483101ff,
2002 .flags = ADDR_TYPE_RT
2006 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2007 .master = &omap3xxx_l4_wkup_hwmod,
2008 .slave = &omap3xxx_gpio1_hwmod,
2009 .addr = omap3xxx_gpio1_addrs,
2010 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2011 .user = OCP_USER_MPU | OCP_USER_SDMA,
2014 /* l4_per -> gpio2 */
2015 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2017 .pa_start = 0x49050000,
2018 .pa_end = 0x490501ff,
2019 .flags = ADDR_TYPE_RT
2023 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2024 .master = &omap3xxx_l4_per_hwmod,
2025 .slave = &omap3xxx_gpio2_hwmod,
2026 .addr = omap3xxx_gpio2_addrs,
2027 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2028 .user = OCP_USER_MPU | OCP_USER_SDMA,
2031 /* l4_per -> gpio3 */
2032 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2034 .pa_start = 0x49052000,
2035 .pa_end = 0x490521ff,
2036 .flags = ADDR_TYPE_RT
2040 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2041 .master = &omap3xxx_l4_per_hwmod,
2042 .slave = &omap3xxx_gpio3_hwmod,
2043 .addr = omap3xxx_gpio3_addrs,
2044 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2045 .user = OCP_USER_MPU | OCP_USER_SDMA,
2048 /* l4_per -> gpio4 */
2049 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2051 .pa_start = 0x49054000,
2052 .pa_end = 0x490541ff,
2053 .flags = ADDR_TYPE_RT
2057 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2058 .master = &omap3xxx_l4_per_hwmod,
2059 .slave = &omap3xxx_gpio4_hwmod,
2060 .addr = omap3xxx_gpio4_addrs,
2061 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2062 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065 /* l4_per -> gpio5 */
2066 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2068 .pa_start = 0x49056000,
2069 .pa_end = 0x490561ff,
2070 .flags = ADDR_TYPE_RT
2074 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2075 .master = &omap3xxx_l4_per_hwmod,
2076 .slave = &omap3xxx_gpio5_hwmod,
2077 .addr = omap3xxx_gpio5_addrs,
2078 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2079 .user = OCP_USER_MPU | OCP_USER_SDMA,
2082 /* l4_per -> gpio6 */
2083 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2085 .pa_start = 0x49058000,
2086 .pa_end = 0x490581ff,
2087 .flags = ADDR_TYPE_RT
2091 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2092 .master = &omap3xxx_l4_per_hwmod,
2093 .slave = &omap3xxx_gpio6_hwmod,
2094 .addr = omap3xxx_gpio6_addrs,
2095 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2096 .user = OCP_USER_MPU | OCP_USER_SDMA,
2101 * general purpose io module
2104 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2106 .sysc_offs = 0x0010,
2107 .syss_offs = 0x0014,
2108 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2109 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2110 SYSS_HAS_RESET_STATUS),
2111 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2112 .sysc_fields = &omap_hwmod_sysc_type1,
2115 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2117 .sysc = &omap3xxx_gpio_sysc,
2122 static struct omap_gpio_dev_attr gpio_dev_attr = {
2128 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2129 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2132 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2133 { .role = "dbclk", .clk = "gpio1_dbck", },
2136 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2137 &omap3xxx_l4_wkup__gpio1,
2140 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2142 .mpu_irqs = omap3xxx_gpio1_irqs,
2143 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2144 .main_clk = "gpio1_ick",
2145 .opt_clks = gpio1_opt_clks,
2146 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
2150 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2151 .module_offs = WKUP_MOD,
2153 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2156 .slaves = omap3xxx_gpio1_slaves,
2157 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2158 .class = &omap3xxx_gpio_hwmod_class,
2159 .dev_attr = &gpio_dev_attr,
2160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2164 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2165 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2168 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2169 { .role = "dbclk", .clk = "gpio2_dbck", },
2172 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2173 &omap3xxx_l4_per__gpio2,
2176 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2178 .mpu_irqs = omap3xxx_gpio2_irqs,
2179 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2180 .main_clk = "gpio2_ick",
2181 .opt_clks = gpio2_opt_clks,
2182 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2186 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2187 .module_offs = OMAP3430_PER_MOD,
2189 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2192 .slaves = omap3xxx_gpio2_slaves,
2193 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2194 .class = &omap3xxx_gpio_hwmod_class,
2195 .dev_attr = &gpio_dev_attr,
2196 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2200 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2201 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2204 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2205 { .role = "dbclk", .clk = "gpio3_dbck", },
2208 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2209 &omap3xxx_l4_per__gpio3,
2212 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2214 .mpu_irqs = omap3xxx_gpio3_irqs,
2215 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2216 .main_clk = "gpio3_ick",
2217 .opt_clks = gpio3_opt_clks,
2218 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2222 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2223 .module_offs = OMAP3430_PER_MOD,
2225 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2228 .slaves = omap3xxx_gpio3_slaves,
2229 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2230 .class = &omap3xxx_gpio_hwmod_class,
2231 .dev_attr = &gpio_dev_attr,
2232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2236 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2237 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2240 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2241 { .role = "dbclk", .clk = "gpio4_dbck", },
2244 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2245 &omap3xxx_l4_per__gpio4,
2248 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2250 .mpu_irqs = omap3xxx_gpio4_irqs,
2251 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2252 .main_clk = "gpio4_ick",
2253 .opt_clks = gpio4_opt_clks,
2254 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2258 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2259 .module_offs = OMAP3430_PER_MOD,
2261 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2264 .slaves = omap3xxx_gpio4_slaves,
2265 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2266 .class = &omap3xxx_gpio_hwmod_class,
2267 .dev_attr = &gpio_dev_attr,
2268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2272 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2273 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2276 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2277 { .role = "dbclk", .clk = "gpio5_dbck", },
2280 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2281 &omap3xxx_l4_per__gpio5,
2284 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2286 .mpu_irqs = omap3xxx_gpio5_irqs,
2287 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2288 .main_clk = "gpio5_ick",
2289 .opt_clks = gpio5_opt_clks,
2290 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2294 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2295 .module_offs = OMAP3430_PER_MOD,
2297 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2300 .slaves = omap3xxx_gpio5_slaves,
2301 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2302 .class = &omap3xxx_gpio_hwmod_class,
2303 .dev_attr = &gpio_dev_attr,
2304 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2308 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2309 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2312 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2313 { .role = "dbclk", .clk = "gpio6_dbck", },
2316 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2317 &omap3xxx_l4_per__gpio6,
2320 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2322 .mpu_irqs = omap3xxx_gpio6_irqs,
2323 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2324 .main_clk = "gpio6_ick",
2325 .opt_clks = gpio6_opt_clks,
2326 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2330 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2331 .module_offs = OMAP3430_PER_MOD,
2333 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2336 .slaves = omap3xxx_gpio6_slaves,
2337 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2338 .class = &omap3xxx_gpio_hwmod_class,
2339 .dev_attr = &gpio_dev_attr,
2340 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2343 /* dma_system -> L3 */
2344 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2345 .master = &omap3xxx_dma_system_hwmod,
2346 .slave = &omap3xxx_l3_main_hwmod,
2347 .clk = "core_l3_ick",
2348 .user = OCP_USER_MPU | OCP_USER_SDMA,
2351 /* dma attributes */
2352 static struct omap_dma_dev_attr dma_dev_attr = {
2353 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2354 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2358 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2360 .sysc_offs = 0x002c,
2361 .syss_offs = 0x0028,
2362 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2363 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2364 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2365 SYSS_HAS_RESET_STATUS),
2366 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2367 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2368 .sysc_fields = &omap_hwmod_sysc_type1,
2371 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2373 .sysc = &omap3xxx_dma_sysc,
2377 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2378 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2379 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2380 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2381 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2384 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2386 .pa_start = 0x48056000,
2387 .pa_end = 0x4a0560ff,
2388 .flags = ADDR_TYPE_RT
2392 /* dma_system master ports */
2393 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2394 &omap3xxx_dma_system__l3,
2397 /* l4_cfg -> dma_system */
2398 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2399 .master = &omap3xxx_l4_core_hwmod,
2400 .slave = &omap3xxx_dma_system_hwmod,
2401 .clk = "core_l4_ick",
2402 .addr = omap3xxx_dma_system_addrs,
2403 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2404 .user = OCP_USER_MPU | OCP_USER_SDMA,
2407 /* dma_system slave ports */
2408 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2409 &omap3xxx_l4_core__dma_system,
2412 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2414 .class = &omap3xxx_dma_hwmod_class,
2415 .mpu_irqs = omap3xxx_dma_system_irqs,
2416 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2417 .main_clk = "core_l3_ick",
2420 .module_offs = CORE_MOD,
2422 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2424 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2427 .slaves = omap3xxx_dma_system_slaves,
2428 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2429 .masters = omap3xxx_dma_system_masters,
2430 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2431 .dev_attr = &dma_dev_attr,
2432 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2433 .flags = HWMOD_NO_IDLEST,
2438 * multi channel buffered serial port controller
2441 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2442 .sysc_offs = 0x008c,
2443 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2444 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2445 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2446 .sysc_fields = &omap_hwmod_sysc_type1,
2450 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2452 .sysc = &omap3xxx_mcbsp_sysc,
2453 .rev = MCBSP_CONFIG_TYPE3,
2457 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2458 { .name = "irq", .irq = 16 },
2459 { .name = "tx", .irq = 59 },
2460 { .name = "rx", .irq = 60 },
2463 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2464 { .name = "rx", .dma_req = 32 },
2465 { .name = "tx", .dma_req = 31 },
2468 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2471 .pa_start = 0x48074000,
2472 .pa_end = 0x480740ff,
2473 .flags = ADDR_TYPE_RT
2477 /* l4_core -> mcbsp1 */
2478 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2479 .master = &omap3xxx_l4_core_hwmod,
2480 .slave = &omap3xxx_mcbsp1_hwmod,
2481 .clk = "mcbsp1_ick",
2482 .addr = omap3xxx_mcbsp1_addrs,
2483 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2487 /* mcbsp1 slave ports */
2488 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2489 &omap3xxx_l4_core__mcbsp1,
2492 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2494 .class = &omap3xxx_mcbsp_hwmod_class,
2495 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2496 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2497 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2498 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2499 .main_clk = "mcbsp1_fck",
2503 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2504 .module_offs = CORE_MOD,
2506 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2509 .slaves = omap3xxx_mcbsp1_slaves,
2510 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2511 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2515 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2516 { .name = "irq", .irq = 17 },
2517 { .name = "tx", .irq = 62 },
2518 { .name = "rx", .irq = 63 },
2521 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2522 { .name = "rx", .dma_req = 34 },
2523 { .name = "tx", .dma_req = 33 },
2526 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2529 .pa_start = 0x49022000,
2530 .pa_end = 0x490220ff,
2531 .flags = ADDR_TYPE_RT
2535 /* l4_per -> mcbsp2 */
2536 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2537 .master = &omap3xxx_l4_per_hwmod,
2538 .slave = &omap3xxx_mcbsp2_hwmod,
2539 .clk = "mcbsp2_ick",
2540 .addr = omap3xxx_mcbsp2_addrs,
2541 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2542 .user = OCP_USER_MPU | OCP_USER_SDMA,
2545 /* mcbsp2 slave ports */
2546 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2547 &omap3xxx_l4_per__mcbsp2,
2550 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2551 .sidetone = "mcbsp2_sidetone",
2554 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2556 .class = &omap3xxx_mcbsp_hwmod_class,
2557 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2558 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2559 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2560 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2561 .main_clk = "mcbsp2_fck",
2565 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2566 .module_offs = OMAP3430_PER_MOD,
2568 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2571 .slaves = omap3xxx_mcbsp2_slaves,
2572 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2573 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2578 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2579 { .name = "irq", .irq = 22 },
2580 { .name = "tx", .irq = 89 },
2581 { .name = "rx", .irq = 90 },
2584 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2585 { .name = "rx", .dma_req = 18 },
2586 { .name = "tx", .dma_req = 17 },
2589 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2592 .pa_start = 0x49024000,
2593 .pa_end = 0x490240ff,
2594 .flags = ADDR_TYPE_RT
2598 /* l4_per -> mcbsp3 */
2599 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2600 .master = &omap3xxx_l4_per_hwmod,
2601 .slave = &omap3xxx_mcbsp3_hwmod,
2602 .clk = "mcbsp3_ick",
2603 .addr = omap3xxx_mcbsp3_addrs,
2604 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2605 .user = OCP_USER_MPU | OCP_USER_SDMA,
2608 /* mcbsp3 slave ports */
2609 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2610 &omap3xxx_l4_per__mcbsp3,
2613 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2614 .sidetone = "mcbsp3_sidetone",
2617 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2619 .class = &omap3xxx_mcbsp_hwmod_class,
2620 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2621 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2622 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2623 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2624 .main_clk = "mcbsp3_fck",
2628 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2629 .module_offs = OMAP3430_PER_MOD,
2631 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2634 .slaves = omap3xxx_mcbsp3_slaves,
2635 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2636 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2637 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2641 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2642 { .name = "irq", .irq = 23 },
2643 { .name = "tx", .irq = 54 },
2644 { .name = "rx", .irq = 55 },
2647 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2648 { .name = "rx", .dma_req = 20 },
2649 { .name = "tx", .dma_req = 19 },
2652 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2655 .pa_start = 0x49026000,
2656 .pa_end = 0x490260ff,
2657 .flags = ADDR_TYPE_RT
2661 /* l4_per -> mcbsp4 */
2662 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2663 .master = &omap3xxx_l4_per_hwmod,
2664 .slave = &omap3xxx_mcbsp4_hwmod,
2665 .clk = "mcbsp4_ick",
2666 .addr = omap3xxx_mcbsp4_addrs,
2667 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2668 .user = OCP_USER_MPU | OCP_USER_SDMA,
2671 /* mcbsp4 slave ports */
2672 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2673 &omap3xxx_l4_per__mcbsp4,
2676 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2678 .class = &omap3xxx_mcbsp_hwmod_class,
2679 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2680 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2681 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2682 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2683 .main_clk = "mcbsp4_fck",
2687 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2688 .module_offs = OMAP3430_PER_MOD,
2690 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2693 .slaves = omap3xxx_mcbsp4_slaves,
2694 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2695 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2699 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2700 { .name = "irq", .irq = 27 },
2701 { .name = "tx", .irq = 81 },
2702 { .name = "rx", .irq = 82 },
2705 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2706 { .name = "rx", .dma_req = 22 },
2707 { .name = "tx", .dma_req = 21 },
2710 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2713 .pa_start = 0x48096000,
2714 .pa_end = 0x480960ff,
2715 .flags = ADDR_TYPE_RT
2719 /* l4_core -> mcbsp5 */
2720 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2721 .master = &omap3xxx_l4_core_hwmod,
2722 .slave = &omap3xxx_mcbsp5_hwmod,
2723 .clk = "mcbsp5_ick",
2724 .addr = omap3xxx_mcbsp5_addrs,
2725 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2726 .user = OCP_USER_MPU | OCP_USER_SDMA,
2729 /* mcbsp5 slave ports */
2730 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2731 &omap3xxx_l4_core__mcbsp5,
2734 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2736 .class = &omap3xxx_mcbsp_hwmod_class,
2737 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2738 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2739 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2740 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2741 .main_clk = "mcbsp5_fck",
2745 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2746 .module_offs = CORE_MOD,
2748 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2751 .slaves = omap3xxx_mcbsp5_slaves,
2752 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2753 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2755 /* 'mcbsp sidetone' class */
2757 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2758 .sysc_offs = 0x0010,
2759 .sysc_flags = SYSC_HAS_AUTOIDLE,
2760 .sysc_fields = &omap_hwmod_sysc_type1,
2763 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2764 .name = "mcbsp_sidetone",
2765 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2768 /* mcbsp2_sidetone */
2769 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2770 { .name = "irq", .irq = 4 },
2773 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2776 .pa_start = 0x49028000,
2777 .pa_end = 0x490280ff,
2778 .flags = ADDR_TYPE_RT
2782 /* l4_per -> mcbsp2_sidetone */
2783 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2784 .master = &omap3xxx_l4_per_hwmod,
2785 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2786 .clk = "mcbsp2_ick",
2787 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2788 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2789 .user = OCP_USER_MPU,
2792 /* mcbsp2_sidetone slave ports */
2793 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2794 &omap3xxx_l4_per__mcbsp2_sidetone,
2797 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2798 .name = "mcbsp2_sidetone",
2799 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2800 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2801 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2802 .main_clk = "mcbsp2_fck",
2806 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2807 .module_offs = OMAP3430_PER_MOD,
2809 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2812 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2813 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2814 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2817 /* mcbsp3_sidetone */
2818 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2819 { .name = "irq", .irq = 5 },
2822 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2825 .pa_start = 0x4902A000,
2826 .pa_end = 0x4902A0ff,
2827 .flags = ADDR_TYPE_RT
2831 /* l4_per -> mcbsp3_sidetone */
2832 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2833 .master = &omap3xxx_l4_per_hwmod,
2834 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2835 .clk = "mcbsp3_ick",
2836 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2837 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2838 .user = OCP_USER_MPU,
2841 /* mcbsp3_sidetone slave ports */
2842 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2843 &omap3xxx_l4_per__mcbsp3_sidetone,
2846 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2847 .name = "mcbsp3_sidetone",
2848 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2849 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2850 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2851 .main_clk = "mcbsp3_fck",
2855 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2856 .module_offs = OMAP3430_PER_MOD,
2858 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2861 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2862 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2863 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2868 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2872 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2874 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2875 .clockact = CLOCKACT_TEST_ICLK,
2876 .sysc_fields = &omap34xx_sr_sysc_fields,
2879 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2880 .name = "smartreflex",
2881 .sysc = &omap34xx_sr_sysc,
2885 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2890 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2892 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2893 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2895 .sysc_fields = &omap36xx_sr_sysc_fields,
2898 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2899 .name = "smartreflex",
2900 .sysc = &omap36xx_sr_sysc,
2905 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2906 &omap3_l4_core__sr1,
2909 static struct omap_hwmod omap34xx_sr1_hwmod = {
2910 .name = "sr1_hwmod",
2911 .class = &omap34xx_smartreflex_hwmod_class,
2912 .main_clk = "sr1_fck",
2917 .module_bit = OMAP3430_EN_SR1_SHIFT,
2918 .module_offs = WKUP_MOD,
2920 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2923 .slaves = omap3_sr1_slaves,
2924 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2925 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2926 CHIP_IS_OMAP3430ES3_0 |
2927 CHIP_IS_OMAP3430ES3_1),
2928 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2931 static struct omap_hwmod omap36xx_sr1_hwmod = {
2932 .name = "sr1_hwmod",
2933 .class = &omap36xx_smartreflex_hwmod_class,
2934 .main_clk = "sr1_fck",
2939 .module_bit = OMAP3430_EN_SR1_SHIFT,
2940 .module_offs = WKUP_MOD,
2942 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2945 .slaves = omap3_sr1_slaves,
2946 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2947 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2951 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2952 &omap3_l4_core__sr2,
2955 static struct omap_hwmod omap34xx_sr2_hwmod = {
2956 .name = "sr2_hwmod",
2957 .class = &omap34xx_smartreflex_hwmod_class,
2958 .main_clk = "sr2_fck",
2963 .module_bit = OMAP3430_EN_SR2_SHIFT,
2964 .module_offs = WKUP_MOD,
2966 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2969 .slaves = omap3_sr2_slaves,
2970 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2971 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2972 CHIP_IS_OMAP3430ES3_0 |
2973 CHIP_IS_OMAP3430ES3_1),
2974 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2977 static struct omap_hwmod omap36xx_sr2_hwmod = {
2978 .name = "sr2_hwmod",
2979 .class = &omap36xx_smartreflex_hwmod_class,
2980 .main_clk = "sr2_fck",
2985 .module_bit = OMAP3430_EN_SR2_SHIFT,
2986 .module_offs = WKUP_MOD,
2988 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2991 .slaves = omap3_sr2_slaves,
2992 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2993 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2998 * mailbox module allowing communication between the on-chip processors
2999 * using a queued mailbox-interrupt mechanism.
3002 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3006 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3007 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3009 .sysc_fields = &omap_hwmod_sysc_type1,
3012 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3014 .sysc = &omap3xxx_mailbox_sysc,
3017 static struct omap_hwmod omap3xxx_mailbox_hwmod;
3018 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3022 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3024 .pa_start = 0x48094000,
3025 .pa_end = 0x480941ff,
3026 .flags = ADDR_TYPE_RT,
3030 /* l4_core -> mailbox */
3031 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3032 .master = &omap3xxx_l4_core_hwmod,
3033 .slave = &omap3xxx_mailbox_hwmod,
3034 .addr = omap3xxx_mailbox_addrs,
3035 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3036 .user = OCP_USER_MPU | OCP_USER_SDMA,
3039 /* mailbox slave ports */
3040 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3041 &omap3xxx_l4_core__mailbox,
3044 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3046 .class = &omap3xxx_mailbox_hwmod_class,
3047 .mpu_irqs = omap3xxx_mailbox_irqs,
3048 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3049 .main_clk = "mailboxes_ick",
3053 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3054 .module_offs = CORE_MOD,
3056 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3059 .slaves = omap3xxx_mailbox_slaves,
3060 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3061 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3064 /* l4 core -> mcspi1 interface */
3065 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3067 .pa_start = 0x48098000,
3068 .pa_end = 0x480980ff,
3069 .flags = ADDR_TYPE_RT,
3073 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3074 .master = &omap3xxx_l4_core_hwmod,
3075 .slave = &omap34xx_mcspi1,
3076 .clk = "mcspi1_ick",
3077 .addr = omap34xx_mcspi1_addr_space,
3078 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3079 .user = OCP_USER_MPU | OCP_USER_SDMA,
3082 /* l4 core -> mcspi2 interface */
3083 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3085 .pa_start = 0x4809a000,
3086 .pa_end = 0x4809a0ff,
3087 .flags = ADDR_TYPE_RT,
3091 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3092 .master = &omap3xxx_l4_core_hwmod,
3093 .slave = &omap34xx_mcspi2,
3094 .clk = "mcspi2_ick",
3095 .addr = omap34xx_mcspi2_addr_space,
3096 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3097 .user = OCP_USER_MPU | OCP_USER_SDMA,
3100 /* l4 core -> mcspi3 interface */
3101 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3103 .pa_start = 0x480b8000,
3104 .pa_end = 0x480b80ff,
3105 .flags = ADDR_TYPE_RT,
3109 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3110 .master = &omap3xxx_l4_core_hwmod,
3111 .slave = &omap34xx_mcspi3,
3112 .clk = "mcspi3_ick",
3113 .addr = omap34xx_mcspi3_addr_space,
3114 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3115 .user = OCP_USER_MPU | OCP_USER_SDMA,
3118 /* l4 core -> mcspi4 interface */
3119 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3121 .pa_start = 0x480ba000,
3122 .pa_end = 0x480ba0ff,
3123 .flags = ADDR_TYPE_RT,
3127 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3128 .master = &omap3xxx_l4_core_hwmod,
3129 .slave = &omap34xx_mcspi4,
3130 .clk = "mcspi4_ick",
3131 .addr = omap34xx_mcspi4_addr_space,
3132 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3133 .user = OCP_USER_MPU | OCP_USER_SDMA,
3138 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3142 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3144 .sysc_offs = 0x0010,
3145 .syss_offs = 0x0014,
3146 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3147 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3148 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3149 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3150 .sysc_fields = &omap_hwmod_sysc_type1,
3153 static struct omap_hwmod_class omap34xx_mcspi_class = {
3155 .sysc = &omap34xx_mcspi_sysc,
3156 .rev = OMAP3_MCSPI_REV,
3160 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3161 { .name = "irq", .irq = 65 },
3164 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3165 { .name = "tx0", .dma_req = 35 },
3166 { .name = "rx0", .dma_req = 36 },
3167 { .name = "tx1", .dma_req = 37 },
3168 { .name = "rx1", .dma_req = 38 },
3169 { .name = "tx2", .dma_req = 39 },
3170 { .name = "rx2", .dma_req = 40 },
3171 { .name = "tx3", .dma_req = 41 },
3172 { .name = "rx3", .dma_req = 42 },
3175 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3176 &omap34xx_l4_core__mcspi1,
3179 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3180 .num_chipselect = 4,
3183 static struct omap_hwmod omap34xx_mcspi1 = {
3185 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
3186 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3187 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3188 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3189 .main_clk = "mcspi1_fck",
3192 .module_offs = CORE_MOD,
3194 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3196 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3199 .slaves = omap34xx_mcspi1_slaves,
3200 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3201 .class = &omap34xx_mcspi_class,
3202 .dev_attr = &omap_mcspi1_dev_attr,
3203 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3207 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3208 { .name = "irq", .irq = 66 },
3211 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3212 { .name = "tx0", .dma_req = 43 },
3213 { .name = "rx0", .dma_req = 44 },
3214 { .name = "tx1", .dma_req = 45 },
3215 { .name = "rx1", .dma_req = 46 },
3218 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3219 &omap34xx_l4_core__mcspi2,
3222 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3223 .num_chipselect = 2,
3226 static struct omap_hwmod omap34xx_mcspi2 = {
3228 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
3229 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3230 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3231 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3232 .main_clk = "mcspi2_fck",
3235 .module_offs = CORE_MOD,
3237 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3239 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3242 .slaves = omap34xx_mcspi2_slaves,
3243 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3244 .class = &omap34xx_mcspi_class,
3245 .dev_attr = &omap_mcspi2_dev_attr,
3246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3250 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3251 { .name = "irq", .irq = 91 }, /* 91 */
3254 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3255 { .name = "tx0", .dma_req = 15 },
3256 { .name = "rx0", .dma_req = 16 },
3257 { .name = "tx1", .dma_req = 23 },
3258 { .name = "rx1", .dma_req = 24 },
3261 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3262 &omap34xx_l4_core__mcspi3,
3265 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3266 .num_chipselect = 2,
3269 static struct omap_hwmod omap34xx_mcspi3 = {
3271 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3272 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3273 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3274 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3275 .main_clk = "mcspi3_fck",
3278 .module_offs = CORE_MOD,
3280 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3282 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3285 .slaves = omap34xx_mcspi3_slaves,
3286 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3287 .class = &omap34xx_mcspi_class,
3288 .dev_attr = &omap_mcspi3_dev_attr,
3289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3293 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3294 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3297 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3298 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3299 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3302 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3303 &omap34xx_l4_core__mcspi4,
3306 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3307 .num_chipselect = 1,
3310 static struct omap_hwmod omap34xx_mcspi4 = {
3312 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3313 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3314 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3315 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3316 .main_clk = "mcspi4_fck",
3319 .module_offs = CORE_MOD,
3321 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3323 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3326 .slaves = omap34xx_mcspi4_slaves,
3327 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3328 .class = &omap34xx_mcspi_class,
3329 .dev_attr = &omap_mcspi4_dev_attr,
3330 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3336 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3338 .sysc_offs = 0x0404,
3339 .syss_offs = 0x0408,
3340 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3341 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3343 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3344 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3345 .sysc_fields = &omap_hwmod_sysc_type1,
3348 static struct omap_hwmod_class usbotg_class = {
3350 .sysc = &omap3xxx_usbhsotg_sysc,
3353 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3355 { .name = "mc", .irq = 92 },
3356 { .name = "dma", .irq = 93 },
3359 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3360 .name = "usb_otg_hs",
3361 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3362 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3363 .main_clk = "hsotgusb_ick",
3367 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3368 .module_offs = CORE_MOD,
3370 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3371 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3374 .masters = omap3xxx_usbhsotg_masters,
3375 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3376 .slaves = omap3xxx_usbhsotg_slaves,
3377 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3378 .class = &usbotg_class,
3381 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3382 * broken when autoidle is enabled
3383 * workaround is to disable the autoidle bit at module level.
3385 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3386 | HWMOD_SWSUP_MSTANDBY,
3387 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3391 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3393 { .name = "mc", .irq = 71 },
3396 static struct omap_hwmod_class am35xx_usbotg_class = {
3397 .name = "am35xx_usbotg",
3401 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3402 .name = "am35x_otg_hs",
3403 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3404 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3410 .masters = am35xx_usbhsotg_masters,
3411 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3412 .slaves = am35xx_usbhsotg_slaves,
3413 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3414 .class = &am35xx_usbotg_class,
3415 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3418 /* MMC/SD/SDIO common */
3420 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3424 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3425 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3426 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3427 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3428 .sysc_fields = &omap_hwmod_sysc_type1,
3431 static struct omap_hwmod_class omap34xx_mmc_class = {
3433 .sysc = &omap34xx_mmc_sysc,
3438 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3442 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3443 { .name = "tx", .dma_req = 61, },
3444 { .name = "rx", .dma_req = 62, },
3447 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3448 { .role = "dbck", .clk = "omap_32k_fck", },
3451 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3452 &omap3xxx_l4_core__mmc1,
3455 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3456 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3459 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3461 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3462 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3463 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3464 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3465 .opt_clks = omap34xx_mmc1_opt_clks,
3466 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3467 .main_clk = "mmchs1_fck",
3470 .module_offs = CORE_MOD,
3472 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3474 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3477 .dev_attr = &mmc1_dev_attr,
3478 .slaves = omap3xxx_mmc1_slaves,
3479 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3480 .class = &omap34xx_mmc_class,
3481 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3486 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3487 { .irq = INT_24XX_MMC2_IRQ, },
3490 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3491 { .name = "tx", .dma_req = 47, },
3492 { .name = "rx", .dma_req = 48, },
3495 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3496 { .role = "dbck", .clk = "omap_32k_fck", },
3499 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3500 &omap3xxx_l4_core__mmc2,
3503 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3505 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3506 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3507 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3508 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3509 .opt_clks = omap34xx_mmc2_opt_clks,
3510 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3511 .main_clk = "mmchs2_fck",
3514 .module_offs = CORE_MOD,
3516 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3518 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3521 .slaves = omap3xxx_mmc2_slaves,
3522 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3523 .class = &omap34xx_mmc_class,
3524 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3529 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3533 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3534 { .name = "tx", .dma_req = 77, },
3535 { .name = "rx", .dma_req = 78, },
3538 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3539 { .role = "dbck", .clk = "omap_32k_fck", },
3542 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3543 &omap3xxx_l4_core__mmc3,
3546 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3548 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3549 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3550 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3551 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3552 .opt_clks = omap34xx_mmc3_opt_clks,
3553 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3554 .main_clk = "mmchs3_fck",
3558 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3560 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3563 .slaves = omap3xxx_mmc3_slaves,
3564 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3565 .class = &omap34xx_mmc_class,
3566 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3569 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3570 &omap3xxx_l3_main_hwmod,
3571 &omap3xxx_l4_core_hwmod,
3572 &omap3xxx_l4_per_hwmod,
3573 &omap3xxx_l4_wkup_hwmod,
3574 &omap3xxx_mmc1_hwmod,
3575 &omap3xxx_mmc2_hwmod,
3576 &omap3xxx_mmc3_hwmod,
3577 &omap3xxx_mpu_hwmod,
3578 &omap3xxx_iva_hwmod,
3580 &omap3xxx_timer1_hwmod,
3581 &omap3xxx_timer2_hwmod,
3582 &omap3xxx_timer3_hwmod,
3583 &omap3xxx_timer4_hwmod,
3584 &omap3xxx_timer5_hwmod,
3585 &omap3xxx_timer6_hwmod,
3586 &omap3xxx_timer7_hwmod,
3587 &omap3xxx_timer8_hwmod,
3588 &omap3xxx_timer9_hwmod,
3589 &omap3xxx_timer10_hwmod,
3590 &omap3xxx_timer11_hwmod,
3591 &omap3xxx_timer12_hwmod,
3593 &omap3xxx_wd_timer2_hwmod,
3594 &omap3xxx_uart1_hwmod,
3595 &omap3xxx_uart2_hwmod,
3596 &omap3xxx_uart3_hwmod,
3597 &omap3xxx_uart4_hwmod,
3599 &omap3430es1_dss_core_hwmod,
3600 &omap3xxx_dss_core_hwmod,
3601 &omap3xxx_dss_dispc_hwmod,
3602 &omap3xxx_dss_dsi1_hwmod,
3603 &omap3xxx_dss_rfbi_hwmod,
3604 &omap3xxx_dss_venc_hwmod,
3607 &omap3xxx_i2c1_hwmod,
3608 &omap3xxx_i2c2_hwmod,
3609 &omap3xxx_i2c3_hwmod,
3610 &omap34xx_sr1_hwmod,
3611 &omap34xx_sr2_hwmod,
3612 &omap36xx_sr1_hwmod,
3613 &omap36xx_sr2_hwmod,
3617 &omap3xxx_gpio1_hwmod,
3618 &omap3xxx_gpio2_hwmod,
3619 &omap3xxx_gpio3_hwmod,
3620 &omap3xxx_gpio4_hwmod,
3621 &omap3xxx_gpio5_hwmod,
3622 &omap3xxx_gpio6_hwmod,
3624 /* dma_system class*/
3625 &omap3xxx_dma_system_hwmod,
3628 &omap3xxx_mcbsp1_hwmod,
3629 &omap3xxx_mcbsp2_hwmod,
3630 &omap3xxx_mcbsp3_hwmod,
3631 &omap3xxx_mcbsp4_hwmod,
3632 &omap3xxx_mcbsp5_hwmod,
3633 &omap3xxx_mcbsp2_sidetone_hwmod,
3634 &omap3xxx_mcbsp3_sidetone_hwmod,
3637 &omap3xxx_mailbox_hwmod,
3646 &omap3xxx_usbhsotg_hwmod,
3648 /* usbotg for am35x */
3649 &am35xx_usbhsotg_hwmod,
3654 int __init omap3xxx_hwmod_init(void)
3656 return omap_hwmod_register(omap3xxx_hwmods);