arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22
  23 #include <linux/omap-dma.h>
  24 #include "l3_3xxx.h"
  25 #include "l4_3xxx.h"
  26 #include <linux/platform_data/asoc-ti-mcbsp.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "soc.h"
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "serial.h"
  39
  40 /*
  41  * OMAP3xxx hardware module integration data
  42  *
  43  * All of the data in this section should be autogeneratable from the
  44  * TI hardware database or other technical documentation.  Data that
  45  * is driver-specific or driver-kernel integration-specific belongs
  46  * elsewhere.
  47  */
  48
  49 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /* L3 */
  56 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  57         { .irq = 9 + OMAP_INTC_START, },
  58         { .irq = 10 + OMAP_INTC_START, },
  59         { .irq = -1 },
  60 };
  61
  62 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  63         .name           = "l3_main",
  64         .class          = &l3_hwmod_class,
  65         .mpu_irqs       = omap3xxx_l3_main_irqs,
  66         .flags          = HWMOD_NO_IDLEST,
  67 };
  68
  69 /* L4 CORE */
  70 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  71         .name           = "l4_core",
  72         .class          = &l4_hwmod_class,
  73         .flags          = HWMOD_NO_IDLEST,
  74 };
  75
  76 /* L4 PER */
  77 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  78         .name           = "l4_per",
  79         .class          = &l4_hwmod_class,
  80         .flags          = HWMOD_NO_IDLEST,
  81 };
  82
  83 /* L4 WKUP */
  84 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  85         .name           = "l4_wkup",
  86         .class          = &l4_hwmod_class,
  87         .flags          = HWMOD_NO_IDLEST,
  88 };
  89
  90 /* L4 SEC */
  91 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  92         .name           = "l4_sec",
  93         .class          = &l4_hwmod_class,
  94         .flags          = HWMOD_NO_IDLEST,
  95 };
  96
  97 /* MPU */
  98 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
  99         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 100         { .irq = -1 }
 101 };
 102
 103 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 104         .name           = "mpu",
 105         .mpu_irqs       = omap3xxx_mpu_irqs,
 106         .class          = &mpu_hwmod_class,
 107         .main_clk       = "arm_fck",
 108 };
 109
 110 /* IVA2 (IVA2) */
 111 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 112         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 113         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 114         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 115 };
 116
 117 static struct omap_hwmod omap3xxx_iva_hwmod = {
 118         .name           = "iva",
 119         .class          = &iva_hwmod_class,
 120         .clkdm_name     = "iva2_clkdm",
 121         .rst_lines      = omap3xxx_iva_resets,
 122         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 123         .main_clk       = "iva2_ck",
 124         .prcm = {
 125                 .omap2 = {
 126                         .module_offs = OMAP3430_IVA2_MOD,
 127                         .prcm_reg_id = 1,
 128                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 129                         .idlest_reg_id = 1,
 130                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 131                 }
 132         },
 133 };
 134
 135 /*
 136  * 'debugss' class
 137  * debug and emulation sub system
 138  */
 139
 140 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 141         .name   = "debugss",
 142 };
 143
 144 /* debugss */
 145 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 146         .name           = "debugss",
 147         .class          = &omap3xxx_debugss_hwmod_class,
 148         .clkdm_name     = "emu_clkdm",
 149         .main_clk       = "emu_src_ck",
 150         .flags          = HWMOD_NO_IDLEST,
 151 };
 152
 153 /* timer class */
 154 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 155         .rev_offs       = 0x0000,
 156         .sysc_offs      = 0x0010,
 157         .syss_offs      = 0x0014,
 158         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 159                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 160                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 161                            SYSS_HAS_RESET_STATUS),
 162         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 163         .clockact       = CLOCKACT_TEST_ICLK,
 164         .sysc_fields    = &omap_hwmod_sysc_type1,
 165 };
 166
 167 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 168         .name = "timer",
 169         .sysc = &omap3xxx_timer_sysc,
 170 };
 171
 172 /* secure timers dev attribute */
 173 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 174         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 175 };
 176
 177 /* always-on timers dev attribute */
 178 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 179         .timer_capability       = OMAP_TIMER_ALWON,
 180 };
 181
 182 /* pwm timers dev attribute */
 183 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 184         .timer_capability       = OMAP_TIMER_HAS_PWM,
 185 };
 186
 187 /* timers with DSP interrupt dev attribute */
 188 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 189         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 190 };
 191
 192 /* pwm timers with DSP interrupt dev attribute */
 193 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 194         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 195 };
 196
 197 /* timer1 */
 198 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 199         .name           = "timer1",
 200         .mpu_irqs       = omap2_timer1_mpu_irqs,
 201         .main_clk       = "gpt1_fck",
 202         .prcm           = {
 203                 .omap2 = {
 204                         .prcm_reg_id = 1,
 205                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 206                         .module_offs = WKUP_MOD,
 207                         .idlest_reg_id = 1,
 208                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 209                 },
 210         },
 211         .dev_attr       = &capability_alwon_dev_attr,
 212         .class          = &omap3xxx_timer_hwmod_class,
 213         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 214 };
 215
 216 /* timer2 */
 217 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 218         .name           = "timer2",
 219         .mpu_irqs       = omap2_timer2_mpu_irqs,
 220         .main_clk       = "gpt2_fck",
 221         .prcm           = {
 222                 .omap2 = {
 223                         .prcm_reg_id = 1,
 224                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 225                         .module_offs = OMAP3430_PER_MOD,
 226                         .idlest_reg_id = 1,
 227                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 228                 },
 229         },
 230         .class          = &omap3xxx_timer_hwmod_class,
 231         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 232 };
 233
 234 /* timer3 */
 235 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 236         .name           = "timer3",
 237         .mpu_irqs       = omap2_timer3_mpu_irqs,
 238         .main_clk       = "gpt3_fck",
 239         .prcm           = {
 240                 .omap2 = {
 241                         .prcm_reg_id = 1,
 242                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 243                         .module_offs = OMAP3430_PER_MOD,
 244                         .idlest_reg_id = 1,
 245                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 246                 },
 247         },
 248         .class          = &omap3xxx_timer_hwmod_class,
 249         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 250 };
 251
 252 /* timer4 */
 253 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 254         .name           = "timer4",
 255         .mpu_irqs       = omap2_timer4_mpu_irqs,
 256         .main_clk       = "gpt4_fck",
 257         .prcm           = {
 258                 .omap2 = {
 259                         .prcm_reg_id = 1,
 260                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 261                         .module_offs = OMAP3430_PER_MOD,
 262                         .idlest_reg_id = 1,
 263                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 264                 },
 265         },
 266         .class          = &omap3xxx_timer_hwmod_class,
 267         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 268 };
 269
 270 /* timer5 */
 271 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 272         .name           = "timer5",
 273         .mpu_irqs       = omap2_timer5_mpu_irqs,
 274         .main_clk       = "gpt5_fck",
 275         .prcm           = {
 276                 .omap2 = {
 277                         .prcm_reg_id = 1,
 278                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 279                         .module_offs = OMAP3430_PER_MOD,
 280                         .idlest_reg_id = 1,
 281                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 282                 },
 283         },
 284         .dev_attr       = &capability_dsp_dev_attr,
 285         .class          = &omap3xxx_timer_hwmod_class,
 286         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 287 };
 288
 289 /* timer6 */
 290 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 291         .name           = "timer6",
 292         .mpu_irqs       = omap2_timer6_mpu_irqs,
 293         .main_clk       = "gpt6_fck",
 294         .prcm           = {
 295                 .omap2 = {
 296                         .prcm_reg_id = 1,
 297                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 298                         .module_offs = OMAP3430_PER_MOD,
 299                         .idlest_reg_id = 1,
 300                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 301                 },
 302         },
 303         .dev_attr       = &capability_dsp_dev_attr,
 304         .class          = &omap3xxx_timer_hwmod_class,
 305         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 306 };
 307
 308 /* timer7 */
 309 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 310         .name           = "timer7",
 311         .mpu_irqs       = omap2_timer7_mpu_irqs,
 312         .main_clk       = "gpt7_fck",
 313         .prcm           = {
 314                 .omap2 = {
 315                         .prcm_reg_id = 1,
 316                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 317                         .module_offs = OMAP3430_PER_MOD,
 318                         .idlest_reg_id = 1,
 319                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 320                 },
 321         },
 322         .dev_attr       = &capability_dsp_dev_attr,
 323         .class          = &omap3xxx_timer_hwmod_class,
 324         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 325 };
 326
 327 /* timer8 */
 328 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 329         .name           = "timer8",
 330         .mpu_irqs       = omap2_timer8_mpu_irqs,
 331         .main_clk       = "gpt8_fck",
 332         .prcm           = {
 333                 .omap2 = {
 334                         .prcm_reg_id = 1,
 335                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 336                         .module_offs = OMAP3430_PER_MOD,
 337                         .idlest_reg_id = 1,
 338                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 339                 },
 340         },
 341         .dev_attr       = &capability_dsp_pwm_dev_attr,
 342         .class          = &omap3xxx_timer_hwmod_class,
 343         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 344 };
 345
 346 /* timer9 */
 347 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 348         .name           = "timer9",
 349         .mpu_irqs       = omap2_timer9_mpu_irqs,
 350         .main_clk       = "gpt9_fck",
 351         .prcm           = {
 352                 .omap2 = {
 353                         .prcm_reg_id = 1,
 354                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 355                         .module_offs = OMAP3430_PER_MOD,
 356                         .idlest_reg_id = 1,
 357                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 358                 },
 359         },
 360         .dev_attr       = &capability_pwm_dev_attr,
 361         .class          = &omap3xxx_timer_hwmod_class,
 362         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 363 };
 364
 365 /* timer10 */
 366 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 367         .name           = "timer10",
 368         .mpu_irqs       = omap2_timer10_mpu_irqs,
 369         .main_clk       = "gpt10_fck",
 370         .prcm           = {
 371                 .omap2 = {
 372                         .prcm_reg_id = 1,
 373                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 374                         .module_offs = CORE_MOD,
 375                         .idlest_reg_id = 1,
 376                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 377                 },
 378         },
 379         .dev_attr       = &capability_pwm_dev_attr,
 380         .class          = &omap3xxx_timer_hwmod_class,
 381         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 382 };
 383
 384 /* timer11 */
 385 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 386         .name           = "timer11",
 387         .mpu_irqs       = omap2_timer11_mpu_irqs,
 388         .main_clk       = "gpt11_fck",
 389         .prcm           = {
 390                 .omap2 = {
 391                         .prcm_reg_id = 1,
 392                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 393                         .module_offs = CORE_MOD,
 394                         .idlest_reg_id = 1,
 395                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 396                 },
 397         },
 398         .dev_attr       = &capability_pwm_dev_attr,
 399         .class          = &omap3xxx_timer_hwmod_class,
 400         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 401 };
 402
 403 /* timer12 */
 404 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 405         { .irq = 95 + OMAP_INTC_START, },
 406         { .irq = -1 },
 407 };
 408
 409 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 410         .name           = "timer12",
 411         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 412         .main_clk       = "gpt12_fck",
 413         .prcm           = {
 414                 .omap2 = {
 415                         .prcm_reg_id = 1,
 416                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 417                         .module_offs = WKUP_MOD,
 418                         .idlest_reg_id = 1,
 419                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 420                 },
 421         },
 422         .dev_attr       = &capability_secure_dev_attr,
 423         .class          = &omap3xxx_timer_hwmod_class,
 424         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 425 };
 426
 427 /*
 428  * 'wd_timer' class
 429  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 430  * overflow condition
 431  */
 432
 433 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 434         .rev_offs       = 0x0000,
 435         .sysc_offs      = 0x0010,
 436         .syss_offs      = 0x0014,
 437         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 438                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 439                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 440                            SYSS_HAS_RESET_STATUS),
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 442         .sysc_fields    = &omap_hwmod_sysc_type1,
 443 };
 444
 445 /* I2C common */
 446 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 447         .rev_offs       = 0x00,
 448         .sysc_offs      = 0x20,
 449         .syss_offs      = 0x10,
 450         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 451                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 452                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 453         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 454         .clockact       = CLOCKACT_TEST_ICLK,
 455         .sysc_fields    = &omap_hwmod_sysc_type1,
 456 };
 457
 458 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 459         .name           = "wd_timer",
 460         .sysc           = &omap3xxx_wd_timer_sysc,
 461         .pre_shutdown   = &omap2_wd_timer_disable,
 462         .reset          = &omap2_wd_timer_reset,
 463 };
 464
 465 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 466         .name           = "wd_timer2",
 467         .class          = &omap3xxx_wd_timer_hwmod_class,
 468         .main_clk       = "wdt2_fck",
 469         .prcm           = {
 470                 .omap2 = {
 471                         .prcm_reg_id = 1,
 472                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 473                         .module_offs = WKUP_MOD,
 474                         .idlest_reg_id = 1,
 475                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 476                 },
 477         },
 478         /*
 479          * XXX: Use software supervised mode, HW supervised smartidle seems to
 480          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 481          */
 482         .flags          = HWMOD_SWSUP_SIDLE,
 483 };
 484
 485 /* UART1 */
 486 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 487         .name           = "uart1",
 488         .mpu_irqs       = omap2_uart1_mpu_irqs,
 489         .sdma_reqs      = omap2_uart1_sdma_reqs,
 490         .main_clk       = "uart1_fck",
 491         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 492         .prcm           = {
 493                 .omap2 = {
 494                         .module_offs = CORE_MOD,
 495                         .prcm_reg_id = 1,
 496                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 497                         .idlest_reg_id = 1,
 498                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 499                 },
 500         },
 501         .class          = &omap2_uart_class,
 502 };
 503
 504 /* UART2 */
 505 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 506         .name           = "uart2",
 507         .mpu_irqs       = omap2_uart2_mpu_irqs,
 508         .sdma_reqs      = omap2_uart2_sdma_reqs,
 509         .main_clk       = "uart2_fck",
 510         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 511         .prcm           = {
 512                 .omap2 = {
 513                         .module_offs = CORE_MOD,
 514                         .prcm_reg_id = 1,
 515                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 516                         .idlest_reg_id = 1,
 517                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 518                 },
 519         },
 520         .class          = &omap2_uart_class,
 521 };
 522
 523 /* UART3 */
 524 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 525         .name           = "uart3",
 526         .mpu_irqs       = omap2_uart3_mpu_irqs,
 527         .sdma_reqs      = omap2_uart3_sdma_reqs,
 528         .main_clk       = "uart3_fck",
 529         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 530                                 HWMOD_SWSUP_SIDLE,
 531         .prcm           = {
 532                 .omap2 = {
 533                         .module_offs = OMAP3430_PER_MOD,
 534                         .prcm_reg_id = 1,
 535                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 536                         .idlest_reg_id = 1,
 537                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 538                 },
 539         },
 540         .class          = &omap2_uart_class,
 541 };
 542
 543 /* UART4 */
 544 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 545         { .irq = 80 + OMAP_INTC_START, },
 546         { .irq = -1 },
 547 };
 548
 549 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 550         { .name = "rx", .dma_req = 82, },
 551         { .name = "tx", .dma_req = 81, },
 552         { .dma_req = -1 }
 553 };
 554
 555 static struct omap_hwmod omap36xx_uart4_hwmod = {
 556         .name           = "uart4",
 557         .mpu_irqs       = uart4_mpu_irqs,
 558         .sdma_reqs      = uart4_sdma_reqs,
 559         .main_clk       = "uart4_fck",
 560         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 561         .prcm           = {
 562                 .omap2 = {
 563                         .module_offs = OMAP3430_PER_MOD,
 564                         .prcm_reg_id = 1,
 565                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 566                         .idlest_reg_id = 1,
 567                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 568                 },
 569         },
 570         .class          = &omap2_uart_class,
 571 };
 572
 573 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 574         { .irq = 84 + OMAP_INTC_START, },
 575         { .irq = -1 },
 576 };
 577
 578 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 579         { .name = "rx", .dma_req = 55, },
 580         { .name = "tx", .dma_req = 54, },
 581         { .dma_req = -1 }
 582 };
 583
 584 /*
 585  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 586  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 587  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 588  * should not be needed.  The functional clock structure of the AM35xx
 589  * UART4 is extremely unclear and opaque; it is unclear what the role
 590  * of uart1/2_fck is for the UART4.  Any clarification from either
 591  * empirical testing or the AM3505/3517 hardware designers would be
 592  * most welcome.
 593  */
 594 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 595         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 596 };
 597
 598 static struct omap_hwmod am35xx_uart4_hwmod = {
 599         .name           = "uart4",
 600         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 601         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 602         .main_clk       = "uart4_fck",
 603         .prcm           = {
 604                 .omap2 = {
 605                         .module_offs = CORE_MOD,
 606                         .prcm_reg_id = 1,
 607                         .module_bit = AM35XX_EN_UART4_SHIFT,
 608                         .idlest_reg_id = 1,
 609                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 610                 },
 611         },
 612         .opt_clks       = am35xx_uart4_opt_clks,
 613         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 614         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 615         .class          = &omap2_uart_class,
 616 };
 617
 618 static struct omap_hwmod_class i2c_class = {
 619         .name   = "i2c",
 620         .sysc   = &i2c_sysc,
 621         .rev    = OMAP_I2C_IP_VERSION_1,
 622         .reset  = &omap_i2c_reset,
 623 };
 624
 625 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 626         { .name = "dispc", .dma_req = 5 },
 627         { .name = "dsi1", .dma_req = 74 },
 628         { .dma_req = -1 }
 629 };
 630
 631 /* dss */
 632 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 633         /*
 634          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 635          * driver does not use these clocks.
 636          */
 637         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 638         { .role = "tv_clk", .clk = "dss_tv_fck" },
 639         /* required only on OMAP3430 */
 640         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 641 };
 642
 643 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 644         .name           = "dss_core",
 645         .class          = &omap2_dss_hwmod_class,
 646         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 647         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 648         .prcm           = {
 649                 .omap2 = {
 650                         .prcm_reg_id = 1,
 651                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 652                         .module_offs = OMAP3430_DSS_MOD,
 653                         .idlest_reg_id = 1,
 654                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 655                 },
 656         },
 657         .opt_clks       = dss_opt_clks,
 658         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 659         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 660 };
 661
 662 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 663         .name           = "dss_core",
 664         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 665         .class          = &omap2_dss_hwmod_class,
 666         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 667         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 668         .prcm           = {
 669                 .omap2 = {
 670                         .prcm_reg_id = 1,
 671                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 672                         .module_offs = OMAP3430_DSS_MOD,
 673                         .idlest_reg_id = 1,
 674                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 675                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 676                 },
 677         },
 678         .opt_clks       = dss_opt_clks,
 679         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 680 };
 681
 682 /*
 683  * 'dispc' class
 684  * display controller
 685  */
 686
 687 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 688         .rev_offs       = 0x0000,
 689         .sysc_offs      = 0x0010,
 690         .syss_offs      = 0x0014,
 691         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 692                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 693                            SYSC_HAS_ENAWAKEUP),
 694         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 695                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 696         .sysc_fields    = &omap_hwmod_sysc_type1,
 697 };
 698
 699 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 700         .name   = "dispc",
 701         .sysc   = &omap3_dispc_sysc,
 702 };
 703
 704 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 705         .name           = "dss_dispc",
 706         .class          = &omap3_dispc_hwmod_class,
 707         .mpu_irqs       = omap2_dispc_irqs,
 708         .main_clk       = "dss1_alwon_fck",
 709         .prcm           = {
 710                 .omap2 = {
 711                         .prcm_reg_id = 1,
 712                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 713                         .module_offs = OMAP3430_DSS_MOD,
 714                 },
 715         },
 716         .flags          = HWMOD_NO_IDLEST,
 717         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 718 };
 719
 720 /*
 721  * 'dsi' class
 722  * display serial interface controller
 723  */
 724
 725 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 726         .name = "dsi",
 727 };
 728
 729 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 730         { .irq = 25 + OMAP_INTC_START, },
 731         { .irq = -1 },
 732 };
 733
 734 /* dss_dsi1 */
 735 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 736         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 737 };
 738
 739 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 740         .name           = "dss_dsi1",
 741         .class          = &omap3xxx_dsi_hwmod_class,
 742         .mpu_irqs       = omap3xxx_dsi1_irqs,
 743         .main_clk       = "dss1_alwon_fck",
 744         .prcm           = {
 745                 .omap2 = {
 746                         .prcm_reg_id = 1,
 747                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 748                         .module_offs = OMAP3430_DSS_MOD,
 749                 },
 750         },
 751         .opt_clks       = dss_dsi1_opt_clks,
 752         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 753         .flags          = HWMOD_NO_IDLEST,
 754 };
 755
 756 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 757         { .role = "ick", .clk = "dss_ick" },
 758 };
 759
 760 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 761         .name           = "dss_rfbi",
 762         .class          = &omap2_rfbi_hwmod_class,
 763         .main_clk       = "dss1_alwon_fck",
 764         .prcm           = {
 765                 .omap2 = {
 766                         .prcm_reg_id = 1,
 767                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 768                         .module_offs = OMAP3430_DSS_MOD,
 769                 },
 770         },
 771         .opt_clks       = dss_rfbi_opt_clks,
 772         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 773         .flags          = HWMOD_NO_IDLEST,
 774 };
 775
 776 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 777         /* required only on OMAP3430 */
 778         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 779 };
 780
 781 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 782         .name           = "dss_venc",
 783         .class          = &omap2_venc_hwmod_class,
 784         .main_clk       = "dss_tv_fck",
 785         .prcm           = {
 786                 .omap2 = {
 787                         .prcm_reg_id = 1,
 788                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 789                         .module_offs = OMAP3430_DSS_MOD,
 790                 },
 791         },
 792         .opt_clks       = dss_venc_opt_clks,
 793         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 794         .flags          = HWMOD_NO_IDLEST,
 795 };
 796
 797 /* I2C1 */
 798 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 799         .fifo_depth     = 8, /* bytes */
 800         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 801 };
 802
 803 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 804         .name           = "i2c1",
 805         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 806         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 807         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 808         .main_clk       = "i2c1_fck",
 809         .prcm           = {
 810                 .omap2 = {
 811                         .module_offs = CORE_MOD,
 812                         .prcm_reg_id = 1,
 813                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 814                         .idlest_reg_id = 1,
 815                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 816                 },
 817         },
 818         .class          = &i2c_class,
 819         .dev_attr       = &i2c1_dev_attr,
 820 };
 821
 822 /* I2C2 */
 823 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 824         .fifo_depth     = 8, /* bytes */
 825         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 826 };
 827
 828 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 829         .name           = "i2c2",
 830         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 831         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 832         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 833         .main_clk       = "i2c2_fck",
 834         .prcm           = {
 835                 .omap2 = {
 836                         .module_offs = CORE_MOD,
 837                         .prcm_reg_id = 1,
 838                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 839                         .idlest_reg_id = 1,
 840                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 841                 },
 842         },
 843         .class          = &i2c_class,
 844         .dev_attr       = &i2c2_dev_attr,
 845 };
 846
 847 /* I2C3 */
 848 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 849         .fifo_depth     = 64, /* bytes */
 850         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 851 };
 852
 853 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 854         { .irq = 61 + OMAP_INTC_START, },
 855         { .irq = -1 },
 856 };
 857
 858 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 859         { .name = "tx", .dma_req = 25 },
 860         { .name = "rx", .dma_req = 26 },
 861         { .dma_req = -1 }
 862 };
 863
 864 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 865         .name           = "i2c3",
 866         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 867         .mpu_irqs       = i2c3_mpu_irqs,
 868         .sdma_reqs      = i2c3_sdma_reqs,
 869         .main_clk       = "i2c3_fck",
 870         .prcm           = {
 871                 .omap2 = {
 872                         .module_offs = CORE_MOD,
 873                         .prcm_reg_id = 1,
 874                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 875                         .idlest_reg_id = 1,
 876                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 877                 },
 878         },
 879         .class          = &i2c_class,
 880         .dev_attr       = &i2c3_dev_attr,
 881 };
 882
 883 /*
 884  * 'gpio' class
 885  * general purpose io module
 886  */
 887
 888 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 889         .rev_offs       = 0x0000,
 890         .sysc_offs      = 0x0010,
 891         .syss_offs      = 0x0014,
 892         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 893                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 894                            SYSS_HAS_RESET_STATUS),
 895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 896         .sysc_fields    = &omap_hwmod_sysc_type1,
 897 };
 898
 899 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 900         .name = "gpio",
 901         .sysc = &omap3xxx_gpio_sysc,
 902         .rev = 1,
 903 };
 904
 905 /* gpio_dev_attr */
 906 static struct omap_gpio_dev_attr gpio_dev_attr = {
 907         .bank_width = 32,
 908         .dbck_flag = true,
 909 };
 910
 911 /* gpio1 */
 912 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 913         { .role = "dbclk", .clk = "gpio1_dbck", },
 914 };
 915
 916 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 917         .name           = "gpio1",
 918         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 919         .mpu_irqs       = omap2_gpio1_irqs,
 920         .main_clk       = "gpio1_ick",
 921         .opt_clks       = gpio1_opt_clks,
 922         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 923         .prcm           = {
 924                 .omap2 = {
 925                         .prcm_reg_id = 1,
 926                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 927                         .module_offs = WKUP_MOD,
 928                         .idlest_reg_id = 1,
 929                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 930                 },
 931         },
 932         .class          = &omap3xxx_gpio_hwmod_class,
 933         .dev_attr       = &gpio_dev_attr,
 934 };
 935
 936 /* gpio2 */
 937 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 938         { .role = "dbclk", .clk = "gpio2_dbck", },
 939 };
 940
 941 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 942         .name           = "gpio2",
 943         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 944         .mpu_irqs       = omap2_gpio2_irqs,
 945         .main_clk       = "gpio2_ick",
 946         .opt_clks       = gpio2_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 948         .prcm           = {
 949                 .omap2 = {
 950                         .prcm_reg_id = 1,
 951                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 952                         .module_offs = OMAP3430_PER_MOD,
 953                         .idlest_reg_id = 1,
 954                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 955                 },
 956         },
 957         .class          = &omap3xxx_gpio_hwmod_class,
 958         .dev_attr       = &gpio_dev_attr,
 959 };
 960
 961 /* gpio3 */
 962 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 963         { .role = "dbclk", .clk = "gpio3_dbck", },
 964 };
 965
 966 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 967         .name           = "gpio3",
 968         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 969         .mpu_irqs       = omap2_gpio3_irqs,
 970         .main_clk       = "gpio3_ick",
 971         .opt_clks       = gpio3_opt_clks,
 972         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 973         .prcm           = {
 974                 .omap2 = {
 975                         .prcm_reg_id = 1,
 976                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 977                         .module_offs = OMAP3430_PER_MOD,
 978                         .idlest_reg_id = 1,
 979                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 980                 },
 981         },
 982         .class          = &omap3xxx_gpio_hwmod_class,
 983         .dev_attr       = &gpio_dev_attr,
 984 };
 985
 986 /* gpio4 */
 987 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 988         { .role = "dbclk", .clk = "gpio4_dbck", },
 989 };
 990
 991 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 992         .name           = "gpio4",
 993         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 994         .mpu_irqs       = omap2_gpio4_irqs,
 995         .main_clk       = "gpio4_ick",
 996         .opt_clks       = gpio4_opt_clks,
 997         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 998         .prcm           = {
 999                 .omap2 = {
1000                         .prcm_reg_id = 1,
1001                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1002                         .module_offs = OMAP3430_PER_MOD,
1003                         .idlest_reg_id = 1,
1004                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1005                 },
1006         },
1007         .class          = &omap3xxx_gpio_hwmod_class,
1008         .dev_attr       = &gpio_dev_attr,
1009 };
1010
1011 /* gpio5 */
1012 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1013         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1014         { .irq = -1 },
1015 };
1016
1017 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1018         { .role = "dbclk", .clk = "gpio5_dbck", },
1019 };
1020
1021 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1022         .name           = "gpio5",
1023         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1024         .mpu_irqs       = omap3xxx_gpio5_irqs,
1025         .main_clk       = "gpio5_ick",
1026         .opt_clks       = gpio5_opt_clks,
1027         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1028         .prcm           = {
1029                 .omap2 = {
1030                         .prcm_reg_id = 1,
1031                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1032                         .module_offs = OMAP3430_PER_MOD,
1033                         .idlest_reg_id = 1,
1034                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1035                 },
1036         },
1037         .class          = &omap3xxx_gpio_hwmod_class,
1038         .dev_attr       = &gpio_dev_attr,
1039 };
1040
1041 /* gpio6 */
1042 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1043         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1044         { .irq = -1 },
1045 };
1046
1047 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1048         { .role = "dbclk", .clk = "gpio6_dbck", },
1049 };
1050
1051 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1052         .name           = "gpio6",
1053         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054         .mpu_irqs       = omap3xxx_gpio6_irqs,
1055         .main_clk       = "gpio6_ick",
1056         .opt_clks       = gpio6_opt_clks,
1057         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1058         .prcm           = {
1059                 .omap2 = {
1060                         .prcm_reg_id = 1,
1061                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1062                         .module_offs = OMAP3430_PER_MOD,
1063                         .idlest_reg_id = 1,
1064                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1065                 },
1066         },
1067         .class          = &omap3xxx_gpio_hwmod_class,
1068         .dev_attr       = &gpio_dev_attr,
1069 };
1070
1071 /* dma attributes */
1072 static struct omap_dma_dev_attr dma_dev_attr = {
1073         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1074                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1075         .lch_count = 32,
1076 };
1077
1078 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1079         .rev_offs       = 0x0000,
1080         .sysc_offs      = 0x002c,
1081         .syss_offs      = 0x0028,
1082         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1083                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1084                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1085                            SYSS_HAS_RESET_STATUS),
1086         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1087                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1088         .sysc_fields    = &omap_hwmod_sysc_type1,
1089 };
1090
1091 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1092         .name = "dma",
1093         .sysc = &omap3xxx_dma_sysc,
1094 };
1095
1096 /* dma_system */
1097 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1098         .name           = "dma",
1099         .class          = &omap3xxx_dma_hwmod_class,
1100         .mpu_irqs       = omap2_dma_system_irqs,
1101         .main_clk       = "core_l3_ick",
1102         .prcm = {
1103                 .omap2 = {
1104                         .module_offs            = CORE_MOD,
1105                         .prcm_reg_id            = 1,
1106                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1107                         .idlest_reg_id          = 1,
1108                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1109                 },
1110         },
1111         .dev_attr       = &dma_dev_attr,
1112         .flags          = HWMOD_NO_IDLEST,
1113 };
1114
1115 /*
1116  * 'mcbsp' class
1117  * multi channel buffered serial port controller
1118  */
1119
1120 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1121         .sysc_offs      = 0x008c,
1122         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1123                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1124         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1125         .sysc_fields    = &omap_hwmod_sysc_type1,
1126         .clockact       = 0x2,
1127 };
1128
1129 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1130         .name = "mcbsp",
1131         .sysc = &omap3xxx_mcbsp_sysc,
1132         .rev  = MCBSP_CONFIG_TYPE3,
1133 };
1134
1135 /* McBSP functional clock mapping */
1136 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1137         { .role = "pad_fck", .clk = "mcbsp_clks" },
1138         { .role = "prcm_fck", .clk = "core_96m_fck" },
1139 };
1140
1141 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1142         { .role = "pad_fck", .clk = "mcbsp_clks" },
1143         { .role = "prcm_fck", .clk = "per_96m_fck" },
1144 };
1145
1146 /* mcbsp1 */
1147 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1148         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1149         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1150         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1151         { .irq = -1 },
1152 };
1153
1154 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1155         .name           = "mcbsp1",
1156         .class          = &omap3xxx_mcbsp_hwmod_class,
1157         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1158         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1159         .main_clk       = "mcbsp1_fck",
1160         .prcm           = {
1161                 .omap2 = {
1162                         .prcm_reg_id = 1,
1163                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1164                         .module_offs = CORE_MOD,
1165                         .idlest_reg_id = 1,
1166                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1167                 },
1168         },
1169         .opt_clks       = mcbsp15_opt_clks,
1170         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1171 };
1172
1173 /* mcbsp2 */
1174 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1175         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1176         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1177         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1178         { .irq = -1 },
1179 };
1180
1181 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1182         .sidetone       = "mcbsp2_sidetone",
1183 };
1184
1185 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1186         .name           = "mcbsp2",
1187         .class          = &omap3xxx_mcbsp_hwmod_class,
1188         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1189         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1190         .main_clk       = "mcbsp2_fck",
1191         .prcm           = {
1192                 .omap2 = {
1193                         .prcm_reg_id = 1,
1194                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1195                         .module_offs = OMAP3430_PER_MOD,
1196                         .idlest_reg_id = 1,
1197                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1198                 },
1199         },
1200         .opt_clks       = mcbsp234_opt_clks,
1201         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1202         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1203 };
1204
1205 /* mcbsp3 */
1206 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1207         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1208         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1209         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1210         { .irq = -1 },
1211 };
1212
1213 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1214         .sidetone       = "mcbsp3_sidetone",
1215 };
1216
1217 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1218         .name           = "mcbsp3",
1219         .class          = &omap3xxx_mcbsp_hwmod_class,
1220         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1221         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1222         .main_clk       = "mcbsp3_fck",
1223         .prcm           = {
1224                 .omap2 = {
1225                         .prcm_reg_id = 1,
1226                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1227                         .module_offs = OMAP3430_PER_MOD,
1228                         .idlest_reg_id = 1,
1229                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1230                 },
1231         },
1232         .opt_clks       = mcbsp234_opt_clks,
1233         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1234         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1235 };
1236
1237 /* mcbsp4 */
1238 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1239         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1240         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1241         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1242         { .irq = -1 },
1243 };
1244
1245 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1246         { .name = "rx", .dma_req = 20 },
1247         { .name = "tx", .dma_req = 19 },
1248         { .dma_req = -1 }
1249 };
1250
1251 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1252         .name           = "mcbsp4",
1253         .class          = &omap3xxx_mcbsp_hwmod_class,
1254         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1255         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1256         .main_clk       = "mcbsp4_fck",
1257         .prcm           = {
1258                 .omap2 = {
1259                         .prcm_reg_id = 1,
1260                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1261                         .module_offs = OMAP3430_PER_MOD,
1262                         .idlest_reg_id = 1,
1263                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1264                 },
1265         },
1266         .opt_clks       = mcbsp234_opt_clks,
1267         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1268 };
1269
1270 /* mcbsp5 */
1271 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1272         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1273         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1274         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1275         { .irq = -1 },
1276 };
1277
1278 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1279         { .name = "rx", .dma_req = 22 },
1280         { .name = "tx", .dma_req = 21 },
1281         { .dma_req = -1 }
1282 };
1283
1284 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1285         .name           = "mcbsp5",
1286         .class          = &omap3xxx_mcbsp_hwmod_class,
1287         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1288         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1289         .main_clk       = "mcbsp5_fck",
1290         .prcm           = {
1291                 .omap2 = {
1292                         .prcm_reg_id = 1,
1293                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1294                         .module_offs = CORE_MOD,
1295                         .idlest_reg_id = 1,
1296                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1297                 },
1298         },
1299         .opt_clks       = mcbsp15_opt_clks,
1300         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1301 };
1302
1303 /* 'mcbsp sidetone' class */
1304 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1305         .sysc_offs      = 0x0010,
1306         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1307         .sysc_fields    = &omap_hwmod_sysc_type1,
1308 };
1309
1310 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1311         .name = "mcbsp_sidetone",
1312         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1313 };
1314
1315 /* mcbsp2_sidetone */
1316 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1317         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1318         { .irq = -1 },
1319 };
1320
1321 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1322         .name           = "mcbsp2_sidetone",
1323         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1324         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1325         .main_clk       = "mcbsp2_ick",
1326         .flags          = HWMOD_NO_IDLEST,
1327 };
1328
1329 /* mcbsp3_sidetone */
1330 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1331         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1332         { .irq = -1 },
1333 };
1334
1335 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1336         .name           = "mcbsp3_sidetone",
1337         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1338         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1339         .main_clk       = "mcbsp3_ick",
1340         .flags          = HWMOD_NO_IDLEST,
1341 };
1342
1343 /* SR common */
1344 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1345         .clkact_shift   = 20,
1346 };
1347
1348 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1349         .sysc_offs      = 0x24,
1350         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1351         .clockact       = CLOCKACT_TEST_ICLK,
1352         .sysc_fields    = &omap34xx_sr_sysc_fields,
1353 };
1354
1355 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1356         .name = "smartreflex",
1357         .sysc = &omap34xx_sr_sysc,
1358         .rev  = 1,
1359 };
1360
1361 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1362         .sidle_shift    = 24,
1363         .enwkup_shift   = 26,
1364 };
1365
1366 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1367         .sysc_offs      = 0x38,
1368         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1369         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1370                         SYSC_NO_CACHE),
1371         .sysc_fields    = &omap36xx_sr_sysc_fields,
1372 };
1373
1374 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1375         .name = "smartreflex",
1376         .sysc = &omap36xx_sr_sysc,
1377         .rev  = 2,
1378 };
1379
1380 /* SR1 */
1381 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1382         .sensor_voltdm_name   = "mpu_iva",
1383 };
1384
1385 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1386         { .irq = 18 + OMAP_INTC_START, },
1387         { .irq = -1 },
1388 };
1389
1390 static struct omap_hwmod omap34xx_sr1_hwmod = {
1391         .name           = "smartreflex_mpu_iva",
1392         .class          = &omap34xx_smartreflex_hwmod_class,
1393         .main_clk       = "sr1_fck",
1394         .prcm           = {
1395                 .omap2 = {
1396                         .prcm_reg_id = 1,
1397                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1398                         .module_offs = WKUP_MOD,
1399                         .idlest_reg_id = 1,
1400                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1401                 },
1402         },
1403         .dev_attr       = &sr1_dev_attr,
1404         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1405         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1406 };
1407
1408 static struct omap_hwmod omap36xx_sr1_hwmod = {
1409         .name           = "smartreflex_mpu_iva",
1410         .class          = &omap36xx_smartreflex_hwmod_class,
1411         .main_clk       = "sr1_fck",
1412         .prcm           = {
1413                 .omap2 = {
1414                         .prcm_reg_id = 1,
1415                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1416                         .module_offs = WKUP_MOD,
1417                         .idlest_reg_id = 1,
1418                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1419                 },
1420         },
1421         .dev_attr       = &sr1_dev_attr,
1422         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1423 };
1424
1425 /* SR2 */
1426 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1427         .sensor_voltdm_name     = "core",
1428 };
1429
1430 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1431         { .irq = 19 + OMAP_INTC_START, },
1432         { .irq = -1 },
1433 };
1434
1435 static struct omap_hwmod omap34xx_sr2_hwmod = {
1436         .name           = "smartreflex_core",
1437         .class          = &omap34xx_smartreflex_hwmod_class,
1438         .main_clk       = "sr2_fck",
1439         .prcm           = {
1440                 .omap2 = {
1441                         .prcm_reg_id = 1,
1442                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1443                         .module_offs = WKUP_MOD,
1444                         .idlest_reg_id = 1,
1445                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1446                 },
1447         },
1448         .dev_attr       = &sr2_dev_attr,
1449         .mpu_irqs       = omap3_smartreflex_core_irqs,
1450         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1451 };
1452
1453 static struct omap_hwmod omap36xx_sr2_hwmod = {
1454         .name           = "smartreflex_core",
1455         .class          = &omap36xx_smartreflex_hwmod_class,
1456         .main_clk       = "sr2_fck",
1457         .prcm           = {
1458                 .omap2 = {
1459                         .prcm_reg_id = 1,
1460                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1461                         .module_offs = WKUP_MOD,
1462                         .idlest_reg_id = 1,
1463                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1464                 },
1465         },
1466         .dev_attr       = &sr2_dev_attr,
1467         .mpu_irqs       = omap3_smartreflex_core_irqs,
1468 };
1469
1470 /*
1471  * 'mailbox' class
1472  * mailbox module allowing communication between the on-chip processors
1473  * using a queued mailbox-interrupt mechanism.
1474  */
1475
1476 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1477         .rev_offs       = 0x000,
1478         .sysc_offs      = 0x010,
1479         .syss_offs      = 0x014,
1480         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1481                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1482         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1483         .sysc_fields    = &omap_hwmod_sysc_type1,
1484 };
1485
1486 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1487         .name = "mailbox",
1488         .sysc = &omap3xxx_mailbox_sysc,
1489 };
1490
1491 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1492         .name           = "mailbox",
1493         .class          = &omap3xxx_mailbox_hwmod_class,
1494         .main_clk       = "mailboxes_ick",
1495         .prcm           = {
1496                 .omap2 = {
1497                         .prcm_reg_id = 1,
1498                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1499                         .module_offs = CORE_MOD,
1500                         .idlest_reg_id = 1,
1501                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1502                 },
1503         },
1504 };
1505
1506 /*
1507  * 'mcspi' class
1508  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1509  * bus
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1513         .rev_offs       = 0x0000,
1514         .sysc_offs      = 0x0010,
1515         .syss_offs      = 0x0014,
1516         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1517                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1518                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1519         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class omap34xx_mcspi_class = {
1524         .name = "mcspi",
1525         .sysc = &omap34xx_mcspi_sysc,
1526         .rev = OMAP3_MCSPI_REV,
1527 };
1528
1529 /* mcspi1 */
1530 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1531         .num_chipselect = 4,
1532 };
1533
1534 static struct omap_hwmod omap34xx_mcspi1 = {
1535         .name           = "mcspi1",
1536         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1537         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1538         .main_clk       = "mcspi1_fck",
1539         .prcm           = {
1540                 .omap2 = {
1541                         .module_offs = CORE_MOD,
1542                         .prcm_reg_id = 1,
1543                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1544                         .idlest_reg_id = 1,
1545                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1546                 },
1547         },
1548         .class          = &omap34xx_mcspi_class,
1549         .dev_attr       = &omap_mcspi1_dev_attr,
1550 };
1551
1552 /* mcspi2 */
1553 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1554         .num_chipselect = 2,
1555 };
1556
1557 static struct omap_hwmod omap34xx_mcspi2 = {
1558         .name           = "mcspi2",
1559         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1560         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1561         .main_clk       = "mcspi2_fck",
1562         .prcm           = {
1563                 .omap2 = {
1564                         .module_offs = CORE_MOD,
1565                         .prcm_reg_id = 1,
1566                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1567                         .idlest_reg_id = 1,
1568                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1569                 },
1570         },
1571         .class          = &omap34xx_mcspi_class,
1572         .dev_attr       = &omap_mcspi2_dev_attr,
1573 };
1574
1575 /* mcspi3 */
1576 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1577         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1578         { .irq = -1 },
1579 };
1580
1581 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1582         { .name = "tx0", .dma_req = 15 },
1583         { .name = "rx0", .dma_req = 16 },
1584         { .name = "tx1", .dma_req = 23 },
1585         { .name = "rx1", .dma_req = 24 },
1586         { .dma_req = -1 }
1587 };
1588
1589 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1590         .num_chipselect = 2,
1591 };
1592
1593 static struct omap_hwmod omap34xx_mcspi3 = {
1594         .name           = "mcspi3",
1595         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1596         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1597         .main_clk       = "mcspi3_fck",
1598         .prcm           = {
1599                 .omap2 = {
1600                         .module_offs = CORE_MOD,
1601                         .prcm_reg_id = 1,
1602                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1603                         .idlest_reg_id = 1,
1604                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1605                 },
1606         },
1607         .class          = &omap34xx_mcspi_class,
1608         .dev_attr       = &omap_mcspi3_dev_attr,
1609 };
1610
1611 /* mcspi4 */
1612 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1613         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1614         { .irq = -1 },
1615 };
1616
1617 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1618         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1619         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1620         { .dma_req = -1 }
1621 };
1622
1623 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1624         .num_chipselect = 1,
1625 };
1626
1627 static struct omap_hwmod omap34xx_mcspi4 = {
1628         .name           = "mcspi4",
1629         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1630         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1631         .main_clk       = "mcspi4_fck",
1632         .prcm           = {
1633                 .omap2 = {
1634                         .module_offs = CORE_MOD,
1635                         .prcm_reg_id = 1,
1636                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1637                         .idlest_reg_id = 1,
1638                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1639                 },
1640         },
1641         .class          = &omap34xx_mcspi_class,
1642         .dev_attr       = &omap_mcspi4_dev_attr,
1643 };
1644
1645 /* usbhsotg */
1646 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1647         .rev_offs       = 0x0400,
1648         .sysc_offs      = 0x0404,
1649         .syss_offs      = 0x0408,
1650         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1651                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1652                           SYSC_HAS_AUTOIDLE),
1653         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1654                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1655         .sysc_fields    = &omap_hwmod_sysc_type1,
1656 };
1657
1658 static struct omap_hwmod_class usbotg_class = {
1659         .name = "usbotg",
1660         .sysc = &omap3xxx_usbhsotg_sysc,
1661 };
1662
1663 /* usb_otg_hs */
1664 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1665
1666         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1667         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1668         { .irq = -1 },
1669 };
1670
1671 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1672         .name           = "usb_otg_hs",
1673         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1674         .main_clk       = "hsotgusb_ick",
1675         .prcm           = {
1676                 .omap2 = {
1677                         .prcm_reg_id = 1,
1678                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1679                         .module_offs = CORE_MOD,
1680                         .idlest_reg_id = 1,
1681                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1682                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1683                 },
1684         },
1685         .class          = &usbotg_class,
1686
1687         /*
1688          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1689          * broken when autoidle is enabled
1690          * workaround is to disable the autoidle bit at module level.
1691          *
1692          * Enabling the device in any other MIDLEMODE setting but force-idle
1693          * causes core_pwrdm not enter idle states at least on OMAP3630.
1694          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1695          * signal when MIDLEMODE is set to force-idle.
1696          */
1697         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1698                           HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1699 };
1700
1701 /* usb_otg_hs */
1702 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1703         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1704         { .irq = -1 },
1705 };
1706
1707 static struct omap_hwmod_class am35xx_usbotg_class = {
1708         .name = "am35xx_usbotg",
1709 };
1710
1711 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1712         .name           = "am35x_otg_hs",
1713         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1714         .main_clk       = "hsotgusb_fck",
1715         .class          = &am35xx_usbotg_class,
1716         .flags          = HWMOD_NO_IDLEST,
1717 };
1718
1719 /* MMC/SD/SDIO common */
1720 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1721         .rev_offs       = 0x1fc,
1722         .sysc_offs      = 0x10,
1723         .syss_offs      = 0x14,
1724         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1725                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1726                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1727         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1728         .sysc_fields    = &omap_hwmod_sysc_type1,
1729 };
1730
1731 static struct omap_hwmod_class omap34xx_mmc_class = {
1732         .name = "mmc",
1733         .sysc = &omap34xx_mmc_sysc,
1734 };
1735
1736 /* MMC/SD/SDIO1 */
1737
1738 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1739         { .irq = 83 + OMAP_INTC_START, },
1740         { .irq = -1 },
1741 };
1742
1743 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1744         { .name = "tx", .dma_req = 61, },
1745         { .name = "rx", .dma_req = 62, },
1746         { .dma_req = -1 }
1747 };
1748
1749 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1750         { .role = "dbck", .clk = "omap_32k_fck", },
1751 };
1752
1753 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1754         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1755 };
1756
1757 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1758 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1759         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1760                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1761 };
1762
1763 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1764         .name           = "mmc1",
1765         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1766         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1767         .opt_clks       = omap34xx_mmc1_opt_clks,
1768         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1769         .main_clk       = "mmchs1_fck",
1770         .prcm           = {
1771                 .omap2 = {
1772                         .module_offs = CORE_MOD,
1773                         .prcm_reg_id = 1,
1774                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1775                         .idlest_reg_id = 1,
1776                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1777                 },
1778         },
1779         .dev_attr       = &mmc1_pre_es3_dev_attr,
1780         .class          = &omap34xx_mmc_class,
1781 };
1782
1783 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1784         .name           = "mmc1",
1785         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1786         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1787         .opt_clks       = omap34xx_mmc1_opt_clks,
1788         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1789         .main_clk       = "mmchs1_fck",
1790         .prcm           = {
1791                 .omap2 = {
1792                         .module_offs = CORE_MOD,
1793                         .prcm_reg_id = 1,
1794                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1795                         .idlest_reg_id = 1,
1796                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1797                 },
1798         },
1799         .dev_attr       = &mmc1_dev_attr,
1800         .class          = &omap34xx_mmc_class,
1801 };
1802
1803 /* MMC/SD/SDIO2 */
1804
1805 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1806         { .irq = 86 + OMAP_INTC_START, },
1807         { .irq = -1 },
1808 };
1809
1810 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1811         { .name = "tx", .dma_req = 47, },
1812         { .name = "rx", .dma_req = 48, },
1813         { .dma_req = -1 }
1814 };
1815
1816 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1817         { .role = "dbck", .clk = "omap_32k_fck", },
1818 };
1819
1820 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1821 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1822         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1823 };
1824
1825 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1826         .name           = "mmc2",
1827         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1828         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1829         .opt_clks       = omap34xx_mmc2_opt_clks,
1830         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1831         .main_clk       = "mmchs2_fck",
1832         .prcm           = {
1833                 .omap2 = {
1834                         .module_offs = CORE_MOD,
1835                         .prcm_reg_id = 1,
1836                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1837                         .idlest_reg_id = 1,
1838                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1839                 },
1840         },
1841         .dev_attr       = &mmc2_pre_es3_dev_attr,
1842         .class          = &omap34xx_mmc_class,
1843 };
1844
1845 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1846         .name           = "mmc2",
1847         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1848         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1849         .opt_clks       = omap34xx_mmc2_opt_clks,
1850         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1851         .main_clk       = "mmchs2_fck",
1852         .prcm           = {
1853                 .omap2 = {
1854                         .module_offs = CORE_MOD,
1855                         .prcm_reg_id = 1,
1856                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1857                         .idlest_reg_id = 1,
1858                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1859                 },
1860         },
1861         .class          = &omap34xx_mmc_class,
1862 };
1863
1864 /* MMC/SD/SDIO3 */
1865
1866 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1867         { .irq = 94 + OMAP_INTC_START, },
1868         { .irq = -1 },
1869 };
1870
1871 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1872         { .name = "tx", .dma_req = 77, },
1873         { .name = "rx", .dma_req = 78, },
1874         { .dma_req = -1 }
1875 };
1876
1877 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1878         { .role = "dbck", .clk = "omap_32k_fck", },
1879 };
1880
1881 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1882         .name           = "mmc3",
1883         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1884         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1885         .opt_clks       = omap34xx_mmc3_opt_clks,
1886         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1887         .main_clk       = "mmchs3_fck",
1888         .prcm           = {
1889                 .omap2 = {
1890                         .prcm_reg_id = 1,
1891                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1892                         .idlest_reg_id = 1,
1893                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1894                 },
1895         },
1896         .class          = &omap34xx_mmc_class,
1897 };
1898
1899 /*
1900  * 'usb_host_hs' class
1901  * high-speed multi-port usb host controller
1902  */
1903
1904 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1905         .rev_offs       = 0x0000,
1906         .sysc_offs      = 0x0010,
1907         .syss_offs      = 0x0014,
1908         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1909                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1910                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1911                            SYSS_HAS_RESET_STATUS),
1912         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1913                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1914         .sysc_fields    = &omap_hwmod_sysc_type1,
1915 };
1916
1917 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1918         .name = "usb_host_hs",
1919         .sysc = &omap3xxx_usb_host_hs_sysc,
1920 };
1921
1922 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1923         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1924         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1925         { .irq = -1 },
1926 };
1927
1928 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1929         .name           = "usb_host_hs",
1930         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1931         .clkdm_name     = "usbhost_clkdm",
1932         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1933         .main_clk       = "usbhost_48m_fck",
1934         .prcm = {
1935                 .omap2 = {
1936                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1937                         .prcm_reg_id = 1,
1938                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1939                         .idlest_reg_id = 1,
1940                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1941                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1942                 },
1943         },
1944
1945         /*
1946          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1947          * id: i660
1948          *
1949          * Description:
1950          * In the following configuration :
1951          * - USBHOST module is set to smart-idle mode
1952          * - PRCM asserts idle_req to the USBHOST module ( This typically
1953          *   happens when the system is going to a low power mode : all ports
1954          *   have been suspended, the master part of the USBHOST module has
1955          *   entered the standby state, and SW has cut the functional clocks)
1956          * - an USBHOST interrupt occurs before the module is able to answer
1957          *   idle_ack, typically a remote wakeup IRQ.
1958          * Then the USB HOST module will enter a deadlock situation where it
1959          * is no more accessible nor functional.
1960          *
1961          * Workaround:
1962          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1963          */
1964
1965         /*
1966          * Errata: USB host EHCI may stall when entering smart-standby mode
1967          * Id: i571
1968          *
1969          * Description:
1970          * When the USBHOST module is set to smart-standby mode, and when it is
1971          * ready to enter the standby state (i.e. all ports are suspended and
1972          * all attached devices are in suspend mode), then it can wrongly assert
1973          * the Mstandby signal too early while there are still some residual OCP
1974          * transactions ongoing. If this condition occurs, the internal state
1975          * machine may go to an undefined state and the USB link may be stuck
1976          * upon the next resume.
1977          *
1978          * Workaround:
1979          * Don't use smart standby; use only force standby,
1980          * hence HWMOD_SWSUP_MSTANDBY
1981          */
1982
1983         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1984 };
1985
1986 /*
1987  * 'usb_tll_hs' class
1988  * usb_tll_hs module is the adapter on the usb_host_hs ports
1989  */
1990 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1991         .rev_offs       = 0x0000,
1992         .sysc_offs      = 0x0010,
1993         .syss_offs      = 0x0014,
1994         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1995                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1996                            SYSC_HAS_AUTOIDLE),
1997         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1998         .sysc_fields    = &omap_hwmod_sysc_type1,
1999 };
2000
2001 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2002         .name = "usb_tll_hs",
2003         .sysc = &omap3xxx_usb_tll_hs_sysc,
2004 };
2005
2006 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2007         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2008         { .irq = -1 },
2009 };
2010
2011 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2012         .name           = "usb_tll_hs",
2013         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2014         .clkdm_name     = "core_l4_clkdm",
2015         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2016         .main_clk       = "usbtll_fck",
2017         .prcm = {
2018                 .omap2 = {
2019                         .module_offs = CORE_MOD,
2020                         .prcm_reg_id = 3,
2021                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2022                         .idlest_reg_id = 3,
2023                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2024                 },
2025         },
2026 };
2027
2028 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2029         .name           = "hdq1w",
2030         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2031         .main_clk       = "hdq_fck",
2032         .prcm           = {
2033                 .omap2 = {
2034                         .module_offs = CORE_MOD,
2035                         .prcm_reg_id = 1,
2036                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2037                         .idlest_reg_id = 1,
2038                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2039                 },
2040         },
2041         .class          = &omap2_hdq1w_class,
2042 };
2043
2044 /* SAD2D */
2045 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2046         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2047         { .name = "rst_modem_sw", .rst_shift = 1 },
2048 };
2049
2050 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2051         .name                   = "sad2d",
2052 };
2053
2054 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2055         .name           = "sad2d",
2056         .rst_lines      = omap3xxx_sad2d_resets,
2057         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2058         .main_clk       = "sad2d_ick",
2059         .prcm           = {
2060                 .omap2 = {
2061                         .module_offs = CORE_MOD,
2062                         .prcm_reg_id = 1,
2063                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2064                         .idlest_reg_id = 1,
2065                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2066                 },
2067         },
2068         .class          = &omap3xxx_sad2d_class,
2069 };
2070
2071 /*
2072  * '32K sync counter' class
2073  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2074  */
2075 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2076         .rev_offs       = 0x0000,
2077         .sysc_offs      = 0x0004,
2078         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2079         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2080         .sysc_fields    = &omap_hwmod_sysc_type1,
2081 };
2082
2083 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2084         .name   = "counter",
2085         .sysc   = &omap3xxx_counter_sysc,
2086 };
2087
2088 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2089         .name           = "counter_32k",
2090         .class          = &omap3xxx_counter_hwmod_class,
2091         .clkdm_name     = "wkup_clkdm",
2092         .flags          = HWMOD_SWSUP_SIDLE,
2093         .main_clk       = "wkup_32k_fck",
2094         .prcm           = {
2095                 .omap2  = {
2096                         .module_offs = WKUP_MOD,
2097                         .prcm_reg_id = 1,
2098                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2099                         .idlest_reg_id = 1,
2100                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2101                 },
2102         },
2103 };
2104
2105 /*
2106  * 'gpmc' class
2107  * general purpose memory controller
2108  */
2109
2110 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2111         .rev_offs       = 0x0000,
2112         .sysc_offs      = 0x0010,
2113         .syss_offs      = 0x0014,
2114         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2115                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2116         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2117         .sysc_fields    = &omap_hwmod_sysc_type1,
2118 };
2119
2120 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2121         .name   = "gpmc",
2122         .sysc   = &omap3xxx_gpmc_sysc,
2123 };
2124
2125 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2126         { .irq = 20 + OMAP_INTC_START, },
2127         { .irq = -1 }
2128 };
2129
2130 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2131         .name           = "gpmc",
2132         .class          = &omap3xxx_gpmc_hwmod_class,
2133         .clkdm_name     = "core_l3_clkdm",
2134         .mpu_irqs       = omap3xxx_gpmc_irqs,
2135         .main_clk       = "gpmc_fck",
2136         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2137         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
2138 };
2139
2140 /*
2141  * interfaces
2142  */
2143
2144 /* L3 -> L4_CORE interface */
2145 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2146         .master = &omap3xxx_l3_main_hwmod,
2147         .slave  = &omap3xxx_l4_core_hwmod,
2148         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2149 };
2150
2151 /* L3 -> L4_PER interface */
2152 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2153         .master = &omap3xxx_l3_main_hwmod,
2154         .slave  = &omap3xxx_l4_per_hwmod,
2155         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2156 };
2157
2158 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2159         {
2160                 .pa_start       = 0x68000000,
2161                 .pa_end         = 0x6800ffff,
2162                 .flags          = ADDR_TYPE_RT,
2163         },
2164         { }
2165 };
2166
2167 /* MPU -> L3 interface */
2168 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2169         .master   = &omap3xxx_mpu_hwmod,
2170         .slave    = &omap3xxx_l3_main_hwmod,
2171         .addr     = omap3xxx_l3_main_addrs,
2172         .user   = OCP_USER_MPU,
2173 };
2174
2175 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2176         {
2177                 .pa_start       = 0x54000000,
2178                 .pa_end         = 0x547fffff,
2179                 .flags          = ADDR_TYPE_RT,
2180         },
2181         { }
2182 };
2183
2184 /* l3 -> debugss */
2185 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2186         .master         = &omap3xxx_l3_main_hwmod,
2187         .slave          = &omap3xxx_debugss_hwmod,
2188         .addr           = omap3xxx_l4_emu_addrs,
2189         .user           = OCP_USER_MPU,
2190 };
2191
2192 /* DSS -> l3 */
2193 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2194         .master         = &omap3430es1_dss_core_hwmod,
2195         .slave          = &omap3xxx_l3_main_hwmod,
2196         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2197 };
2198
2199 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2200         .master         = &omap3xxx_dss_core_hwmod,
2201         .slave          = &omap3xxx_l3_main_hwmod,
2202         .fw = {
2203                 .omap2 = {
2204                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2205                         .flags  = OMAP_FIREWALL_L3,
2206                 }
2207         },
2208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2209 };
2210
2211 /* l3_core -> usbhsotg interface */
2212 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2213         .master         = &omap3xxx_usbhsotg_hwmod,
2214         .slave          = &omap3xxx_l3_main_hwmod,
2215         .clk            = "core_l3_ick",
2216         .user           = OCP_USER_MPU,
2217 };
2218
2219 /* l3_core -> am35xx_usbhsotg interface */
2220 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2221         .master         = &am35xx_usbhsotg_hwmod,
2222         .slave          = &omap3xxx_l3_main_hwmod,
2223         .clk            = "hsotgusb_ick",
2224         .user           = OCP_USER_MPU,
2225 };
2226
2227 /* l3_core -> sad2d interface */
2228 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2229         .master         = &omap3xxx_sad2d_hwmod,
2230         .slave          = &omap3xxx_l3_main_hwmod,
2231         .clk            = "core_l3_ick",
2232         .user           = OCP_USER_MPU,
2233 };
2234
2235 /* L4_CORE -> L4_WKUP interface */
2236 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2237         .master = &omap3xxx_l4_core_hwmod,
2238         .slave  = &omap3xxx_l4_wkup_hwmod,
2239         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* L4 CORE -> MMC1 interface */
2243 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2244         .master         = &omap3xxx_l4_core_hwmod,
2245         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2246         .clk            = "mmchs1_ick",
2247         .addr           = omap2430_mmc1_addr_space,
2248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2249         .flags          = OMAP_FIREWALL_L4
2250 };
2251
2252 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2253         .master         = &omap3xxx_l4_core_hwmod,
2254         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2255         .clk            = "mmchs1_ick",
2256         .addr           = omap2430_mmc1_addr_space,
2257         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2258         .flags          = OMAP_FIREWALL_L4
2259 };
2260
2261 /* L4 CORE -> MMC2 interface */
2262 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2263         .master         = &omap3xxx_l4_core_hwmod,
2264         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2265         .clk            = "mmchs2_ick",
2266         .addr           = omap2430_mmc2_addr_space,
2267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2268         .flags          = OMAP_FIREWALL_L4
2269 };
2270
2271 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2272         .master         = &omap3xxx_l4_core_hwmod,
2273         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2274         .clk            = "mmchs2_ick",
2275         .addr           = omap2430_mmc2_addr_space,
2276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2277         .flags          = OMAP_FIREWALL_L4
2278 };
2279
2280 /* L4 CORE -> MMC3 interface */
2281 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2282         {
2283                 .pa_start       = 0x480ad000,
2284                 .pa_end         = 0x480ad1ff,
2285                 .flags          = ADDR_TYPE_RT,
2286         },
2287         { }
2288 };
2289
2290 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2291         .master         = &omap3xxx_l4_core_hwmod,
2292         .slave          = &omap3xxx_mmc3_hwmod,
2293         .clk            = "mmchs3_ick",
2294         .addr           = omap3xxx_mmc3_addr_space,
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296         .flags          = OMAP_FIREWALL_L4
2297 };
2298
2299 /* L4 CORE -> UART1 interface */
2300 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2301         {
2302                 .pa_start       = OMAP3_UART1_BASE,
2303                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2304                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2305         },
2306         { }
2307 };
2308
2309 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2310         .master         = &omap3xxx_l4_core_hwmod,
2311         .slave          = &omap3xxx_uart1_hwmod,
2312         .clk            = "uart1_ick",
2313         .addr           = omap3xxx_uart1_addr_space,
2314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2315 };
2316
2317 /* L4 CORE -> UART2 interface */
2318 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2319         {
2320                 .pa_start       = OMAP3_UART2_BASE,
2321                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2322                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2323         },
2324         { }
2325 };
2326
2327 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2328         .master         = &omap3xxx_l4_core_hwmod,
2329         .slave          = &omap3xxx_uart2_hwmod,
2330         .clk            = "uart2_ick",
2331         .addr           = omap3xxx_uart2_addr_space,
2332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2333 };
2334
2335 /* L4 PER -> UART3 interface */
2336 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2337         {
2338                 .pa_start       = OMAP3_UART3_BASE,
2339                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2340                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2341         },
2342         { }
2343 };
2344
2345 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2346         .master         = &omap3xxx_l4_per_hwmod,
2347         .slave          = &omap3xxx_uart3_hwmod,
2348         .clk            = "uart3_ick",
2349         .addr           = omap3xxx_uart3_addr_space,
2350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2351 };
2352
2353 /* L4 PER -> UART4 interface */
2354 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2355         {
2356                 .pa_start       = OMAP3_UART4_BASE,
2357                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2358                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2359         },
2360         { }
2361 };
2362
2363 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2364         .master         = &omap3xxx_l4_per_hwmod,
2365         .slave          = &omap36xx_uart4_hwmod,
2366         .clk            = "uart4_ick",
2367         .addr           = omap36xx_uart4_addr_space,
2368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2369 };
2370
2371 /* AM35xx: L4 CORE -> UART4 interface */
2372 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2373         {
2374                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2375                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2376                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2377         },
2378         { }
2379 };
2380
2381 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2382         .master         = &omap3xxx_l4_core_hwmod,
2383         .slave          = &am35xx_uart4_hwmod,
2384         .clk            = "uart4_ick",
2385         .addr           = am35xx_uart4_addr_space,
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388
2389 /* L4 CORE -> I2C1 interface */
2390 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2391         .master         = &omap3xxx_l4_core_hwmod,
2392         .slave          = &omap3xxx_i2c1_hwmod,
2393         .clk            = "i2c1_ick",
2394         .addr           = omap2_i2c1_addr_space,
2395         .fw = {
2396                 .omap2 = {
2397                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2398                         .l4_prot_group = 7,
2399                         .flags  = OMAP_FIREWALL_L4,
2400                 }
2401         },
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* L4 CORE -> I2C2 interface */
2406 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2407         .master         = &omap3xxx_l4_core_hwmod,
2408         .slave          = &omap3xxx_i2c2_hwmod,
2409         .clk            = "i2c2_ick",
2410         .addr           = omap2_i2c2_addr_space,
2411         .fw = {
2412                 .omap2 = {
2413                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2414                         .l4_prot_group = 7,
2415                         .flags = OMAP_FIREWALL_L4,
2416                 }
2417         },
2418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420
2421 /* L4 CORE -> I2C3 interface */
2422 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2423         {
2424                 .pa_start       = 0x48060000,
2425                 .pa_end         = 0x48060000 + SZ_128 - 1,
2426                 .flags          = ADDR_TYPE_RT,
2427         },
2428         { }
2429 };
2430
2431 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2432         .master         = &omap3xxx_l4_core_hwmod,
2433         .slave          = &omap3xxx_i2c3_hwmod,
2434         .clk            = "i2c3_ick",
2435         .addr           = omap3xxx_i2c3_addr_space,
2436         .fw = {
2437                 .omap2 = {
2438                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2439                         .l4_prot_group = 7,
2440                         .flags = OMAP_FIREWALL_L4,
2441                 }
2442         },
2443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 /* L4 CORE -> SR1 interface */
2447 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2448         {
2449                 .pa_start       = OMAP34XX_SR1_BASE,
2450                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2451                 .flags          = ADDR_TYPE_RT,
2452         },
2453         { }
2454 };
2455
2456 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2457         .master         = &omap3xxx_l4_core_hwmod,
2458         .slave          = &omap34xx_sr1_hwmod,
2459         .clk            = "sr_l4_ick",
2460         .addr           = omap3_sr1_addr_space,
2461         .user           = OCP_USER_MPU,
2462 };
2463
2464 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2465         .master         = &omap3xxx_l4_core_hwmod,
2466         .slave          = &omap36xx_sr1_hwmod,
2467         .clk            = "sr_l4_ick",
2468         .addr           = omap3_sr1_addr_space,
2469         .user           = OCP_USER_MPU,
2470 };
2471
2472 /* L4 CORE -> SR1 interface */
2473 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2474         {
2475                 .pa_start       = OMAP34XX_SR2_BASE,
2476                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2477                 .flags          = ADDR_TYPE_RT,
2478         },
2479         { }
2480 };
2481
2482 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2483         .master         = &omap3xxx_l4_core_hwmod,
2484         .slave          = &omap34xx_sr2_hwmod,
2485         .clk            = "sr_l4_ick",
2486         .addr           = omap3_sr2_addr_space,
2487         .user           = OCP_USER_MPU,
2488 };
2489
2490 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2491         .master         = &omap3xxx_l4_core_hwmod,
2492         .slave          = &omap36xx_sr2_hwmod,
2493         .clk            = "sr_l4_ick",
2494         .addr           = omap3_sr2_addr_space,
2495         .user           = OCP_USER_MPU,
2496 };
2497
2498 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2499         {
2500                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2501                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2502                 .flags          = ADDR_TYPE_RT
2503         },
2504         { }
2505 };
2506
2507 /* l4_core -> usbhsotg  */
2508 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2509         .master         = &omap3xxx_l4_core_hwmod,
2510         .slave          = &omap3xxx_usbhsotg_hwmod,
2511         .clk            = "l4_ick",
2512         .addr           = omap3xxx_usbhsotg_addrs,
2513         .user           = OCP_USER_MPU,
2514 };
2515
2516 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2517         {
2518                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2519                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2520                 .flags          = ADDR_TYPE_RT
2521         },
2522         { }
2523 };
2524
2525 /* l4_core -> usbhsotg  */
2526 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2527         .master         = &omap3xxx_l4_core_hwmod,
2528         .slave          = &am35xx_usbhsotg_hwmod,
2529         .clk            = "hsotgusb_ick",
2530         .addr           = am35xx_usbhsotg_addrs,
2531         .user           = OCP_USER_MPU,
2532 };
2533
2534 /* L4_WKUP -> L4_SEC interface */
2535 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2536         .master = &omap3xxx_l4_wkup_hwmod,
2537         .slave  = &omap3xxx_l4_sec_hwmod,
2538         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2539 };
2540
2541 /* IVA2 <- L3 interface */
2542 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2543         .master         = &omap3xxx_l3_main_hwmod,
2544         .slave          = &omap3xxx_iva_hwmod,
2545         .clk            = "core_l3_ick",
2546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2547 };
2548
2549 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2550         {
2551                 .pa_start       = 0x48318000,
2552                 .pa_end         = 0x48318000 + SZ_1K - 1,
2553                 .flags          = ADDR_TYPE_RT
2554         },
2555         { }
2556 };
2557
2558 /* l4_wkup -> timer1 */
2559 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2560         .master         = &omap3xxx_l4_wkup_hwmod,
2561         .slave          = &omap3xxx_timer1_hwmod,
2562         .clk            = "gpt1_ick",
2563         .addr           = omap3xxx_timer1_addrs,
2564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2565 };
2566
2567 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2568         {
2569                 .pa_start       = 0x49032000,
2570                 .pa_end         = 0x49032000 + SZ_1K - 1,
2571                 .flags          = ADDR_TYPE_RT
2572         },
2573         { }
2574 };
2575
2576 /* l4_per -> timer2 */
2577 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2578         .master         = &omap3xxx_l4_per_hwmod,
2579         .slave          = &omap3xxx_timer2_hwmod,
2580         .clk            = "gpt2_ick",
2581         .addr           = omap3xxx_timer2_addrs,
2582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2583 };
2584
2585 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2586         {
2587                 .pa_start       = 0x49034000,
2588                 .pa_end         = 0x49034000 + SZ_1K - 1,
2589                 .flags          = ADDR_TYPE_RT
2590         },
2591         { }
2592 };
2593
2594 /* l4_per -> timer3 */
2595 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2596         .master         = &omap3xxx_l4_per_hwmod,
2597         .slave          = &omap3xxx_timer3_hwmod,
2598         .clk            = "gpt3_ick",
2599         .addr           = omap3xxx_timer3_addrs,
2600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2601 };
2602
2603 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2604         {
2605                 .pa_start       = 0x49036000,
2606                 .pa_end         = 0x49036000 + SZ_1K - 1,
2607                 .flags          = ADDR_TYPE_RT
2608         },
2609         { }
2610 };
2611
2612 /* l4_per -> timer4 */
2613 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2614         .master         = &omap3xxx_l4_per_hwmod,
2615         .slave          = &omap3xxx_timer4_hwmod,
2616         .clk            = "gpt4_ick",
2617         .addr           = omap3xxx_timer4_addrs,
2618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2619 };
2620
2621 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2622         {
2623                 .pa_start       = 0x49038000,
2624                 .pa_end         = 0x49038000 + SZ_1K - 1,
2625                 .flags          = ADDR_TYPE_RT
2626         },
2627         { }
2628 };
2629
2630 /* l4_per -> timer5 */
2631 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2632         .master         = &omap3xxx_l4_per_hwmod,
2633         .slave          = &omap3xxx_timer5_hwmod,
2634         .clk            = "gpt5_ick",
2635         .addr           = omap3xxx_timer5_addrs,
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2640         {
2641                 .pa_start       = 0x4903A000,
2642                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2643                 .flags          = ADDR_TYPE_RT
2644         },
2645         { }
2646 };
2647
2648 /* l4_per -> timer6 */
2649 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2650         .master         = &omap3xxx_l4_per_hwmod,
2651         .slave          = &omap3xxx_timer6_hwmod,
2652         .clk            = "gpt6_ick",
2653         .addr           = omap3xxx_timer6_addrs,
2654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2655 };
2656
2657 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2658         {
2659                 .pa_start       = 0x4903C000,
2660                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2661                 .flags          = ADDR_TYPE_RT
2662         },
2663         { }
2664 };
2665
2666 /* l4_per -> timer7 */
2667 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2668         .master         = &omap3xxx_l4_per_hwmod,
2669         .slave          = &omap3xxx_timer7_hwmod,
2670         .clk            = "gpt7_ick",
2671         .addr           = omap3xxx_timer7_addrs,
2672         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2673 };
2674
2675 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2676         {
2677                 .pa_start       = 0x4903E000,
2678                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2679                 .flags          = ADDR_TYPE_RT
2680         },
2681         { }
2682 };
2683
2684 /* l4_per -> timer8 */
2685 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2686         .master         = &omap3xxx_l4_per_hwmod,
2687         .slave          = &omap3xxx_timer8_hwmod,
2688         .clk            = "gpt8_ick",
2689         .addr           = omap3xxx_timer8_addrs,
2690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2691 };
2692
2693 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2694         {
2695                 .pa_start       = 0x49040000,
2696                 .pa_end         = 0x49040000 + SZ_1K - 1,
2697                 .flags          = ADDR_TYPE_RT
2698         },
2699         { }
2700 };
2701
2702 /* l4_per -> timer9 */
2703 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2704         .master         = &omap3xxx_l4_per_hwmod,
2705         .slave          = &omap3xxx_timer9_hwmod,
2706         .clk            = "gpt9_ick",
2707         .addr           = omap3xxx_timer9_addrs,
2708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2709 };
2710
2711 /* l4_core -> timer10 */
2712 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2713         .master         = &omap3xxx_l4_core_hwmod,
2714         .slave          = &omap3xxx_timer10_hwmod,
2715         .clk            = "gpt10_ick",
2716         .addr           = omap2_timer10_addrs,
2717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2718 };
2719
2720 /* l4_core -> timer11 */
2721 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2722         .master         = &omap3xxx_l4_core_hwmod,
2723         .slave          = &omap3xxx_timer11_hwmod,
2724         .clk            = "gpt11_ick",
2725         .addr           = omap2_timer11_addrs,
2726         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2727 };
2728
2729 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2730         {
2731                 .pa_start       = 0x48304000,
2732                 .pa_end         = 0x48304000 + SZ_1K - 1,
2733                 .flags          = ADDR_TYPE_RT
2734         },
2735         { }
2736 };
2737
2738 /* l4_core -> timer12 */
2739 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2740         .master         = &omap3xxx_l4_sec_hwmod,
2741         .slave          = &omap3xxx_timer12_hwmod,
2742         .clk            = "gpt12_ick",
2743         .addr           = omap3xxx_timer12_addrs,
2744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2745 };
2746
2747 /* l4_wkup -> wd_timer2 */
2748 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2749         {
2750                 .pa_start       = 0x48314000,
2751                 .pa_end         = 0x4831407f,
2752                 .flags          = ADDR_TYPE_RT
2753         },
2754         { }
2755 };
2756
2757 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2758         .master         = &omap3xxx_l4_wkup_hwmod,
2759         .slave          = &omap3xxx_wd_timer2_hwmod,
2760         .clk            = "wdt2_ick",
2761         .addr           = omap3xxx_wd_timer2_addrs,
2762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2763 };
2764
2765 /* l4_core -> dss */
2766 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2767         .master         = &omap3xxx_l4_core_hwmod,
2768         .slave          = &omap3430es1_dss_core_hwmod,
2769         .clk            = "dss_ick",
2770         .addr           = omap2_dss_addrs,
2771         .fw = {
2772                 .omap2 = {
2773                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2774                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2775                         .flags  = OMAP_FIREWALL_L4,
2776                 }
2777         },
2778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2779 };
2780
2781 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2782         .master         = &omap3xxx_l4_core_hwmod,
2783         .slave          = &omap3xxx_dss_core_hwmod,
2784         .clk            = "dss_ick",
2785         .addr           = omap2_dss_addrs,
2786         .fw = {
2787                 .omap2 = {
2788                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2789                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2790                         .flags  = OMAP_FIREWALL_L4,
2791                 }
2792         },
2793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2794 };
2795
2796 /* l4_core -> dss_dispc */
2797 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2798         .master         = &omap3xxx_l4_core_hwmod,
2799         .slave          = &omap3xxx_dss_dispc_hwmod,
2800         .clk            = "dss_ick",
2801         .addr           = omap2_dss_dispc_addrs,
2802         .fw = {
2803                 .omap2 = {
2804                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2805                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2806                         .flags  = OMAP_FIREWALL_L4,
2807                 }
2808         },
2809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2810 };
2811
2812 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2813         {
2814                 .pa_start       = 0x4804FC00,
2815                 .pa_end         = 0x4804FFFF,
2816                 .flags          = ADDR_TYPE_RT
2817         },
2818         { }
2819 };
2820
2821 /* l4_core -> dss_dsi1 */
2822 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2823         .master         = &omap3xxx_l4_core_hwmod,
2824         .slave          = &omap3xxx_dss_dsi1_hwmod,
2825         .clk            = "dss_ick",
2826         .addr           = omap3xxx_dss_dsi1_addrs,
2827         .fw = {
2828                 .omap2 = {
2829                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2830                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2831                         .flags  = OMAP_FIREWALL_L4,
2832                 }
2833         },
2834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2835 };
2836
2837 /* l4_core -> dss_rfbi */
2838 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2839         .master         = &omap3xxx_l4_core_hwmod,
2840         .slave          = &omap3xxx_dss_rfbi_hwmod,
2841         .clk            = "dss_ick",
2842         .addr           = omap2_dss_rfbi_addrs,
2843         .fw = {
2844                 .omap2 = {
2845                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2846                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2847                         .flags  = OMAP_FIREWALL_L4,
2848                 }
2849         },
2850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2851 };
2852
2853 /* l4_core -> dss_venc */
2854 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2855         .master         = &omap3xxx_l4_core_hwmod,
2856         .slave          = &omap3xxx_dss_venc_hwmod,
2857         .clk            = "dss_ick",
2858         .addr           = omap2_dss_venc_addrs,
2859         .fw = {
2860                 .omap2 = {
2861                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2862                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2863                         .flags  = OMAP_FIREWALL_L4,
2864                 }
2865         },
2866         .flags          = OCPIF_SWSUP_IDLE,
2867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2868 };
2869
2870 /* l4_wkup -> gpio1 */
2871 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2872         {
2873                 .pa_start       = 0x48310000,
2874                 .pa_end         = 0x483101ff,
2875                 .flags          = ADDR_TYPE_RT
2876         },
2877         { }
2878 };
2879
2880 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2881         .master         = &omap3xxx_l4_wkup_hwmod,
2882         .slave          = &omap3xxx_gpio1_hwmod,
2883         .addr           = omap3xxx_gpio1_addrs,
2884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2886
2887 /* l4_per -> gpio2 */
2888 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2889         {
2890                 .pa_start       = 0x49050000,
2891                 .pa_end         = 0x490501ff,
2892                 .flags          = ADDR_TYPE_RT
2893         },
2894         { }
2895 };
2896
2897 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2898         .master         = &omap3xxx_l4_per_hwmod,
2899         .slave          = &omap3xxx_gpio2_hwmod,
2900         .addr           = omap3xxx_gpio2_addrs,
2901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2902 };
2903
2904 /* l4_per -> gpio3 */
2905 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2906         {
2907                 .pa_start       = 0x49052000,
2908                 .pa_end         = 0x490521ff,
2909                 .flags          = ADDR_TYPE_RT
2910         },
2911         { }
2912 };
2913
2914 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2915         .master         = &omap3xxx_l4_per_hwmod,
2916         .slave          = &omap3xxx_gpio3_hwmod,
2917         .addr           = omap3xxx_gpio3_addrs,
2918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2919 };
2920
2921 /*
2922  * 'mmu' class
2923  * The memory management unit performs virtual to physical address translation
2924  * for its requestors.
2925  */
2926
2927 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2928         .rev_offs       = 0x000,
2929         .sysc_offs      = 0x010,
2930         .syss_offs      = 0x014,
2931         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2932                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2933         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2934         .sysc_fields    = &omap_hwmod_sysc_type1,
2935 };
2936
2937 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2938         .name = "mmu",
2939         .sysc = &mmu_sysc,
2940 };
2941
2942 /* mmu isp */
2943 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2944
2945 /* l4_core -> mmu isp */
2946 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2947         .master         = &omap3xxx_l4_core_hwmod,
2948         .slave          = &omap3xxx_mmu_isp_hwmod,
2949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2950 };
2951
2952 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2953         .name           = "mmu_isp",
2954         .class          = &omap3xxx_mmu_hwmod_class,
2955         .main_clk       = "cam_ick",
2956         .flags          = HWMOD_NO_IDLEST,
2957 };
2958
2959 /* mmu iva */
2960
2961 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2962
2963 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2964         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2965 };
2966
2967 /* l3_main -> iva mmu */
2968 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2969         .master         = &omap3xxx_l3_main_hwmod,
2970         .slave          = &omap3xxx_mmu_iva_hwmod,
2971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2972 };
2973
2974 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2975         .name           = "mmu_iva",
2976         .class          = &omap3xxx_mmu_hwmod_class,
2977         .clkdm_name     = "iva2_clkdm",
2978         .rst_lines      = omap3xxx_mmu_iva_resets,
2979         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2980         .main_clk       = "iva2_ck",
2981         .prcm = {
2982                 .omap2 = {
2983                         .module_offs = OMAP3430_IVA2_MOD,
2984                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2985                         .idlest_reg_id = 1,
2986                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2987                 },
2988         },
2989         .flags          = HWMOD_NO_IDLEST,
2990 };
2991
2992 /* l4_per -> gpio4 */
2993 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2994         {
2995                 .pa_start       = 0x49054000,
2996                 .pa_end         = 0x490541ff,
2997                 .flags          = ADDR_TYPE_RT
2998         },
2999         { }
3000 };
3001
3002 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3003         .master         = &omap3xxx_l4_per_hwmod,
3004         .slave          = &omap3xxx_gpio4_hwmod,
3005         .addr           = omap3xxx_gpio4_addrs,
3006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3007 };
3008
3009 /* l4_per -> gpio5 */
3010 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3011         {
3012                 .pa_start       = 0x49056000,
3013                 .pa_end         = 0x490561ff,
3014                 .flags          = ADDR_TYPE_RT
3015         },
3016         { }
3017 };
3018
3019 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3020         .master         = &omap3xxx_l4_per_hwmod,
3021         .slave          = &omap3xxx_gpio5_hwmod,
3022         .addr           = omap3xxx_gpio5_addrs,
3023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3024 };
3025
3026 /* l4_per -> gpio6 */
3027 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3028         {
3029                 .pa_start       = 0x49058000,
3030                 .pa_end         = 0x490581ff,
3031                 .flags          = ADDR_TYPE_RT
3032         },
3033         { }
3034 };
3035
3036 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3037         .master         = &omap3xxx_l4_per_hwmod,
3038         .slave          = &omap3xxx_gpio6_hwmod,
3039         .addr           = omap3xxx_gpio6_addrs,
3040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3041 };
3042
3043 /* dma_system -> L3 */
3044 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3045         .master         = &omap3xxx_dma_system_hwmod,
3046         .slave          = &omap3xxx_l3_main_hwmod,
3047         .clk            = "core_l3_ick",
3048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3049 };
3050
3051 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3052         {
3053                 .pa_start       = 0x48056000,
3054                 .pa_end         = 0x48056fff,
3055                 .flags          = ADDR_TYPE_RT
3056         },
3057         { }
3058 };
3059
3060 /* l4_cfg -> dma_system */
3061 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3062         .master         = &omap3xxx_l4_core_hwmod,
3063         .slave          = &omap3xxx_dma_system_hwmod,
3064         .clk            = "core_l4_ick",
3065         .addr           = omap3xxx_dma_system_addrs,
3066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3067 };
3068
3069 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3070         {
3071                 .name           = "mpu",
3072                 .pa_start       = 0x48074000,
3073                 .pa_end         = 0x480740ff,
3074                 .flags          = ADDR_TYPE_RT
3075         },
3076         { }
3077 };
3078
3079 /* l4_core -> mcbsp1 */
3080 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3081         .master         = &omap3xxx_l4_core_hwmod,
3082         .slave          = &omap3xxx_mcbsp1_hwmod,
3083         .clk            = "mcbsp1_ick",
3084         .addr           = omap3xxx_mcbsp1_addrs,
3085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3086 };
3087
3088 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3089         {
3090                 .name           = "mpu",
3091                 .pa_start       = 0x49022000,
3092                 .pa_end         = 0x490220ff,
3093                 .flags          = ADDR_TYPE_RT
3094         },
3095         { }
3096 };
3097
3098 /* l4_per -> mcbsp2 */
3099 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3100         .master         = &omap3xxx_l4_per_hwmod,
3101         .slave          = &omap3xxx_mcbsp2_hwmod,
3102         .clk            = "mcbsp2_ick",
3103         .addr           = omap3xxx_mcbsp2_addrs,
3104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3105 };
3106
3107 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3108         {
3109                 .name           = "mpu",
3110                 .pa_start       = 0x49024000,
3111                 .pa_end         = 0x490240ff,
3112                 .flags          = ADDR_TYPE_RT
3113         },
3114         { }
3115 };
3116
3117 /* l4_per -> mcbsp3 */
3118 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3119         .master         = &omap3xxx_l4_per_hwmod,
3120         .slave          = &omap3xxx_mcbsp3_hwmod,
3121         .clk            = "mcbsp3_ick",
3122         .addr           = omap3xxx_mcbsp3_addrs,
3123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3124 };
3125
3126 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3127         {
3128                 .name           = "mpu",
3129                 .pa_start       = 0x49026000,
3130                 .pa_end         = 0x490260ff,
3131                 .flags          = ADDR_TYPE_RT
3132         },
3133         { }
3134 };
3135
3136 /* l4_per -> mcbsp4 */
3137 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3138         .master         = &omap3xxx_l4_per_hwmod,
3139         .slave          = &omap3xxx_mcbsp4_hwmod,
3140         .clk            = "mcbsp4_ick",
3141         .addr           = omap3xxx_mcbsp4_addrs,
3142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3143 };
3144
3145 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3146         {
3147                 .name           = "mpu",
3148                 .pa_start       = 0x48096000,
3149                 .pa_end         = 0x480960ff,
3150                 .flags          = ADDR_TYPE_RT
3151         },
3152         { }
3153 };
3154
3155 /* l4_core -> mcbsp5 */
3156 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3157         .master         = &omap3xxx_l4_core_hwmod,
3158         .slave          = &omap3xxx_mcbsp5_hwmod,
3159         .clk            = "mcbsp5_ick",
3160         .addr           = omap3xxx_mcbsp5_addrs,
3161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3162 };
3163
3164 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3165         {
3166                 .name           = "sidetone",
3167                 .pa_start       = 0x49028000,
3168                 .pa_end         = 0x490280ff,
3169                 .flags          = ADDR_TYPE_RT
3170         },
3171         { }
3172 };
3173
3174 /* l4_per -> mcbsp2_sidetone */
3175 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3176         .master         = &omap3xxx_l4_per_hwmod,
3177         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3178         .clk            = "mcbsp2_ick",
3179         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3180         .user           = OCP_USER_MPU,
3181 };
3182
3183 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3184         {
3185                 .name           = "sidetone",
3186                 .pa_start       = 0x4902A000,
3187                 .pa_end         = 0x4902A0ff,
3188                 .flags          = ADDR_TYPE_RT
3189         },
3190         { }
3191 };
3192
3193 /* l4_per -> mcbsp3_sidetone */
3194 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3195         .master         = &omap3xxx_l4_per_hwmod,
3196         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3197         .clk            = "mcbsp3_ick",
3198         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3199         .user           = OCP_USER_MPU,
3200 };
3201
3202 /* l4_core -> mailbox */
3203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3204         .master         = &omap3xxx_l4_core_hwmod,
3205         .slave          = &omap3xxx_mailbox_hwmod,
3206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3207 };
3208
3209 /* l4 core -> mcspi1 interface */
3210 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3211         .master         = &omap3xxx_l4_core_hwmod,
3212         .slave          = &omap34xx_mcspi1,
3213         .clk            = "mcspi1_ick",
3214         .addr           = omap2_mcspi1_addr_space,
3215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3216 };
3217
3218 /* l4 core -> mcspi2 interface */
3219 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3220         .master         = &omap3xxx_l4_core_hwmod,
3221         .slave          = &omap34xx_mcspi2,
3222         .clk            = "mcspi2_ick",
3223         .addr           = omap2_mcspi2_addr_space,
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* l4 core -> mcspi3 interface */
3228 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3229         .master         = &omap3xxx_l4_core_hwmod,
3230         .slave          = &omap34xx_mcspi3,
3231         .clk            = "mcspi3_ick",
3232         .addr           = omap2430_mcspi3_addr_space,
3233         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3234 };
3235
3236 /* l4 core -> mcspi4 interface */
3237 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3238         {
3239                 .pa_start       = 0x480ba000,
3240                 .pa_end         = 0x480ba0ff,
3241                 .flags          = ADDR_TYPE_RT,
3242         },
3243         { }
3244 };
3245
3246 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3247         .master         = &omap3xxx_l4_core_hwmod,
3248         .slave          = &omap34xx_mcspi4,
3249         .clk            = "mcspi4_ick",
3250         .addr           = omap34xx_mcspi4_addr_space,
3251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3252 };
3253
3254 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3255         .master         = &omap3xxx_usb_host_hs_hwmod,
3256         .slave          = &omap3xxx_l3_main_hwmod,
3257         .clk            = "core_l3_ick",
3258         .user           = OCP_USER_MPU,
3259 };
3260
3261 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3262         {
3263                 .name           = "uhh",
3264                 .pa_start       = 0x48064000,
3265                 .pa_end         = 0x480643ff,
3266                 .flags          = ADDR_TYPE_RT
3267         },
3268         {
3269                 .name           = "ohci",
3270                 .pa_start       = 0x48064400,
3271                 .pa_end         = 0x480647ff,
3272         },
3273         {
3274                 .name           = "ehci",
3275                 .pa_start       = 0x48064800,
3276                 .pa_end         = 0x48064cff,
3277         },
3278         {}
3279 };
3280
3281 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3282         .master         = &omap3xxx_l4_core_hwmod,
3283         .slave          = &omap3xxx_usb_host_hs_hwmod,
3284         .clk            = "usbhost_ick",
3285         .addr           = omap3xxx_usb_host_hs_addrs,
3286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3287 };
3288
3289 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3290         {
3291                 .name           = "tll",
3292                 .pa_start       = 0x48062000,
3293                 .pa_end         = 0x48062fff,
3294                 .flags          = ADDR_TYPE_RT
3295         },
3296         {}
3297 };
3298
3299 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3300         .master         = &omap3xxx_l4_core_hwmod,
3301         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3302         .clk            = "usbtll_ick",
3303         .addr           = omap3xxx_usb_tll_hs_addrs,
3304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3306
3307 /* l4_core -> hdq1w interface */
3308 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3309         .master         = &omap3xxx_l4_core_hwmod,
3310         .slave          = &omap3xxx_hdq1w_hwmod,
3311         .clk            = "hdq_ick",
3312         .addr           = omap2_hdq1w_addr_space,
3313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3314         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3315 };
3316
3317 /* l4_wkup -> 32ksync_counter */
3318 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3319         {
3320                 .pa_start       = 0x48320000,
3321                 .pa_end         = 0x4832001f,
3322                 .flags          = ADDR_TYPE_RT
3323         },
3324         { }
3325 };
3326
3327 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3328         {
3329                 .pa_start       = 0x6e000000,
3330                 .pa_end         = 0x6e000fff,
3331                 .flags          = ADDR_TYPE_RT
3332         },
3333         { }
3334 };
3335
3336 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3337         .master         = &omap3xxx_l4_wkup_hwmod,
3338         .slave          = &omap3xxx_counter_32k_hwmod,
3339         .clk            = "omap_32ksync_ick",
3340         .addr           = omap3xxx_counter_32k_addrs,
3341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3342 };
3343
3344 /* am35xx has Davinci MDIO & EMAC */
3345 static struct omap_hwmod_class am35xx_mdio_class = {
3346         .name = "davinci_mdio",
3347 };
3348
3349 static struct omap_hwmod am35xx_mdio_hwmod = {
3350         .name           = "davinci_mdio",
3351         .class          = &am35xx_mdio_class,
3352         .flags          = HWMOD_NO_IDLEST,
3353 };
3354
3355 /*
3356  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3357  * but this will probably require some additional hwmod core support,
3358  * so is left as a future to-do item.
3359  */
3360 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3361         .master         = &am35xx_mdio_hwmod,
3362         .slave          = &omap3xxx_l3_main_hwmod,
3363         .clk            = "emac_fck",
3364         .user           = OCP_USER_MPU,
3365 };
3366
3367 /* l4_core -> davinci mdio  */
3368 /*
3369  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3370  * but this will probably require some additional hwmod core support,
3371  * so is left as a future to-do item.
3372  */
3373 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3374         .master         = &omap3xxx_l4_core_hwmod,
3375         .slave          = &am35xx_mdio_hwmod,
3376         .clk            = "emac_fck",
3377         .user           = OCP_USER_MPU,
3378 };
3379
3380 static struct omap_hwmod_class am35xx_emac_class = {
3381         .name = "davinci_emac",
3382 };
3383
3384 static struct omap_hwmod am35xx_emac_hwmod = {
3385         .name           = "davinci_emac",
3386         .class          = &am35xx_emac_class,
3387         /*
3388          * According to Mark Greer, the MPU will not return from WFI
3389          * when the EMAC signals an interrupt.
3390          * http://www.spinics.net/lists/arm-kernel/msg174734.html
3391          */
3392         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3393 };
3394
3395 /* l3_core -> davinci emac interface */
3396 /*
3397  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3398  * but this will probably require some additional hwmod core support,
3399  * so is left as a future to-do item.
3400  */
3401 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3402         .master         = &am35xx_emac_hwmod,
3403         .slave          = &omap3xxx_l3_main_hwmod,
3404         .clk            = "emac_ick",
3405         .user           = OCP_USER_MPU,
3406 };
3407
3408 /* l4_core -> davinci emac  */
3409 /*
3410  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3411  * but this will probably require some additional hwmod core support,
3412  * so is left as a future to-do item.
3413  */
3414 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3415         .master         = &omap3xxx_l4_core_hwmod,
3416         .slave          = &am35xx_emac_hwmod,
3417         .clk            = "emac_ick",
3418         .user           = OCP_USER_MPU,
3419 };
3420
3421 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3422         .master         = &omap3xxx_l3_main_hwmod,
3423         .slave          = &omap3xxx_gpmc_hwmod,
3424         .clk            = "core_l3_ick",
3425         .addr           = omap3xxx_gpmc_addrs,
3426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3427 };
3428
3429 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3430 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3431         .sidle_shift    = 4,
3432         .srst_shift     = 1,
3433         .autoidle_shift = 0,
3434 };
3435
3436 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3437         .rev_offs       = 0x5c,
3438         .sysc_offs      = 0x60,
3439         .syss_offs      = 0x64,
3440         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3441                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3442         .sysc_fields    = &omap3_sham_sysc_fields,
3443 };
3444
3445 static struct omap_hwmod_class omap3xxx_sham_class = {
3446         .name   = "sham",
3447         .sysc   = &omap3_sham_sysc,
3448 };
3449
3450 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3451         { .irq = 49 + OMAP_INTC_START, },
3452         { .irq = -1 }
3453 };
3454
3455 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3456         { .name = "rx", .dma_req = 69, },
3457         { .dma_req = -1 }
3458 };
3459
3460 static struct omap_hwmod omap3xxx_sham_hwmod = {
3461         .name           = "sham",
3462         .mpu_irqs       = omap3_sham_mpu_irqs,
3463         .sdma_reqs      = omap3_sham_sdma_reqs,
3464         .main_clk       = "sha12_ick",
3465         .prcm           = {
3466                 .omap2 = {
3467                         .module_offs = CORE_MOD,
3468                         .prcm_reg_id = 1,
3469                         .module_bit = OMAP3430_EN_SHA12_SHIFT,
3470                         .idlest_reg_id = 1,
3471                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3472                 },
3473         },
3474         .class          = &omap3xxx_sham_class,
3475 };
3476
3477 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3478         {
3479                 .pa_start       = 0x480c3000,
3480                 .pa_end         = 0x480c3000 + 0x64 - 1,
3481                 .flags          = ADDR_TYPE_RT
3482         },
3483         { }
3484 };
3485
3486 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3487         .master         = &omap3xxx_l4_core_hwmod,
3488         .slave          = &omap3xxx_sham_hwmod,
3489         .clk            = "sha12_ick",
3490         .addr           = omap3xxx_sham_addrs,
3491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3492 };
3493
3494 /* l4_core -> AES */
3495 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3496         .sidle_shift    = 6,
3497         .srst_shift     = 1,
3498         .autoidle_shift = 0,
3499 };
3500
3501 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3502         .rev_offs       = 0x44,
3503         .sysc_offs      = 0x48,
3504         .syss_offs      = 0x4c,
3505         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3506                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3507         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3508         .sysc_fields    = &omap3xxx_aes_sysc_fields,
3509 };
3510
3511 static struct omap_hwmod_class omap3xxx_aes_class = {
3512         .name   = "aes",
3513         .sysc   = &omap3_aes_sysc,
3514 };
3515
3516 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3517         { .name = "tx", .dma_req = 65, },
3518         { .name = "rx", .dma_req = 66, },
3519         { .dma_req = -1 }
3520 };
3521
3522 static struct omap_hwmod omap3xxx_aes_hwmod = {
3523         .name           = "aes",
3524         .sdma_reqs      = omap3_aes_sdma_reqs,
3525         .main_clk       = "aes2_ick",
3526         .prcm           = {
3527                 .omap2 = {
3528                         .module_offs = CORE_MOD,
3529                         .prcm_reg_id = 1,
3530                         .module_bit = OMAP3430_EN_AES2_SHIFT,
3531                         .idlest_reg_id = 1,
3532                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3533                 },
3534         },
3535         .class          = &omap3xxx_aes_class,
3536 };
3537
3538 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3539         {
3540                 .pa_start       = 0x480c5000,
3541                 .pa_end         = 0x480c5000 + 0x50 - 1,
3542                 .flags          = ADDR_TYPE_RT
3543         },
3544         { }
3545 };
3546
3547 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3548         .master         = &omap3xxx_l4_core_hwmod,
3549         .slave          = &omap3xxx_aes_hwmod,
3550         .clk            = "aes2_ick",
3551         .addr           = omap3xxx_aes_addrs,
3552         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3553 };
3554
3555 /*
3556  * 'ssi' class
3557  * synchronous serial interface (multichannel and full-duplex serial if)
3558  */
3559
3560 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3561         .rev_offs       = 0x0000,
3562         .sysc_offs      = 0x0010,
3563         .syss_offs      = 0x0014,
3564         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
3565                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3566         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3567         .sysc_fields    = &omap_hwmod_sysc_type1,
3568 };
3569
3570 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
3571         .name   = "ssi",
3572         .sysc   = &omap34xx_ssi_sysc,
3573 };
3574
3575 static struct omap_hwmod omap3xxx_ssi_hwmod = {
3576         .name           = "ssi",
3577         .class          = &omap3xxx_ssi_hwmod_class,
3578         .clkdm_name     = "core_l4_clkdm",
3579         .main_clk       = "ssi_ssr_fck",
3580         .prcm           = {
3581                 .omap2 = {
3582                         .prcm_reg_id            = 1,
3583                         .module_bit             = OMAP3430_EN_SSI_SHIFT,
3584                         .module_offs            = CORE_MOD,
3585                         .idlest_reg_id          = 1,
3586                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
3587                 },
3588         },
3589 };
3590
3591 /* L4 CORE -> SSI */
3592 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
3593         .master         = &omap3xxx_l4_core_hwmod,
3594         .slave          = &omap3xxx_ssi_hwmod,
3595         .clk            = "ssi_ick",
3596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3597 };
3598
3599 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3600         &omap3xxx_l3_main__l4_core,
3601         &omap3xxx_l3_main__l4_per,
3602         &omap3xxx_mpu__l3_main,
3603         &omap3xxx_l3_main__l4_debugss,
3604         &omap3xxx_l4_core__l4_wkup,
3605         &omap3xxx_l4_core__mmc3,
3606         &omap3_l4_core__uart1,
3607         &omap3_l4_core__uart2,
3608         &omap3_l4_per__uart3,
3609         &omap3_l4_core__i2c1,
3610         &omap3_l4_core__i2c2,
3611         &omap3_l4_core__i2c3,
3612         &omap3xxx_l4_wkup__l4_sec,
3613         &omap3xxx_l4_wkup__timer1,
3614         &omap3xxx_l4_per__timer2,
3615         &omap3xxx_l4_per__timer3,
3616         &omap3xxx_l4_per__timer4,
3617         &omap3xxx_l4_per__timer5,
3618         &omap3xxx_l4_per__timer6,
3619         &omap3xxx_l4_per__timer7,
3620         &omap3xxx_l4_per__timer8,
3621         &omap3xxx_l4_per__timer9,
3622         &omap3xxx_l4_core__timer10,
3623         &omap3xxx_l4_core__timer11,
3624         &omap3xxx_l4_wkup__wd_timer2,
3625         &omap3xxx_l4_wkup__gpio1,
3626         &omap3xxx_l4_per__gpio2,
3627         &omap3xxx_l4_per__gpio3,
3628         &omap3xxx_l4_per__gpio4,
3629         &omap3xxx_l4_per__gpio5,
3630         &omap3xxx_l4_per__gpio6,
3631         &omap3xxx_dma_system__l3,
3632         &omap3xxx_l4_core__dma_system,
3633         &omap3xxx_l4_core__mcbsp1,
3634         &omap3xxx_l4_per__mcbsp2,
3635         &omap3xxx_l4_per__mcbsp3,
3636         &omap3xxx_l4_per__mcbsp4,
3637         &omap3xxx_l4_core__mcbsp5,
3638         &omap3xxx_l4_per__mcbsp2_sidetone,
3639         &omap3xxx_l4_per__mcbsp3_sidetone,
3640         &omap34xx_l4_core__mcspi1,
3641         &omap34xx_l4_core__mcspi2,
3642         &omap34xx_l4_core__mcspi3,
3643         &omap34xx_l4_core__mcspi4,
3644         &omap3xxx_l4_wkup__counter_32k,
3645         &omap3xxx_l3_main__gpmc,
3646         NULL,
3647 };
3648
3649 /* GP-only hwmod links */
3650 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3651         &omap3xxx_l4_sec__timer12,
3652         NULL
3653 };
3654
3655 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3656         &omap3xxx_l4_sec__timer12,
3657         NULL
3658 };
3659
3660 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3661         &omap3xxx_l4_sec__timer12,
3662         NULL
3663 };
3664
3665 /* crypto hwmod links */
3666 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3667         &omap3xxx_l4_core__sham,
3668         NULL
3669 };
3670
3671 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3672         &omap3xxx_l4_core__aes,
3673         NULL
3674 };
3675
3676 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
3677         &omap3xxx_l4_core__sham,
3678         NULL
3679 };
3680
3681 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
3682         &omap3xxx_l4_core__aes,
3683         NULL
3684 };
3685
3686 /*
3687  * Apparently the SHA/MD5 and AES accelerator IP blocks are
3688  * only present on some AM35xx chips, and no one knows which
3689  * ones.  See
3690  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3691  * if you need these IP blocks on an AM35xx, try uncommenting
3692  * the following lines.
3693  */
3694 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3695         /* &omap3xxx_l4_core__sham, */
3696         NULL
3697 };
3698
3699 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3700         /* &omap3xxx_l4_core__aes, */
3701         NULL
3702 };
3703
3704 /* 3430ES1-only hwmod links */
3705 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3706         &omap3430es1_dss__l3,
3707         &omap3430es1_l4_core__dss,
3708         NULL
3709 };
3710
3711 /* 3430ES2+-only hwmod links */
3712 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3713         &omap3xxx_dss__l3,
3714         &omap3xxx_l4_core__dss,
3715         &omap3xxx_usbhsotg__l3,
3716         &omap3xxx_l4_core__usbhsotg,
3717         &omap3xxx_usb_host_hs__l3_main_2,
3718         &omap3xxx_l4_core__usb_host_hs,
3719         &omap3xxx_l4_core__usb_tll_hs,
3720         NULL
3721 };
3722
3723 /* <= 3430ES3-only hwmod links */
3724 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3725         &omap3xxx_l4_core__pre_es3_mmc1,
3726         &omap3xxx_l4_core__pre_es3_mmc2,
3727         NULL
3728 };
3729
3730 /* 3430ES3+-only hwmod links */
3731 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3732         &omap3xxx_l4_core__es3plus_mmc1,
3733         &omap3xxx_l4_core__es3plus_mmc2,
3734         NULL
3735 };
3736
3737 /* 34xx-only hwmod links (all ES revisions) */
3738 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3739         &omap3xxx_l3__iva,
3740         &omap34xx_l4_core__sr1,
3741         &omap34xx_l4_core__sr2,
3742         &omap3xxx_l4_core__mailbox,
3743         &omap3xxx_l4_core__hdq1w,
3744         &omap3xxx_sad2d__l3,
3745         &omap3xxx_l4_core__mmu_isp,
3746         &omap3xxx_l3_main__mmu_iva,
3747         &omap3xxx_l4_core__ssi,
3748         NULL
3749 };
3750
3751 /* 36xx-only hwmod links (all ES revisions) */
3752 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3753         &omap3xxx_l3__iva,
3754         &omap36xx_l4_per__uart4,
3755         &omap3xxx_dss__l3,
3756         &omap3xxx_l4_core__dss,
3757         &omap36xx_l4_core__sr1,
3758         &omap36xx_l4_core__sr2,
3759         &omap3xxx_usbhsotg__l3,
3760         &omap3xxx_l4_core__usbhsotg,
3761         &omap3xxx_l4_core__mailbox,
3762         &omap3xxx_usb_host_hs__l3_main_2,
3763         &omap3xxx_l4_core__usb_host_hs,
3764         &omap3xxx_l4_core__usb_tll_hs,
3765         &omap3xxx_l4_core__es3plus_mmc1,
3766         &omap3xxx_l4_core__es3plus_mmc2,
3767         &omap3xxx_l4_core__hdq1w,
3768         &omap3xxx_sad2d__l3,
3769         &omap3xxx_l4_core__mmu_isp,
3770         &omap3xxx_l3_main__mmu_iva,
3771         &omap3xxx_l4_core__ssi,
3772         NULL
3773 };
3774
3775 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3776         &omap3xxx_dss__l3,
3777         &omap3xxx_l4_core__dss,
3778         &am35xx_usbhsotg__l3,
3779         &am35xx_l4_core__usbhsotg,
3780         &am35xx_l4_core__uart4,
3781         &omap3xxx_usb_host_hs__l3_main_2,
3782         &omap3xxx_l4_core__usb_host_hs,
3783         &omap3xxx_l4_core__usb_tll_hs,
3784         &omap3xxx_l4_core__es3plus_mmc1,
3785         &omap3xxx_l4_core__es3plus_mmc2,
3786         &omap3xxx_l4_core__hdq1w,
3787         &am35xx_mdio__l3,
3788         &am35xx_l4_core__mdio,
3789         &am35xx_emac__l3,
3790         &am35xx_l4_core__emac,
3791         NULL
3792 };
3793
3794 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3795         &omap3xxx_l4_core__dss_dispc,
3796         &omap3xxx_l4_core__dss_dsi1,
3797         &omap3xxx_l4_core__dss_rfbi,
3798         &omap3xxx_l4_core__dss_venc,
3799         NULL
3800 };
3801
3802 /**
3803  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3804  * @bus: struct device_node * for the top-level OMAP DT data
3805  * @dev_name: device name used in the DT file
3806  *
3807  * Determine whether a "secure" IP block @dev_name is usable by Linux.
3808  * There doesn't appear to be a 100% reliable way to determine this,
3809  * so we rely on heuristics.  If @bus is null, meaning there's no DT
3810  * data, then we only assume the IP block is accessible if the OMAP is
3811  * fused as a 'general-purpose' SoC.  If however DT data is present,
3812  * test to see if the IP block is described in the DT data and set to
3813  * 'status = "okay"'.  If so then we assume the ODM has configured the
3814  * OMAP firewalls to allow access to the IP block.
3815  *
3816  * Return: 0 if device named @dev_name is not likely to be accessible,
3817  * or 1 if it is likely to be accessible.
3818  */
3819 static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3820                                                        const char *dev_name)
3821 {
3822         if (!bus)
3823                 return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
3824
3825         if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
3826                 return 1;
3827
3828         return 0;
3829 }
3830
3831 int __init omap3xxx_hwmod_init(void)
3832 {
3833         int r;
3834         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3835         struct omap_hwmod_ocp_if **h_aes = NULL;
3836         struct device_node *bus = NULL;
3837         unsigned int rev;
3838
3839         omap_hwmod_init();
3840
3841         /* Register hwmod links common to all OMAP3 */
3842         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3843         if (r < 0)
3844                 return r;
3845
3846         rev = omap_rev();
3847
3848         /*
3849          * Register hwmod links common to individual OMAP3 families, all
3850          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3851          * All possible revisions should be included in this conditional.
3852          */
3853         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3854             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3855             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3856                 h = omap34xx_hwmod_ocp_ifs;
3857                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3858                 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3859                 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3860         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3861                 h = am35xx_hwmod_ocp_ifs;
3862                 h_gp = am35xx_gp_hwmod_ocp_ifs;
3863                 h_sham = am35xx_sham_hwmod_ocp_ifs;
3864                 h_aes = am35xx_aes_hwmod_ocp_ifs;
3865         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3866                    rev == OMAP3630_REV_ES1_2) {
3867                 h = omap36xx_hwmod_ocp_ifs;
3868                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3869                 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3870                 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3871         } else {
3872                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3873                 return -EINVAL;
3874         }
3875
3876         r = omap_hwmod_register_links(h);
3877         if (r < 0)
3878                 return r;
3879
3880         /* Register GP-only hwmod links. */
3881         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3882                 r = omap_hwmod_register_links(h_gp);
3883                 if (r < 0)
3884                         return r;
3885         }
3886
3887         /*
3888          * Register crypto hwmod links only if they are not disabled in DT.
3889          * If DT information is missing, enable them only for GP devices.
3890          */
3891
3892         if (of_have_populated_dt())
3893                 bus = of_find_node_by_name(NULL, "ocp");
3894
3895         if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3896                 r = omap_hwmod_register_links(h_sham);
3897                 if (r < 0)
3898                         return r;
3899         }
3900
3901         if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3902                 r = omap_hwmod_register_links(h_aes);
3903                 if (r < 0)
3904                         return r;
3905         }
3906
3907         /*
3908          * Register hwmod links specific to certain ES levels of a
3909          * particular family of silicon (e.g., 34xx ES1.0)
3910          */
3911         h = NULL;
3912         if (rev == OMAP3430_REV_ES1_0) {
3913                 h = omap3430es1_hwmod_ocp_ifs;
3914         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3915                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3916                    rev == OMAP3430_REV_ES3_1_2) {
3917                 h = omap3430es2plus_hwmod_ocp_ifs;
3918         }
3919
3920         if (h) {
3921                 r = omap_hwmod_register_links(h);
3922                 if (r < 0)
3923                         return r;
3924         }
3925
3926         h = NULL;
3927         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3928             rev == OMAP3430_REV_ES2_1) {
3929                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3930         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3931                    rev == OMAP3430_REV_ES3_1_2) {
3932                 h = omap3430_es3plus_hwmod_ocp_ifs;
3933         }
3934
3935         if (h)
3936                 r = omap_hwmod_register_links(h);
3937         if (r < 0)
3938                 return r;
3939
3940         /*
3941          * DSS code presumes that dss_core hwmod is handled first,
3942          * _before_ any other DSS related hwmods so register common
3943          * DSS hwmod links last to ensure that dss_core is already
3944          * registered.  Otherwise some change things may happen, for
3945          * ex. if dispc is handled before dss_core and DSS is enabled
3946          * in bootloader DISPC will be reset with outputs enabled
3947          * which sometimes leads to unrecoverable L3 error.  XXX The
3948          * long-term fix to this is to ensure hwmods are set up in
3949          * dependency order in the hwmod core code.
3950          */
3951         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3952
3953         return r;
3954 }