2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
15 * XXX these should be marked initdata for multi-OMAP kernels
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/omap-dma.h>
25 #include <linux/platform_data/asoc-ti-mcbsp.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/iommu-omap.h>
28 #include <plat/dmtimer.h>
33 #include "omap_hwmod.h"
34 #include "omap_hwmod_common_data.h"
35 #include "prm-regbits-34xx.h"
36 #include "cm-regbits-34xx.h"
45 * OMAP3xxx hardware module integration data
47 * All of the data in this section should be autogeneratable from the
48 * TI hardware database or other technical documentation. Data that
49 * is driver-specific or driver-kernel integration-specific belongs
58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
59 { .irq = 9 + OMAP_INTC_START, },
60 { .irq = 10 + OMAP_INTC_START, },
64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
66 .class = &l3_hwmod_class,
67 .mpu_irqs = omap3xxx_l3_main_irqs,
68 .flags = HWMOD_NO_IDLEST,
72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
74 .class = &l4_hwmod_class,
75 .flags = HWMOD_NO_IDLEST,
79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
81 .class = &l4_hwmod_class,
82 .flags = HWMOD_NO_IDLEST,
86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
88 .class = &l4_hwmod_class,
89 .flags = HWMOD_NO_IDLEST,
93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
95 .class = &l4_hwmod_class,
96 .flags = HWMOD_NO_IDLEST,
100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
101 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
107 .mpu_irqs = omap3xxx_mpu_irqs,
108 .class = &mpu_hwmod_class,
109 .main_clk = "arm_fck",
113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
114 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
119 static struct omap_hwmod omap3xxx_iva_hwmod = {
121 .class = &iva_hwmod_class,
122 .clkdm_name = "iva2_clkdm",
123 .rst_lines = omap3xxx_iva_resets,
124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
125 .main_clk = "iva2_ck",
128 .module_offs = OMAP3430_IVA2_MOD,
130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
139 * debug and emulation sub system
142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
149 .class = &omap3xxx_debugss_hwmod_class,
150 .clkdm_name = "emu_clkdm",
151 .main_clk = "emu_src_ck",
152 .flags = HWMOD_NO_IDLEST,
156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
166 .sysc_fields = &omap_hwmod_sysc_type1,
169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
171 .sysc = &omap3xxx_timer_sysc,
174 /* secure timers dev attribute */
175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
179 /* always-on timers dev attribute */
180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
181 .timer_capability = OMAP_TIMER_ALWON,
184 /* pwm timers dev attribute */
185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
186 .timer_capability = OMAP_TIMER_HAS_PWM,
189 /* timers with DSP interrupt dev attribute */
190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
194 /* pwm timers with DSP interrupt dev attribute */
195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
202 .mpu_irqs = omap2_timer1_mpu_irqs,
203 .main_clk = "gpt1_fck",
207 .module_bit = OMAP3430_EN_GPT1_SHIFT,
208 .module_offs = WKUP_MOD,
210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
213 .dev_attr = &capability_alwon_dev_attr,
214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
221 .mpu_irqs = omap2_timer2_mpu_irqs,
222 .main_clk = "gpt2_fck",
226 .module_bit = OMAP3430_EN_GPT2_SHIFT,
227 .module_offs = OMAP3430_PER_MOD,
229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
239 .mpu_irqs = omap2_timer3_mpu_irqs,
240 .main_clk = "gpt3_fck",
244 .module_bit = OMAP3430_EN_GPT3_SHIFT,
245 .module_offs = OMAP3430_PER_MOD,
247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
257 .mpu_irqs = omap2_timer4_mpu_irqs,
258 .main_clk = "gpt4_fck",
262 .module_bit = OMAP3430_EN_GPT4_SHIFT,
263 .module_offs = OMAP3430_PER_MOD,
265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
275 .mpu_irqs = omap2_timer5_mpu_irqs,
276 .main_clk = "gpt5_fck",
280 .module_bit = OMAP3430_EN_GPT5_SHIFT,
281 .module_offs = OMAP3430_PER_MOD,
283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
286 .dev_attr = &capability_dsp_dev_attr,
287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
294 .mpu_irqs = omap2_timer6_mpu_irqs,
295 .main_clk = "gpt6_fck",
299 .module_bit = OMAP3430_EN_GPT6_SHIFT,
300 .module_offs = OMAP3430_PER_MOD,
302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
305 .dev_attr = &capability_dsp_dev_attr,
306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
313 .mpu_irqs = omap2_timer7_mpu_irqs,
314 .main_clk = "gpt7_fck",
318 .module_bit = OMAP3430_EN_GPT7_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
324 .dev_attr = &capability_dsp_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
332 .mpu_irqs = omap2_timer8_mpu_irqs,
333 .main_clk = "gpt8_fck",
337 .module_bit = OMAP3430_EN_GPT8_SHIFT,
338 .module_offs = OMAP3430_PER_MOD,
340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
343 .dev_attr = &capability_dsp_pwm_dev_attr,
344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
351 .mpu_irqs = omap2_timer9_mpu_irqs,
352 .main_clk = "gpt9_fck",
356 .module_bit = OMAP3430_EN_GPT9_SHIFT,
357 .module_offs = OMAP3430_PER_MOD,
359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
362 .dev_attr = &capability_pwm_dev_attr,
363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
370 .mpu_irqs = omap2_timer10_mpu_irqs,
371 .main_clk = "gpt10_fck",
375 .module_bit = OMAP3430_EN_GPT10_SHIFT,
376 .module_offs = CORE_MOD,
378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
381 .dev_attr = &capability_pwm_dev_attr,
382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
389 .mpu_irqs = omap2_timer11_mpu_irqs,
390 .main_clk = "gpt11_fck",
394 .module_bit = OMAP3430_EN_GPT11_SHIFT,
395 .module_offs = CORE_MOD,
397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
400 .dev_attr = &capability_pwm_dev_attr,
401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
407 { .irq = 95 + OMAP_INTC_START, },
411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
413 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
414 .main_clk = "gpt12_fck",
418 .module_bit = OMAP3430_EN_GPT12_SHIFT,
419 .module_offs = WKUP_MOD,
421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
424 .dev_attr = &capability_secure_dev_attr,
425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444 .sysc_fields = &omap_hwmod_sysc_type1,
448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
456 .clockact = CLOCKACT_TEST_ICLK,
457 .sysc_fields = &omap_hwmod_sysc_type1,
460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
462 .sysc = &omap3xxx_wd_timer_sysc,
463 .pre_shutdown = &omap2_wd_timer_disable,
464 .reset = &omap2_wd_timer_reset,
467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
469 .class = &omap3xxx_wd_timer_hwmod_class,
470 .main_clk = "wdt2_fck",
474 .module_bit = OMAP3430_EN_WDT2_SHIFT,
475 .module_offs = WKUP_MOD,
477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
481 * XXX: Use software supervised mode, HW supervised smartidle seems to
482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
484 .flags = HWMOD_SWSUP_SIDLE,
488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck",
495 .module_offs = CORE_MOD,
497 .module_bit = OMAP3430_EN_UART1_SHIFT,
499 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
502 .class = &omap2_uart_class,
506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
508 .mpu_irqs = omap2_uart2_mpu_irqs,
509 .sdma_reqs = omap2_uart2_sdma_reqs,
510 .main_clk = "uart2_fck",
513 .module_offs = CORE_MOD,
515 .module_bit = OMAP3430_EN_UART2_SHIFT,
517 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
520 .class = &omap2_uart_class,
524 static struct omap_hwmod omap3xxx_uart3_hwmod = {
526 .mpu_irqs = omap2_uart3_mpu_irqs,
527 .sdma_reqs = omap2_uart3_sdma_reqs,
528 .main_clk = "uart3_fck",
531 .module_offs = OMAP3430_PER_MOD,
533 .module_bit = OMAP3430_EN_UART3_SHIFT,
535 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
538 .class = &omap2_uart_class,
542 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
543 { .irq = 80 + OMAP_INTC_START, },
547 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
548 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
549 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
553 static struct omap_hwmod omap36xx_uart4_hwmod = {
555 .mpu_irqs = uart4_mpu_irqs,
556 .sdma_reqs = uart4_sdma_reqs,
557 .main_clk = "uart4_fck",
560 .module_offs = OMAP3430_PER_MOD,
562 .module_bit = OMAP3630_EN_UART4_SHIFT,
564 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
567 .class = &omap2_uart_class,
570 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
571 { .irq = 84 + OMAP_INTC_START, },
575 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
576 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
577 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
582 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
583 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
584 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
585 * should not be needed. The functional clock structure of the AM35xx
586 * UART4 is extremely unclear and opaque; it is unclear what the role
587 * of uart1/2_fck is for the UART4. Any clarification from either
588 * empirical testing or the AM3505/3517 hardware designers would be
591 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
592 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
595 static struct omap_hwmod am35xx_uart4_hwmod = {
597 .mpu_irqs = am35xx_uart4_mpu_irqs,
598 .sdma_reqs = am35xx_uart4_sdma_reqs,
599 .main_clk = "uart4_fck",
602 .module_offs = CORE_MOD,
604 .module_bit = AM35XX_EN_UART4_SHIFT,
606 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
609 .opt_clks = am35xx_uart4_opt_clks,
610 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
611 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
612 .class = &omap2_uart_class,
615 static struct omap_hwmod_class i2c_class = {
618 .rev = OMAP_I2C_IP_VERSION_1,
619 .reset = &omap_i2c_reset,
622 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
623 { .name = "dispc", .dma_req = 5 },
624 { .name = "dsi1", .dma_req = 74 },
629 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
631 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
632 * driver does not use these clocks.
634 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
635 { .role = "tv_clk", .clk = "dss_tv_fck" },
636 /* required only on OMAP3430 */
637 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
640 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
642 .class = &omap2_dss_hwmod_class,
643 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
644 .sdma_reqs = omap3xxx_dss_sdma_chs,
648 .module_bit = OMAP3430_EN_DSS1_SHIFT,
649 .module_offs = OMAP3430_DSS_MOD,
651 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
654 .opt_clks = dss_opt_clks,
655 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
656 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
659 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
661 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
662 .class = &omap2_dss_hwmod_class,
663 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
664 .sdma_reqs = omap3xxx_dss_sdma_chs,
668 .module_bit = OMAP3430_EN_DSS1_SHIFT,
669 .module_offs = OMAP3430_DSS_MOD,
671 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
672 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
675 .opt_clks = dss_opt_clks,
676 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
684 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
688 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
689 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
691 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
692 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
693 .sysc_fields = &omap_hwmod_sysc_type1,
696 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
698 .sysc = &omap3_dispc_sysc,
701 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
703 .class = &omap3_dispc_hwmod_class,
704 .mpu_irqs = omap2_dispc_irqs,
705 .main_clk = "dss1_alwon_fck",
709 .module_bit = OMAP3430_EN_DSS1_SHIFT,
710 .module_offs = OMAP3430_DSS_MOD,
713 .flags = HWMOD_NO_IDLEST,
714 .dev_attr = &omap2_3_dss_dispc_dev_attr
719 * display serial interface controller
722 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
726 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
727 { .irq = 25 + OMAP_INTC_START, },
732 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
733 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
736 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
738 .class = &omap3xxx_dsi_hwmod_class,
739 .mpu_irqs = omap3xxx_dsi1_irqs,
740 .main_clk = "dss1_alwon_fck",
744 .module_bit = OMAP3430_EN_DSS1_SHIFT,
745 .module_offs = OMAP3430_DSS_MOD,
748 .opt_clks = dss_dsi1_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
750 .flags = HWMOD_NO_IDLEST,
753 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
754 { .role = "ick", .clk = "dss_ick" },
757 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
759 .class = &omap2_rfbi_hwmod_class,
760 .main_clk = "dss1_alwon_fck",
764 .module_bit = OMAP3430_EN_DSS1_SHIFT,
765 .module_offs = OMAP3430_DSS_MOD,
768 .opt_clks = dss_rfbi_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
770 .flags = HWMOD_NO_IDLEST,
773 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
774 /* required only on OMAP3430 */
775 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
778 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
780 .class = &omap2_venc_hwmod_class,
781 .main_clk = "dss_tv_fck",
785 .module_bit = OMAP3430_EN_DSS1_SHIFT,
786 .module_offs = OMAP3430_DSS_MOD,
789 .opt_clks = dss_venc_opt_clks,
790 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
791 .flags = HWMOD_NO_IDLEST,
795 static struct omap_i2c_dev_attr i2c1_dev_attr = {
796 .fifo_depth = 8, /* bytes */
797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
800 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
802 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
803 .mpu_irqs = omap2_i2c1_mpu_irqs,
804 .sdma_reqs = omap2_i2c1_sdma_reqs,
805 .main_clk = "i2c1_fck",
808 .module_offs = CORE_MOD,
810 .module_bit = OMAP3430_EN_I2C1_SHIFT,
812 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
816 .dev_attr = &i2c1_dev_attr,
820 static struct omap_i2c_dev_attr i2c2_dev_attr = {
821 .fifo_depth = 8, /* bytes */
822 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
825 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
827 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
828 .mpu_irqs = omap2_i2c2_mpu_irqs,
829 .sdma_reqs = omap2_i2c2_sdma_reqs,
830 .main_clk = "i2c2_fck",
833 .module_offs = CORE_MOD,
835 .module_bit = OMAP3430_EN_I2C2_SHIFT,
837 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
841 .dev_attr = &i2c2_dev_attr,
845 static struct omap_i2c_dev_attr i2c3_dev_attr = {
846 .fifo_depth = 64, /* bytes */
847 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
850 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
851 { .irq = 61 + OMAP_INTC_START, },
855 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
856 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
857 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
861 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
863 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
864 .mpu_irqs = i2c3_mpu_irqs,
865 .sdma_reqs = i2c3_sdma_reqs,
866 .main_clk = "i2c3_fck",
869 .module_offs = CORE_MOD,
871 .module_bit = OMAP3430_EN_I2C3_SHIFT,
873 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
877 .dev_attr = &i2c3_dev_attr,
882 * general purpose io module
885 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
889 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
890 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
891 SYSS_HAS_RESET_STATUS),
892 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
893 .sysc_fields = &omap_hwmod_sysc_type1,
896 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
898 .sysc = &omap3xxx_gpio_sysc,
903 static struct omap_gpio_dev_attr gpio_dev_attr = {
909 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
910 { .role = "dbclk", .clk = "gpio1_dbck", },
913 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
915 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
916 .mpu_irqs = omap2_gpio1_irqs,
917 .main_clk = "gpio1_ick",
918 .opt_clks = gpio1_opt_clks,
919 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
923 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
924 .module_offs = WKUP_MOD,
926 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
929 .class = &omap3xxx_gpio_hwmod_class,
930 .dev_attr = &gpio_dev_attr,
934 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
935 { .role = "dbclk", .clk = "gpio2_dbck", },
938 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
940 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
941 .mpu_irqs = omap2_gpio2_irqs,
942 .main_clk = "gpio2_ick",
943 .opt_clks = gpio2_opt_clks,
944 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
948 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
949 .module_offs = OMAP3430_PER_MOD,
951 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
954 .class = &omap3xxx_gpio_hwmod_class,
955 .dev_attr = &gpio_dev_attr,
959 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
960 { .role = "dbclk", .clk = "gpio3_dbck", },
963 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
966 .mpu_irqs = omap2_gpio3_irqs,
967 .main_clk = "gpio3_ick",
968 .opt_clks = gpio3_opt_clks,
969 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
973 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
974 .module_offs = OMAP3430_PER_MOD,
976 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
979 .class = &omap3xxx_gpio_hwmod_class,
980 .dev_attr = &gpio_dev_attr,
984 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
985 { .role = "dbclk", .clk = "gpio4_dbck", },
988 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
990 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
991 .mpu_irqs = omap2_gpio4_irqs,
992 .main_clk = "gpio4_ick",
993 .opt_clks = gpio4_opt_clks,
994 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
998 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
999 .module_offs = OMAP3430_PER_MOD,
1001 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1004 .class = &omap3xxx_gpio_hwmod_class,
1005 .dev_attr = &gpio_dev_attr,
1009 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1010 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1014 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1015 { .role = "dbclk", .clk = "gpio5_dbck", },
1018 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1020 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1021 .mpu_irqs = omap3xxx_gpio5_irqs,
1022 .main_clk = "gpio5_ick",
1023 .opt_clks = gpio5_opt_clks,
1024 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1028 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1029 .module_offs = OMAP3430_PER_MOD,
1031 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1034 .class = &omap3xxx_gpio_hwmod_class,
1035 .dev_attr = &gpio_dev_attr,
1039 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1040 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1044 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1045 { .role = "dbclk", .clk = "gpio6_dbck", },
1048 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1050 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1051 .mpu_irqs = omap3xxx_gpio6_irqs,
1052 .main_clk = "gpio6_ick",
1053 .opt_clks = gpio6_opt_clks,
1054 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1058 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1059 .module_offs = OMAP3430_PER_MOD,
1061 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1064 .class = &omap3xxx_gpio_hwmod_class,
1065 .dev_attr = &gpio_dev_attr,
1068 /* dma attributes */
1069 static struct omap_dma_dev_attr dma_dev_attr = {
1070 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1071 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1075 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1077 .sysc_offs = 0x002c,
1078 .syss_offs = 0x0028,
1079 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1080 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1081 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1082 SYSS_HAS_RESET_STATUS),
1083 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1084 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1085 .sysc_fields = &omap_hwmod_sysc_type1,
1088 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1090 .sysc = &omap3xxx_dma_sysc,
1094 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1096 .class = &omap3xxx_dma_hwmod_class,
1097 .mpu_irqs = omap2_dma_system_irqs,
1098 .main_clk = "core_l3_ick",
1101 .module_offs = CORE_MOD,
1103 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1105 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1108 .dev_attr = &dma_dev_attr,
1109 .flags = HWMOD_NO_IDLEST,
1114 * multi channel buffered serial port controller
1117 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1118 .sysc_offs = 0x008c,
1119 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1120 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1121 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1122 .sysc_fields = &omap_hwmod_sysc_type1,
1126 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1128 .sysc = &omap3xxx_mcbsp_sysc,
1129 .rev = MCBSP_CONFIG_TYPE3,
1132 /* McBSP functional clock mapping */
1133 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1134 { .role = "pad_fck", .clk = "mcbsp_clks" },
1135 { .role = "prcm_fck", .clk = "core_96m_fck" },
1138 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1139 { .role = "pad_fck", .clk = "mcbsp_clks" },
1140 { .role = "prcm_fck", .clk = "per_96m_fck" },
1144 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1145 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1146 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1147 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1151 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1153 .class = &omap3xxx_mcbsp_hwmod_class,
1154 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1155 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1156 .main_clk = "mcbsp1_fck",
1160 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1161 .module_offs = CORE_MOD,
1163 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1166 .opt_clks = mcbsp15_opt_clks,
1167 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1171 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1172 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1173 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1174 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1178 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1179 .sidetone = "mcbsp2_sidetone",
1182 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1184 .class = &omap3xxx_mcbsp_hwmod_class,
1185 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1186 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1187 .main_clk = "mcbsp2_fck",
1191 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1192 .module_offs = OMAP3430_PER_MOD,
1194 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1197 .opt_clks = mcbsp234_opt_clks,
1198 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1199 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1203 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1204 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1205 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1206 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1210 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1211 .sidetone = "mcbsp3_sidetone",
1214 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1216 .class = &omap3xxx_mcbsp_hwmod_class,
1217 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1218 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1219 .main_clk = "mcbsp3_fck",
1223 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1224 .module_offs = OMAP3430_PER_MOD,
1226 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1229 .opt_clks = mcbsp234_opt_clks,
1230 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1231 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1235 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1236 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1237 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1238 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1242 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1243 { .name = "rx", .dma_req = 20 },
1244 { .name = "tx", .dma_req = 19 },
1248 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1250 .class = &omap3xxx_mcbsp_hwmod_class,
1251 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1252 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1253 .main_clk = "mcbsp4_fck",
1257 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1258 .module_offs = OMAP3430_PER_MOD,
1260 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1263 .opt_clks = mcbsp234_opt_clks,
1264 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1268 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1269 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1270 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1271 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1275 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1276 { .name = "rx", .dma_req = 22 },
1277 { .name = "tx", .dma_req = 21 },
1281 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1283 .class = &omap3xxx_mcbsp_hwmod_class,
1284 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1285 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1286 .main_clk = "mcbsp5_fck",
1290 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1291 .module_offs = CORE_MOD,
1293 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1296 .opt_clks = mcbsp15_opt_clks,
1297 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1300 /* 'mcbsp sidetone' class */
1301 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1302 .sysc_offs = 0x0010,
1303 .sysc_flags = SYSC_HAS_AUTOIDLE,
1304 .sysc_fields = &omap_hwmod_sysc_type1,
1307 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1308 .name = "mcbsp_sidetone",
1309 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1312 /* mcbsp2_sidetone */
1313 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1314 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1318 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1319 .name = "mcbsp2_sidetone",
1320 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1321 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1322 .main_clk = "mcbsp2_fck",
1326 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1327 .module_offs = OMAP3430_PER_MOD,
1329 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1334 /* mcbsp3_sidetone */
1335 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1336 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1340 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1341 .name = "mcbsp3_sidetone",
1342 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1343 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1344 .main_clk = "mcbsp3_fck",
1348 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1349 .module_offs = OMAP3430_PER_MOD,
1351 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1357 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1361 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1363 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1364 .clockact = CLOCKACT_TEST_ICLK,
1365 .sysc_fields = &omap34xx_sr_sysc_fields,
1368 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1369 .name = "smartreflex",
1370 .sysc = &omap34xx_sr_sysc,
1374 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1379 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1381 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1382 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1384 .sysc_fields = &omap36xx_sr_sysc_fields,
1387 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1388 .name = "smartreflex",
1389 .sysc = &omap36xx_sr_sysc,
1394 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1395 .sensor_voltdm_name = "mpu_iva",
1398 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1399 { .irq = 18 + OMAP_INTC_START, },
1403 static struct omap_hwmod omap34xx_sr1_hwmod = {
1404 .name = "smartreflex_mpu_iva",
1405 .class = &omap34xx_smartreflex_hwmod_class,
1406 .main_clk = "sr1_fck",
1410 .module_bit = OMAP3430_EN_SR1_SHIFT,
1411 .module_offs = WKUP_MOD,
1413 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1416 .dev_attr = &sr1_dev_attr,
1417 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1418 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1421 static struct omap_hwmod omap36xx_sr1_hwmod = {
1422 .name = "smartreflex_mpu_iva",
1423 .class = &omap36xx_smartreflex_hwmod_class,
1424 .main_clk = "sr1_fck",
1428 .module_bit = OMAP3430_EN_SR1_SHIFT,
1429 .module_offs = WKUP_MOD,
1431 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1434 .dev_attr = &sr1_dev_attr,
1435 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1439 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1440 .sensor_voltdm_name = "core",
1443 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1444 { .irq = 19 + OMAP_INTC_START, },
1448 static struct omap_hwmod omap34xx_sr2_hwmod = {
1449 .name = "smartreflex_core",
1450 .class = &omap34xx_smartreflex_hwmod_class,
1451 .main_clk = "sr2_fck",
1455 .module_bit = OMAP3430_EN_SR2_SHIFT,
1456 .module_offs = WKUP_MOD,
1458 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1461 .dev_attr = &sr2_dev_attr,
1462 .mpu_irqs = omap3_smartreflex_core_irqs,
1463 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1466 static struct omap_hwmod omap36xx_sr2_hwmod = {
1467 .name = "smartreflex_core",
1468 .class = &omap36xx_smartreflex_hwmod_class,
1469 .main_clk = "sr2_fck",
1473 .module_bit = OMAP3430_EN_SR2_SHIFT,
1474 .module_offs = WKUP_MOD,
1476 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1479 .dev_attr = &sr2_dev_attr,
1480 .mpu_irqs = omap3_smartreflex_core_irqs,
1485 * mailbox module allowing communication between the on-chip processors
1486 * using a queued mailbox-interrupt mechanism.
1489 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1493 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1494 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1496 .sysc_fields = &omap_hwmod_sysc_type1,
1499 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1501 .sysc = &omap3xxx_mailbox_sysc,
1504 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1505 { .irq = 26 + OMAP_INTC_START, },
1509 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1511 .class = &omap3xxx_mailbox_hwmod_class,
1512 .mpu_irqs = omap3xxx_mailbox_irqs,
1513 .main_clk = "mailboxes_ick",
1517 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1518 .module_offs = CORE_MOD,
1520 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1527 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1531 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1533 .sysc_offs = 0x0010,
1534 .syss_offs = 0x0014,
1535 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1536 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1537 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1539 .sysc_fields = &omap_hwmod_sysc_type1,
1542 static struct omap_hwmod_class omap34xx_mcspi_class = {
1544 .sysc = &omap34xx_mcspi_sysc,
1545 .rev = OMAP3_MCSPI_REV,
1549 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1550 .num_chipselect = 4,
1553 static struct omap_hwmod omap34xx_mcspi1 = {
1555 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1556 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1557 .main_clk = "mcspi1_fck",
1560 .module_offs = CORE_MOD,
1562 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1564 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1567 .class = &omap34xx_mcspi_class,
1568 .dev_attr = &omap_mcspi1_dev_attr,
1572 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1573 .num_chipselect = 2,
1576 static struct omap_hwmod omap34xx_mcspi2 = {
1578 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1579 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1580 .main_clk = "mcspi2_fck",
1583 .module_offs = CORE_MOD,
1585 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1587 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1590 .class = &omap34xx_mcspi_class,
1591 .dev_attr = &omap_mcspi2_dev_attr,
1595 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1596 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1600 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1601 { .name = "tx0", .dma_req = 15 },
1602 { .name = "rx0", .dma_req = 16 },
1603 { .name = "tx1", .dma_req = 23 },
1604 { .name = "rx1", .dma_req = 24 },
1608 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1609 .num_chipselect = 2,
1612 static struct omap_hwmod omap34xx_mcspi3 = {
1614 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1615 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1616 .main_clk = "mcspi3_fck",
1619 .module_offs = CORE_MOD,
1621 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1623 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1626 .class = &omap34xx_mcspi_class,
1627 .dev_attr = &omap_mcspi3_dev_attr,
1631 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1632 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1636 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1637 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1638 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1642 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1643 .num_chipselect = 1,
1646 static struct omap_hwmod omap34xx_mcspi4 = {
1648 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1649 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1650 .main_clk = "mcspi4_fck",
1653 .module_offs = CORE_MOD,
1655 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1657 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1660 .class = &omap34xx_mcspi_class,
1661 .dev_attr = &omap_mcspi4_dev_attr,
1665 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1667 .sysc_offs = 0x0404,
1668 .syss_offs = 0x0408,
1669 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1670 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1672 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1673 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1674 .sysc_fields = &omap_hwmod_sysc_type1,
1677 static struct omap_hwmod_class usbotg_class = {
1679 .sysc = &omap3xxx_usbhsotg_sysc,
1683 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1685 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1686 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1690 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1691 .name = "usb_otg_hs",
1692 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1693 .main_clk = "hsotgusb_ick",
1697 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1698 .module_offs = CORE_MOD,
1700 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1701 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1704 .class = &usbotg_class,
1707 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1708 * broken when autoidle is enabled
1709 * workaround is to disable the autoidle bit at module level.
1711 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1712 | HWMOD_SWSUP_MSTANDBY,
1716 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1717 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1721 static struct omap_hwmod_class am35xx_usbotg_class = {
1722 .name = "am35xx_usbotg",
1725 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1726 .name = "am35x_otg_hs",
1727 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1728 .main_clk = "hsotgusb_fck",
1729 .class = &am35xx_usbotg_class,
1730 .flags = HWMOD_NO_IDLEST,
1733 /* MMC/SD/SDIO common */
1734 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1738 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1739 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1740 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1741 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1742 .sysc_fields = &omap_hwmod_sysc_type1,
1745 static struct omap_hwmod_class omap34xx_mmc_class = {
1747 .sysc = &omap34xx_mmc_sysc,
1752 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1753 { .irq = 83 + OMAP_INTC_START, },
1757 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1758 { .name = "tx", .dma_req = 61, },
1759 { .name = "rx", .dma_req = 62, },
1763 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1764 { .role = "dbck", .clk = "omap_32k_fck", },
1767 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1768 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1771 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1772 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1773 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1774 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1777 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1779 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1780 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1781 .opt_clks = omap34xx_mmc1_opt_clks,
1782 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1783 .main_clk = "mmchs1_fck",
1786 .module_offs = CORE_MOD,
1788 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1790 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1793 .dev_attr = &mmc1_pre_es3_dev_attr,
1794 .class = &omap34xx_mmc_class,
1797 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1799 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1800 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1801 .opt_clks = omap34xx_mmc1_opt_clks,
1802 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1803 .main_clk = "mmchs1_fck",
1806 .module_offs = CORE_MOD,
1808 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1810 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1813 .dev_attr = &mmc1_dev_attr,
1814 .class = &omap34xx_mmc_class,
1819 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1820 { .irq = 86 + OMAP_INTC_START, },
1824 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1825 { .name = "tx", .dma_req = 47, },
1826 { .name = "rx", .dma_req = 48, },
1830 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1831 { .role = "dbck", .clk = "omap_32k_fck", },
1834 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1835 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1836 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1839 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1841 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1842 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1843 .opt_clks = omap34xx_mmc2_opt_clks,
1844 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1845 .main_clk = "mmchs2_fck",
1848 .module_offs = CORE_MOD,
1850 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1852 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1855 .dev_attr = &mmc2_pre_es3_dev_attr,
1856 .class = &omap34xx_mmc_class,
1859 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1861 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1862 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1863 .opt_clks = omap34xx_mmc2_opt_clks,
1864 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1865 .main_clk = "mmchs2_fck",
1868 .module_offs = CORE_MOD,
1870 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1872 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1875 .class = &omap34xx_mmc_class,
1880 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1881 { .irq = 94 + OMAP_INTC_START, },
1885 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1886 { .name = "tx", .dma_req = 77, },
1887 { .name = "rx", .dma_req = 78, },
1891 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1892 { .role = "dbck", .clk = "omap_32k_fck", },
1895 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1897 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1898 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1899 .opt_clks = omap34xx_mmc3_opt_clks,
1900 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1901 .main_clk = "mmchs3_fck",
1905 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1907 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1910 .class = &omap34xx_mmc_class,
1914 * 'usb_host_hs' class
1915 * high-speed multi-port usb host controller
1918 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1920 .sysc_offs = 0x0010,
1921 .syss_offs = 0x0014,
1922 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1923 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1924 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1925 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1926 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1927 .sysc_fields = &omap_hwmod_sysc_type1,
1930 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1931 .name = "usb_host_hs",
1932 .sysc = &omap3xxx_usb_host_hs_sysc,
1935 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1936 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1939 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1940 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1941 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1945 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1946 .name = "usb_host_hs",
1947 .class = &omap3xxx_usb_host_hs_hwmod_class,
1948 .clkdm_name = "l3_init_clkdm",
1949 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1950 .main_clk = "usbhost_48m_fck",
1953 .module_offs = OMAP3430ES2_USBHOST_MOD,
1955 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1957 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1958 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1961 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1962 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1965 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1969 * In the following configuration :
1970 * - USBHOST module is set to smart-idle mode
1971 * - PRCM asserts idle_req to the USBHOST module ( This typically
1972 * happens when the system is going to a low power mode : all ports
1973 * have been suspended, the master part of the USBHOST module has
1974 * entered the standby state, and SW has cut the functional clocks)
1975 * - an USBHOST interrupt occurs before the module is able to answer
1976 * idle_ack, typically a remote wakeup IRQ.
1977 * Then the USB HOST module will enter a deadlock situation where it
1978 * is no more accessible nor functional.
1981 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1985 * Errata: USB host EHCI may stall when entering smart-standby mode
1989 * When the USBHOST module is set to smart-standby mode, and when it is
1990 * ready to enter the standby state (i.e. all ports are suspended and
1991 * all attached devices are in suspend mode), then it can wrongly assert
1992 * the Mstandby signal too early while there are still some residual OCP
1993 * transactions ongoing. If this condition occurs, the internal state
1994 * machine may go to an undefined state and the USB link may be stuck
1995 * upon the next resume.
1998 * Don't use smart standby; use only force standby,
1999 * hence HWMOD_SWSUP_MSTANDBY
2003 * During system boot; If the hwmod framework resets the module
2004 * the module will have smart idle settings; which can lead to deadlock
2005 * (above Errata Id:i660); so, dont reset the module during boot;
2006 * Use HWMOD_INIT_NO_RESET.
2009 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2010 HWMOD_INIT_NO_RESET,
2014 * 'usb_tll_hs' class
2015 * usb_tll_hs module is the adapter on the usb_host_hs ports
2017 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2019 .sysc_offs = 0x0010,
2020 .syss_offs = 0x0014,
2021 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2022 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2024 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2025 .sysc_fields = &omap_hwmod_sysc_type1,
2028 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2029 .name = "usb_tll_hs",
2030 .sysc = &omap3xxx_usb_tll_hs_sysc,
2033 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2034 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2038 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2039 .name = "usb_tll_hs",
2040 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2041 .clkdm_name = "l3_init_clkdm",
2042 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2043 .main_clk = "usbtll_fck",
2046 .module_offs = CORE_MOD,
2048 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2050 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2055 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2057 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2058 .main_clk = "hdq_fck",
2061 .module_offs = CORE_MOD,
2063 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2065 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2068 .class = &omap2_hdq1w_class,
2072 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2073 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2074 { .name = "rst_modem_sw", .rst_shift = 1 },
2077 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2081 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2083 .rst_lines = omap3xxx_sad2d_resets,
2084 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2085 .main_clk = "sad2d_ick",
2088 .module_offs = CORE_MOD,
2090 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2092 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2095 .class = &omap3xxx_sad2d_class,
2099 * '32K sync counter' class
2100 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2102 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2104 .sysc_offs = 0x0004,
2105 .sysc_flags = SYSC_HAS_SIDLEMODE,
2106 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2107 .sysc_fields = &omap_hwmod_sysc_type1,
2110 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2112 .sysc = &omap3xxx_counter_sysc,
2115 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2116 .name = "counter_32k",
2117 .class = &omap3xxx_counter_hwmod_class,
2118 .clkdm_name = "wkup_clkdm",
2119 .flags = HWMOD_SWSUP_SIDLE,
2120 .main_clk = "wkup_32k_fck",
2123 .module_offs = WKUP_MOD,
2125 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2127 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2134 * general purpose memory controller
2137 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2139 .sysc_offs = 0x0010,
2140 .syss_offs = 0x0014,
2141 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2142 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2144 .sysc_fields = &omap_hwmod_sysc_type1,
2147 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2149 .sysc = &omap3xxx_gpmc_sysc,
2152 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2157 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2159 .class = &omap3xxx_gpmc_hwmod_class,
2160 .clkdm_name = "core_l3_clkdm",
2161 .mpu_irqs = omap3xxx_gpmc_irqs,
2162 .main_clk = "gpmc_fck",
2164 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2165 * block. It is not being added due to any known bugs with
2166 * resetting the GPMC IP block, but rather because any timings
2167 * set by the bootloader are not being correctly programmed by
2168 * the kernel from the board file or DT data.
2169 * HWMOD_INIT_NO_RESET should be removed ASAP.
2171 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2179 /* L3 -> L4_CORE interface */
2180 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2181 .master = &omap3xxx_l3_main_hwmod,
2182 .slave = &omap3xxx_l4_core_hwmod,
2183 .user = OCP_USER_MPU | OCP_USER_SDMA,
2186 /* L3 -> L4_PER interface */
2187 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2188 .master = &omap3xxx_l3_main_hwmod,
2189 .slave = &omap3xxx_l4_per_hwmod,
2190 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2195 .pa_start = 0x68000000,
2196 .pa_end = 0x6800ffff,
2197 .flags = ADDR_TYPE_RT,
2202 /* MPU -> L3 interface */
2203 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2204 .master = &omap3xxx_mpu_hwmod,
2205 .slave = &omap3xxx_l3_main_hwmod,
2206 .addr = omap3xxx_l3_main_addrs,
2207 .user = OCP_USER_MPU,
2210 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2212 .pa_start = 0x54000000,
2213 .pa_end = 0x547fffff,
2214 .flags = ADDR_TYPE_RT,
2220 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2221 .master = &omap3xxx_l3_main_hwmod,
2222 .slave = &omap3xxx_debugss_hwmod,
2223 .addr = omap3xxx_l4_emu_addrs,
2224 .user = OCP_USER_MPU,
2228 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2229 .master = &omap3430es1_dss_core_hwmod,
2230 .slave = &omap3xxx_l3_main_hwmod,
2231 .user = OCP_USER_MPU | OCP_USER_SDMA,
2234 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2235 .master = &omap3xxx_dss_core_hwmod,
2236 .slave = &omap3xxx_l3_main_hwmod,
2239 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2240 .flags = OMAP_FIREWALL_L3,
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246 /* l3_core -> usbhsotg interface */
2247 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2248 .master = &omap3xxx_usbhsotg_hwmod,
2249 .slave = &omap3xxx_l3_main_hwmod,
2250 .clk = "core_l3_ick",
2251 .user = OCP_USER_MPU,
2254 /* l3_core -> am35xx_usbhsotg interface */
2255 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2256 .master = &am35xx_usbhsotg_hwmod,
2257 .slave = &omap3xxx_l3_main_hwmod,
2258 .clk = "hsotgusb_ick",
2259 .user = OCP_USER_MPU,
2262 /* l3_core -> sad2d interface */
2263 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2264 .master = &omap3xxx_sad2d_hwmod,
2265 .slave = &omap3xxx_l3_main_hwmod,
2266 .clk = "core_l3_ick",
2267 .user = OCP_USER_MPU,
2270 /* L4_CORE -> L4_WKUP interface */
2271 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2272 .master = &omap3xxx_l4_core_hwmod,
2273 .slave = &omap3xxx_l4_wkup_hwmod,
2274 .user = OCP_USER_MPU | OCP_USER_SDMA,
2277 /* L4 CORE -> MMC1 interface */
2278 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2279 .master = &omap3xxx_l4_core_hwmod,
2280 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2281 .clk = "mmchs1_ick",
2282 .addr = omap2430_mmc1_addr_space,
2283 .user = OCP_USER_MPU | OCP_USER_SDMA,
2284 .flags = OMAP_FIREWALL_L4
2287 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2288 .master = &omap3xxx_l4_core_hwmod,
2289 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2290 .clk = "mmchs1_ick",
2291 .addr = omap2430_mmc1_addr_space,
2292 .user = OCP_USER_MPU | OCP_USER_SDMA,
2293 .flags = OMAP_FIREWALL_L4
2296 /* L4 CORE -> MMC2 interface */
2297 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2298 .master = &omap3xxx_l4_core_hwmod,
2299 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2300 .clk = "mmchs2_ick",
2301 .addr = omap2430_mmc2_addr_space,
2302 .user = OCP_USER_MPU | OCP_USER_SDMA,
2303 .flags = OMAP_FIREWALL_L4
2306 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2307 .master = &omap3xxx_l4_core_hwmod,
2308 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2309 .clk = "mmchs2_ick",
2310 .addr = omap2430_mmc2_addr_space,
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312 .flags = OMAP_FIREWALL_L4
2315 /* L4 CORE -> MMC3 interface */
2316 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2318 .pa_start = 0x480ad000,
2319 .pa_end = 0x480ad1ff,
2320 .flags = ADDR_TYPE_RT,
2325 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2326 .master = &omap3xxx_l4_core_hwmod,
2327 .slave = &omap3xxx_mmc3_hwmod,
2328 .clk = "mmchs3_ick",
2329 .addr = omap3xxx_mmc3_addr_space,
2330 .user = OCP_USER_MPU | OCP_USER_SDMA,
2331 .flags = OMAP_FIREWALL_L4
2334 /* L4 CORE -> UART1 interface */
2335 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2337 .pa_start = OMAP3_UART1_BASE,
2338 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2339 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2344 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2345 .master = &omap3xxx_l4_core_hwmod,
2346 .slave = &omap3xxx_uart1_hwmod,
2348 .addr = omap3xxx_uart1_addr_space,
2349 .user = OCP_USER_MPU | OCP_USER_SDMA,
2352 /* L4 CORE -> UART2 interface */
2353 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2355 .pa_start = OMAP3_UART2_BASE,
2356 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2357 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2362 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2363 .master = &omap3xxx_l4_core_hwmod,
2364 .slave = &omap3xxx_uart2_hwmod,
2366 .addr = omap3xxx_uart2_addr_space,
2367 .user = OCP_USER_MPU | OCP_USER_SDMA,
2370 /* L4 PER -> UART3 interface */
2371 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2373 .pa_start = OMAP3_UART3_BASE,
2374 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2375 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2380 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2381 .master = &omap3xxx_l4_per_hwmod,
2382 .slave = &omap3xxx_uart3_hwmod,
2384 .addr = omap3xxx_uart3_addr_space,
2385 .user = OCP_USER_MPU | OCP_USER_SDMA,
2388 /* L4 PER -> UART4 interface */
2389 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2391 .pa_start = OMAP3_UART4_BASE,
2392 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2393 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2398 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2399 .master = &omap3xxx_l4_per_hwmod,
2400 .slave = &omap36xx_uart4_hwmod,
2402 .addr = omap36xx_uart4_addr_space,
2403 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406 /* AM35xx: L4 CORE -> UART4 interface */
2407 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2409 .pa_start = OMAP3_UART4_AM35XX_BASE,
2410 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2411 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2416 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2417 .master = &omap3xxx_l4_core_hwmod,
2418 .slave = &am35xx_uart4_hwmod,
2420 .addr = am35xx_uart4_addr_space,
2421 .user = OCP_USER_MPU | OCP_USER_SDMA,
2424 /* L4 CORE -> I2C1 interface */
2425 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2426 .master = &omap3xxx_l4_core_hwmod,
2427 .slave = &omap3xxx_i2c1_hwmod,
2429 .addr = omap2_i2c1_addr_space,
2432 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2434 .flags = OMAP_FIREWALL_L4,
2437 .user = OCP_USER_MPU | OCP_USER_SDMA,
2440 /* L4 CORE -> I2C2 interface */
2441 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2442 .master = &omap3xxx_l4_core_hwmod,
2443 .slave = &omap3xxx_i2c2_hwmod,
2445 .addr = omap2_i2c2_addr_space,
2448 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2450 .flags = OMAP_FIREWALL_L4,
2453 .user = OCP_USER_MPU | OCP_USER_SDMA,
2456 /* L4 CORE -> I2C3 interface */
2457 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2459 .pa_start = 0x48060000,
2460 .pa_end = 0x48060000 + SZ_128 - 1,
2461 .flags = ADDR_TYPE_RT,
2466 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2467 .master = &omap3xxx_l4_core_hwmod,
2468 .slave = &omap3xxx_i2c3_hwmod,
2470 .addr = omap3xxx_i2c3_addr_space,
2473 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2475 .flags = OMAP_FIREWALL_L4,
2478 .user = OCP_USER_MPU | OCP_USER_SDMA,
2481 /* L4 CORE -> SR1 interface */
2482 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2484 .pa_start = OMAP34XX_SR1_BASE,
2485 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2486 .flags = ADDR_TYPE_RT,
2491 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2492 .master = &omap3xxx_l4_core_hwmod,
2493 .slave = &omap34xx_sr1_hwmod,
2495 .addr = omap3_sr1_addr_space,
2496 .user = OCP_USER_MPU,
2499 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2500 .master = &omap3xxx_l4_core_hwmod,
2501 .slave = &omap36xx_sr1_hwmod,
2503 .addr = omap3_sr1_addr_space,
2504 .user = OCP_USER_MPU,
2507 /* L4 CORE -> SR1 interface */
2508 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2510 .pa_start = OMAP34XX_SR2_BASE,
2511 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2512 .flags = ADDR_TYPE_RT,
2517 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2518 .master = &omap3xxx_l4_core_hwmod,
2519 .slave = &omap34xx_sr2_hwmod,
2521 .addr = omap3_sr2_addr_space,
2522 .user = OCP_USER_MPU,
2525 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2526 .master = &omap3xxx_l4_core_hwmod,
2527 .slave = &omap36xx_sr2_hwmod,
2529 .addr = omap3_sr2_addr_space,
2530 .user = OCP_USER_MPU,
2533 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2535 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2536 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2537 .flags = ADDR_TYPE_RT
2542 /* l4_core -> usbhsotg */
2543 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2544 .master = &omap3xxx_l4_core_hwmod,
2545 .slave = &omap3xxx_usbhsotg_hwmod,
2547 .addr = omap3xxx_usbhsotg_addrs,
2548 .user = OCP_USER_MPU,
2551 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2553 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2554 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2555 .flags = ADDR_TYPE_RT
2560 /* l4_core -> usbhsotg */
2561 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2562 .master = &omap3xxx_l4_core_hwmod,
2563 .slave = &am35xx_usbhsotg_hwmod,
2564 .clk = "hsotgusb_ick",
2565 .addr = am35xx_usbhsotg_addrs,
2566 .user = OCP_USER_MPU,
2569 /* L4_WKUP -> L4_SEC interface */
2570 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2571 .master = &omap3xxx_l4_wkup_hwmod,
2572 .slave = &omap3xxx_l4_sec_hwmod,
2573 .user = OCP_USER_MPU | OCP_USER_SDMA,
2576 /* IVA2 <- L3 interface */
2577 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2578 .master = &omap3xxx_l3_main_hwmod,
2579 .slave = &omap3xxx_iva_hwmod,
2580 .clk = "core_l3_ick",
2581 .user = OCP_USER_MPU | OCP_USER_SDMA,
2584 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2586 .pa_start = 0x48318000,
2587 .pa_end = 0x48318000 + SZ_1K - 1,
2588 .flags = ADDR_TYPE_RT
2593 /* l4_wkup -> timer1 */
2594 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2595 .master = &omap3xxx_l4_wkup_hwmod,
2596 .slave = &omap3xxx_timer1_hwmod,
2598 .addr = omap3xxx_timer1_addrs,
2599 .user = OCP_USER_MPU | OCP_USER_SDMA,
2602 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2604 .pa_start = 0x49032000,
2605 .pa_end = 0x49032000 + SZ_1K - 1,
2606 .flags = ADDR_TYPE_RT
2611 /* l4_per -> timer2 */
2612 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2613 .master = &omap3xxx_l4_per_hwmod,
2614 .slave = &omap3xxx_timer2_hwmod,
2616 .addr = omap3xxx_timer2_addrs,
2617 .user = OCP_USER_MPU | OCP_USER_SDMA,
2620 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2622 .pa_start = 0x49034000,
2623 .pa_end = 0x49034000 + SZ_1K - 1,
2624 .flags = ADDR_TYPE_RT
2629 /* l4_per -> timer3 */
2630 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2631 .master = &omap3xxx_l4_per_hwmod,
2632 .slave = &omap3xxx_timer3_hwmod,
2634 .addr = omap3xxx_timer3_addrs,
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2638 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2640 .pa_start = 0x49036000,
2641 .pa_end = 0x49036000 + SZ_1K - 1,
2642 .flags = ADDR_TYPE_RT
2647 /* l4_per -> timer4 */
2648 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2649 .master = &omap3xxx_l4_per_hwmod,
2650 .slave = &omap3xxx_timer4_hwmod,
2652 .addr = omap3xxx_timer4_addrs,
2653 .user = OCP_USER_MPU | OCP_USER_SDMA,
2656 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2658 .pa_start = 0x49038000,
2659 .pa_end = 0x49038000 + SZ_1K - 1,
2660 .flags = ADDR_TYPE_RT
2665 /* l4_per -> timer5 */
2666 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2667 .master = &omap3xxx_l4_per_hwmod,
2668 .slave = &omap3xxx_timer5_hwmod,
2670 .addr = omap3xxx_timer5_addrs,
2671 .user = OCP_USER_MPU | OCP_USER_SDMA,
2674 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2676 .pa_start = 0x4903A000,
2677 .pa_end = 0x4903A000 + SZ_1K - 1,
2678 .flags = ADDR_TYPE_RT
2683 /* l4_per -> timer6 */
2684 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2685 .master = &omap3xxx_l4_per_hwmod,
2686 .slave = &omap3xxx_timer6_hwmod,
2688 .addr = omap3xxx_timer6_addrs,
2689 .user = OCP_USER_MPU | OCP_USER_SDMA,
2692 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2694 .pa_start = 0x4903C000,
2695 .pa_end = 0x4903C000 + SZ_1K - 1,
2696 .flags = ADDR_TYPE_RT
2701 /* l4_per -> timer7 */
2702 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2703 .master = &omap3xxx_l4_per_hwmod,
2704 .slave = &omap3xxx_timer7_hwmod,
2706 .addr = omap3xxx_timer7_addrs,
2707 .user = OCP_USER_MPU | OCP_USER_SDMA,
2710 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2712 .pa_start = 0x4903E000,
2713 .pa_end = 0x4903E000 + SZ_1K - 1,
2714 .flags = ADDR_TYPE_RT
2719 /* l4_per -> timer8 */
2720 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2721 .master = &omap3xxx_l4_per_hwmod,
2722 .slave = &omap3xxx_timer8_hwmod,
2724 .addr = omap3xxx_timer8_addrs,
2725 .user = OCP_USER_MPU | OCP_USER_SDMA,
2728 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2730 .pa_start = 0x49040000,
2731 .pa_end = 0x49040000 + SZ_1K - 1,
2732 .flags = ADDR_TYPE_RT
2737 /* l4_per -> timer9 */
2738 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2739 .master = &omap3xxx_l4_per_hwmod,
2740 .slave = &omap3xxx_timer9_hwmod,
2742 .addr = omap3xxx_timer9_addrs,
2743 .user = OCP_USER_MPU | OCP_USER_SDMA,
2746 /* l4_core -> timer10 */
2747 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2748 .master = &omap3xxx_l4_core_hwmod,
2749 .slave = &omap3xxx_timer10_hwmod,
2751 .addr = omap2_timer10_addrs,
2752 .user = OCP_USER_MPU | OCP_USER_SDMA,
2755 /* l4_core -> timer11 */
2756 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2757 .master = &omap3xxx_l4_core_hwmod,
2758 .slave = &omap3xxx_timer11_hwmod,
2760 .addr = omap2_timer11_addrs,
2761 .user = OCP_USER_MPU | OCP_USER_SDMA,
2764 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2766 .pa_start = 0x48304000,
2767 .pa_end = 0x48304000 + SZ_1K - 1,
2768 .flags = ADDR_TYPE_RT
2773 /* l4_core -> timer12 */
2774 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2775 .master = &omap3xxx_l4_sec_hwmod,
2776 .slave = &omap3xxx_timer12_hwmod,
2778 .addr = omap3xxx_timer12_addrs,
2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
2782 /* l4_wkup -> wd_timer2 */
2783 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2785 .pa_start = 0x48314000,
2786 .pa_end = 0x4831407f,
2787 .flags = ADDR_TYPE_RT
2792 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2793 .master = &omap3xxx_l4_wkup_hwmod,
2794 .slave = &omap3xxx_wd_timer2_hwmod,
2796 .addr = omap3xxx_wd_timer2_addrs,
2797 .user = OCP_USER_MPU | OCP_USER_SDMA,
2800 /* l4_core -> dss */
2801 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2802 .master = &omap3xxx_l4_core_hwmod,
2803 .slave = &omap3430es1_dss_core_hwmod,
2805 .addr = omap2_dss_addrs,
2808 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2809 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2810 .flags = OMAP_FIREWALL_L4,
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2816 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2817 .master = &omap3xxx_l4_core_hwmod,
2818 .slave = &omap3xxx_dss_core_hwmod,
2820 .addr = omap2_dss_addrs,
2823 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2824 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2825 .flags = OMAP_FIREWALL_L4,
2828 .user = OCP_USER_MPU | OCP_USER_SDMA,
2831 /* l4_core -> dss_dispc */
2832 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2833 .master = &omap3xxx_l4_core_hwmod,
2834 .slave = &omap3xxx_dss_dispc_hwmod,
2836 .addr = omap2_dss_dispc_addrs,
2839 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2840 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2841 .flags = OMAP_FIREWALL_L4,
2844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2849 .pa_start = 0x4804FC00,
2850 .pa_end = 0x4804FFFF,
2851 .flags = ADDR_TYPE_RT
2856 /* l4_core -> dss_dsi1 */
2857 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2858 .master = &omap3xxx_l4_core_hwmod,
2859 .slave = &omap3xxx_dss_dsi1_hwmod,
2861 .addr = omap3xxx_dss_dsi1_addrs,
2864 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2865 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2866 .flags = OMAP_FIREWALL_L4,
2869 .user = OCP_USER_MPU | OCP_USER_SDMA,
2872 /* l4_core -> dss_rfbi */
2873 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2874 .master = &omap3xxx_l4_core_hwmod,
2875 .slave = &omap3xxx_dss_rfbi_hwmod,
2877 .addr = omap2_dss_rfbi_addrs,
2880 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2881 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2882 .flags = OMAP_FIREWALL_L4,
2885 .user = OCP_USER_MPU | OCP_USER_SDMA,
2888 /* l4_core -> dss_venc */
2889 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2890 .master = &omap3xxx_l4_core_hwmod,
2891 .slave = &omap3xxx_dss_venc_hwmod,
2893 .addr = omap2_dss_venc_addrs,
2896 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2897 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2898 .flags = OMAP_FIREWALL_L4,
2901 .flags = OCPIF_SWSUP_IDLE,
2902 .user = OCP_USER_MPU | OCP_USER_SDMA,
2905 /* l4_wkup -> gpio1 */
2906 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2908 .pa_start = 0x48310000,
2909 .pa_end = 0x483101ff,
2910 .flags = ADDR_TYPE_RT
2915 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2916 .master = &omap3xxx_l4_wkup_hwmod,
2917 .slave = &omap3xxx_gpio1_hwmod,
2918 .addr = omap3xxx_gpio1_addrs,
2919 .user = OCP_USER_MPU | OCP_USER_SDMA,
2922 /* l4_per -> gpio2 */
2923 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2925 .pa_start = 0x49050000,
2926 .pa_end = 0x490501ff,
2927 .flags = ADDR_TYPE_RT
2932 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2933 .master = &omap3xxx_l4_per_hwmod,
2934 .slave = &omap3xxx_gpio2_hwmod,
2935 .addr = omap3xxx_gpio2_addrs,
2936 .user = OCP_USER_MPU | OCP_USER_SDMA,
2939 /* l4_per -> gpio3 */
2940 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2942 .pa_start = 0x49052000,
2943 .pa_end = 0x490521ff,
2944 .flags = ADDR_TYPE_RT
2949 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2950 .master = &omap3xxx_l4_per_hwmod,
2951 .slave = &omap3xxx_gpio3_hwmod,
2952 .addr = omap3xxx_gpio3_addrs,
2953 .user = OCP_USER_MPU | OCP_USER_SDMA,
2958 * The memory management unit performs virtual to physical address translation
2959 * for its requestors.
2962 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2966 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2967 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2968 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2969 .sysc_fields = &omap_hwmod_sysc_type1,
2972 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2979 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2981 .da_end = 0xfffff000,
2982 .nr_tlb_entries = 8,
2985 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2986 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2991 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2993 .pa_start = 0x480bd400,
2994 .pa_end = 0x480bd47f,
2995 .flags = ADDR_TYPE_RT,
3000 /* l4_core -> mmu isp */
3001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3002 .master = &omap3xxx_l4_core_hwmod,
3003 .slave = &omap3xxx_mmu_isp_hwmod,
3004 .addr = omap3xxx_mmu_isp_addrs,
3005 .user = OCP_USER_MPU | OCP_USER_SDMA,
3008 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3010 .class = &omap3xxx_mmu_hwmod_class,
3011 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3012 .main_clk = "cam_ick",
3013 .dev_attr = &mmu_isp_dev_attr,
3014 .flags = HWMOD_NO_IDLEST,
3017 #ifdef CONFIG_OMAP_IOMMU_IVA2
3021 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3022 .da_start = 0x11000000,
3023 .da_end = 0xfffff000,
3024 .nr_tlb_entries = 32,
3027 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3028 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3033 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3034 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3037 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3039 .pa_start = 0x5d000000,
3040 .pa_end = 0x5d00007f,
3041 .flags = ADDR_TYPE_RT,
3046 /* l3_main -> iva mmu */
3047 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3048 .master = &omap3xxx_l3_main_hwmod,
3049 .slave = &omap3xxx_mmu_iva_hwmod,
3050 .addr = omap3xxx_mmu_iva_addrs,
3051 .user = OCP_USER_MPU | OCP_USER_SDMA,
3054 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3056 .class = &omap3xxx_mmu_hwmod_class,
3057 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3058 .rst_lines = omap3xxx_mmu_iva_resets,
3059 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3060 .main_clk = "iva2_ck",
3063 .module_offs = OMAP3430_IVA2_MOD,
3066 .dev_attr = &mmu_iva_dev_attr,
3067 .flags = HWMOD_NO_IDLEST,
3072 /* l4_per -> gpio4 */
3073 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3075 .pa_start = 0x49054000,
3076 .pa_end = 0x490541ff,
3077 .flags = ADDR_TYPE_RT
3082 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3083 .master = &omap3xxx_l4_per_hwmod,
3084 .slave = &omap3xxx_gpio4_hwmod,
3085 .addr = omap3xxx_gpio4_addrs,
3086 .user = OCP_USER_MPU | OCP_USER_SDMA,
3089 /* l4_per -> gpio5 */
3090 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3092 .pa_start = 0x49056000,
3093 .pa_end = 0x490561ff,
3094 .flags = ADDR_TYPE_RT
3099 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3100 .master = &omap3xxx_l4_per_hwmod,
3101 .slave = &omap3xxx_gpio5_hwmod,
3102 .addr = omap3xxx_gpio5_addrs,
3103 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106 /* l4_per -> gpio6 */
3107 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3109 .pa_start = 0x49058000,
3110 .pa_end = 0x490581ff,
3111 .flags = ADDR_TYPE_RT
3116 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3117 .master = &omap3xxx_l4_per_hwmod,
3118 .slave = &omap3xxx_gpio6_hwmod,
3119 .addr = omap3xxx_gpio6_addrs,
3120 .user = OCP_USER_MPU | OCP_USER_SDMA,
3123 /* dma_system -> L3 */
3124 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3125 .master = &omap3xxx_dma_system_hwmod,
3126 .slave = &omap3xxx_l3_main_hwmod,
3127 .clk = "core_l3_ick",
3128 .user = OCP_USER_MPU | OCP_USER_SDMA,
3131 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3133 .pa_start = 0x48056000,
3134 .pa_end = 0x48056fff,
3135 .flags = ADDR_TYPE_RT
3140 /* l4_cfg -> dma_system */
3141 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3142 .master = &omap3xxx_l4_core_hwmod,
3143 .slave = &omap3xxx_dma_system_hwmod,
3144 .clk = "core_l4_ick",
3145 .addr = omap3xxx_dma_system_addrs,
3146 .user = OCP_USER_MPU | OCP_USER_SDMA,
3149 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3152 .pa_start = 0x48074000,
3153 .pa_end = 0x480740ff,
3154 .flags = ADDR_TYPE_RT
3159 /* l4_core -> mcbsp1 */
3160 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3161 .master = &omap3xxx_l4_core_hwmod,
3162 .slave = &omap3xxx_mcbsp1_hwmod,
3163 .clk = "mcbsp1_ick",
3164 .addr = omap3xxx_mcbsp1_addrs,
3165 .user = OCP_USER_MPU | OCP_USER_SDMA,
3168 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3171 .pa_start = 0x49022000,
3172 .pa_end = 0x490220ff,
3173 .flags = ADDR_TYPE_RT
3178 /* l4_per -> mcbsp2 */
3179 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3180 .master = &omap3xxx_l4_per_hwmod,
3181 .slave = &omap3xxx_mcbsp2_hwmod,
3182 .clk = "mcbsp2_ick",
3183 .addr = omap3xxx_mcbsp2_addrs,
3184 .user = OCP_USER_MPU | OCP_USER_SDMA,
3187 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3190 .pa_start = 0x49024000,
3191 .pa_end = 0x490240ff,
3192 .flags = ADDR_TYPE_RT
3197 /* l4_per -> mcbsp3 */
3198 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3199 .master = &omap3xxx_l4_per_hwmod,
3200 .slave = &omap3xxx_mcbsp3_hwmod,
3201 .clk = "mcbsp3_ick",
3202 .addr = omap3xxx_mcbsp3_addrs,
3203 .user = OCP_USER_MPU | OCP_USER_SDMA,
3206 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3209 .pa_start = 0x49026000,
3210 .pa_end = 0x490260ff,
3211 .flags = ADDR_TYPE_RT
3216 /* l4_per -> mcbsp4 */
3217 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3218 .master = &omap3xxx_l4_per_hwmod,
3219 .slave = &omap3xxx_mcbsp4_hwmod,
3220 .clk = "mcbsp4_ick",
3221 .addr = omap3xxx_mcbsp4_addrs,
3222 .user = OCP_USER_MPU | OCP_USER_SDMA,
3225 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3228 .pa_start = 0x48096000,
3229 .pa_end = 0x480960ff,
3230 .flags = ADDR_TYPE_RT
3235 /* l4_core -> mcbsp5 */
3236 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3237 .master = &omap3xxx_l4_core_hwmod,
3238 .slave = &omap3xxx_mcbsp5_hwmod,
3239 .clk = "mcbsp5_ick",
3240 .addr = omap3xxx_mcbsp5_addrs,
3241 .user = OCP_USER_MPU | OCP_USER_SDMA,
3244 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3247 .pa_start = 0x49028000,
3248 .pa_end = 0x490280ff,
3249 .flags = ADDR_TYPE_RT
3254 /* l4_per -> mcbsp2_sidetone */
3255 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3256 .master = &omap3xxx_l4_per_hwmod,
3257 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3258 .clk = "mcbsp2_ick",
3259 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3260 .user = OCP_USER_MPU,
3263 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3266 .pa_start = 0x4902A000,
3267 .pa_end = 0x4902A0ff,
3268 .flags = ADDR_TYPE_RT
3273 /* l4_per -> mcbsp3_sidetone */
3274 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3275 .master = &omap3xxx_l4_per_hwmod,
3276 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3277 .clk = "mcbsp3_ick",
3278 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3279 .user = OCP_USER_MPU,
3282 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3284 .pa_start = 0x48094000,
3285 .pa_end = 0x480941ff,
3286 .flags = ADDR_TYPE_RT,
3291 /* l4_core -> mailbox */
3292 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3293 .master = &omap3xxx_l4_core_hwmod,
3294 .slave = &omap3xxx_mailbox_hwmod,
3295 .addr = omap3xxx_mailbox_addrs,
3296 .user = OCP_USER_MPU | OCP_USER_SDMA,
3299 /* l4 core -> mcspi1 interface */
3300 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3301 .master = &omap3xxx_l4_core_hwmod,
3302 .slave = &omap34xx_mcspi1,
3303 .clk = "mcspi1_ick",
3304 .addr = omap2_mcspi1_addr_space,
3305 .user = OCP_USER_MPU | OCP_USER_SDMA,
3308 /* l4 core -> mcspi2 interface */
3309 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3310 .master = &omap3xxx_l4_core_hwmod,
3311 .slave = &omap34xx_mcspi2,
3312 .clk = "mcspi2_ick",
3313 .addr = omap2_mcspi2_addr_space,
3314 .user = OCP_USER_MPU | OCP_USER_SDMA,
3317 /* l4 core -> mcspi3 interface */
3318 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3319 .master = &omap3xxx_l4_core_hwmod,
3320 .slave = &omap34xx_mcspi3,
3321 .clk = "mcspi3_ick",
3322 .addr = omap2430_mcspi3_addr_space,
3323 .user = OCP_USER_MPU | OCP_USER_SDMA,
3326 /* l4 core -> mcspi4 interface */
3327 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3329 .pa_start = 0x480ba000,
3330 .pa_end = 0x480ba0ff,
3331 .flags = ADDR_TYPE_RT,
3336 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3337 .master = &omap3xxx_l4_core_hwmod,
3338 .slave = &omap34xx_mcspi4,
3339 .clk = "mcspi4_ick",
3340 .addr = omap34xx_mcspi4_addr_space,
3341 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3345 .master = &omap3xxx_usb_host_hs_hwmod,
3346 .slave = &omap3xxx_l3_main_hwmod,
3347 .clk = "core_l3_ick",
3348 .user = OCP_USER_MPU,
3351 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3354 .pa_start = 0x48064000,
3355 .pa_end = 0x480643ff,
3356 .flags = ADDR_TYPE_RT
3360 .pa_start = 0x48064400,
3361 .pa_end = 0x480647ff,
3365 .pa_start = 0x48064800,
3366 .pa_end = 0x48064cff,
3371 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3372 .master = &omap3xxx_l4_core_hwmod,
3373 .slave = &omap3xxx_usb_host_hs_hwmod,
3374 .clk = "usbhost_ick",
3375 .addr = omap3xxx_usb_host_hs_addrs,
3376 .user = OCP_USER_MPU | OCP_USER_SDMA,
3379 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3382 .pa_start = 0x48062000,
3383 .pa_end = 0x48062fff,
3384 .flags = ADDR_TYPE_RT
3389 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3390 .master = &omap3xxx_l4_core_hwmod,
3391 .slave = &omap3xxx_usb_tll_hs_hwmod,
3392 .clk = "usbtll_ick",
3393 .addr = omap3xxx_usb_tll_hs_addrs,
3394 .user = OCP_USER_MPU | OCP_USER_SDMA,
3397 /* l4_core -> hdq1w interface */
3398 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3399 .master = &omap3xxx_l4_core_hwmod,
3400 .slave = &omap3xxx_hdq1w_hwmod,
3402 .addr = omap2_hdq1w_addr_space,
3403 .user = OCP_USER_MPU | OCP_USER_SDMA,
3404 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3407 /* l4_wkup -> 32ksync_counter */
3408 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3410 .pa_start = 0x48320000,
3411 .pa_end = 0x4832001f,
3412 .flags = ADDR_TYPE_RT
3417 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3419 .pa_start = 0x6e000000,
3420 .pa_end = 0x6e000fff,
3421 .flags = ADDR_TYPE_RT
3426 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3427 .master = &omap3xxx_l4_wkup_hwmod,
3428 .slave = &omap3xxx_counter_32k_hwmod,
3429 .clk = "omap_32ksync_ick",
3430 .addr = omap3xxx_counter_32k_addrs,
3431 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434 /* am35xx has Davinci MDIO & EMAC */
3435 static struct omap_hwmod_class am35xx_mdio_class = {
3436 .name = "davinci_mdio",
3439 static struct omap_hwmod am35xx_mdio_hwmod = {
3440 .name = "davinci_mdio",
3441 .class = &am35xx_mdio_class,
3442 .flags = HWMOD_NO_IDLEST,
3446 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3447 * but this will probably require some additional hwmod core support,
3448 * so is left as a future to-do item.
3450 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3451 .master = &am35xx_mdio_hwmod,
3452 .slave = &omap3xxx_l3_main_hwmod,
3454 .user = OCP_USER_MPU,
3457 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3459 .pa_start = AM35XX_IPSS_MDIO_BASE,
3460 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3461 .flags = ADDR_TYPE_RT,
3466 /* l4_core -> davinci mdio */
3468 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3469 * but this will probably require some additional hwmod core support,
3470 * so is left as a future to-do item.
3472 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3473 .master = &omap3xxx_l4_core_hwmod,
3474 .slave = &am35xx_mdio_hwmod,
3476 .addr = am35xx_mdio_addrs,
3477 .user = OCP_USER_MPU,
3480 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3481 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3482 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3483 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3484 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3488 static struct omap_hwmod_class am35xx_emac_class = {
3489 .name = "davinci_emac",
3492 static struct omap_hwmod am35xx_emac_hwmod = {
3493 .name = "davinci_emac",
3494 .mpu_irqs = am35xx_emac_mpu_irqs,
3495 .class = &am35xx_emac_class,
3497 * According to Mark Greer, the MPU will not return from WFI
3498 * when the EMAC signals an interrupt.
3499 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3501 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3504 /* l3_core -> davinci emac interface */
3506 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3507 * but this will probably require some additional hwmod core support,
3508 * so is left as a future to-do item.
3510 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3511 .master = &am35xx_emac_hwmod,
3512 .slave = &omap3xxx_l3_main_hwmod,
3514 .user = OCP_USER_MPU,
3517 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3519 .pa_start = AM35XX_IPSS_EMAC_BASE,
3520 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3521 .flags = ADDR_TYPE_RT,
3526 /* l4_core -> davinci emac */
3528 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3529 * but this will probably require some additional hwmod core support,
3530 * so is left as a future to-do item.
3532 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3533 .master = &omap3xxx_l4_core_hwmod,
3534 .slave = &am35xx_emac_hwmod,
3536 .addr = am35xx_emac_addrs,
3537 .user = OCP_USER_MPU,
3540 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3541 .master = &omap3xxx_l3_main_hwmod,
3542 .slave = &omap3xxx_gpmc_hwmod,
3543 .clk = "core_l3_ick",
3544 .addr = omap3xxx_gpmc_addrs,
3545 .user = OCP_USER_MPU | OCP_USER_SDMA,
3548 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3549 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3552 .autoidle_shift = 0,
3555 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3559 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3560 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3561 .sysc_fields = &omap3_sham_sysc_fields,
3564 static struct omap_hwmod_class omap3xxx_sham_class = {
3566 .sysc = &omap3_sham_sysc,
3569 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3570 { .irq = 49 + OMAP_INTC_START, },
3574 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3575 { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
3579 static struct omap_hwmod omap3xxx_sham_hwmod = {
3581 .mpu_irqs = omap3_sham_mpu_irqs,
3582 .sdma_reqs = omap3_sham_sdma_reqs,
3583 .main_clk = "sha12_ick",
3586 .module_offs = CORE_MOD,
3588 .module_bit = OMAP3430_EN_SHA12_SHIFT,
3590 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3593 .class = &omap3xxx_sham_class,
3596 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3598 .pa_start = 0x480c3000,
3599 .pa_end = 0x480c3000 + 0x64 - 1,
3600 .flags = ADDR_TYPE_RT
3605 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3606 .master = &omap3xxx_l4_core_hwmod,
3607 .slave = &omap3xxx_sham_hwmod,
3609 .addr = omap3xxx_sham_addrs,
3610 .user = OCP_USER_MPU | OCP_USER_SDMA,
3613 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3614 &omap3xxx_l3_main__l4_core,
3615 &omap3xxx_l3_main__l4_per,
3616 &omap3xxx_mpu__l3_main,
3617 &omap3xxx_l3_main__l4_debugss,
3618 &omap3xxx_l4_core__l4_wkup,
3619 &omap3xxx_l4_core__mmc3,
3620 &omap3_l4_core__uart1,
3621 &omap3_l4_core__uart2,
3622 &omap3_l4_per__uart3,
3623 &omap3_l4_core__i2c1,
3624 &omap3_l4_core__i2c2,
3625 &omap3_l4_core__i2c3,
3626 &omap3xxx_l4_wkup__l4_sec,
3627 &omap3xxx_l4_wkup__timer1,
3628 &omap3xxx_l4_per__timer2,
3629 &omap3xxx_l4_per__timer3,
3630 &omap3xxx_l4_per__timer4,
3631 &omap3xxx_l4_per__timer5,
3632 &omap3xxx_l4_per__timer6,
3633 &omap3xxx_l4_per__timer7,
3634 &omap3xxx_l4_per__timer8,
3635 &omap3xxx_l4_per__timer9,
3636 &omap3xxx_l4_core__timer10,
3637 &omap3xxx_l4_core__timer11,
3638 &omap3xxx_l4_wkup__wd_timer2,
3639 &omap3xxx_l4_wkup__gpio1,
3640 &omap3xxx_l4_per__gpio2,
3641 &omap3xxx_l4_per__gpio3,
3642 &omap3xxx_l4_per__gpio4,
3643 &omap3xxx_l4_per__gpio5,
3644 &omap3xxx_l4_per__gpio6,
3645 &omap3xxx_dma_system__l3,
3646 &omap3xxx_l4_core__dma_system,
3647 &omap3xxx_l4_core__mcbsp1,
3648 &omap3xxx_l4_per__mcbsp2,
3649 &omap3xxx_l4_per__mcbsp3,
3650 &omap3xxx_l4_per__mcbsp4,
3651 &omap3xxx_l4_core__mcbsp5,
3652 &omap3xxx_l4_per__mcbsp2_sidetone,
3653 &omap3xxx_l4_per__mcbsp3_sidetone,
3654 &omap34xx_l4_core__mcspi1,
3655 &omap34xx_l4_core__mcspi2,
3656 &omap34xx_l4_core__mcspi3,
3657 &omap34xx_l4_core__mcspi4,
3658 &omap3xxx_l4_wkup__counter_32k,
3659 &omap3xxx_l3_main__gpmc,
3663 /* GP-only hwmod links */
3664 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3665 &omap3xxx_l4_sec__timer12,
3666 &omap3xxx_l4_core__sham,
3670 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3671 &omap3xxx_l4_sec__timer12,
3672 &omap3xxx_l4_core__sham,
3676 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3677 &omap3xxx_l4_sec__timer12,
3679 * Apparently the SHA/MD5 accelerator IP block is only present
3680 * on some AM35xx chips, and no one knows which ones. See
3681 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3682 * if you need this IP block on an AM35xx, try uncommenting
3685 /* &omap3xxx_l4_core__sham, */
3689 /* 3430ES1-only hwmod links */
3690 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3691 &omap3430es1_dss__l3,
3692 &omap3430es1_l4_core__dss,
3696 /* 3430ES2+-only hwmod links */
3697 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3699 &omap3xxx_l4_core__dss,
3700 &omap3xxx_usbhsotg__l3,
3701 &omap3xxx_l4_core__usbhsotg,
3702 &omap3xxx_usb_host_hs__l3_main_2,
3703 &omap3xxx_l4_core__usb_host_hs,
3704 &omap3xxx_l4_core__usb_tll_hs,
3708 /* <= 3430ES3-only hwmod links */
3709 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3710 &omap3xxx_l4_core__pre_es3_mmc1,
3711 &omap3xxx_l4_core__pre_es3_mmc2,
3715 /* 3430ES3+-only hwmod links */
3716 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3717 &omap3xxx_l4_core__es3plus_mmc1,
3718 &omap3xxx_l4_core__es3plus_mmc2,
3722 /* 34xx-only hwmod links (all ES revisions) */
3723 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3725 &omap34xx_l4_core__sr1,
3726 &omap34xx_l4_core__sr2,
3727 &omap3xxx_l4_core__mailbox,
3728 &omap3xxx_l4_core__hdq1w,
3729 &omap3xxx_sad2d__l3,
3730 &omap3xxx_l4_core__mmu_isp,
3731 #ifdef CONFIG_OMAP_IOMMU_IVA2
3732 &omap3xxx_l3_main__mmu_iva,
3737 /* 36xx-only hwmod links (all ES revisions) */
3738 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3740 &omap36xx_l4_per__uart4,
3742 &omap3xxx_l4_core__dss,
3743 &omap36xx_l4_core__sr1,
3744 &omap36xx_l4_core__sr2,
3745 &omap3xxx_usbhsotg__l3,
3746 &omap3xxx_l4_core__usbhsotg,
3747 &omap3xxx_l4_core__mailbox,
3748 &omap3xxx_usb_host_hs__l3_main_2,
3749 &omap3xxx_l4_core__usb_host_hs,
3750 &omap3xxx_l4_core__usb_tll_hs,
3751 &omap3xxx_l4_core__es3plus_mmc1,
3752 &omap3xxx_l4_core__es3plus_mmc2,
3753 &omap3xxx_l4_core__hdq1w,
3754 &omap3xxx_sad2d__l3,
3755 &omap3xxx_l4_core__mmu_isp,
3756 #ifdef CONFIG_OMAP_IOMMU_IVA2
3757 &omap3xxx_l3_main__mmu_iva,
3762 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3764 &omap3xxx_l4_core__dss,
3765 &am35xx_usbhsotg__l3,
3766 &am35xx_l4_core__usbhsotg,
3767 &am35xx_l4_core__uart4,
3768 &omap3xxx_usb_host_hs__l3_main_2,
3769 &omap3xxx_l4_core__usb_host_hs,
3770 &omap3xxx_l4_core__usb_tll_hs,
3771 &omap3xxx_l4_core__es3plus_mmc1,
3772 &omap3xxx_l4_core__es3plus_mmc2,
3773 &omap3xxx_l4_core__hdq1w,
3775 &am35xx_l4_core__mdio,
3777 &am35xx_l4_core__emac,
3781 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3782 &omap3xxx_l4_core__dss_dispc,
3783 &omap3xxx_l4_core__dss_dsi1,
3784 &omap3xxx_l4_core__dss_rfbi,
3785 &omap3xxx_l4_core__dss_venc,
3789 int __init omap3xxx_hwmod_init(void)
3792 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
3797 /* Register hwmod links common to all OMAP3 */
3798 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3805 * Register hwmod links common to individual OMAP3 families, all
3806 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3807 * All possible revisions should be included in this conditional.
3809 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3810 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3811 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3812 h = omap34xx_hwmod_ocp_ifs;
3813 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3814 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3815 h = am35xx_hwmod_ocp_ifs;
3816 h_gp = am35xx_gp_hwmod_ocp_ifs;
3817 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3818 rev == OMAP3630_REV_ES1_2) {
3819 h = omap36xx_hwmod_ocp_ifs;
3820 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3822 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3826 r = omap_hwmod_register_links(h);
3830 /* Register GP-only hwmod links. */
3831 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3832 r = omap_hwmod_register_links(h_gp);
3839 * Register hwmod links specific to certain ES levels of a
3840 * particular family of silicon (e.g., 34xx ES1.0)
3843 if (rev == OMAP3430_REV_ES1_0) {
3844 h = omap3430es1_hwmod_ocp_ifs;
3845 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3846 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3847 rev == OMAP3430_REV_ES3_1_2) {
3848 h = omap3430es2plus_hwmod_ocp_ifs;
3852 r = omap_hwmod_register_links(h);
3858 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3859 rev == OMAP3430_REV_ES2_1) {
3860 h = omap3430_pre_es3_hwmod_ocp_ifs;
3861 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3862 rev == OMAP3430_REV_ES3_1_2) {
3863 h = omap3430_es3plus_hwmod_ocp_ifs;
3867 r = omap_hwmod_register_links(h);
3872 * DSS code presumes that dss_core hwmod is handled first,
3873 * _before_ any other DSS related hwmods so register common
3874 * DSS hwmod links last to ensure that dss_core is already
3875 * registered. Otherwise some change things may happen, for
3876 * ex. if dispc is handled before dss_core and DSS is enabled
3877 * in bootloader DISPC will be reset with outputs enabled
3878 * which sometimes leads to unrecoverable L3 error. XXX The
3879 * long-term fix to this is to ensure hwmods are set up in
3880 * dependency order in the hwmod core code.
3882 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);