arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20
  21 #include "omap_hwmod_common_data.h"
  22
  23 #include "prm-regbits-34xx.h"
  24 #include "cm-regbits-34xx.h"
  25
  26 /*
  27  * OMAP3xxx hardware module integration data
  28  *
  29  * ALl of the data in this section should be autogeneratable from the
  30  * TI hardware database or other technical documentation.  Data that
  31  * is driver-specific or driver-kernel integration-specific belongs
  32  * elsewhere.
  33  */
  34
  35 static struct omap_hwmod omap3xxx_mpu_hwmod;
  36 static struct omap_hwmod omap3xxx_iva_hwmod;
  37 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  38 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  39 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  40 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  41
  42 /* L3 -> L4_CORE interface */
  43 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  44         .master = &omap3xxx_l3_main_hwmod,
  45         .slave  = &omap3xxx_l4_core_hwmod,
  46         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  47 };
  48
  49 /* L3 -> L4_PER interface */
  50 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  51         .master = &omap3xxx_l3_main_hwmod,
  52         .slave  = &omap3xxx_l4_per_hwmod,
  53         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  54 };
  55
  56 /* MPU -> L3 interface */
  57 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  58         .master = &omap3xxx_mpu_hwmod,
  59         .slave  = &omap3xxx_l3_main_hwmod,
  60         .user   = OCP_USER_MPU,
  61 };
  62
  63 /* Slave interfaces on the L3 interconnect */
  64 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
  65         &omap3xxx_mpu__l3_main,
  66 };
  67
  68 /* Master interfaces on the L3 interconnect */
  69 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
  70         &omap3xxx_l3_main__l4_core,
  71         &omap3xxx_l3_main__l4_per,
  72 };
  73
  74 /* L3 */
  75 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  76         .name           = "l3_main",
  77         .class          = &l3_hwmod_class,
  78         .masters        = omap3xxx_l3_main_masters,
  79         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
  80         .slaves         = omap3xxx_l3_main_slaves,
  81         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
  82         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  83         .flags          = HWMOD_NO_IDLEST,
  84 };
  85
  86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
  87
  88 /* L4_CORE -> L4_WKUP interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
  90         .master = &omap3xxx_l4_core_hwmod,
  91         .slave  = &omap3xxx_l4_wkup_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* Slave interfaces on the L4_CORE interconnect */
  96 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
  97         &omap3xxx_l3_main__l4_core,
  98 };
  99
 100 /* Master interfaces on the L4_CORE interconnect */
 101 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 102         &omap3xxx_l4_core__l4_wkup,
 103 };
 104
 105 /* L4 CORE */
 106 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 107         .name           = "l4_core",
 108         .class          = &l4_hwmod_class,
 109         .masters        = omap3xxx_l4_core_masters,
 110         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
 111         .slaves         = omap3xxx_l4_core_slaves,
 112         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 114         .flags          = HWMOD_NO_IDLEST,
 115 };
 116
 117 /* Slave interfaces on the L4_PER interconnect */
 118 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 119         &omap3xxx_l3_main__l4_per,
 120 };
 121
 122 /* Master interfaces on the L4_PER interconnect */
 123 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
 124 };
 125
 126 /* L4 PER */
 127 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 128         .name           = "l4_per",
 129         .class          = &l4_hwmod_class,
 130         .masters        = omap3xxx_l4_per_masters,
 131         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
 132         .slaves         = omap3xxx_l4_per_slaves,
 133         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 134         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 135         .flags          = HWMOD_NO_IDLEST,
 136 };
 137
 138 /* Slave interfaces on the L4_WKUP interconnect */
 139 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 140         &omap3xxx_l4_core__l4_wkup,
 141 };
 142
 143 /* Master interfaces on the L4_WKUP interconnect */
 144 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
 145 };
 146
 147 /* L4 WKUP */
 148 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 149         .name           = "l4_wkup",
 150         .class          = &l4_hwmod_class,
 151         .masters        = omap3xxx_l4_wkup_masters,
 152         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
 153         .slaves         = omap3xxx_l4_wkup_slaves,
 154         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 155         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 156         .flags          = HWMOD_NO_IDLEST,
 157 };
 158
 159 /* Master interfaces on the MPU device */
 160 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 161         &omap3xxx_mpu__l3_main,
 162 };
 163
 164 /* MPU */
 165 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 166         .name           = "mpu",
 167         .class          = &mpu_hwmod_class,
 168         .main_clk       = "arm_fck",
 169         .masters        = omap3xxx_mpu_masters,
 170         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 171         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 172 };
 173
 174 /*
 175  * IVA2_2 interface data
 176  */
 177
 178 /* IVA2 <- L3 interface */
 179 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 180         .master         = &omap3xxx_l3_main_hwmod,
 181         .slave          = &omap3xxx_iva_hwmod,
 182         .clk            = "iva2_ck",
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 187         &omap3xxx_l3__iva,
 188 };
 189
 190 /*
 191  * IVA2 (IVA2)
 192  */
 193
 194 static struct omap_hwmod omap3xxx_iva_hwmod = {
 195         .name           = "iva",
 196         .class          = &iva_hwmod_class,
 197         .masters        = omap3xxx_iva_masters,
 198         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 199         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 200 };
 201
 202 /* l4_wkup -> wd_timer2 */
 203 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 204         {
 205                 .pa_start       = 0x48314000,
 206                 .pa_end         = 0x4831407f,
 207                 .flags          = ADDR_TYPE_RT
 208         },
 209 };
 210
 211 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 212         .master         = &omap3xxx_l4_wkup_hwmod,
 213         .slave          = &omap3xxx_wd_timer2_hwmod,
 214         .clk            = "wdt2_ick",
 215         .addr           = omap3xxx_wd_timer2_addrs,
 216         .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 218 };
 219
 220 /*
 221  * 'wd_timer' class
 222  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 223  * overflow condition
 224  */
 225
 226 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 227         .rev_offs       = 0x0000,
 228         .sysc_offs      = 0x0010,
 229         .syss_offs      = 0x0014,
 230         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 231                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 232                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 233         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 234         .sysc_fields    = &omap_hwmod_sysc_type1,
 235 };
 236
 237 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 238         .name = "wd_timer",
 239         .sysc = &omap3xxx_wd_timer_sysc,
 240 };
 241
 242 /* wd_timer2 */
 243 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 244         &omap3xxx_l4_wkup__wd_timer2,
 245 };
 246
 247 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 248         .name           = "wd_timer2",
 249         .class          = &omap3xxx_wd_timer_hwmod_class,
 250         .main_clk       = "wdt2_fck",
 251         .prcm           = {
 252                 .omap2 = {
 253                         .prcm_reg_id = 1,
 254                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 255                         .module_offs = WKUP_MOD,
 256                         .idlest_reg_id = 1,
 257                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 258                 },
 259         },
 260         .slaves         = omap3xxx_wd_timer2_slaves,
 261         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 262         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 263 };
 264
 265 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 266         &omap3xxx_l3_main_hwmod,
 267         &omap3xxx_l4_core_hwmod,
 268         &omap3xxx_l4_per_hwmod,
 269         &omap3xxx_l4_wkup_hwmod,
 270         &omap3xxx_mpu_hwmod,
 271         &omap3xxx_iva_hwmod,
 272         &omap3xxx_wd_timer2_hwmod,
 273         NULL,
 274 };
 275
 276 int __init omap3xxx_hwmod_init(void)
 277 {
 278         return omap_hwmod_init(omap3xxx_hwmods);
 279 }
 280
 281