arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25 #include <linux/i2c-omap.h>
  26
  27 #include <linux/omap-dma.h>
  28
  29 #include <linux/platform_data/spi-omap2-mcspi.h>
  30 #include <linux/platform_data/asoc-ti-mcbsp.h>
  31 #include <linux/platform_data/iommu-omap.h>
  32 #include <plat/dmtimer.h>
  33
  34 #include "omap_hwmod.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "i2c.h"
  41 #include "mmc.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'c2c_target_fw' class
  56  * instance(s): c2c_target_fw
  57  */
  58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  59         .name   = "c2c_target_fw",
  60 };
  61
  62 /* c2c_target_fw */
  63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  64         .name           = "c2c_target_fw",
  65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  66         .clkdm_name     = "d2d_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 static struct omap_hwmod omap44xx_dmm_hwmod = {
  90         .name           = "dmm",
  91         .class          = &omap44xx_dmm_hwmod_class,
  92         .clkdm_name     = "l3_emif_clkdm",
  93         .mpu_irqs       = omap44xx_dmm_irqs,
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /*
 103  * 'emif_fw' class
 104  * instance(s): emif_fw
 105  */
 106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 107         .name   = "emif_fw",
 108 };
 109
 110 /* emif_fw */
 111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 112         .name           = "emif_fw",
 113         .class          = &omap44xx_emif_fw_hwmod_class,
 114         .clkdm_name     = "l3_emif_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /*
 124  * 'l3' class
 125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 126  */
 127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 128         .name   = "l3",
 129 };
 130
 131 /* l3_instr */
 132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 133         .name           = "l3_instr",
 134         .class          = &omap44xx_l3_hwmod_class,
 135         .clkdm_name     = "l3_instr_clkdm",
 136         .prcm = {
 137                 .omap4 = {
 138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 140                         .modulemode   = MODULEMODE_HWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /* l3_main_1 */
 146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 149         { .irq = -1 }
 150 };
 151
 152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 153         .name           = "l3_main_1",
 154         .class          = &omap44xx_l3_hwmod_class,
 155         .clkdm_name     = "l3_1_clkdm",
 156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 157         .prcm = {
 158                 .omap4 = {
 159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 161                 },
 162         },
 163 };
 164
 165 /* l3_main_2 */
 166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 167         .name           = "l3_main_2",
 168         .class          = &omap44xx_l3_hwmod_class,
 169         .clkdm_name     = "l3_2_clkdm",
 170         .prcm = {
 171                 .omap4 = {
 172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 174                 },
 175         },
 176 };
 177
 178 /* l3_main_3 */
 179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 180         .name           = "l3_main_3",
 181         .class          = &omap44xx_l3_hwmod_class,
 182         .clkdm_name     = "l3_instr_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 187                         .modulemode   = MODULEMODE_HWCTRL,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * 'l4' class
 194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 195  */
 196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 197         .name   = "l4",
 198 };
 199
 200 /* l4_abe */
 201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 202         .name           = "l4_abe",
 203         .class          = &omap44xx_l4_hwmod_class,
 204         .clkdm_name     = "abe_clkdm",
 205         .prcm = {
 206                 .omap4 = {
 207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 211                 },
 212         },
 213 };
 214
 215 /* l4_cfg */
 216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 217         .name           = "l4_cfg",
 218         .class          = &omap44xx_l4_hwmod_class,
 219         .clkdm_name     = "l4_cfg_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 224                 },
 225         },
 226 };
 227
 228 /* l4_per */
 229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 230         .name           = "l4_per",
 231         .class          = &omap44xx_l4_hwmod_class,
 232         .clkdm_name     = "l4_per_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 237                 },
 238         },
 239 };
 240
 241 /* l4_wkup */
 242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 243         .name           = "l4_wkup",
 244         .class          = &omap44xx_l4_hwmod_class,
 245         .clkdm_name     = "l4_wkup_clkdm",
 246         .prcm = {
 247                 .omap4 = {
 248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 250                 },
 251         },
 252 };
 253
 254 /*
 255  * 'mpu_bus' class
 256  * instance(s): mpu_private
 257  */
 258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 259         .name   = "mpu_bus",
 260 };
 261
 262 /* mpu_private */
 263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 264         .name           = "mpu_private",
 265         .class          = &omap44xx_mpu_bus_hwmod_class,
 266         .clkdm_name     = "mpuss_clkdm",
 267         .prcm = {
 268                 .omap4 = {
 269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 270                 },
 271         },
 272 };
 273
 274 /*
 275  * 'ocp_wp_noc' class
 276  * instance(s): ocp_wp_noc
 277  */
 278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 279         .name   = "ocp_wp_noc",
 280 };
 281
 282 /* ocp_wp_noc */
 283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 284         .name           = "ocp_wp_noc",
 285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 286         .clkdm_name     = "l3_instr_clkdm",
 287         .prcm = {
 288                 .omap4 = {
 289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 291                         .modulemode   = MODULEMODE_HWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /*
 297  * Modules omap_hwmod structures
 298  *
 299  * The following IPs are excluded for the moment because:
 300  * - They do not need an explicit SW control using omap_hwmod API.
 301  * - They still need to be validated with the driver
 302  *   properly adapted to omap_hwmod / omap_device
 303  *
 304  * usim
 305  */
 306
 307 /*
 308  * 'aess' class
 309  * audio engine sub system
 310  */
 311
 312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 313         .rev_offs       = 0x0000,
 314         .sysc_offs      = 0x0010,
 315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 318                            MSTANDBY_SMART_WKUP),
 319         .sysc_fields    = &omap_hwmod_sysc_type2,
 320 };
 321
 322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 323         .name   = "aess",
 324         .sysc   = &omap44xx_aess_sysc,
 325 };
 326
 327 /* aess */
 328 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 329         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 330         { .irq = -1 }
 331 };
 332
 333 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 334         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 342         { .dma_req = -1 }
 343 };
 344
 345 static struct omap_hwmod omap44xx_aess_hwmod = {
 346         .name           = "aess",
 347         .class          = &omap44xx_aess_hwmod_class,
 348         .clkdm_name     = "abe_clkdm",
 349         .mpu_irqs       = omap44xx_aess_irqs,
 350         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 351         .main_clk       = "aess_fck",
 352         .prcm = {
 353                 .omap4 = {
 354                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 355                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 356                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 357                         .modulemode   = MODULEMODE_SWCTRL,
 358                 },
 359         },
 360 };
 361
 362 /*
 363  * 'c2c' class
 364  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 365  * soc
 366  */
 367
 368 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 369         .name   = "c2c",
 370 };
 371
 372 /* c2c */
 373 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 374         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 375         { .irq = -1 }
 376 };
 377
 378 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 379         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 380         { .dma_req = -1 }
 381 };
 382
 383 static struct omap_hwmod omap44xx_c2c_hwmod = {
 384         .name           = "c2c",
 385         .class          = &omap44xx_c2c_hwmod_class,
 386         .clkdm_name     = "d2d_clkdm",
 387         .mpu_irqs       = omap44xx_c2c_irqs,
 388         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 389         .prcm = {
 390                 .omap4 = {
 391                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 392                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 393                 },
 394         },
 395 };
 396
 397 /*
 398  * 'counter' class
 399  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 400  */
 401
 402 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 403         .rev_offs       = 0x0000,
 404         .sysc_offs      = 0x0004,
 405         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 407         .sysc_fields    = &omap_hwmod_sysc_type1,
 408 };
 409
 410 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 411         .name   = "counter",
 412         .sysc   = &omap44xx_counter_sysc,
 413 };
 414
 415 /* counter_32k */
 416 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 417         .name           = "counter_32k",
 418         .class          = &omap44xx_counter_hwmod_class,
 419         .clkdm_name     = "l4_wkup_clkdm",
 420         .flags          = HWMOD_SWSUP_SIDLE,
 421         .main_clk       = "sys_32k_ck",
 422         .prcm = {
 423                 .omap4 = {
 424                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 425                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 426                 },
 427         },
 428 };
 429
 430 /*
 431  * 'ctrl_module' class
 432  * attila core control module + core pad control module + wkup pad control
 433  * module + attila wkup control module
 434  */
 435
 436 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 437         .rev_offs       = 0x0000,
 438         .sysc_offs      = 0x0010,
 439         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 441                            SIDLE_SMART_WKUP),
 442         .sysc_fields    = &omap_hwmod_sysc_type2,
 443 };
 444
 445 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 446         .name   = "ctrl_module",
 447         .sysc   = &omap44xx_ctrl_module_sysc,
 448 };
 449
 450 /* ctrl_module_core */
 451 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 452         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 453         { .irq = -1 }
 454 };
 455
 456 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 457         .name           = "ctrl_module_core",
 458         .class          = &omap44xx_ctrl_module_hwmod_class,
 459         .clkdm_name     = "l4_cfg_clkdm",
 460         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 461         .prcm = {
 462                 .omap4 = {
 463                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 464                 },
 465         },
 466 };
 467
 468 /* ctrl_module_pad_core */
 469 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 470         .name           = "ctrl_module_pad_core",
 471         .class          = &omap44xx_ctrl_module_hwmod_class,
 472         .clkdm_name     = "l4_cfg_clkdm",
 473         .prcm = {
 474                 .omap4 = {
 475                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 476                 },
 477         },
 478 };
 479
 480 /* ctrl_module_wkup */
 481 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 482         .name           = "ctrl_module_wkup",
 483         .class          = &omap44xx_ctrl_module_hwmod_class,
 484         .clkdm_name     = "l4_wkup_clkdm",
 485         .prcm = {
 486                 .omap4 = {
 487                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 488                 },
 489         },
 490 };
 491
 492 /* ctrl_module_pad_wkup */
 493 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 494         .name           = "ctrl_module_pad_wkup",
 495         .class          = &omap44xx_ctrl_module_hwmod_class,
 496         .clkdm_name     = "l4_wkup_clkdm",
 497         .prcm = {
 498                 .omap4 = {
 499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 500                 },
 501         },
 502 };
 503
 504 /*
 505  * 'debugss' class
 506  * debug and emulation sub system
 507  */
 508
 509 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 510         .name   = "debugss",
 511 };
 512
 513 /* debugss */
 514 static struct omap_hwmod omap44xx_debugss_hwmod = {
 515         .name           = "debugss",
 516         .class          = &omap44xx_debugss_hwmod_class,
 517         .clkdm_name     = "emu_sys_clkdm",
 518         .main_clk       = "trace_clk_div_ck",
 519         .prcm = {
 520                 .omap4 = {
 521                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 522                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 523                 },
 524         },
 525 };
 526
 527 /*
 528  * 'dma' class
 529  * dma controller for data exchange between memory to memory (i.e. internal or
 530  * external memory) and gp peripherals to memory or memory to gp peripherals
 531  */
 532
 533 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 534         .rev_offs       = 0x0000,
 535         .sysc_offs      = 0x002c,
 536         .syss_offs      = 0x0028,
 537         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 538                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 539                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 540                            SYSS_HAS_RESET_STATUS),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 542                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 543         .sysc_fields    = &omap_hwmod_sysc_type1,
 544 };
 545
 546 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 547         .name   = "dma",
 548         .sysc   = &omap44xx_dma_sysc,
 549 };
 550
 551 /* dma dev_attr */
 552 static struct omap_dma_dev_attr dma_dev_attr = {
 553         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 554                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 555         .lch_count      = 32,
 556 };
 557
 558 /* dma_system */
 559 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 560         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 564         { .irq = -1 }
 565 };
 566
 567 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 568         .name           = "dma_system",
 569         .class          = &omap44xx_dma_hwmod_class,
 570         .clkdm_name     = "l3_dma_clkdm",
 571         .mpu_irqs       = omap44xx_dma_system_irqs,
 572         .main_clk       = "l3_div_ck",
 573         .prcm = {
 574                 .omap4 = {
 575                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 576                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 577                 },
 578         },
 579         .dev_attr       = &dma_dev_attr,
 580 };
 581
 582 /*
 583  * 'dmic' class
 584  * digital microphone controller
 585  */
 586
 587 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 588         .rev_offs       = 0x0000,
 589         .sysc_offs      = 0x0010,
 590         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 591                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 593                            SIDLE_SMART_WKUP),
 594         .sysc_fields    = &omap_hwmod_sysc_type2,
 595 };
 596
 597 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 598         .name   = "dmic",
 599         .sysc   = &omap44xx_dmic_sysc,
 600 };
 601
 602 /* dmic */
 603 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 604         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 605         { .irq = -1 }
 606 };
 607
 608 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 609         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 610         { .dma_req = -1 }
 611 };
 612
 613 static struct omap_hwmod omap44xx_dmic_hwmod = {
 614         .name           = "dmic",
 615         .class          = &omap44xx_dmic_hwmod_class,
 616         .clkdm_name     = "abe_clkdm",
 617         .mpu_irqs       = omap44xx_dmic_irqs,
 618         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 619         .main_clk       = "dmic_fck",
 620         .prcm = {
 621                 .omap4 = {
 622                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 623                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 624                         .modulemode   = MODULEMODE_SWCTRL,
 625                 },
 626         },
 627 };
 628
 629 /*
 630  * 'dsp' class
 631  * dsp sub-system
 632  */
 633
 634 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 635         .name   = "dsp",
 636 };
 637
 638 /* dsp */
 639 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 640         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 641         { .irq = -1 }
 642 };
 643
 644 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 645         { .name = "dsp", .rst_shift = 0 },
 646 };
 647
 648 static struct omap_hwmod omap44xx_dsp_hwmod = {
 649         .name           = "dsp",
 650         .class          = &omap44xx_dsp_hwmod_class,
 651         .clkdm_name     = "tesla_clkdm",
 652         .mpu_irqs       = omap44xx_dsp_irqs,
 653         .rst_lines      = omap44xx_dsp_resets,
 654         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 655         .main_clk       = "dpll_iva_m4x2_ck",
 656         .prcm = {
 657                 .omap4 = {
 658                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 659                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 660                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 661                         .modulemode   = MODULEMODE_HWCTRL,
 662                 },
 663         },
 664 };
 665
 666 /*
 667  * 'dss' class
 668  * display sub-system
 669  */
 670
 671 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 672         .rev_offs       = 0x0000,
 673         .syss_offs      = 0x0014,
 674         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 675 };
 676
 677 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 678         .name   = "dss",
 679         .sysc   = &omap44xx_dss_sysc,
 680         .reset  = omap_dss_reset,
 681 };
 682
 683 /* dss */
 684 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 685         { .role = "sys_clk", .clk = "dss_sys_clk" },
 686         { .role = "tv_clk", .clk = "dss_tv_clk" },
 687         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 688 };
 689
 690 static struct omap_hwmod omap44xx_dss_hwmod = {
 691         .name           = "dss_core",
 692         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 693         .class          = &omap44xx_dss_hwmod_class,
 694         .clkdm_name     = "l3_dss_clkdm",
 695         .main_clk       = "dss_dss_clk",
 696         .prcm = {
 697                 .omap4 = {
 698                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 699                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 700                 },
 701         },
 702         .opt_clks       = dss_opt_clks,
 703         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 704 };
 705
 706 /*
 707  * 'dispc' class
 708  * display controller
 709  */
 710
 711 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 712         .rev_offs       = 0x0000,
 713         .sysc_offs      = 0x0010,
 714         .syss_offs      = 0x0014,
 715         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 716                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 717                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 718                            SYSS_HAS_RESET_STATUS),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 720                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 721         .sysc_fields    = &omap_hwmod_sysc_type1,
 722 };
 723
 724 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 725         .name   = "dispc",
 726         .sysc   = &omap44xx_dispc_sysc,
 727 };
 728
 729 /* dss_dispc */
 730 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 731         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 732         { .irq = -1 }
 733 };
 734
 735 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 736         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 737         { .dma_req = -1 }
 738 };
 739
 740 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 741         .manager_count          = 3,
 742         .has_framedonetv_irq    = 1
 743 };
 744
 745 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 746         .name           = "dss_dispc",
 747         .class          = &omap44xx_dispc_hwmod_class,
 748         .clkdm_name     = "l3_dss_clkdm",
 749         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 750         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 751         .main_clk       = "dss_dss_clk",
 752         .prcm = {
 753                 .omap4 = {
 754                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 755                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 756                 },
 757         },
 758         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 759 };
 760
 761 /*
 762  * 'dsi' class
 763  * display serial interface controller
 764  */
 765
 766 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 767         .rev_offs       = 0x0000,
 768         .sysc_offs      = 0x0010,
 769         .syss_offs      = 0x0014,
 770         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 771                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 772                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 774         .sysc_fields    = &omap_hwmod_sysc_type1,
 775 };
 776
 777 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 778         .name   = "dsi",
 779         .sysc   = &omap44xx_dsi_sysc,
 780 };
 781
 782 /* dss_dsi1 */
 783 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 784         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 785         { .irq = -1 }
 786 };
 787
 788 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 789         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 790         { .dma_req = -1 }
 791 };
 792
 793 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 794         { .role = "sys_clk", .clk = "dss_sys_clk" },
 795 };
 796
 797 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 798         .name           = "dss_dsi1",
 799         .class          = &omap44xx_dsi_hwmod_class,
 800         .clkdm_name     = "l3_dss_clkdm",
 801         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 802         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 803         .main_clk       = "dss_dss_clk",
 804         .prcm = {
 805                 .omap4 = {
 806                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 807                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 808                 },
 809         },
 810         .opt_clks       = dss_dsi1_opt_clks,
 811         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 812 };
 813
 814 /* dss_dsi2 */
 815 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 816         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 817         { .irq = -1 }
 818 };
 819
 820 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 821         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 822         { .dma_req = -1 }
 823 };
 824
 825 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 826         { .role = "sys_clk", .clk = "dss_sys_clk" },
 827 };
 828
 829 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 830         .name           = "dss_dsi2",
 831         .class          = &omap44xx_dsi_hwmod_class,
 832         .clkdm_name     = "l3_dss_clkdm",
 833         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 834         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 835         .main_clk       = "dss_dss_clk",
 836         .prcm = {
 837                 .omap4 = {
 838                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 839                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 840                 },
 841         },
 842         .opt_clks       = dss_dsi2_opt_clks,
 843         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 844 };
 845
 846 /*
 847  * 'hdmi' class
 848  * hdmi controller
 849  */
 850
 851 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 852         .rev_offs       = 0x0000,
 853         .sysc_offs      = 0x0010,
 854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 855                            SYSC_HAS_SOFTRESET),
 856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 857                            SIDLE_SMART_WKUP),
 858         .sysc_fields    = &omap_hwmod_sysc_type2,
 859 };
 860
 861 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 862         .name   = "hdmi",
 863         .sysc   = &omap44xx_hdmi_sysc,
 864 };
 865
 866 /* dss_hdmi */
 867 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 868         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 869         { .irq = -1 }
 870 };
 871
 872 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 873         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 874         { .dma_req = -1 }
 875 };
 876
 877 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 878         { .role = "sys_clk", .clk = "dss_sys_clk" },
 879 };
 880
 881 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 882         .name           = "dss_hdmi",
 883         .class          = &omap44xx_hdmi_hwmod_class,
 884         .clkdm_name     = "l3_dss_clkdm",
 885         /*
 886          * HDMI audio requires to use no-idle mode. Hence,
 887          * set idle mode by software.
 888          */
 889         .flags          = HWMOD_SWSUP_SIDLE,
 890         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 891         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 892         .main_clk       = "dss_48mhz_clk",
 893         .prcm = {
 894                 .omap4 = {
 895                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 896                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 897                 },
 898         },
 899         .opt_clks       = dss_hdmi_opt_clks,
 900         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 901 };
 902
 903 /*
 904  * 'rfbi' class
 905  * remote frame buffer interface
 906  */
 907
 908 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 909         .rev_offs       = 0x0000,
 910         .sysc_offs      = 0x0010,
 911         .syss_offs      = 0x0014,
 912         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 913                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 914         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 915         .sysc_fields    = &omap_hwmod_sysc_type1,
 916 };
 917
 918 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 919         .name   = "rfbi",
 920         .sysc   = &omap44xx_rfbi_sysc,
 921 };
 922
 923 /* dss_rfbi */
 924 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 925         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 926         { .dma_req = -1 }
 927 };
 928
 929 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 930         { .role = "ick", .clk = "dss_fck" },
 931 };
 932
 933 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 934         .name           = "dss_rfbi",
 935         .class          = &omap44xx_rfbi_hwmod_class,
 936         .clkdm_name     = "l3_dss_clkdm",
 937         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 938         .main_clk       = "dss_dss_clk",
 939         .prcm = {
 940                 .omap4 = {
 941                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 942                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 943                 },
 944         },
 945         .opt_clks       = dss_rfbi_opt_clks,
 946         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 947 };
 948
 949 /*
 950  * 'venc' class
 951  * video encoder
 952  */
 953
 954 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 955         .name   = "venc",
 956 };
 957
 958 /* dss_venc */
 959 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 960         .name           = "dss_venc",
 961         .class          = &omap44xx_venc_hwmod_class,
 962         .clkdm_name     = "l3_dss_clkdm",
 963         .main_clk       = "dss_tv_clk",
 964         .prcm = {
 965                 .omap4 = {
 966                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 967                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 968                 },
 969         },
 970 };
 971
 972 /*
 973  * 'elm' class
 974  * bch error location module
 975  */
 976
 977 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 978         .rev_offs       = 0x0000,
 979         .sysc_offs      = 0x0010,
 980         .syss_offs      = 0x0014,
 981         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 982                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 983                            SYSS_HAS_RESET_STATUS),
 984         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 985         .sysc_fields    = &omap_hwmod_sysc_type1,
 986 };
 987
 988 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 989         .name   = "elm",
 990         .sysc   = &omap44xx_elm_sysc,
 991 };
 992
 993 /* elm */
 994 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 995         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 996         { .irq = -1 }
 997 };
 998
 999 static struct omap_hwmod omap44xx_elm_hwmod = {
1000         .name           = "elm",
1001         .class          = &omap44xx_elm_hwmod_class,
1002         .clkdm_name     = "l4_per_clkdm",
1003         .mpu_irqs       = omap44xx_elm_irqs,
1004         .prcm = {
1005                 .omap4 = {
1006                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1007                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1008                 },
1009         },
1010 };
1011
1012 /*
1013  * 'emif' class
1014  * external memory interface no1
1015  */
1016
1017 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1018         .rev_offs       = 0x0000,
1019 };
1020
1021 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1022         .name   = "emif",
1023         .sysc   = &omap44xx_emif_sysc,
1024 };
1025
1026 /* emif1 */
1027 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1028         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1029         { .irq = -1 }
1030 };
1031
1032 static struct omap_hwmod omap44xx_emif1_hwmod = {
1033         .name           = "emif1",
1034         .class          = &omap44xx_emif_hwmod_class,
1035         .clkdm_name     = "l3_emif_clkdm",
1036         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1037         .mpu_irqs       = omap44xx_emif1_irqs,
1038         .main_clk       = "ddrphy_ck",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_HWCTRL,
1044                 },
1045         },
1046 };
1047
1048 /* emif2 */
1049 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1050         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1051         { .irq = -1 }
1052 };
1053
1054 static struct omap_hwmod omap44xx_emif2_hwmod = {
1055         .name           = "emif2",
1056         .class          = &omap44xx_emif_hwmod_class,
1057         .clkdm_name     = "l3_emif_clkdm",
1058         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1059         .mpu_irqs       = omap44xx_emif2_irqs,
1060         .main_clk       = "ddrphy_ck",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_HWCTRL,
1066                 },
1067         },
1068 };
1069
1070 /*
1071  * 'fdif' class
1072  * face detection hw accelerator module
1073  */
1074
1075 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1076         .rev_offs       = 0x0000,
1077         .sysc_offs      = 0x0010,
1078         /*
1079          * FDIF needs 100 OCP clk cycles delay after a softreset before
1080          * accessing sysconfig again.
1081          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1082          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1083          *
1084          * TODO: Indicate errata when available.
1085          */
1086         .srst_udelay    = 2,
1087         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1088                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1089         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091         .sysc_fields    = &omap_hwmod_sysc_type2,
1092 };
1093
1094 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1095         .name   = "fdif",
1096         .sysc   = &omap44xx_fdif_sysc,
1097 };
1098
1099 /* fdif */
1100 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1101         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1102         { .irq = -1 }
1103 };
1104
1105 static struct omap_hwmod omap44xx_fdif_hwmod = {
1106         .name           = "fdif",
1107         .class          = &omap44xx_fdif_hwmod_class,
1108         .clkdm_name     = "iss_clkdm",
1109         .mpu_irqs       = omap44xx_fdif_irqs,
1110         .main_clk       = "fdif_fck",
1111         .prcm = {
1112                 .omap4 = {
1113                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1114                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1115                         .modulemode   = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118 };
1119
1120 /*
1121  * 'gpio' class
1122  * general purpose io module
1123  */
1124
1125 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1126         .rev_offs       = 0x0000,
1127         .sysc_offs      = 0x0010,
1128         .syss_offs      = 0x0114,
1129         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1130                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1131                            SYSS_HAS_RESET_STATUS),
1132         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1133                            SIDLE_SMART_WKUP),
1134         .sysc_fields    = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1138         .name   = "gpio",
1139         .sysc   = &omap44xx_gpio_sysc,
1140         .rev    = 2,
1141 };
1142
1143 /* gpio dev_attr */
1144 static struct omap_gpio_dev_attr gpio_dev_attr = {
1145         .bank_width     = 32,
1146         .dbck_flag      = true,
1147 };
1148
1149 /* gpio1 */
1150 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1151         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1152         { .irq = -1 }
1153 };
1154
1155 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1156         { .role = "dbclk", .clk = "gpio1_dbclk" },
1157 };
1158
1159 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1160         .name           = "gpio1",
1161         .class          = &omap44xx_gpio_hwmod_class,
1162         .clkdm_name     = "l4_wkup_clkdm",
1163         .mpu_irqs       = omap44xx_gpio1_irqs,
1164         .main_clk       = "gpio1_ick",
1165         .prcm = {
1166                 .omap4 = {
1167                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .opt_clks       = gpio1_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1174         .dev_attr       = &gpio_dev_attr,
1175 };
1176
1177 /* gpio2 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1179         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1180         { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio2_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1188         .name           = "gpio2",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .mpu_irqs       = omap44xx_gpio2_irqs,
1193         .main_clk       = "gpio2_ick",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio2_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio3 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1208         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1209         { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio3_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1217         .name           = "gpio3",
1218         .class          = &omap44xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4_per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .mpu_irqs       = omap44xx_gpio3_irqs,
1222         .main_clk       = "gpio3_ick",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1226                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1227                         .modulemode   = MODULEMODE_HWCTRL,
1228                 },
1229         },
1230         .opt_clks       = gpio3_opt_clks,
1231         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1232         .dev_attr       = &gpio_dev_attr,
1233 };
1234
1235 /* gpio4 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1237         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1238         { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1242         { .role = "dbclk", .clk = "gpio4_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1246         .name           = "gpio4",
1247         .class          = &omap44xx_gpio_hwmod_class,
1248         .clkdm_name     = "l4_per_clkdm",
1249         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250         .mpu_irqs       = omap44xx_gpio4_irqs,
1251         .main_clk       = "gpio4_ick",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1256                         .modulemode   = MODULEMODE_HWCTRL,
1257                 },
1258         },
1259         .opt_clks       = gpio4_opt_clks,
1260         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1261         .dev_attr       = &gpio_dev_attr,
1262 };
1263
1264 /* gpio5 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1266         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1267         { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1271         { .role = "dbclk", .clk = "gpio5_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1275         .name           = "gpio5",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .clkdm_name     = "l4_per_clkdm",
1278         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279         .mpu_irqs       = omap44xx_gpio5_irqs,
1280         .main_clk       = "gpio5_ick",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_HWCTRL,
1286                 },
1287         },
1288         .opt_clks       = gpio5_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1290         .dev_attr       = &gpio_dev_attr,
1291 };
1292
1293 /* gpio6 */
1294 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1295         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1296         { .irq = -1 }
1297 };
1298
1299 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1300         { .role = "dbclk", .clk = "gpio6_dbclk" },
1301 };
1302
1303 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1304         .name           = "gpio6",
1305         .class          = &omap44xx_gpio_hwmod_class,
1306         .clkdm_name     = "l4_per_clkdm",
1307         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1308         .mpu_irqs       = omap44xx_gpio6_irqs,
1309         .main_clk       = "gpio6_ick",
1310         .prcm = {
1311                 .omap4 = {
1312                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1313                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1314                         .modulemode   = MODULEMODE_HWCTRL,
1315                 },
1316         },
1317         .opt_clks       = gpio6_opt_clks,
1318         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1319         .dev_attr       = &gpio_dev_attr,
1320 };
1321
1322 /*
1323  * 'gpmc' class
1324  * general purpose memory controller
1325  */
1326
1327 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1328         .rev_offs       = 0x0000,
1329         .sysc_offs      = 0x0010,
1330         .syss_offs      = 0x0014,
1331         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1332                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1334         .sysc_fields    = &omap_hwmod_sysc_type1,
1335 };
1336
1337 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1338         .name   = "gpmc",
1339         .sysc   = &omap44xx_gpmc_sysc,
1340 };
1341
1342 /* gpmc */
1343 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1344         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1345         { .irq = -1 }
1346 };
1347
1348 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1349         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1350         { .dma_req = -1 }
1351 };
1352
1353 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1354         .name           = "gpmc",
1355         .class          = &omap44xx_gpmc_hwmod_class,
1356         .clkdm_name     = "l3_2_clkdm",
1357         /*
1358          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1359          * block.  It is not being added due to any known bugs with
1360          * resetting the GPMC IP block, but rather because any timings
1361          * set by the bootloader are not being correctly programmed by
1362          * the kernel from the board file or DT data.
1363          * HWMOD_INIT_NO_RESET should be removed ASAP.
1364          */
1365         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1366         .mpu_irqs       = omap44xx_gpmc_irqs,
1367         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_HWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'gpu' class
1379  * 2d/3d graphics accelerator
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1383         .rev_offs       = 0x1fc00,
1384         .sysc_offs      = 0x1fc10,
1385         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1386         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1387                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1388                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1389         .sysc_fields    = &omap_hwmod_sysc_type2,
1390 };
1391
1392 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1393         .name   = "gpu",
1394         .sysc   = &omap44xx_gpu_sysc,
1395 };
1396
1397 /* gpu */
1398 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1399         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1400         { .irq = -1 }
1401 };
1402
1403 static struct omap_hwmod omap44xx_gpu_hwmod = {
1404         .name           = "gpu",
1405         .class          = &omap44xx_gpu_hwmod_class,
1406         .clkdm_name     = "l3_gfx_clkdm",
1407         .mpu_irqs       = omap44xx_gpu_irqs,
1408         .main_clk       = "gpu_fck",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hdq1w' class
1420  * hdq / 1-wire serial interface controller
1421  */
1422
1423 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1424         .rev_offs       = 0x0000,
1425         .sysc_offs      = 0x0014,
1426         .syss_offs      = 0x0018,
1427         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1428                            SYSS_HAS_RESET_STATUS),
1429         .sysc_fields    = &omap_hwmod_sysc_type1,
1430 };
1431
1432 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1433         .name   = "hdq1w",
1434         .sysc   = &omap44xx_hdq1w_sysc,
1435 };
1436
1437 /* hdq1w */
1438 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1439         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1440         { .irq = -1 }
1441 };
1442
1443 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1444         .name           = "hdq1w",
1445         .class          = &omap44xx_hdq1w_hwmod_class,
1446         .clkdm_name     = "l4_per_clkdm",
1447         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1448         .mpu_irqs       = omap44xx_hdq1w_irqs,
1449         .main_clk       = "hdq1w_fck",
1450         .prcm = {
1451                 .omap4 = {
1452                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1453                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1454                         .modulemode   = MODULEMODE_SWCTRL,
1455                 },
1456         },
1457 };
1458
1459 /*
1460  * 'hsi' class
1461  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1462  * serial if)
1463  */
1464
1465 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1466         .rev_offs       = 0x0000,
1467         .sysc_offs      = 0x0010,
1468         .syss_offs      = 0x0014,
1469         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1470                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1471                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1474                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1475         .sysc_fields    = &omap_hwmod_sysc_type1,
1476 };
1477
1478 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1479         .name   = "hsi",
1480         .sysc   = &omap44xx_hsi_sysc,
1481 };
1482
1483 /* hsi */
1484 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1485         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1488         { .irq = -1 }
1489 };
1490
1491 static struct omap_hwmod omap44xx_hsi_hwmod = {
1492         .name           = "hsi",
1493         .class          = &omap44xx_hsi_hwmod_class,
1494         .clkdm_name     = "l3_init_clkdm",
1495         .mpu_irqs       = omap44xx_hsi_irqs,
1496         .main_clk       = "hsi_fck",
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1500                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1501                         .modulemode   = MODULEMODE_HWCTRL,
1502                 },
1503         },
1504 };
1505
1506 /*
1507  * 'i2c' class
1508  * multimaster high-speed i2c controller
1509  */
1510
1511 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1512         .sysc_offs      = 0x0010,
1513         .syss_offs      = 0x0090,
1514         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1515                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1516                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1517         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1518                            SIDLE_SMART_WKUP),
1519         .clockact       = CLOCKACT_TEST_ICLK,
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1524         .name   = "i2c",
1525         .sysc   = &omap44xx_i2c_sysc,
1526         .rev    = OMAP_I2C_IP_VERSION_2,
1527         .reset  = &omap_i2c_reset,
1528 };
1529
1530 static struct omap_i2c_dev_attr i2c_dev_attr = {
1531         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1532 };
1533
1534 /* i2c1 */
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1537         { .irq = -1 }
1538 };
1539
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1543         { .dma_req = -1 }
1544 };
1545
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1547         .name           = "i2c1",
1548         .class          = &omap44xx_i2c_hwmod_class,
1549         .clkdm_name     = "l4_per_clkdm",
1550         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551         .mpu_irqs       = omap44xx_i2c1_irqs,
1552         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1553         .main_clk       = "i2c1_fck",
1554         .prcm = {
1555                 .omap4 = {
1556                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558                         .modulemode   = MODULEMODE_SWCTRL,
1559                 },
1560         },
1561         .dev_attr       = &i2c_dev_attr,
1562 };
1563
1564 /* i2c2 */
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1567         { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1573         { .dma_req = -1 }
1574 };
1575
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1577         .name           = "i2c2",
1578         .class          = &omap44xx_i2c_hwmod_class,
1579         .clkdm_name     = "l4_per_clkdm",
1580         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581         .mpu_irqs       = omap44xx_i2c2_irqs,
1582         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1583         .main_clk       = "i2c2_fck",
1584         .prcm = {
1585                 .omap4 = {
1586                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588                         .modulemode   = MODULEMODE_SWCTRL,
1589                 },
1590         },
1591         .dev_attr       = &i2c_dev_attr,
1592 };
1593
1594 /* i2c3 */
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1597         { .irq = -1 }
1598 };
1599
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1603         { .dma_req = -1 }
1604 };
1605
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1607         .name           = "i2c3",
1608         .class          = &omap44xx_i2c_hwmod_class,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611         .mpu_irqs       = omap44xx_i2c3_irqs,
1612         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1613         .main_clk       = "i2c3_fck",
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618                         .modulemode   = MODULEMODE_SWCTRL,
1619                 },
1620         },
1621         .dev_attr       = &i2c_dev_attr,
1622 };
1623
1624 /* i2c4 */
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1627         { .irq = -1 }
1628 };
1629
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1633         { .dma_req = -1 }
1634 };
1635
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1637         .name           = "i2c4",
1638         .class          = &omap44xx_i2c_hwmod_class,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641         .mpu_irqs       = omap44xx_i2c4_irqs,
1642         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1643         .main_clk       = "i2c4_fck",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_SWCTRL,
1649                 },
1650         },
1651         .dev_attr       = &i2c_dev_attr,
1652 };
1653
1654 /*
1655  * 'ipu' class
1656  * imaging processor unit
1657  */
1658
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1660         .name   = "ipu",
1661 };
1662
1663 /* ipu */
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1666         { .irq = -1 }
1667 };
1668
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670         { .name = "cpu0", .rst_shift = 0 },
1671         { .name = "cpu1", .rst_shift = 1 },
1672 };
1673
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1675         .name           = "ipu",
1676         .class          = &omap44xx_ipu_hwmod_class,
1677         .clkdm_name     = "ducati_clkdm",
1678         .mpu_irqs       = omap44xx_ipu_irqs,
1679         .rst_lines      = omap44xx_ipu_resets,
1680         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1681         .main_clk       = "ducati_clk_mux_ck",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_HWCTRL,
1688                 },
1689         },
1690 };
1691
1692 /*
1693  * 'iss' class
1694  * external images sensor pixel data processor
1695  */
1696
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         /*
1701          * ISS needs 100 OCP clk cycles delay after a softreset before
1702          * accessing sysconfig again.
1703          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1705          *
1706          * TODO: Indicate errata when available.
1707          */
1708         .srst_udelay    = 2,
1709         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714         .sysc_fields    = &omap_hwmod_sysc_type2,
1715 };
1716
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1718         .name   = "iss",
1719         .sysc   = &omap44xx_iss_sysc,
1720 };
1721
1722 /* iss */
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1725         { .irq = -1 }
1726 };
1727
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1733         { .dma_req = -1 }
1734 };
1735
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1738 };
1739
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1741         .name           = "iss",
1742         .class          = &omap44xx_iss_hwmod_class,
1743         .clkdm_name     = "iss_clkdm",
1744         .mpu_irqs       = omap44xx_iss_irqs,
1745         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1746         .main_clk       = "iss_fck",
1747         .prcm = {
1748                 .omap4 = {
1749                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751                         .modulemode   = MODULEMODE_SWCTRL,
1752                 },
1753         },
1754         .opt_clks       = iss_opt_clks,
1755         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1756 };
1757
1758 /*
1759  * 'iva' class
1760  * multi-standard video encoder/decoder hardware accelerator
1761  */
1762
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1764         .name   = "iva",
1765 };
1766
1767 /* iva */
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776         { .name = "seq0", .rst_shift = 0 },
1777         { .name = "seq1", .rst_shift = 1 },
1778         { .name = "logic", .rst_shift = 2 },
1779 };
1780
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1782         .name           = "iva",
1783         .class          = &omap44xx_iva_hwmod_class,
1784         .clkdm_name     = "ivahd_clkdm",
1785         .mpu_irqs       = omap44xx_iva_irqs,
1786         .rst_lines      = omap44xx_iva_resets,
1787         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1788         .main_clk       = "iva_fck",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794                         .modulemode   = MODULEMODE_HWCTRL,
1795                 },
1796         },
1797 };
1798
1799 /*
1800  * 'kbd' class
1801  * keyboard controller
1802  */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0014,
1808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811                            SYSS_HAS_RESET_STATUS),
1812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813         .sysc_fields    = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1817         .name   = "kbd",
1818         .sysc   = &omap44xx_kbd_sysc,
1819 };
1820
1821 /* kbd */
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1828         .name           = "kbd",
1829         .class          = &omap44xx_kbd_hwmod_class,
1830         .clkdm_name     = "l4_wkup_clkdm",
1831         .mpu_irqs       = omap44xx_kbd_irqs,
1832         .main_clk       = "kbd_fck",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mailbox' class
1844  * mailbox module allowing communication between the on-chip processors using a
1845  * queued mailbox-interrupt mechanism.
1846  */
1847
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1849         .rev_offs       = 0x0000,
1850         .sysc_offs      = 0x0010,
1851         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852                            SYSC_HAS_SOFTRESET),
1853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854         .sysc_fields    = &omap_hwmod_sysc_type2,
1855 };
1856
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1858         .name   = "mailbox",
1859         .sysc   = &omap44xx_mailbox_sysc,
1860 };
1861
1862 /* mailbox */
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1865         { .irq = -1 }
1866 };
1867
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1869         .name           = "mailbox",
1870         .class          = &omap44xx_mailbox_hwmod_class,
1871         .clkdm_name     = "l4_cfg_clkdm",
1872         .mpu_irqs       = omap44xx_mailbox_irqs,
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'mcasp' class
1883  * multi-channel audio serial port controller
1884  */
1885
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1888         .sidle_shift    = 0,
1889 };
1890
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892         .sysc_offs      = 0x0004,
1893         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1895                            SIDLE_SMART_WKUP),
1896         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1897 };
1898
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1900         .name   = "mcasp",
1901         .sysc   = &omap44xx_mcasp_sysc,
1902 };
1903
1904 /* mcasp */
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1908         { .irq = -1 }
1909 };
1910
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1914         { .dma_req = -1 }
1915 };
1916
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1918         .name           = "mcasp",
1919         .class          = &omap44xx_mcasp_hwmod_class,
1920         .clkdm_name     = "abe_clkdm",
1921         .mpu_irqs       = omap44xx_mcasp_irqs,
1922         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1923         .main_clk       = "mcasp_fck",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931 };
1932
1933 /*
1934  * 'mcbsp' class
1935  * multi channel buffered serial port controller
1936  */
1937
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939         .sysc_offs      = 0x008c,
1940         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943         .sysc_fields    = &omap_hwmod_sysc_type1,
1944 };
1945
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1947         .name   = "mcbsp",
1948         .sysc   = &omap44xx_mcbsp_sysc,
1949         .rev    = MCBSP_CONFIG_TYPE4,
1950 };
1951
1952 /* mcbsp1 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1970         .name           = "mcbsp1",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1975         .main_clk       = "mcbsp1_fck",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp1_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1985 };
1986
1987 /* mcbsp2 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2005         .name           = "mcbsp2",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2010         .main_clk       = "mcbsp2_fck",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp2_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2020 };
2021
2022 /* mcbsp3 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2040         .name           = "mcbsp3",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "abe_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2045         .main_clk       = "mcbsp3_fck",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp3_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2055 };
2056
2057 /* mcbsp4 */
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2060         { .irq = -1 }
2061 };
2062
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2066         { .dma_req = -1 }
2067 };
2068
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070         { .role = "pad_fck", .clk = "pad_clks_ck" },
2071         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2072 };
2073
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2075         .name           = "mcbsp4",
2076         .class          = &omap44xx_mcbsp_hwmod_class,
2077         .clkdm_name     = "l4_per_clkdm",
2078         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2079         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2080         .main_clk       = "mcbsp4_fck",
2081         .prcm = {
2082                 .omap4 = {
2083                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085                         .modulemode   = MODULEMODE_SWCTRL,
2086                 },
2087         },
2088         .opt_clks       = mcbsp4_opt_clks,
2089         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2090 };
2091
2092 /*
2093  * 'mcpdm' class
2094  * multi channel pdm controller (proprietary interface with phoenix power
2095  * ic)
2096  */
2097
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2099         .rev_offs       = 0x0000,
2100         .sysc_offs      = 0x0010,
2101         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2104                            SIDLE_SMART_WKUP),
2105         .sysc_fields    = &omap_hwmod_sysc_type2,
2106 };
2107
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2109         .name   = "mcpdm",
2110         .sysc   = &omap44xx_mcpdm_sysc,
2111 };
2112
2113 /* mcpdm */
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2116         { .irq = -1 }
2117 };
2118
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2122         { .dma_req = -1 }
2123 };
2124
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2126         .name           = "mcpdm",
2127         .class          = &omap44xx_mcpdm_hwmod_class,
2128         .clkdm_name     = "abe_clkdm",
2129         /*
2130          * It's suspected that the McPDM requires an off-chip main
2131          * functional clock, controlled via I2C.  This IP block is
2132          * currently reset very early during boot, before I2C is
2133          * available, so it doesn't seem that we have any choice in
2134          * the kernel other than to avoid resetting it.
2135          */
2136         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2137         .mpu_irqs       = omap44xx_mcpdm_irqs,
2138         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2139         .main_clk       = "mcpdm_fck",
2140         .prcm = {
2141                 .omap4 = {
2142                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2143                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2144                         .modulemode   = MODULEMODE_SWCTRL,
2145                 },
2146         },
2147 };
2148
2149 /*
2150  * 'mcspi' class
2151  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2152  * bus
2153  */
2154
2155 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2156         .rev_offs       = 0x0000,
2157         .sysc_offs      = 0x0010,
2158         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2159                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2160         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2161                            SIDLE_SMART_WKUP),
2162         .sysc_fields    = &omap_hwmod_sysc_type2,
2163 };
2164
2165 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2166         .name   = "mcspi",
2167         .sysc   = &omap44xx_mcspi_sysc,
2168         .rev    = OMAP4_MCSPI_REV,
2169 };
2170
2171 /* mcspi1 */
2172 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2173         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2174         { .irq = -1 }
2175 };
2176
2177 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2178         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2179         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2180         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2181         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2182         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2183         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2184         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2185         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2186         { .dma_req = -1 }
2187 };
2188
2189 /* mcspi1 dev_attr */
2190 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2191         .num_chipselect = 4,
2192 };
2193
2194 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2195         .name           = "mcspi1",
2196         .class          = &omap44xx_mcspi_hwmod_class,
2197         .clkdm_name     = "l4_per_clkdm",
2198         .mpu_irqs       = omap44xx_mcspi1_irqs,
2199         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2200         .main_clk       = "mcspi1_fck",
2201         .prcm = {
2202                 .omap4 = {
2203                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2204                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2205                         .modulemode   = MODULEMODE_SWCTRL,
2206                 },
2207         },
2208         .dev_attr       = &mcspi1_dev_attr,
2209 };
2210
2211 /* mcspi2 */
2212 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2213         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2214         { .irq = -1 }
2215 };
2216
2217 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2218         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2219         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2220         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2221         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2222         { .dma_req = -1 }
2223 };
2224
2225 /* mcspi2 dev_attr */
2226 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2227         .num_chipselect = 2,
2228 };
2229
2230 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2231         .name           = "mcspi2",
2232         .class          = &omap44xx_mcspi_hwmod_class,
2233         .clkdm_name     = "l4_per_clkdm",
2234         .mpu_irqs       = omap44xx_mcspi2_irqs,
2235         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2236         .main_clk       = "mcspi2_fck",
2237         .prcm = {
2238                 .omap4 = {
2239                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2240                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2241                         .modulemode   = MODULEMODE_SWCTRL,
2242                 },
2243         },
2244         .dev_attr       = &mcspi2_dev_attr,
2245 };
2246
2247 /* mcspi3 */
2248 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2249         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2250         { .irq = -1 }
2251 };
2252
2253 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2254         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2255         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2256         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2257         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2258         { .dma_req = -1 }
2259 };
2260
2261 /* mcspi3 dev_attr */
2262 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2263         .num_chipselect = 2,
2264 };
2265
2266 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2267         .name           = "mcspi3",
2268         .class          = &omap44xx_mcspi_hwmod_class,
2269         .clkdm_name     = "l4_per_clkdm",
2270         .mpu_irqs       = omap44xx_mcspi3_irqs,
2271         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2272         .main_clk       = "mcspi3_fck",
2273         .prcm = {
2274                 .omap4 = {
2275                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2276                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2277                         .modulemode   = MODULEMODE_SWCTRL,
2278                 },
2279         },
2280         .dev_attr       = &mcspi3_dev_attr,
2281 };
2282
2283 /* mcspi4 */
2284 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2285         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2286         { .irq = -1 }
2287 };
2288
2289 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2290         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2291         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2292         { .dma_req = -1 }
2293 };
2294
2295 /* mcspi4 dev_attr */
2296 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2297         .num_chipselect = 1,
2298 };
2299
2300 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2301         .name           = "mcspi4",
2302         .class          = &omap44xx_mcspi_hwmod_class,
2303         .clkdm_name     = "l4_per_clkdm",
2304         .mpu_irqs       = omap44xx_mcspi4_irqs,
2305         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2306         .main_clk       = "mcspi4_fck",
2307         .prcm = {
2308                 .omap4 = {
2309                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2310                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2311                         .modulemode   = MODULEMODE_SWCTRL,
2312                 },
2313         },
2314         .dev_attr       = &mcspi4_dev_attr,
2315 };
2316
2317 /*
2318  * 'mmc' class
2319  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2320  */
2321
2322 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2323         .rev_offs       = 0x0000,
2324         .sysc_offs      = 0x0010,
2325         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2326                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2327                            SYSC_HAS_SOFTRESET),
2328         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2329                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2330                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2331         .sysc_fields    = &omap_hwmod_sysc_type2,
2332 };
2333
2334 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2335         .name   = "mmc",
2336         .sysc   = &omap44xx_mmc_sysc,
2337 };
2338
2339 /* mmc1 */
2340 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2341         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2342         { .irq = -1 }
2343 };
2344
2345 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2346         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2347         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2348         { .dma_req = -1 }
2349 };
2350
2351 /* mmc1 dev_attr */
2352 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2353         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2354 };
2355
2356 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2357         .name           = "mmc1",
2358         .class          = &omap44xx_mmc_hwmod_class,
2359         .clkdm_name     = "l3_init_clkdm",
2360         .mpu_irqs       = omap44xx_mmc1_irqs,
2361         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2362         .main_clk       = "mmc1_fck",
2363         .prcm = {
2364                 .omap4 = {
2365                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2366                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2367                         .modulemode   = MODULEMODE_SWCTRL,
2368                 },
2369         },
2370         .dev_attr       = &mmc1_dev_attr,
2371 };
2372
2373 /* mmc2 */
2374 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2375         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2376         { .irq = -1 }
2377 };
2378
2379 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2380         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2381         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2382         { .dma_req = -1 }
2383 };
2384
2385 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2386         .name           = "mmc2",
2387         .class          = &omap44xx_mmc_hwmod_class,
2388         .clkdm_name     = "l3_init_clkdm",
2389         .mpu_irqs       = omap44xx_mmc2_irqs,
2390         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2391         .main_clk       = "mmc2_fck",
2392         .prcm = {
2393                 .omap4 = {
2394                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2395                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2396                         .modulemode   = MODULEMODE_SWCTRL,
2397                 },
2398         },
2399 };
2400
2401 /* mmc3 */
2402 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2403         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2404         { .irq = -1 }
2405 };
2406
2407 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2408         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2409         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2410         { .dma_req = -1 }
2411 };
2412
2413 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2414         .name           = "mmc3",
2415         .class          = &omap44xx_mmc_hwmod_class,
2416         .clkdm_name     = "l4_per_clkdm",
2417         .mpu_irqs       = omap44xx_mmc3_irqs,
2418         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2419         .main_clk       = "mmc3_fck",
2420         .prcm = {
2421                 .omap4 = {
2422                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2423                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2424                         .modulemode   = MODULEMODE_SWCTRL,
2425                 },
2426         },
2427 };
2428
2429 /* mmc4 */
2430 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2431         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2432         { .irq = -1 }
2433 };
2434
2435 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2436         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2437         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2438         { .dma_req = -1 }
2439 };
2440
2441 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2442         .name           = "mmc4",
2443         .class          = &omap44xx_mmc_hwmod_class,
2444         .clkdm_name     = "l4_per_clkdm",
2445         .mpu_irqs       = omap44xx_mmc4_irqs,
2446         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2447         .main_clk       = "mmc4_fck",
2448         .prcm = {
2449                 .omap4 = {
2450                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2451                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2452                         .modulemode   = MODULEMODE_SWCTRL,
2453                 },
2454         },
2455 };
2456
2457 /* mmc5 */
2458 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2459         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2460         { .irq = -1 }
2461 };
2462
2463 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2464         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2465         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2466         { .dma_req = -1 }
2467 };
2468
2469 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2470         .name           = "mmc5",
2471         .class          = &omap44xx_mmc_hwmod_class,
2472         .clkdm_name     = "l4_per_clkdm",
2473         .mpu_irqs       = omap44xx_mmc5_irqs,
2474         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2475         .main_clk       = "mmc5_fck",
2476         .prcm = {
2477                 .omap4 = {
2478                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2479                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2480                         .modulemode   = MODULEMODE_SWCTRL,
2481                 },
2482         },
2483 };
2484
2485 /*
2486  * 'mmu' class
2487  * The memory management unit performs virtual to physical address translation
2488  * for its requestors.
2489  */
2490
2491 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2492         .rev_offs       = 0x000,
2493         .sysc_offs      = 0x010,
2494         .syss_offs      = 0x014,
2495         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2496                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2497         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2498         .sysc_fields    = &omap_hwmod_sysc_type1,
2499 };
2500
2501 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2502         .name = "mmu",
2503         .sysc = &mmu_sysc,
2504 };
2505
2506 /* mmu ipu */
2507
2508 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2509         .da_start       = 0x0,
2510         .da_end         = 0xfffff000,
2511         .nr_tlb_entries = 32,
2512 };
2513
2514 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2515 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2516         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2517         { .irq = -1 }
2518 };
2519
2520 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2521         { .name = "mmu_cache", .rst_shift = 2 },
2522 };
2523
2524 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2525         {
2526                 .pa_start       = 0x55082000,
2527                 .pa_end         = 0x550820ff,
2528                 .flags          = ADDR_TYPE_RT,
2529         },
2530         { }
2531 };
2532
2533 /* l3_main_2 -> mmu_ipu */
2534 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2535         .master         = &omap44xx_l3_main_2_hwmod,
2536         .slave          = &omap44xx_mmu_ipu_hwmod,
2537         .clk            = "l3_div_ck",
2538         .addr           = omap44xx_mmu_ipu_addrs,
2539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2540 };
2541
2542 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2543         .name           = "mmu_ipu",
2544         .class          = &omap44xx_mmu_hwmod_class,
2545         .clkdm_name     = "ducati_clkdm",
2546         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2547         .rst_lines      = omap44xx_mmu_ipu_resets,
2548         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2549         .main_clk       = "ducati_clk_mux_ck",
2550         .prcm = {
2551                 .omap4 = {
2552                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2553                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2554                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2555                         .modulemode   = MODULEMODE_HWCTRL,
2556                 },
2557         },
2558         .dev_attr       = &mmu_ipu_dev_attr,
2559 };
2560
2561 /* mmu dsp */
2562
2563 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2564         .da_start       = 0x0,
2565         .da_end         = 0xfffff000,
2566         .nr_tlb_entries = 32,
2567 };
2568
2569 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2570 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2571         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2572         { .irq = -1 }
2573 };
2574
2575 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2576         { .name = "mmu_cache", .rst_shift = 1 },
2577 };
2578
2579 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2580         {
2581                 .pa_start       = 0x4a066000,
2582                 .pa_end         = 0x4a0660ff,
2583                 .flags          = ADDR_TYPE_RT,
2584         },
2585         { }
2586 };
2587
2588 /* l4_cfg -> dsp */
2589 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2590         .master         = &omap44xx_l4_cfg_hwmod,
2591         .slave          = &omap44xx_mmu_dsp_hwmod,
2592         .clk            = "l4_div_ck",
2593         .addr           = omap44xx_mmu_dsp_addrs,
2594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596
2597 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2598         .name           = "mmu_dsp",
2599         .class          = &omap44xx_mmu_hwmod_class,
2600         .clkdm_name     = "tesla_clkdm",
2601         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2602         .rst_lines      = omap44xx_mmu_dsp_resets,
2603         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2604         .main_clk       = "dpll_iva_m4x2_ck",
2605         .prcm = {
2606                 .omap4 = {
2607                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2608                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2609                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2610                         .modulemode   = MODULEMODE_HWCTRL,
2611                 },
2612         },
2613         .dev_attr       = &mmu_dsp_dev_attr,
2614 };
2615
2616 /*
2617  * 'mpu' class
2618  * mpu sub-system
2619  */
2620
2621 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2622         .name   = "mpu",
2623 };
2624
2625 /* mpu */
2626 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2627         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2628         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2629         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2630         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2631         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2632         { .irq = -1 }
2633 };
2634
2635 static struct omap_hwmod omap44xx_mpu_hwmod = {
2636         .name           = "mpu",
2637         .class          = &omap44xx_mpu_hwmod_class,
2638         .clkdm_name     = "mpuss_clkdm",
2639         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2640         .mpu_irqs       = omap44xx_mpu_irqs,
2641         .main_clk       = "dpll_mpu_m2_ck",
2642         .prcm = {
2643                 .omap4 = {
2644                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2645                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2646                 },
2647         },
2648 };
2649
2650 /*
2651  * 'ocmc_ram' class
2652  * top-level core on-chip ram
2653  */
2654
2655 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2656         .name   = "ocmc_ram",
2657 };
2658
2659 /* ocmc_ram */
2660 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2661         .name           = "ocmc_ram",
2662         .class          = &omap44xx_ocmc_ram_hwmod_class,
2663         .clkdm_name     = "l3_2_clkdm",
2664         .prcm = {
2665                 .omap4 = {
2666                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2667                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2668                 },
2669         },
2670 };
2671
2672 /*
2673  * 'ocp2scp' class
2674  * bridge to transform ocp interface protocol to scp (serial control port)
2675  * protocol
2676  */
2677
2678 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2679         .rev_offs       = 0x0000,
2680         .sysc_offs      = 0x0010,
2681         .syss_offs      = 0x0014,
2682         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2683                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2684         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2685         .sysc_fields    = &omap_hwmod_sysc_type1,
2686 };
2687
2688 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2689         .name   = "ocp2scp",
2690         .sysc   = &omap44xx_ocp2scp_sysc,
2691 };
2692
2693 /* ocp2scp dev_attr */
2694 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2695         {
2696                 .name           = "usb_phy",
2697                 .start          = 0x4a0ad080,
2698                 .end            = 0x4a0ae000,
2699                 .flags          = IORESOURCE_MEM,
2700         },
2701         {
2702                 /* XXX: Remove this once control module driver is in place */
2703                 .name           = "ctrl_dev",
2704                 .start          = 0x4a002300,
2705                 .end            = 0x4a002303,
2706                 .flags          = IORESOURCE_MEM,
2707         },
2708         { }
2709 };
2710
2711 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2712         {
2713                 .drv_name       = "omap-usb2",
2714                 .res            = omap44xx_usb_phy_and_pll_addrs,
2715         },
2716         { }
2717 };
2718
2719 /* ocp2scp_usb_phy */
2720 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2721         .name           = "ocp2scp_usb_phy",
2722         .class          = &omap44xx_ocp2scp_hwmod_class,
2723         .clkdm_name     = "l3_init_clkdm",
2724         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2725         .prcm = {
2726                 .omap4 = {
2727                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2728                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2729                         .modulemode   = MODULEMODE_HWCTRL,
2730                 },
2731         },
2732         .dev_attr       = ocp2scp_dev_attr,
2733 };
2734
2735 /*
2736  * 'prcm' class
2737  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2738  * + clock manager 1 (in always on power domain) + local prm in mpu
2739  */
2740
2741 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2742         .name   = "prcm",
2743 };
2744
2745 /* prcm_mpu */
2746 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2747         .name           = "prcm_mpu",
2748         .class          = &omap44xx_prcm_hwmod_class,
2749         .clkdm_name     = "l4_wkup_clkdm",
2750         .flags          = HWMOD_NO_IDLEST,
2751         .prcm = {
2752                 .omap4 = {
2753                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2754                 },
2755         },
2756 };
2757
2758 /* cm_core_aon */
2759 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2760         .name           = "cm_core_aon",
2761         .class          = &omap44xx_prcm_hwmod_class,
2762         .flags          = HWMOD_NO_IDLEST,
2763         .prcm = {
2764                 .omap4 = {
2765                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2766                 },
2767         },
2768 };
2769
2770 /* cm_core */
2771 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2772         .name           = "cm_core",
2773         .class          = &omap44xx_prcm_hwmod_class,
2774         .flags          = HWMOD_NO_IDLEST,
2775         .prcm = {
2776                 .omap4 = {
2777                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2778                 },
2779         },
2780 };
2781
2782 /* prm */
2783 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2784         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2785         { .irq = -1 }
2786 };
2787
2788 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2789         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2790         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2791 };
2792
2793 static struct omap_hwmod omap44xx_prm_hwmod = {
2794         .name           = "prm",
2795         .class          = &omap44xx_prcm_hwmod_class,
2796         .mpu_irqs       = omap44xx_prm_irqs,
2797         .rst_lines      = omap44xx_prm_resets,
2798         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2799 };
2800
2801 /*
2802  * 'scrm' class
2803  * system clock and reset manager
2804  */
2805
2806 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2807         .name   = "scrm",
2808 };
2809
2810 /* scrm */
2811 static struct omap_hwmod omap44xx_scrm_hwmod = {
2812         .name           = "scrm",
2813         .class          = &omap44xx_scrm_hwmod_class,
2814         .clkdm_name     = "l4_wkup_clkdm",
2815         .prcm = {
2816                 .omap4 = {
2817                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2818                 },
2819         },
2820 };
2821
2822 /*
2823  * 'sl2if' class
2824  * shared level 2 memory interface
2825  */
2826
2827 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2828         .name   = "sl2if",
2829 };
2830
2831 /* sl2if */
2832 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2833         .name           = "sl2if",
2834         .class          = &omap44xx_sl2if_hwmod_class,
2835         .clkdm_name     = "ivahd_clkdm",
2836         .prcm = {
2837                 .omap4 = {
2838                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2839                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2840                         .modulemode   = MODULEMODE_HWCTRL,
2841                 },
2842         },
2843 };
2844
2845 /*
2846  * 'slimbus' class
2847  * bidirectional, multi-drop, multi-channel two-line serial interface between
2848  * the device and external components
2849  */
2850
2851 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2852         .rev_offs       = 0x0000,
2853         .sysc_offs      = 0x0010,
2854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2855                            SYSC_HAS_SOFTRESET),
2856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2857                            SIDLE_SMART_WKUP),
2858         .sysc_fields    = &omap_hwmod_sysc_type2,
2859 };
2860
2861 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2862         .name   = "slimbus",
2863         .sysc   = &omap44xx_slimbus_sysc,
2864 };
2865
2866 /* slimbus1 */
2867 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2868         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2869         { .irq = -1 }
2870 };
2871
2872 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2873         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2874         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2875         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2876         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2877         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2878         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2879         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2880         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2881         { .dma_req = -1 }
2882 };
2883
2884 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2885         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2886         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2887         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2888         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2889 };
2890
2891 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2892         .name           = "slimbus1",
2893         .class          = &omap44xx_slimbus_hwmod_class,
2894         .clkdm_name     = "abe_clkdm",
2895         .mpu_irqs       = omap44xx_slimbus1_irqs,
2896         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2897         .prcm = {
2898                 .omap4 = {
2899                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2900                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2901                         .modulemode   = MODULEMODE_SWCTRL,
2902                 },
2903         },
2904         .opt_clks       = slimbus1_opt_clks,
2905         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2906 };
2907
2908 /* slimbus2 */
2909 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2910         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2911         { .irq = -1 }
2912 };
2913
2914 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2915         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2916         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2917         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2918         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2919         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2920         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2921         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2922         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2923         { .dma_req = -1 }
2924 };
2925
2926 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2927         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2928         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2929         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2930 };
2931
2932 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2933         .name           = "slimbus2",
2934         .class          = &omap44xx_slimbus_hwmod_class,
2935         .clkdm_name     = "l4_per_clkdm",
2936         .mpu_irqs       = omap44xx_slimbus2_irqs,
2937         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2938         .prcm = {
2939                 .omap4 = {
2940                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2941                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2942                         .modulemode   = MODULEMODE_SWCTRL,
2943                 },
2944         },
2945         .opt_clks       = slimbus2_opt_clks,
2946         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2947 };
2948
2949 /*
2950  * 'smartreflex' class
2951  * smartreflex module (monitor silicon performance and outputs a measure of
2952  * performance error)
2953  */
2954
2955 /* The IP is not compliant to type1 / type2 scheme */
2956 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2957         .sidle_shift    = 24,
2958         .enwkup_shift   = 26,
2959 };
2960
2961 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2962         .sysc_offs      = 0x0038,
2963         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2964         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2965                            SIDLE_SMART_WKUP),
2966         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2967 };
2968
2969 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2970         .name   = "smartreflex",
2971         .sysc   = &omap44xx_smartreflex_sysc,
2972         .rev    = 2,
2973 };
2974
2975 /* smartreflex_core */
2976 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2977         .sensor_voltdm_name   = "core",
2978 };
2979
2980 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2981         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2982         { .irq = -1 }
2983 };
2984
2985 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2986         .name           = "smartreflex_core",
2987         .class          = &omap44xx_smartreflex_hwmod_class,
2988         .clkdm_name     = "l4_ao_clkdm",
2989         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2990
2991         .main_clk       = "smartreflex_core_fck",
2992         .prcm = {
2993                 .omap4 = {
2994                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2995                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2996                         .modulemode   = MODULEMODE_SWCTRL,
2997                 },
2998         },
2999         .dev_attr       = &smartreflex_core_dev_attr,
3000 };
3001
3002 /* smartreflex_iva */
3003 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3004         .sensor_voltdm_name     = "iva",
3005 };
3006
3007 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3008         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3009         { .irq = -1 }
3010 };
3011
3012 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3013         .name           = "smartreflex_iva",
3014         .class          = &omap44xx_smartreflex_hwmod_class,
3015         .clkdm_name     = "l4_ao_clkdm",
3016         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3017         .main_clk       = "smartreflex_iva_fck",
3018         .prcm = {
3019                 .omap4 = {
3020                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3021                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3022                         .modulemode   = MODULEMODE_SWCTRL,
3023                 },
3024         },
3025         .dev_attr       = &smartreflex_iva_dev_attr,
3026 };
3027
3028 /* smartreflex_mpu */
3029 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3030         .sensor_voltdm_name     = "mpu",
3031 };
3032
3033 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3034         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3035         { .irq = -1 }
3036 };
3037
3038 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3039         .name           = "smartreflex_mpu",
3040         .class          = &omap44xx_smartreflex_hwmod_class,
3041         .clkdm_name     = "l4_ao_clkdm",
3042         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3043         .main_clk       = "smartreflex_mpu_fck",
3044         .prcm = {
3045                 .omap4 = {
3046                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3047                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3048                         .modulemode   = MODULEMODE_SWCTRL,
3049                 },
3050         },
3051         .dev_attr       = &smartreflex_mpu_dev_attr,
3052 };
3053
3054 /*
3055  * 'spinlock' class
3056  * spinlock provides hardware assistance for synchronizing the processes
3057  * running on multiple processors
3058  */
3059
3060 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3061         .rev_offs       = 0x0000,
3062         .sysc_offs      = 0x0010,
3063         .syss_offs      = 0x0014,
3064         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3065                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3066                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3067         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3068                            SIDLE_SMART_WKUP),
3069         .sysc_fields    = &omap_hwmod_sysc_type1,
3070 };
3071
3072 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3073         .name   = "spinlock",
3074         .sysc   = &omap44xx_spinlock_sysc,
3075 };
3076
3077 /* spinlock */
3078 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3079         .name           = "spinlock",
3080         .class          = &omap44xx_spinlock_hwmod_class,
3081         .clkdm_name     = "l4_cfg_clkdm",
3082         .prcm = {
3083                 .omap4 = {
3084                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3085                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3086                 },
3087         },
3088 };
3089
3090 /*
3091  * 'timer' class
3092  * general purpose timer module with accurate 1ms tick
3093  * This class contains several variants: ['timer_1ms', 'timer']
3094  */
3095
3096 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3097         .rev_offs       = 0x0000,
3098         .sysc_offs      = 0x0010,
3099         .syss_offs      = 0x0014,
3100         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3101                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3103                            SYSS_HAS_RESET_STATUS),
3104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3105         .clockact       = CLOCKACT_TEST_ICLK,
3106         .sysc_fields    = &omap_hwmod_sysc_type1,
3107 };
3108
3109 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3110         .name   = "timer",
3111         .sysc   = &omap44xx_timer_1ms_sysc,
3112 };
3113
3114 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3115         .rev_offs       = 0x0000,
3116         .sysc_offs      = 0x0010,
3117         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3118                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3119         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3120                            SIDLE_SMART_WKUP),
3121         .sysc_fields    = &omap_hwmod_sysc_type2,
3122 };
3123
3124 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3125         .name   = "timer",
3126         .sysc   = &omap44xx_timer_sysc,
3127 };
3128
3129 /* always-on timers dev attribute */
3130 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3131         .timer_capability       = OMAP_TIMER_ALWON,
3132 };
3133
3134 /* pwm timers dev attribute */
3135 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3136         .timer_capability       = OMAP_TIMER_HAS_PWM,
3137 };
3138
3139 /* timers with DSP interrupt dev attribute */
3140 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3141         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3142 };
3143
3144 /* pwm timers with DSP interrupt dev attribute */
3145 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3146         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3147 };
3148
3149 /* timer1 */
3150 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3151         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3152         { .irq = -1 }
3153 };
3154
3155 static struct omap_hwmod omap44xx_timer1_hwmod = {
3156         .name           = "timer1",
3157         .class          = &omap44xx_timer_1ms_hwmod_class,
3158         .clkdm_name     = "l4_wkup_clkdm",
3159         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3160         .mpu_irqs       = omap44xx_timer1_irqs,
3161         .main_clk       = "timer1_fck",
3162         .prcm = {
3163                 .omap4 = {
3164                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3165                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3166                         .modulemode   = MODULEMODE_SWCTRL,
3167                 },
3168         },
3169         .dev_attr       = &capability_alwon_dev_attr,
3170 };
3171
3172 /* timer2 */
3173 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3174         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3175         { .irq = -1 }
3176 };
3177
3178 static struct omap_hwmod omap44xx_timer2_hwmod = {
3179         .name           = "timer2",
3180         .class          = &omap44xx_timer_1ms_hwmod_class,
3181         .clkdm_name     = "l4_per_clkdm",
3182         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3183         .mpu_irqs       = omap44xx_timer2_irqs,
3184         .main_clk       = "timer2_fck",
3185         .prcm = {
3186                 .omap4 = {
3187                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3188                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3189                         .modulemode   = MODULEMODE_SWCTRL,
3190                 },
3191         },
3192 };
3193
3194 /* timer3 */
3195 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3196         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3197         { .irq = -1 }
3198 };
3199
3200 static struct omap_hwmod omap44xx_timer3_hwmod = {
3201         .name           = "timer3",
3202         .class          = &omap44xx_timer_hwmod_class,
3203         .clkdm_name     = "l4_per_clkdm",
3204         .mpu_irqs       = omap44xx_timer3_irqs,
3205         .main_clk       = "timer3_fck",
3206         .prcm = {
3207                 .omap4 = {
3208                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3209                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3210                         .modulemode   = MODULEMODE_SWCTRL,
3211                 },
3212         },
3213 };
3214
3215 /* timer4 */
3216 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3217         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3218         { .irq = -1 }
3219 };
3220
3221 static struct omap_hwmod omap44xx_timer4_hwmod = {
3222         .name           = "timer4",
3223         .class          = &omap44xx_timer_hwmod_class,
3224         .clkdm_name     = "l4_per_clkdm",
3225         .mpu_irqs       = omap44xx_timer4_irqs,
3226         .main_clk       = "timer4_fck",
3227         .prcm = {
3228                 .omap4 = {
3229                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3230                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3231                         .modulemode   = MODULEMODE_SWCTRL,
3232                 },
3233         },
3234 };
3235
3236 /* timer5 */
3237 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3238         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3239         { .irq = -1 }
3240 };
3241
3242 static struct omap_hwmod omap44xx_timer5_hwmod = {
3243         .name           = "timer5",
3244         .class          = &omap44xx_timer_hwmod_class,
3245         .clkdm_name     = "abe_clkdm",
3246         .mpu_irqs       = omap44xx_timer5_irqs,
3247         .main_clk       = "timer5_fck",
3248         .prcm = {
3249                 .omap4 = {
3250                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3251                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3252                         .modulemode   = MODULEMODE_SWCTRL,
3253                 },
3254         },
3255         .dev_attr       = &capability_dsp_dev_attr,
3256 };
3257
3258 /* timer6 */
3259 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3260         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3261         { .irq = -1 }
3262 };
3263
3264 static struct omap_hwmod omap44xx_timer6_hwmod = {
3265         .name           = "timer6",
3266         .class          = &omap44xx_timer_hwmod_class,
3267         .clkdm_name     = "abe_clkdm",
3268         .mpu_irqs       = omap44xx_timer6_irqs,
3269
3270         .main_clk       = "timer6_fck",
3271         .prcm = {
3272                 .omap4 = {
3273                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3274                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3275                         .modulemode   = MODULEMODE_SWCTRL,
3276                 },
3277         },
3278         .dev_attr       = &capability_dsp_dev_attr,
3279 };
3280
3281 /* timer7 */
3282 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3283         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3284         { .irq = -1 }
3285 };
3286
3287 static struct omap_hwmod omap44xx_timer7_hwmod = {
3288         .name           = "timer7",
3289         .class          = &omap44xx_timer_hwmod_class,
3290         .clkdm_name     = "abe_clkdm",
3291         .mpu_irqs       = omap44xx_timer7_irqs,
3292         .main_clk       = "timer7_fck",
3293         .prcm = {
3294                 .omap4 = {
3295                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3296                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3297                         .modulemode   = MODULEMODE_SWCTRL,
3298                 },
3299         },
3300         .dev_attr       = &capability_dsp_dev_attr,
3301 };
3302
3303 /* timer8 */
3304 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3305         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3306         { .irq = -1 }
3307 };
3308
3309 static struct omap_hwmod omap44xx_timer8_hwmod = {
3310         .name           = "timer8",
3311         .class          = &omap44xx_timer_hwmod_class,
3312         .clkdm_name     = "abe_clkdm",
3313         .mpu_irqs       = omap44xx_timer8_irqs,
3314         .main_clk       = "timer8_fck",
3315         .prcm = {
3316                 .omap4 = {
3317                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3318                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3319                         .modulemode   = MODULEMODE_SWCTRL,
3320                 },
3321         },
3322         .dev_attr       = &capability_dsp_pwm_dev_attr,
3323 };
3324
3325 /* timer9 */
3326 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3327         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3328         { .irq = -1 }
3329 };
3330
3331 static struct omap_hwmod omap44xx_timer9_hwmod = {
3332         .name           = "timer9",
3333         .class          = &omap44xx_timer_hwmod_class,
3334         .clkdm_name     = "l4_per_clkdm",
3335         .mpu_irqs       = omap44xx_timer9_irqs,
3336         .main_clk       = "timer9_fck",
3337         .prcm = {
3338                 .omap4 = {
3339                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3340                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3341                         .modulemode   = MODULEMODE_SWCTRL,
3342                 },
3343         },
3344         .dev_attr       = &capability_pwm_dev_attr,
3345 };
3346
3347 /* timer10 */
3348 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3349         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3350         { .irq = -1 }
3351 };
3352
3353 static struct omap_hwmod omap44xx_timer10_hwmod = {
3354         .name           = "timer10",
3355         .class          = &omap44xx_timer_1ms_hwmod_class,
3356         .clkdm_name     = "l4_per_clkdm",
3357         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3358         .mpu_irqs       = omap44xx_timer10_irqs,
3359         .main_clk       = "timer10_fck",
3360         .prcm = {
3361                 .omap4 = {
3362                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3363                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3364                         .modulemode   = MODULEMODE_SWCTRL,
3365                 },
3366         },
3367         .dev_attr       = &capability_pwm_dev_attr,
3368 };
3369
3370 /* timer11 */
3371 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3372         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3373         { .irq = -1 }
3374 };
3375
3376 static struct omap_hwmod omap44xx_timer11_hwmod = {
3377         .name           = "timer11",
3378         .class          = &omap44xx_timer_hwmod_class,
3379         .clkdm_name     = "l4_per_clkdm",
3380         .mpu_irqs       = omap44xx_timer11_irqs,
3381         .main_clk       = "timer11_fck",
3382         .prcm = {
3383                 .omap4 = {
3384                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3385                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3386                         .modulemode   = MODULEMODE_SWCTRL,
3387                 },
3388         },
3389         .dev_attr       = &capability_pwm_dev_attr,
3390 };
3391
3392 /*
3393  * 'uart' class
3394  * universal asynchronous receiver/transmitter (uart)
3395  */
3396
3397 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3398         .rev_offs       = 0x0050,
3399         .sysc_offs      = 0x0054,
3400         .syss_offs      = 0x0058,
3401         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3402                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3403                            SYSS_HAS_RESET_STATUS),
3404         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3405                            SIDLE_SMART_WKUP),
3406         .sysc_fields    = &omap_hwmod_sysc_type1,
3407 };
3408
3409 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3410         .name   = "uart",
3411         .sysc   = &omap44xx_uart_sysc,
3412 };
3413
3414 /* uart1 */
3415 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3416         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3417         { .irq = -1 }
3418 };
3419
3420 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3421         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3422         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3423         { .dma_req = -1 }
3424 };
3425
3426 static struct omap_hwmod omap44xx_uart1_hwmod = {
3427         .name           = "uart1",
3428         .class          = &omap44xx_uart_hwmod_class,
3429         .clkdm_name     = "l4_per_clkdm",
3430         .mpu_irqs       = omap44xx_uart1_irqs,
3431         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3432         .main_clk       = "uart1_fck",
3433         .prcm = {
3434                 .omap4 = {
3435                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3436                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3437                         .modulemode   = MODULEMODE_SWCTRL,
3438                 },
3439         },
3440 };
3441
3442 /* uart2 */
3443 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3444         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3445         { .irq = -1 }
3446 };
3447
3448 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3449         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3450         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3451         { .dma_req = -1 }
3452 };
3453
3454 static struct omap_hwmod omap44xx_uart2_hwmod = {
3455         .name           = "uart2",
3456         .class          = &omap44xx_uart_hwmod_class,
3457         .clkdm_name     = "l4_per_clkdm",
3458         .mpu_irqs       = omap44xx_uart2_irqs,
3459         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3460         .main_clk       = "uart2_fck",
3461         .prcm = {
3462                 .omap4 = {
3463                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3464                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3465                         .modulemode   = MODULEMODE_SWCTRL,
3466                 },
3467         },
3468 };
3469
3470 /* uart3 */
3471 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3472         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3473         { .irq = -1 }
3474 };
3475
3476 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3477         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3478         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3479         { .dma_req = -1 }
3480 };
3481
3482 static struct omap_hwmod omap44xx_uart3_hwmod = {
3483         .name           = "uart3",
3484         .class          = &omap44xx_uart_hwmod_class,
3485         .clkdm_name     = "l4_per_clkdm",
3486         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3487         .mpu_irqs       = omap44xx_uart3_irqs,
3488         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3489         .main_clk       = "uart3_fck",
3490         .prcm = {
3491                 .omap4 = {
3492                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3493                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3494                         .modulemode   = MODULEMODE_SWCTRL,
3495                 },
3496         },
3497 };
3498
3499 /* uart4 */
3500 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3501         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3502         { .irq = -1 }
3503 };
3504
3505 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3506         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3507         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3508         { .dma_req = -1 }
3509 };
3510
3511 static struct omap_hwmod omap44xx_uart4_hwmod = {
3512         .name           = "uart4",
3513         .class          = &omap44xx_uart_hwmod_class,
3514         .clkdm_name     = "l4_per_clkdm",
3515         .mpu_irqs       = omap44xx_uart4_irqs,
3516         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3517         .main_clk       = "uart4_fck",
3518         .prcm = {
3519                 .omap4 = {
3520                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3521                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3522                         .modulemode   = MODULEMODE_SWCTRL,
3523                 },
3524         },
3525 };
3526
3527 /*
3528  * 'usb_host_fs' class
3529  * full-speed usb host controller
3530  */
3531
3532 /* The IP is not compliant to type1 / type2 scheme */
3533 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3534         .midle_shift    = 4,
3535         .sidle_shift    = 2,
3536         .srst_shift     = 1,
3537 };
3538
3539 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3540         .rev_offs       = 0x0000,
3541         .sysc_offs      = 0x0210,
3542         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3543                            SYSC_HAS_SOFTRESET),
3544         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3545                            SIDLE_SMART_WKUP),
3546         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3547 };
3548
3549 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3550         .name   = "usb_host_fs",
3551         .sysc   = &omap44xx_usb_host_fs_sysc,
3552 };
3553
3554 /* usb_host_fs */
3555 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3556         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3557         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3558         { .irq = -1 }
3559 };
3560
3561 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3562         .name           = "usb_host_fs",
3563         .class          = &omap44xx_usb_host_fs_hwmod_class,
3564         .clkdm_name     = "l3_init_clkdm",
3565         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3566         .main_clk       = "usb_host_fs_fck",
3567         .prcm = {
3568                 .omap4 = {
3569                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3570                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3571                         .modulemode   = MODULEMODE_SWCTRL,
3572                 },
3573         },
3574 };
3575
3576 /*
3577  * 'usb_host_hs' class
3578  * high-speed multi-port usb host controller
3579  */
3580
3581 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3582         .rev_offs       = 0x0000,
3583         .sysc_offs      = 0x0010,
3584         .syss_offs      = 0x0014,
3585         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3586                            SYSC_HAS_SOFTRESET),
3587         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3588                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3589                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3590         .sysc_fields    = &omap_hwmod_sysc_type2,
3591 };
3592
3593 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3594         .name   = "usb_host_hs",
3595         .sysc   = &omap44xx_usb_host_hs_sysc,
3596 };
3597
3598 /* usb_host_hs */
3599 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3600         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3601         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3602         { .irq = -1 }
3603 };
3604
3605 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3606         .name           = "usb_host_hs",
3607         .class          = &omap44xx_usb_host_hs_hwmod_class,
3608         .clkdm_name     = "l3_init_clkdm",
3609         .main_clk       = "usb_host_hs_fck",
3610         .prcm = {
3611                 .omap4 = {
3612                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3613                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3614                         .modulemode   = MODULEMODE_SWCTRL,
3615                 },
3616         },
3617         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3618
3619         /*
3620          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3621          * id: i660
3622          *
3623          * Description:
3624          * In the following configuration :
3625          * - USBHOST module is set to smart-idle mode
3626          * - PRCM asserts idle_req to the USBHOST module ( This typically
3627          *   happens when the system is going to a low power mode : all ports
3628          *   have been suspended, the master part of the USBHOST module has
3629          *   entered the standby state, and SW has cut the functional clocks)
3630          * - an USBHOST interrupt occurs before the module is able to answer
3631          *   idle_ack, typically a remote wakeup IRQ.
3632          * Then the USB HOST module will enter a deadlock situation where it
3633          * is no more accessible nor functional.
3634          *
3635          * Workaround:
3636          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3637          */
3638
3639         /*
3640          * Errata: USB host EHCI may stall when entering smart-standby mode
3641          * Id: i571
3642          *
3643          * Description:
3644          * When the USBHOST module is set to smart-standby mode, and when it is
3645          * ready to enter the standby state (i.e. all ports are suspended and
3646          * all attached devices are in suspend mode), then it can wrongly assert
3647          * the Mstandby signal too early while there are still some residual OCP
3648          * transactions ongoing. If this condition occurs, the internal state
3649          * machine may go to an undefined state and the USB link may be stuck
3650          * upon the next resume.
3651          *
3652          * Workaround:
3653          * Don't use smart standby; use only force standby,
3654          * hence HWMOD_SWSUP_MSTANDBY
3655          */
3656
3657         /*
3658          * During system boot; If the hwmod framework resets the module
3659          * the module will have smart idle settings; which can lead to deadlock
3660          * (above Errata Id:i660); so, dont reset the module during boot;
3661          * Use HWMOD_INIT_NO_RESET.
3662          */
3663
3664         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3665                           HWMOD_INIT_NO_RESET,
3666 };
3667
3668 /*
3669  * 'usb_otg_hs' class
3670  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3671  */
3672
3673 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3674         .rev_offs       = 0x0400,
3675         .sysc_offs      = 0x0404,
3676         .syss_offs      = 0x0408,
3677         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3678                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3679                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3680         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3681                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3682                            MSTANDBY_SMART),
3683         .sysc_fields    = &omap_hwmod_sysc_type1,
3684 };
3685
3686 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3687         .name   = "usb_otg_hs",
3688         .sysc   = &omap44xx_usb_otg_hs_sysc,
3689 };
3690
3691 /* usb_otg_hs */
3692 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3693         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3694         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3695         { .irq = -1 }
3696 };
3697
3698 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3699         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3700 };
3701
3702 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3703         .name           = "usb_otg_hs",
3704         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3705         .clkdm_name     = "l3_init_clkdm",
3706         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3707         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3708         .main_clk       = "usb_otg_hs_ick",
3709         .prcm = {
3710                 .omap4 = {
3711                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3712                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3713                         .modulemode   = MODULEMODE_HWCTRL,
3714                 },
3715         },
3716         .opt_clks       = usb_otg_hs_opt_clks,
3717         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3718 };
3719
3720 /*
3721  * 'usb_tll_hs' class
3722  * usb_tll_hs module is the adapter on the usb_host_hs ports
3723  */
3724
3725 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3726         .rev_offs       = 0x0000,
3727         .sysc_offs      = 0x0010,
3728         .syss_offs      = 0x0014,
3729         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3730                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3731                            SYSC_HAS_AUTOIDLE),
3732         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3733         .sysc_fields    = &omap_hwmod_sysc_type1,
3734 };
3735
3736 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3737         .name   = "usb_tll_hs",
3738         .sysc   = &omap44xx_usb_tll_hs_sysc,
3739 };
3740
3741 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3742         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3743         { .irq = -1 }
3744 };
3745
3746 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3747         .name           = "usb_tll_hs",
3748         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3749         .clkdm_name     = "l3_init_clkdm",
3750         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3751         .main_clk       = "usb_tll_hs_ick",
3752         .prcm = {
3753                 .omap4 = {
3754                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3755                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3756                         .modulemode   = MODULEMODE_HWCTRL,
3757                 },
3758         },
3759 };
3760
3761 /*
3762  * 'wd_timer' class
3763  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3764  * overflow condition
3765  */
3766
3767 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3768         .rev_offs       = 0x0000,
3769         .sysc_offs      = 0x0010,
3770         .syss_offs      = 0x0014,
3771         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3772                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3774                            SIDLE_SMART_WKUP),
3775         .sysc_fields    = &omap_hwmod_sysc_type1,
3776 };
3777
3778 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3779         .name           = "wd_timer",
3780         .sysc           = &omap44xx_wd_timer_sysc,
3781         .pre_shutdown   = &omap2_wd_timer_disable,
3782         .reset          = &omap2_wd_timer_reset,
3783 };
3784
3785 /* wd_timer2 */
3786 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3787         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3788         { .irq = -1 }
3789 };
3790
3791 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3792         .name           = "wd_timer2",
3793         .class          = &omap44xx_wd_timer_hwmod_class,
3794         .clkdm_name     = "l4_wkup_clkdm",
3795         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3796         .main_clk       = "wd_timer2_fck",
3797         .prcm = {
3798                 .omap4 = {
3799                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3800                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3801                         .modulemode   = MODULEMODE_SWCTRL,
3802                 },
3803         },
3804 };
3805
3806 /* wd_timer3 */
3807 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3808         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3809         { .irq = -1 }
3810 };
3811
3812 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3813         .name           = "wd_timer3",
3814         .class          = &omap44xx_wd_timer_hwmod_class,
3815         .clkdm_name     = "abe_clkdm",
3816         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3817         .main_clk       = "wd_timer3_fck",
3818         .prcm = {
3819                 .omap4 = {
3820                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3821                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3822                         .modulemode   = MODULEMODE_SWCTRL,
3823                 },
3824         },
3825 };
3826
3827
3828 /*
3829  * interfaces
3830  */
3831
3832 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3833         {
3834                 .pa_start       = 0x4a204000,
3835                 .pa_end         = 0x4a2040ff,
3836                 .flags          = ADDR_TYPE_RT
3837         },
3838         { }
3839 };
3840
3841 /* c2c -> c2c_target_fw */
3842 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3843         .master         = &omap44xx_c2c_hwmod,
3844         .slave          = &omap44xx_c2c_target_fw_hwmod,
3845         .clk            = "div_core_ck",
3846         .addr           = omap44xx_c2c_target_fw_addrs,
3847         .user           = OCP_USER_MPU,
3848 };
3849
3850 /* l4_cfg -> c2c_target_fw */
3851 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3852         .master         = &omap44xx_l4_cfg_hwmod,
3853         .slave          = &omap44xx_c2c_target_fw_hwmod,
3854         .clk            = "l4_div_ck",
3855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3856 };
3857
3858 /* l3_main_1 -> dmm */
3859 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3860         .master         = &omap44xx_l3_main_1_hwmod,
3861         .slave          = &omap44xx_dmm_hwmod,
3862         .clk            = "l3_div_ck",
3863         .user           = OCP_USER_SDMA,
3864 };
3865
3866 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3867         {
3868                 .pa_start       = 0x4e000000,
3869                 .pa_end         = 0x4e0007ff,
3870                 .flags          = ADDR_TYPE_RT
3871         },
3872         { }
3873 };
3874
3875 /* mpu -> dmm */
3876 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3877         .master         = &omap44xx_mpu_hwmod,
3878         .slave          = &omap44xx_dmm_hwmod,
3879         .clk            = "l3_div_ck",
3880         .addr           = omap44xx_dmm_addrs,
3881         .user           = OCP_USER_MPU,
3882 };
3883
3884 /* c2c -> emif_fw */
3885 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3886         .master         = &omap44xx_c2c_hwmod,
3887         .slave          = &omap44xx_emif_fw_hwmod,
3888         .clk            = "div_core_ck",
3889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3890 };
3891
3892 /* dmm -> emif_fw */
3893 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3894         .master         = &omap44xx_dmm_hwmod,
3895         .slave          = &omap44xx_emif_fw_hwmod,
3896         .clk            = "l3_div_ck",
3897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3898 };
3899
3900 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3901         {
3902                 .pa_start       = 0x4a20c000,
3903                 .pa_end         = 0x4a20c0ff,
3904                 .flags          = ADDR_TYPE_RT
3905         },
3906         { }
3907 };
3908
3909 /* l4_cfg -> emif_fw */
3910 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3911         .master         = &omap44xx_l4_cfg_hwmod,
3912         .slave          = &omap44xx_emif_fw_hwmod,
3913         .clk            = "l4_div_ck",
3914         .addr           = omap44xx_emif_fw_addrs,
3915         .user           = OCP_USER_MPU,
3916 };
3917
3918 /* iva -> l3_instr */
3919 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3920         .master         = &omap44xx_iva_hwmod,
3921         .slave          = &omap44xx_l3_instr_hwmod,
3922         .clk            = "l3_div_ck",
3923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3924 };
3925
3926 /* l3_main_3 -> l3_instr */
3927 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3928         .master         = &omap44xx_l3_main_3_hwmod,
3929         .slave          = &omap44xx_l3_instr_hwmod,
3930         .clk            = "l3_div_ck",
3931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3932 };
3933
3934 /* ocp_wp_noc -> l3_instr */
3935 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3936         .master         = &omap44xx_ocp_wp_noc_hwmod,
3937         .slave          = &omap44xx_l3_instr_hwmod,
3938         .clk            = "l3_div_ck",
3939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3940 };
3941
3942 /* dsp -> l3_main_1 */
3943 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3944         .master         = &omap44xx_dsp_hwmod,
3945         .slave          = &omap44xx_l3_main_1_hwmod,
3946         .clk            = "l3_div_ck",
3947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3948 };
3949
3950 /* dss -> l3_main_1 */
3951 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3952         .master         = &omap44xx_dss_hwmod,
3953         .slave          = &omap44xx_l3_main_1_hwmod,
3954         .clk            = "l3_div_ck",
3955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3957
3958 /* l3_main_2 -> l3_main_1 */
3959 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3960         .master         = &omap44xx_l3_main_2_hwmod,
3961         .slave          = &omap44xx_l3_main_1_hwmod,
3962         .clk            = "l3_div_ck",
3963         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3964 };
3965
3966 /* l4_cfg -> l3_main_1 */
3967 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3968         .master         = &omap44xx_l4_cfg_hwmod,
3969         .slave          = &omap44xx_l3_main_1_hwmod,
3970         .clk            = "l4_div_ck",
3971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3972 };
3973
3974 /* mmc1 -> l3_main_1 */
3975 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3976         .master         = &omap44xx_mmc1_hwmod,
3977         .slave          = &omap44xx_l3_main_1_hwmod,
3978         .clk            = "l3_div_ck",
3979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3980 };
3981
3982 /* mmc2 -> l3_main_1 */
3983 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3984         .master         = &omap44xx_mmc2_hwmod,
3985         .slave          = &omap44xx_l3_main_1_hwmod,
3986         .clk            = "l3_div_ck",
3987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3988 };
3989
3990 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3991         {
3992                 .pa_start       = 0x44000000,
3993                 .pa_end         = 0x44000fff,
3994                 .flags          = ADDR_TYPE_RT
3995         },
3996         { }
3997 };
3998
3999 /* mpu -> l3_main_1 */
4000 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4001         .master         = &omap44xx_mpu_hwmod,
4002         .slave          = &omap44xx_l3_main_1_hwmod,
4003         .clk            = "l3_div_ck",
4004         .addr           = omap44xx_l3_main_1_addrs,
4005         .user           = OCP_USER_MPU,
4006 };
4007
4008 /* c2c_target_fw -> l3_main_2 */
4009 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4010         .master         = &omap44xx_c2c_target_fw_hwmod,
4011         .slave          = &omap44xx_l3_main_2_hwmod,
4012         .clk            = "l3_div_ck",
4013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4014 };
4015
4016 /* debugss -> l3_main_2 */
4017 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4018         .master         = &omap44xx_debugss_hwmod,
4019         .slave          = &omap44xx_l3_main_2_hwmod,
4020         .clk            = "dbgclk_mux_ck",
4021         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4022 };
4023
4024 /* dma_system -> l3_main_2 */
4025 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4026         .master         = &omap44xx_dma_system_hwmod,
4027         .slave          = &omap44xx_l3_main_2_hwmod,
4028         .clk            = "l3_div_ck",
4029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4030 };
4031
4032 /* fdif -> l3_main_2 */
4033 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4034         .master         = &omap44xx_fdif_hwmod,
4035         .slave          = &omap44xx_l3_main_2_hwmod,
4036         .clk            = "l3_div_ck",
4037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4038 };
4039
4040 /* gpu -> l3_main_2 */
4041 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4042         .master         = &omap44xx_gpu_hwmod,
4043         .slave          = &omap44xx_l3_main_2_hwmod,
4044         .clk            = "l3_div_ck",
4045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4046 };
4047
4048 /* hsi -> l3_main_2 */
4049 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4050         .master         = &omap44xx_hsi_hwmod,
4051         .slave          = &omap44xx_l3_main_2_hwmod,
4052         .clk            = "l3_div_ck",
4053         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4054 };
4055
4056 /* ipu -> l3_main_2 */
4057 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4058         .master         = &omap44xx_ipu_hwmod,
4059         .slave          = &omap44xx_l3_main_2_hwmod,
4060         .clk            = "l3_div_ck",
4061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4062 };
4063
4064 /* iss -> l3_main_2 */
4065 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4066         .master         = &omap44xx_iss_hwmod,
4067         .slave          = &omap44xx_l3_main_2_hwmod,
4068         .clk            = "l3_div_ck",
4069         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4070 };
4071
4072 /* iva -> l3_main_2 */
4073 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4074         .master         = &omap44xx_iva_hwmod,
4075         .slave          = &omap44xx_l3_main_2_hwmod,
4076         .clk            = "l3_div_ck",
4077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4078 };
4079
4080 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4081         {
4082                 .pa_start       = 0x44800000,
4083                 .pa_end         = 0x44801fff,
4084                 .flags          = ADDR_TYPE_RT
4085         },
4086         { }
4087 };
4088
4089 /* l3_main_1 -> l3_main_2 */
4090 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4091         .master         = &omap44xx_l3_main_1_hwmod,
4092         .slave          = &omap44xx_l3_main_2_hwmod,
4093         .clk            = "l3_div_ck",
4094         .addr           = omap44xx_l3_main_2_addrs,
4095         .user           = OCP_USER_MPU,
4096 };
4097
4098 /* l4_cfg -> l3_main_2 */
4099 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4100         .master         = &omap44xx_l4_cfg_hwmod,
4101         .slave          = &omap44xx_l3_main_2_hwmod,
4102         .clk            = "l4_div_ck",
4103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4104 };
4105
4106 /* usb_host_fs -> l3_main_2 */
4107 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4108         .master         = &omap44xx_usb_host_fs_hwmod,
4109         .slave          = &omap44xx_l3_main_2_hwmod,
4110         .clk            = "l3_div_ck",
4111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4112 };
4113
4114 /* usb_host_hs -> l3_main_2 */
4115 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4116         .master         = &omap44xx_usb_host_hs_hwmod,
4117         .slave          = &omap44xx_l3_main_2_hwmod,
4118         .clk            = "l3_div_ck",
4119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4120 };
4121
4122 /* usb_otg_hs -> l3_main_2 */
4123 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4124         .master         = &omap44xx_usb_otg_hs_hwmod,
4125         .slave          = &omap44xx_l3_main_2_hwmod,
4126         .clk            = "l3_div_ck",
4127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4128 };
4129
4130 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4131         {
4132                 .pa_start       = 0x45000000,
4133                 .pa_end         = 0x45000fff,
4134                 .flags          = ADDR_TYPE_RT
4135         },
4136         { }
4137 };
4138
4139 /* l3_main_1 -> l3_main_3 */
4140 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4141         .master         = &omap44xx_l3_main_1_hwmod,
4142         .slave          = &omap44xx_l3_main_3_hwmod,
4143         .clk            = "l3_div_ck",
4144         .addr           = omap44xx_l3_main_3_addrs,
4145         .user           = OCP_USER_MPU,
4146 };
4147
4148 /* l3_main_2 -> l3_main_3 */
4149 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4150         .master         = &omap44xx_l3_main_2_hwmod,
4151         .slave          = &omap44xx_l3_main_3_hwmod,
4152         .clk            = "l3_div_ck",
4153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4154 };
4155
4156 /* l4_cfg -> l3_main_3 */
4157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4158         .master         = &omap44xx_l4_cfg_hwmod,
4159         .slave          = &omap44xx_l3_main_3_hwmod,
4160         .clk            = "l4_div_ck",
4161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4162 };
4163
4164 /* aess -> l4_abe */
4165 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4166         .master         = &omap44xx_aess_hwmod,
4167         .slave          = &omap44xx_l4_abe_hwmod,
4168         .clk            = "ocp_abe_iclk",
4169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4170 };
4171
4172 /* dsp -> l4_abe */
4173 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4174         .master         = &omap44xx_dsp_hwmod,
4175         .slave          = &omap44xx_l4_abe_hwmod,
4176         .clk            = "ocp_abe_iclk",
4177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4179
4180 /* l3_main_1 -> l4_abe */
4181 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4182         .master         = &omap44xx_l3_main_1_hwmod,
4183         .slave          = &omap44xx_l4_abe_hwmod,
4184         .clk            = "l3_div_ck",
4185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4186 };
4187
4188 /* mpu -> l4_abe */
4189 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4190         .master         = &omap44xx_mpu_hwmod,
4191         .slave          = &omap44xx_l4_abe_hwmod,
4192         .clk            = "ocp_abe_iclk",
4193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4194 };
4195
4196 /* l3_main_1 -> l4_cfg */
4197 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4198         .master         = &omap44xx_l3_main_1_hwmod,
4199         .slave          = &omap44xx_l4_cfg_hwmod,
4200         .clk            = "l3_div_ck",
4201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4202 };
4203
4204 /* l3_main_2 -> l4_per */
4205 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4206         .master         = &omap44xx_l3_main_2_hwmod,
4207         .slave          = &omap44xx_l4_per_hwmod,
4208         .clk            = "l3_div_ck",
4209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4210 };
4211
4212 /* l4_cfg -> l4_wkup */
4213 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4214         .master         = &omap44xx_l4_cfg_hwmod,
4215         .slave          = &omap44xx_l4_wkup_hwmod,
4216         .clk            = "l4_div_ck",
4217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4218 };
4219
4220 /* mpu -> mpu_private */
4221 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4222         .master         = &omap44xx_mpu_hwmod,
4223         .slave          = &omap44xx_mpu_private_hwmod,
4224         .clk            = "l3_div_ck",
4225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4226 };
4227
4228 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4229         {
4230                 .pa_start       = 0x4a102000,
4231                 .pa_end         = 0x4a10207f,
4232                 .flags          = ADDR_TYPE_RT
4233         },
4234         { }
4235 };
4236
4237 /* l4_cfg -> ocp_wp_noc */
4238 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4239         .master         = &omap44xx_l4_cfg_hwmod,
4240         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4241         .clk            = "l4_div_ck",
4242         .addr           = omap44xx_ocp_wp_noc_addrs,
4243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4244 };
4245
4246 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4247         {
4248                 .pa_start       = 0x401f1000,
4249                 .pa_end         = 0x401f13ff,
4250                 .flags          = ADDR_TYPE_RT
4251         },
4252         { }
4253 };
4254
4255 /* l4_abe -> aess */
4256 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4257         .master         = &omap44xx_l4_abe_hwmod,
4258         .slave          = &omap44xx_aess_hwmod,
4259         .clk            = "ocp_abe_iclk",
4260         .addr           = omap44xx_aess_addrs,
4261         .user           = OCP_USER_MPU,
4262 };
4263
4264 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4265         {
4266                 .pa_start       = 0x490f1000,
4267                 .pa_end         = 0x490f13ff,
4268                 .flags          = ADDR_TYPE_RT
4269         },
4270         { }
4271 };
4272
4273 /* l4_abe -> aess (dma) */
4274 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4275         .master         = &omap44xx_l4_abe_hwmod,
4276         .slave          = &omap44xx_aess_hwmod,
4277         .clk            = "ocp_abe_iclk",
4278         .addr           = omap44xx_aess_dma_addrs,
4279         .user           = OCP_USER_SDMA,
4280 };
4281
4282 /* l3_main_2 -> c2c */
4283 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4284         .master         = &omap44xx_l3_main_2_hwmod,
4285         .slave          = &omap44xx_c2c_hwmod,
4286         .clk            = "l3_div_ck",
4287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4288 };
4289
4290 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4291         {
4292                 .pa_start       = 0x4a304000,
4293                 .pa_end         = 0x4a30401f,
4294                 .flags          = ADDR_TYPE_RT
4295         },
4296         { }
4297 };
4298
4299 /* l4_wkup -> counter_32k */
4300 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4301         .master         = &omap44xx_l4_wkup_hwmod,
4302         .slave          = &omap44xx_counter_32k_hwmod,
4303         .clk            = "l4_wkup_clk_mux_ck",
4304         .addr           = omap44xx_counter_32k_addrs,
4305         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4306 };
4307
4308 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4309         {
4310                 .pa_start       = 0x4a002000,
4311                 .pa_end         = 0x4a0027ff,
4312                 .flags          = ADDR_TYPE_RT
4313         },
4314         { }
4315 };
4316
4317 /* l4_cfg -> ctrl_module_core */
4318 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4319         .master         = &omap44xx_l4_cfg_hwmod,
4320         .slave          = &omap44xx_ctrl_module_core_hwmod,
4321         .clk            = "l4_div_ck",
4322         .addr           = omap44xx_ctrl_module_core_addrs,
4323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4324 };
4325
4326 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4327         {
4328                 .pa_start       = 0x4a100000,
4329                 .pa_end         = 0x4a1007ff,
4330                 .flags          = ADDR_TYPE_RT
4331         },
4332         { }
4333 };
4334
4335 /* l4_cfg -> ctrl_module_pad_core */
4336 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4337         .master         = &omap44xx_l4_cfg_hwmod,
4338         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4339         .clk            = "l4_div_ck",
4340         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4342 };
4343
4344 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4345         {
4346                 .pa_start       = 0x4a30c000,
4347                 .pa_end         = 0x4a30c7ff,
4348                 .flags          = ADDR_TYPE_RT
4349         },
4350         { }
4351 };
4352
4353 /* l4_wkup -> ctrl_module_wkup */
4354 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4355         .master         = &omap44xx_l4_wkup_hwmod,
4356         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4357         .clk            = "l4_wkup_clk_mux_ck",
4358         .addr           = omap44xx_ctrl_module_wkup_addrs,
4359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4360 };
4361
4362 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4363         {
4364                 .pa_start       = 0x4a31e000,
4365                 .pa_end         = 0x4a31e7ff,
4366                 .flags          = ADDR_TYPE_RT
4367         },
4368         { }
4369 };
4370
4371 /* l4_wkup -> ctrl_module_pad_wkup */
4372 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4373         .master         = &omap44xx_l4_wkup_hwmod,
4374         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4375         .clk            = "l4_wkup_clk_mux_ck",
4376         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4378 };
4379
4380 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4381         {
4382                 .pa_start       = 0x54160000,
4383                 .pa_end         = 0x54167fff,
4384                 .flags          = ADDR_TYPE_RT
4385         },
4386         { }
4387 };
4388
4389 /* l3_instr -> debugss */
4390 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4391         .master         = &omap44xx_l3_instr_hwmod,
4392         .slave          = &omap44xx_debugss_hwmod,
4393         .clk            = "l3_div_ck",
4394         .addr           = omap44xx_debugss_addrs,
4395         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4396 };
4397
4398 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4399         {
4400                 .pa_start       = 0x4a056000,
4401                 .pa_end         = 0x4a056fff,
4402                 .flags          = ADDR_TYPE_RT
4403         },
4404         { }
4405 };
4406
4407 /* l4_cfg -> dma_system */
4408 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4409         .master         = &omap44xx_l4_cfg_hwmod,
4410         .slave          = &omap44xx_dma_system_hwmod,
4411         .clk            = "l4_div_ck",
4412         .addr           = omap44xx_dma_system_addrs,
4413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4414 };
4415
4416 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4417         {
4418                 .name           = "mpu",
4419                 .pa_start       = 0x4012e000,
4420                 .pa_end         = 0x4012e07f,
4421                 .flags          = ADDR_TYPE_RT
4422         },
4423         { }
4424 };
4425
4426 /* l4_abe -> dmic */
4427 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4428         .master         = &omap44xx_l4_abe_hwmod,
4429         .slave          = &omap44xx_dmic_hwmod,
4430         .clk            = "ocp_abe_iclk",
4431         .addr           = omap44xx_dmic_addrs,
4432         .user           = OCP_USER_MPU,
4433 };
4434
4435 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4436         {
4437                 .name           = "dma",
4438                 .pa_start       = 0x4902e000,
4439                 .pa_end         = 0x4902e07f,
4440                 .flags          = ADDR_TYPE_RT
4441         },
4442         { }
4443 };
4444
4445 /* l4_abe -> dmic (dma) */
4446 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4447         .master         = &omap44xx_l4_abe_hwmod,
4448         .slave          = &omap44xx_dmic_hwmod,
4449         .clk            = "ocp_abe_iclk",
4450         .addr           = omap44xx_dmic_dma_addrs,
4451         .user           = OCP_USER_SDMA,
4452 };
4453
4454 /* dsp -> iva */
4455 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4456         .master         = &omap44xx_dsp_hwmod,
4457         .slave          = &omap44xx_iva_hwmod,
4458         .clk            = "dpll_iva_m5x2_ck",
4459         .user           = OCP_USER_DSP,
4460 };
4461
4462 /* dsp -> sl2if */
4463 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4464         .master         = &omap44xx_dsp_hwmod,
4465         .slave          = &omap44xx_sl2if_hwmod,
4466         .clk            = "dpll_iva_m5x2_ck",
4467         .user           = OCP_USER_DSP,
4468 };
4469
4470 /* l4_cfg -> dsp */
4471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4472         .master         = &omap44xx_l4_cfg_hwmod,
4473         .slave          = &omap44xx_dsp_hwmod,
4474         .clk            = "l4_div_ck",
4475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4476 };
4477
4478 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4479         {
4480                 .pa_start       = 0x58000000,
4481                 .pa_end         = 0x5800007f,
4482                 .flags          = ADDR_TYPE_RT
4483         },
4484         { }
4485 };
4486
4487 /* l3_main_2 -> dss */
4488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4489         .master         = &omap44xx_l3_main_2_hwmod,
4490         .slave          = &omap44xx_dss_hwmod,
4491         .clk            = "dss_fck",
4492         .addr           = omap44xx_dss_dma_addrs,
4493         .user           = OCP_USER_SDMA,
4494 };
4495
4496 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4497         {
4498                 .pa_start       = 0x48040000,
4499                 .pa_end         = 0x4804007f,
4500                 .flags          = ADDR_TYPE_RT
4501         },
4502         { }
4503 };
4504
4505 /* l4_per -> dss */
4506 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4507         .master         = &omap44xx_l4_per_hwmod,
4508         .slave          = &omap44xx_dss_hwmod,
4509         .clk            = "l4_div_ck",
4510         .addr           = omap44xx_dss_addrs,
4511         .user           = OCP_USER_MPU,
4512 };
4513
4514 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4515         {
4516                 .pa_start       = 0x58001000,
4517                 .pa_end         = 0x58001fff,
4518                 .flags          = ADDR_TYPE_RT
4519         },
4520         { }
4521 };
4522
4523 /* l3_main_2 -> dss_dispc */
4524 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4525         .master         = &omap44xx_l3_main_2_hwmod,
4526         .slave          = &omap44xx_dss_dispc_hwmod,
4527         .clk            = "dss_fck",
4528         .addr           = omap44xx_dss_dispc_dma_addrs,
4529         .user           = OCP_USER_SDMA,
4530 };
4531
4532 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4533         {
4534                 .pa_start       = 0x48041000,
4535                 .pa_end         = 0x48041fff,
4536                 .flags          = ADDR_TYPE_RT
4537         },
4538         { }
4539 };
4540
4541 /* l4_per -> dss_dispc */
4542 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4543         .master         = &omap44xx_l4_per_hwmod,
4544         .slave          = &omap44xx_dss_dispc_hwmod,
4545         .clk            = "l4_div_ck",
4546         .addr           = omap44xx_dss_dispc_addrs,
4547         .user           = OCP_USER_MPU,
4548 };
4549
4550 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4551         {
4552                 .pa_start       = 0x58004000,
4553                 .pa_end         = 0x580041ff,
4554                 .flags          = ADDR_TYPE_RT
4555         },
4556         { }
4557 };
4558
4559 /* l3_main_2 -> dss_dsi1 */
4560 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4561         .master         = &omap44xx_l3_main_2_hwmod,
4562         .slave          = &omap44xx_dss_dsi1_hwmod,
4563         .clk            = "dss_fck",
4564         .addr           = omap44xx_dss_dsi1_dma_addrs,
4565         .user           = OCP_USER_SDMA,
4566 };
4567
4568 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4569         {
4570                 .pa_start       = 0x48044000,
4571                 .pa_end         = 0x480441ff,
4572                 .flags          = ADDR_TYPE_RT
4573         },
4574         { }
4575 };
4576
4577 /* l4_per -> dss_dsi1 */
4578 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4579         .master         = &omap44xx_l4_per_hwmod,
4580         .slave          = &omap44xx_dss_dsi1_hwmod,
4581         .clk            = "l4_div_ck",
4582         .addr           = omap44xx_dss_dsi1_addrs,
4583         .user           = OCP_USER_MPU,
4584 };
4585
4586 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4587         {
4588                 .pa_start       = 0x58005000,
4589                 .pa_end         = 0x580051ff,
4590                 .flags          = ADDR_TYPE_RT
4591         },
4592         { }
4593 };
4594
4595 /* l3_main_2 -> dss_dsi2 */
4596 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4597         .master         = &omap44xx_l3_main_2_hwmod,
4598         .slave          = &omap44xx_dss_dsi2_hwmod,
4599         .clk            = "dss_fck",
4600         .addr           = omap44xx_dss_dsi2_dma_addrs,
4601         .user           = OCP_USER_SDMA,
4602 };
4603
4604 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4605         {
4606                 .pa_start       = 0x48045000,
4607                 .pa_end         = 0x480451ff,
4608                 .flags          = ADDR_TYPE_RT
4609         },
4610         { }
4611 };
4612
4613 /* l4_per -> dss_dsi2 */
4614 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4615         .master         = &omap44xx_l4_per_hwmod,
4616         .slave          = &omap44xx_dss_dsi2_hwmod,
4617         .clk            = "l4_div_ck",
4618         .addr           = omap44xx_dss_dsi2_addrs,
4619         .user           = OCP_USER_MPU,
4620 };
4621
4622 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4623         {
4624                 .pa_start       = 0x58006000,
4625                 .pa_end         = 0x58006fff,
4626                 .flags          = ADDR_TYPE_RT
4627         },
4628         { }
4629 };
4630
4631 /* l3_main_2 -> dss_hdmi */
4632 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4633         .master         = &omap44xx_l3_main_2_hwmod,
4634         .slave          = &omap44xx_dss_hdmi_hwmod,
4635         .clk            = "dss_fck",
4636         .addr           = omap44xx_dss_hdmi_dma_addrs,
4637         .user           = OCP_USER_SDMA,
4638 };
4639
4640 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4641         {
4642                 .pa_start       = 0x48046000,
4643                 .pa_end         = 0x48046fff,
4644                 .flags          = ADDR_TYPE_RT
4645         },
4646         { }
4647 };
4648
4649 /* l4_per -> dss_hdmi */
4650 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4651         .master         = &omap44xx_l4_per_hwmod,
4652         .slave          = &omap44xx_dss_hdmi_hwmod,
4653         .clk            = "l4_div_ck",
4654         .addr           = omap44xx_dss_hdmi_addrs,
4655         .user           = OCP_USER_MPU,
4656 };
4657
4658 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4659         {
4660                 .pa_start       = 0x58002000,
4661                 .pa_end         = 0x580020ff,
4662                 .flags          = ADDR_TYPE_RT
4663         },
4664         { }
4665 };
4666
4667 /* l3_main_2 -> dss_rfbi */
4668 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4669         .master         = &omap44xx_l3_main_2_hwmod,
4670         .slave          = &omap44xx_dss_rfbi_hwmod,
4671         .clk            = "dss_fck",
4672         .addr           = omap44xx_dss_rfbi_dma_addrs,
4673         .user           = OCP_USER_SDMA,
4674 };
4675
4676 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4677         {
4678                 .pa_start       = 0x48042000,
4679                 .pa_end         = 0x480420ff,
4680                 .flags          = ADDR_TYPE_RT
4681         },
4682         { }
4683 };
4684
4685 /* l4_per -> dss_rfbi */
4686 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4687         .master         = &omap44xx_l4_per_hwmod,
4688         .slave          = &omap44xx_dss_rfbi_hwmod,
4689         .clk            = "l4_div_ck",
4690         .addr           = omap44xx_dss_rfbi_addrs,
4691         .user           = OCP_USER_MPU,
4692 };
4693
4694 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4695         {
4696                 .pa_start       = 0x58003000,
4697                 .pa_end         = 0x580030ff,
4698                 .flags          = ADDR_TYPE_RT
4699         },
4700         { }
4701 };
4702
4703 /* l3_main_2 -> dss_venc */
4704 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4705         .master         = &omap44xx_l3_main_2_hwmod,
4706         .slave          = &omap44xx_dss_venc_hwmod,
4707         .clk            = "dss_fck",
4708         .addr           = omap44xx_dss_venc_dma_addrs,
4709         .user           = OCP_USER_SDMA,
4710 };
4711
4712 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4713         {
4714                 .pa_start       = 0x48043000,
4715                 .pa_end         = 0x480430ff,
4716                 .flags          = ADDR_TYPE_RT
4717         },
4718         { }
4719 };
4720
4721 /* l4_per -> dss_venc */
4722 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4723         .master         = &omap44xx_l4_per_hwmod,
4724         .slave          = &omap44xx_dss_venc_hwmod,
4725         .clk            = "l4_div_ck",
4726         .addr           = omap44xx_dss_venc_addrs,
4727         .user           = OCP_USER_MPU,
4728 };
4729
4730 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4731         {
4732                 .pa_start       = 0x48078000,
4733                 .pa_end         = 0x48078fff,
4734                 .flags          = ADDR_TYPE_RT
4735         },
4736         { }
4737 };
4738
4739 /* l4_per -> elm */
4740 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4741         .master         = &omap44xx_l4_per_hwmod,
4742         .slave          = &omap44xx_elm_hwmod,
4743         .clk            = "l4_div_ck",
4744         .addr           = omap44xx_elm_addrs,
4745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4746 };
4747
4748 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4749         {
4750                 .pa_start       = 0x4c000000,
4751                 .pa_end         = 0x4c0000ff,
4752                 .flags          = ADDR_TYPE_RT
4753         },
4754         { }
4755 };
4756
4757 /* emif_fw -> emif1 */
4758 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4759         .master         = &omap44xx_emif_fw_hwmod,
4760         .slave          = &omap44xx_emif1_hwmod,
4761         .clk            = "l3_div_ck",
4762         .addr           = omap44xx_emif1_addrs,
4763         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4764 };
4765
4766 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4767         {
4768                 .pa_start       = 0x4d000000,
4769                 .pa_end         = 0x4d0000ff,
4770                 .flags          = ADDR_TYPE_RT
4771         },
4772         { }
4773 };
4774
4775 /* emif_fw -> emif2 */
4776 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4777         .master         = &omap44xx_emif_fw_hwmod,
4778         .slave          = &omap44xx_emif2_hwmod,
4779         .clk            = "l3_div_ck",
4780         .addr           = omap44xx_emif2_addrs,
4781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4782 };
4783
4784 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4785         {
4786                 .pa_start       = 0x4a10a000,
4787                 .pa_end         = 0x4a10a1ff,
4788                 .flags          = ADDR_TYPE_RT
4789         },
4790         { }
4791 };
4792
4793 /* l4_cfg -> fdif */
4794 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4795         .master         = &omap44xx_l4_cfg_hwmod,
4796         .slave          = &omap44xx_fdif_hwmod,
4797         .clk            = "l4_div_ck",
4798         .addr           = omap44xx_fdif_addrs,
4799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4800 };
4801
4802 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4803         {
4804                 .pa_start       = 0x4a310000,
4805                 .pa_end         = 0x4a3101ff,
4806                 .flags          = ADDR_TYPE_RT
4807         },
4808         { }
4809 };
4810
4811 /* l4_wkup -> gpio1 */
4812 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4813         .master         = &omap44xx_l4_wkup_hwmod,
4814         .slave          = &omap44xx_gpio1_hwmod,
4815         .clk            = "l4_wkup_clk_mux_ck",
4816         .addr           = omap44xx_gpio1_addrs,
4817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4818 };
4819
4820 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4821         {
4822                 .pa_start       = 0x48055000,
4823                 .pa_end         = 0x480551ff,
4824                 .flags          = ADDR_TYPE_RT
4825         },
4826         { }
4827 };
4828
4829 /* l4_per -> gpio2 */
4830 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4831         .master         = &omap44xx_l4_per_hwmod,
4832         .slave          = &omap44xx_gpio2_hwmod,
4833         .clk            = "l4_div_ck",
4834         .addr           = omap44xx_gpio2_addrs,
4835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4836 };
4837
4838 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4839         {
4840                 .pa_start       = 0x48057000,
4841                 .pa_end         = 0x480571ff,
4842                 .flags          = ADDR_TYPE_RT
4843         },
4844         { }
4845 };
4846
4847 /* l4_per -> gpio3 */
4848 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4849         .master         = &omap44xx_l4_per_hwmod,
4850         .slave          = &omap44xx_gpio3_hwmod,
4851         .clk            = "l4_div_ck",
4852         .addr           = omap44xx_gpio3_addrs,
4853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4854 };
4855
4856 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4857         {
4858                 .pa_start       = 0x48059000,
4859                 .pa_end         = 0x480591ff,
4860                 .flags          = ADDR_TYPE_RT
4861         },
4862         { }
4863 };
4864
4865 /* l4_per -> gpio4 */
4866 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4867         .master         = &omap44xx_l4_per_hwmod,
4868         .slave          = &omap44xx_gpio4_hwmod,
4869         .clk            = "l4_div_ck",
4870         .addr           = omap44xx_gpio4_addrs,
4871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4872 };
4873
4874 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4875         {
4876                 .pa_start       = 0x4805b000,
4877                 .pa_end         = 0x4805b1ff,
4878                 .flags          = ADDR_TYPE_RT
4879         },
4880         { }
4881 };
4882
4883 /* l4_per -> gpio5 */
4884 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4885         .master         = &omap44xx_l4_per_hwmod,
4886         .slave          = &omap44xx_gpio5_hwmod,
4887         .clk            = "l4_div_ck",
4888         .addr           = omap44xx_gpio5_addrs,
4889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4890 };
4891
4892 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4893         {
4894                 .pa_start       = 0x4805d000,
4895                 .pa_end         = 0x4805d1ff,
4896                 .flags          = ADDR_TYPE_RT
4897         },
4898         { }
4899 };
4900
4901 /* l4_per -> gpio6 */
4902 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4903         .master         = &omap44xx_l4_per_hwmod,
4904         .slave          = &omap44xx_gpio6_hwmod,
4905         .clk            = "l4_div_ck",
4906         .addr           = omap44xx_gpio6_addrs,
4907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4908 };
4909
4910 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4911         {
4912                 .pa_start       = 0x50000000,
4913                 .pa_end         = 0x500003ff,
4914                 .flags          = ADDR_TYPE_RT
4915         },
4916         { }
4917 };
4918
4919 /* l3_main_2 -> gpmc */
4920 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4921         .master         = &omap44xx_l3_main_2_hwmod,
4922         .slave          = &omap44xx_gpmc_hwmod,
4923         .clk            = "l3_div_ck",
4924         .addr           = omap44xx_gpmc_addrs,
4925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4926 };
4927
4928 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4929         {
4930                 .pa_start       = 0x56000000,
4931                 .pa_end         = 0x5600ffff,
4932                 .flags          = ADDR_TYPE_RT
4933         },
4934         { }
4935 };
4936
4937 /* l3_main_2 -> gpu */
4938 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4939         .master         = &omap44xx_l3_main_2_hwmod,
4940         .slave          = &omap44xx_gpu_hwmod,
4941         .clk            = "l3_div_ck",
4942         .addr           = omap44xx_gpu_addrs,
4943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4944 };
4945
4946 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4947         {
4948                 .pa_start       = 0x480b2000,
4949                 .pa_end         = 0x480b201f,
4950                 .flags          = ADDR_TYPE_RT
4951         },
4952         { }
4953 };
4954
4955 /* l4_per -> hdq1w */
4956 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4957         .master         = &omap44xx_l4_per_hwmod,
4958         .slave          = &omap44xx_hdq1w_hwmod,
4959         .clk            = "l4_div_ck",
4960         .addr           = omap44xx_hdq1w_addrs,
4961         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4962 };
4963
4964 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4965         {
4966                 .pa_start       = 0x4a058000,
4967                 .pa_end         = 0x4a05bfff,
4968                 .flags          = ADDR_TYPE_RT
4969         },
4970         { }
4971 };
4972
4973 /* l4_cfg -> hsi */
4974 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4975         .master         = &omap44xx_l4_cfg_hwmod,
4976         .slave          = &omap44xx_hsi_hwmod,
4977         .clk            = "l4_div_ck",
4978         .addr           = omap44xx_hsi_addrs,
4979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4980 };
4981
4982 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4983         {
4984                 .pa_start       = 0x48070000,
4985                 .pa_end         = 0x480700ff,
4986                 .flags          = ADDR_TYPE_RT
4987         },
4988         { }
4989 };
4990
4991 /* l4_per -> i2c1 */
4992 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4993         .master         = &omap44xx_l4_per_hwmod,
4994         .slave          = &omap44xx_i2c1_hwmod,
4995         .clk            = "l4_div_ck",
4996         .addr           = omap44xx_i2c1_addrs,
4997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4998 };
4999
5000 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5001         {
5002                 .pa_start       = 0x48072000,
5003                 .pa_end         = 0x480720ff,
5004                 .flags          = ADDR_TYPE_RT
5005         },
5006         { }
5007 };
5008
5009 /* l4_per -> i2c2 */
5010 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5011         .master         = &omap44xx_l4_per_hwmod,
5012         .slave          = &omap44xx_i2c2_hwmod,
5013         .clk            = "l4_div_ck",
5014         .addr           = omap44xx_i2c2_addrs,
5015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5016 };
5017
5018 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5019         {
5020                 .pa_start       = 0x48060000,
5021                 .pa_end         = 0x480600ff,
5022                 .flags          = ADDR_TYPE_RT
5023         },
5024         { }
5025 };
5026
5027 /* l4_per -> i2c3 */
5028 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5029         .master         = &omap44xx_l4_per_hwmod,
5030         .slave          = &omap44xx_i2c3_hwmod,
5031         .clk            = "l4_div_ck",
5032         .addr           = omap44xx_i2c3_addrs,
5033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5034 };
5035
5036 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5037         {
5038                 .pa_start       = 0x48350000,
5039                 .pa_end         = 0x483500ff,
5040                 .flags          = ADDR_TYPE_RT
5041         },
5042         { }
5043 };
5044
5045 /* l4_per -> i2c4 */
5046 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5047         .master         = &omap44xx_l4_per_hwmod,
5048         .slave          = &omap44xx_i2c4_hwmod,
5049         .clk            = "l4_div_ck",
5050         .addr           = omap44xx_i2c4_addrs,
5051         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5052 };
5053
5054 /* l3_main_2 -> ipu */
5055 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5056         .master         = &omap44xx_l3_main_2_hwmod,
5057         .slave          = &omap44xx_ipu_hwmod,
5058         .clk            = "l3_div_ck",
5059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5060 };
5061
5062 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5063         {
5064                 .pa_start       = 0x52000000,
5065                 .pa_end         = 0x520000ff,
5066                 .flags          = ADDR_TYPE_RT
5067         },
5068         { }
5069 };
5070
5071 /* l3_main_2 -> iss */
5072 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5073         .master         = &omap44xx_l3_main_2_hwmod,
5074         .slave          = &omap44xx_iss_hwmod,
5075         .clk            = "l3_div_ck",
5076         .addr           = omap44xx_iss_addrs,
5077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5078 };
5079
5080 /* iva -> sl2if */
5081 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5082         .master         = &omap44xx_iva_hwmod,
5083         .slave          = &omap44xx_sl2if_hwmod,
5084         .clk            = "dpll_iva_m5x2_ck",
5085         .user           = OCP_USER_IVA,
5086 };
5087
5088 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5089         {
5090                 .pa_start       = 0x5a000000,
5091                 .pa_end         = 0x5a07ffff,
5092                 .flags          = ADDR_TYPE_RT
5093         },
5094         { }
5095 };
5096
5097 /* l3_main_2 -> iva */
5098 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5099         .master         = &omap44xx_l3_main_2_hwmod,
5100         .slave          = &omap44xx_iva_hwmod,
5101         .clk            = "l3_div_ck",
5102         .addr           = omap44xx_iva_addrs,
5103         .user           = OCP_USER_MPU,
5104 };
5105
5106 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5107         {
5108                 .pa_start       = 0x4a31c000,
5109                 .pa_end         = 0x4a31c07f,
5110                 .flags          = ADDR_TYPE_RT
5111         },
5112         { }
5113 };
5114
5115 /* l4_wkup -> kbd */
5116 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5117         .master         = &omap44xx_l4_wkup_hwmod,
5118         .slave          = &omap44xx_kbd_hwmod,
5119         .clk            = "l4_wkup_clk_mux_ck",
5120         .addr           = omap44xx_kbd_addrs,
5121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5122 };
5123
5124 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5125         {
5126                 .pa_start       = 0x4a0f4000,
5127                 .pa_end         = 0x4a0f41ff,
5128                 .flags          = ADDR_TYPE_RT
5129         },
5130         { }
5131 };
5132
5133 /* l4_cfg -> mailbox */
5134 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5135         .master         = &omap44xx_l4_cfg_hwmod,
5136         .slave          = &omap44xx_mailbox_hwmod,
5137         .clk            = "l4_div_ck",
5138         .addr           = omap44xx_mailbox_addrs,
5139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5140 };
5141
5142 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5143         {
5144                 .pa_start       = 0x40128000,
5145                 .pa_end         = 0x401283ff,
5146                 .flags          = ADDR_TYPE_RT
5147         },
5148         { }
5149 };
5150
5151 /* l4_abe -> mcasp */
5152 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5153         .master         = &omap44xx_l4_abe_hwmod,
5154         .slave          = &omap44xx_mcasp_hwmod,
5155         .clk            = "ocp_abe_iclk",
5156         .addr           = omap44xx_mcasp_addrs,
5157         .user           = OCP_USER_MPU,
5158 };
5159
5160 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5161         {
5162                 .pa_start       = 0x49028000,
5163                 .pa_end         = 0x490283ff,
5164                 .flags          = ADDR_TYPE_RT
5165         },
5166         { }
5167 };
5168
5169 /* l4_abe -> mcasp (dma) */
5170 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5171         .master         = &omap44xx_l4_abe_hwmod,
5172         .slave          = &omap44xx_mcasp_hwmod,
5173         .clk            = "ocp_abe_iclk",
5174         .addr           = omap44xx_mcasp_dma_addrs,
5175         .user           = OCP_USER_SDMA,
5176 };
5177
5178 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5179         {
5180                 .name           = "mpu",
5181                 .pa_start       = 0x40122000,
5182                 .pa_end         = 0x401220ff,
5183                 .flags          = ADDR_TYPE_RT
5184         },
5185         { }
5186 };
5187
5188 /* l4_abe -> mcbsp1 */
5189 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5190         .master         = &omap44xx_l4_abe_hwmod,
5191         .slave          = &omap44xx_mcbsp1_hwmod,
5192         .clk            = "ocp_abe_iclk",
5193         .addr           = omap44xx_mcbsp1_addrs,
5194         .user           = OCP_USER_MPU,
5195 };
5196
5197 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5198         {
5199                 .name           = "dma",
5200                 .pa_start       = 0x49022000,
5201                 .pa_end         = 0x490220ff,
5202                 .flags          = ADDR_TYPE_RT
5203         },
5204         { }
5205 };
5206
5207 /* l4_abe -> mcbsp1 (dma) */
5208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5209         .master         = &omap44xx_l4_abe_hwmod,
5210         .slave          = &omap44xx_mcbsp1_hwmod,
5211         .clk            = "ocp_abe_iclk",
5212         .addr           = omap44xx_mcbsp1_dma_addrs,
5213         .user           = OCP_USER_SDMA,
5214 };
5215
5216 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5217         {
5218                 .name           = "mpu",
5219                 .pa_start       = 0x40124000,
5220                 .pa_end         = 0x401240ff,
5221                 .flags          = ADDR_TYPE_RT
5222         },
5223         { }
5224 };
5225
5226 /* l4_abe -> mcbsp2 */
5227 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5228         .master         = &omap44xx_l4_abe_hwmod,
5229         .slave          = &omap44xx_mcbsp2_hwmod,
5230         .clk            = "ocp_abe_iclk",
5231         .addr           = omap44xx_mcbsp2_addrs,
5232         .user           = OCP_USER_MPU,
5233 };
5234
5235 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5236         {
5237                 .name           = "dma",
5238                 .pa_start       = 0x49024000,
5239                 .pa_end         = 0x490240ff,
5240                 .flags          = ADDR_TYPE_RT
5241         },
5242         { }
5243 };
5244
5245 /* l4_abe -> mcbsp2 (dma) */
5246 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5247         .master         = &omap44xx_l4_abe_hwmod,
5248         .slave          = &omap44xx_mcbsp2_hwmod,
5249         .clk            = "ocp_abe_iclk",
5250         .addr           = omap44xx_mcbsp2_dma_addrs,
5251         .user           = OCP_USER_SDMA,
5252 };
5253
5254 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5255         {
5256                 .name           = "mpu",
5257                 .pa_start       = 0x40126000,
5258                 .pa_end         = 0x401260ff,
5259                 .flags          = ADDR_TYPE_RT
5260         },
5261         { }
5262 };
5263
5264 /* l4_abe -> mcbsp3 */
5265 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5266         .master         = &omap44xx_l4_abe_hwmod,
5267         .slave          = &omap44xx_mcbsp3_hwmod,
5268         .clk            = "ocp_abe_iclk",
5269         .addr           = omap44xx_mcbsp3_addrs,
5270         .user           = OCP_USER_MPU,
5271 };
5272
5273 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5274         {
5275                 .name           = "dma",
5276                 .pa_start       = 0x49026000,
5277                 .pa_end         = 0x490260ff,
5278                 .flags          = ADDR_TYPE_RT
5279         },
5280         { }
5281 };
5282
5283 /* l4_abe -> mcbsp3 (dma) */
5284 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5285         .master         = &omap44xx_l4_abe_hwmod,
5286         .slave          = &omap44xx_mcbsp3_hwmod,
5287         .clk            = "ocp_abe_iclk",
5288         .addr           = omap44xx_mcbsp3_dma_addrs,
5289         .user           = OCP_USER_SDMA,
5290 };
5291
5292 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5293         {
5294                 .pa_start       = 0x48096000,
5295                 .pa_end         = 0x480960ff,
5296                 .flags          = ADDR_TYPE_RT
5297         },
5298         { }
5299 };
5300
5301 /* l4_per -> mcbsp4 */
5302 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5303         .master         = &omap44xx_l4_per_hwmod,
5304         .slave          = &omap44xx_mcbsp4_hwmod,
5305         .clk            = "l4_div_ck",
5306         .addr           = omap44xx_mcbsp4_addrs,
5307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5308 };
5309
5310 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5311         {
5312                 .name           = "mpu",
5313                 .pa_start       = 0x40132000,
5314                 .pa_end         = 0x4013207f,
5315                 .flags          = ADDR_TYPE_RT
5316         },
5317         { }
5318 };
5319
5320 /* l4_abe -> mcpdm */
5321 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5322         .master         = &omap44xx_l4_abe_hwmod,
5323         .slave          = &omap44xx_mcpdm_hwmod,
5324         .clk            = "ocp_abe_iclk",
5325         .addr           = omap44xx_mcpdm_addrs,
5326         .user           = OCP_USER_MPU,
5327 };
5328
5329 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5330         {
5331                 .name           = "dma",
5332                 .pa_start       = 0x49032000,
5333                 .pa_end         = 0x4903207f,
5334                 .flags          = ADDR_TYPE_RT
5335         },
5336         { }
5337 };
5338
5339 /* l4_abe -> mcpdm (dma) */
5340 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5341         .master         = &omap44xx_l4_abe_hwmod,
5342         .slave          = &omap44xx_mcpdm_hwmod,
5343         .clk            = "ocp_abe_iclk",
5344         .addr           = omap44xx_mcpdm_dma_addrs,
5345         .user           = OCP_USER_SDMA,
5346 };
5347
5348 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5349         {
5350                 .pa_start       = 0x48098000,
5351                 .pa_end         = 0x480981ff,
5352                 .flags          = ADDR_TYPE_RT
5353         },
5354         { }
5355 };
5356
5357 /* l4_per -> mcspi1 */
5358 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5359         .master         = &omap44xx_l4_per_hwmod,
5360         .slave          = &omap44xx_mcspi1_hwmod,
5361         .clk            = "l4_div_ck",
5362         .addr           = omap44xx_mcspi1_addrs,
5363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5364 };
5365
5366 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5367         {
5368                 .pa_start       = 0x4809a000,
5369                 .pa_end         = 0x4809a1ff,
5370                 .flags          = ADDR_TYPE_RT
5371         },
5372         { }
5373 };
5374
5375 /* l4_per -> mcspi2 */
5376 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5377         .master         = &omap44xx_l4_per_hwmod,
5378         .slave          = &omap44xx_mcspi2_hwmod,
5379         .clk            = "l4_div_ck",
5380         .addr           = omap44xx_mcspi2_addrs,
5381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5382 };
5383
5384 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5385         {
5386                 .pa_start       = 0x480b8000,
5387                 .pa_end         = 0x480b81ff,
5388                 .flags          = ADDR_TYPE_RT
5389         },
5390         { }
5391 };
5392
5393 /* l4_per -> mcspi3 */
5394 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5395         .master         = &omap44xx_l4_per_hwmod,
5396         .slave          = &omap44xx_mcspi3_hwmod,
5397         .clk            = "l4_div_ck",
5398         .addr           = omap44xx_mcspi3_addrs,
5399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5400 };
5401
5402 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5403         {
5404                 .pa_start       = 0x480ba000,
5405                 .pa_end         = 0x480ba1ff,
5406                 .flags          = ADDR_TYPE_RT
5407         },
5408         { }
5409 };
5410
5411 /* l4_per -> mcspi4 */
5412 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5413         .master         = &omap44xx_l4_per_hwmod,
5414         .slave          = &omap44xx_mcspi4_hwmod,
5415         .clk            = "l4_div_ck",
5416         .addr           = omap44xx_mcspi4_addrs,
5417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5418 };
5419
5420 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5421         {
5422                 .pa_start       = 0x4809c000,
5423                 .pa_end         = 0x4809c3ff,
5424                 .flags          = ADDR_TYPE_RT
5425         },
5426         { }
5427 };
5428
5429 /* l4_per -> mmc1 */
5430 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5431         .master         = &omap44xx_l4_per_hwmod,
5432         .slave          = &omap44xx_mmc1_hwmod,
5433         .clk            = "l4_div_ck",
5434         .addr           = omap44xx_mmc1_addrs,
5435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5436 };
5437
5438 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5439         {
5440                 .pa_start       = 0x480b4000,
5441                 .pa_end         = 0x480b43ff,
5442                 .flags          = ADDR_TYPE_RT
5443         },
5444         { }
5445 };
5446
5447 /* l4_per -> mmc2 */
5448 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5449         .master         = &omap44xx_l4_per_hwmod,
5450         .slave          = &omap44xx_mmc2_hwmod,
5451         .clk            = "l4_div_ck",
5452         .addr           = omap44xx_mmc2_addrs,
5453         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5454 };
5455
5456 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5457         {
5458                 .pa_start       = 0x480ad000,
5459                 .pa_end         = 0x480ad3ff,
5460                 .flags          = ADDR_TYPE_RT
5461         },
5462         { }
5463 };
5464
5465 /* l4_per -> mmc3 */
5466 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5467         .master         = &omap44xx_l4_per_hwmod,
5468         .slave          = &omap44xx_mmc3_hwmod,
5469         .clk            = "l4_div_ck",
5470         .addr           = omap44xx_mmc3_addrs,
5471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5472 };
5473
5474 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5475         {
5476                 .pa_start       = 0x480d1000,
5477                 .pa_end         = 0x480d13ff,
5478                 .flags          = ADDR_TYPE_RT
5479         },
5480         { }
5481 };
5482
5483 /* l4_per -> mmc4 */
5484 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5485         .master         = &omap44xx_l4_per_hwmod,
5486         .slave          = &omap44xx_mmc4_hwmod,
5487         .clk            = "l4_div_ck",
5488         .addr           = omap44xx_mmc4_addrs,
5489         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5490 };
5491
5492 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5493         {
5494                 .pa_start       = 0x480d5000,
5495                 .pa_end         = 0x480d53ff,
5496                 .flags          = ADDR_TYPE_RT
5497         },
5498         { }
5499 };
5500
5501 /* l4_per -> mmc5 */
5502 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5503         .master         = &omap44xx_l4_per_hwmod,
5504         .slave          = &omap44xx_mmc5_hwmod,
5505         .clk            = "l4_div_ck",
5506         .addr           = omap44xx_mmc5_addrs,
5507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5508 };
5509
5510 /* l3_main_2 -> ocmc_ram */
5511 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5512         .master         = &omap44xx_l3_main_2_hwmod,
5513         .slave          = &omap44xx_ocmc_ram_hwmod,
5514         .clk            = "l3_div_ck",
5515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5516 };
5517
5518 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5519         {
5520                 .pa_start       = 0x4a0ad000,
5521                 .pa_end         = 0x4a0ad01f,
5522                 .flags          = ADDR_TYPE_RT
5523         },
5524         { }
5525 };
5526
5527 /* l4_cfg -> ocp2scp_usb_phy */
5528 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5529         .master         = &omap44xx_l4_cfg_hwmod,
5530         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5531         .clk            = "l4_div_ck",
5532         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5534 };
5535
5536 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5537         {
5538                 .pa_start       = 0x48243000,
5539                 .pa_end         = 0x48243fff,
5540                 .flags          = ADDR_TYPE_RT
5541         },
5542         { }
5543 };
5544
5545 /* mpu_private -> prcm_mpu */
5546 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5547         .master         = &omap44xx_mpu_private_hwmod,
5548         .slave          = &omap44xx_prcm_mpu_hwmod,
5549         .clk            = "l3_div_ck",
5550         .addr           = omap44xx_prcm_mpu_addrs,
5551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5552 };
5553
5554 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5555         {
5556                 .pa_start       = 0x4a004000,
5557                 .pa_end         = 0x4a004fff,
5558                 .flags          = ADDR_TYPE_RT
5559         },
5560         { }
5561 };
5562
5563 /* l4_wkup -> cm_core_aon */
5564 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5565         .master         = &omap44xx_l4_wkup_hwmod,
5566         .slave          = &omap44xx_cm_core_aon_hwmod,
5567         .clk            = "l4_wkup_clk_mux_ck",
5568         .addr           = omap44xx_cm_core_aon_addrs,
5569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5570 };
5571
5572 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5573         {
5574                 .pa_start       = 0x4a008000,
5575                 .pa_end         = 0x4a009fff,
5576                 .flags          = ADDR_TYPE_RT
5577         },
5578         { }
5579 };
5580
5581 /* l4_cfg -> cm_core */
5582 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5583         .master         = &omap44xx_l4_cfg_hwmod,
5584         .slave          = &omap44xx_cm_core_hwmod,
5585         .clk            = "l4_div_ck",
5586         .addr           = omap44xx_cm_core_addrs,
5587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5588 };
5589
5590 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5591         {
5592                 .pa_start       = 0x4a306000,
5593                 .pa_end         = 0x4a307fff,
5594                 .flags          = ADDR_TYPE_RT
5595         },
5596         { }
5597 };
5598
5599 /* l4_wkup -> prm */
5600 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5601         .master         = &omap44xx_l4_wkup_hwmod,
5602         .slave          = &omap44xx_prm_hwmod,
5603         .clk            = "l4_wkup_clk_mux_ck",
5604         .addr           = omap44xx_prm_addrs,
5605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5606 };
5607
5608 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5609         {
5610                 .pa_start       = 0x4a30a000,
5611                 .pa_end         = 0x4a30a7ff,
5612                 .flags          = ADDR_TYPE_RT
5613         },
5614         { }
5615 };
5616
5617 /* l4_wkup -> scrm */
5618 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5619         .master         = &omap44xx_l4_wkup_hwmod,
5620         .slave          = &omap44xx_scrm_hwmod,
5621         .clk            = "l4_wkup_clk_mux_ck",
5622         .addr           = omap44xx_scrm_addrs,
5623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5624 };
5625
5626 /* l3_main_2 -> sl2if */
5627 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5628         .master         = &omap44xx_l3_main_2_hwmod,
5629         .slave          = &omap44xx_sl2if_hwmod,
5630         .clk            = "l3_div_ck",
5631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5632 };
5633
5634 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5635         {
5636                 .pa_start       = 0x4012c000,
5637                 .pa_end         = 0x4012c3ff,
5638                 .flags          = ADDR_TYPE_RT
5639         },
5640         { }
5641 };
5642
5643 /* l4_abe -> slimbus1 */
5644 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5645         .master         = &omap44xx_l4_abe_hwmod,
5646         .slave          = &omap44xx_slimbus1_hwmod,
5647         .clk            = "ocp_abe_iclk",
5648         .addr           = omap44xx_slimbus1_addrs,
5649         .user           = OCP_USER_MPU,
5650 };
5651
5652 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5653         {
5654                 .pa_start       = 0x4902c000,
5655                 .pa_end         = 0x4902c3ff,
5656                 .flags          = ADDR_TYPE_RT
5657         },
5658         { }
5659 };
5660
5661 /* l4_abe -> slimbus1 (dma) */
5662 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5663         .master         = &omap44xx_l4_abe_hwmod,
5664         .slave          = &omap44xx_slimbus1_hwmod,
5665         .clk            = "ocp_abe_iclk",
5666         .addr           = omap44xx_slimbus1_dma_addrs,
5667         .user           = OCP_USER_SDMA,
5668 };
5669
5670 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5671         {
5672                 .pa_start       = 0x48076000,
5673                 .pa_end         = 0x480763ff,
5674                 .flags          = ADDR_TYPE_RT
5675         },
5676         { }
5677 };
5678
5679 /* l4_per -> slimbus2 */
5680 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5681         .master         = &omap44xx_l4_per_hwmod,
5682         .slave          = &omap44xx_slimbus2_hwmod,
5683         .clk            = "l4_div_ck",
5684         .addr           = omap44xx_slimbus2_addrs,
5685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5686 };
5687
5688 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5689         {
5690                 .pa_start       = 0x4a0dd000,
5691                 .pa_end         = 0x4a0dd03f,
5692                 .flags          = ADDR_TYPE_RT
5693         },
5694         { }
5695 };
5696
5697 /* l4_cfg -> smartreflex_core */
5698 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5699         .master         = &omap44xx_l4_cfg_hwmod,
5700         .slave          = &omap44xx_smartreflex_core_hwmod,
5701         .clk            = "l4_div_ck",
5702         .addr           = omap44xx_smartreflex_core_addrs,
5703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5704 };
5705
5706 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5707         {
5708                 .pa_start       = 0x4a0db000,
5709                 .pa_end         = 0x4a0db03f,
5710                 .flags          = ADDR_TYPE_RT
5711         },
5712         { }
5713 };
5714
5715 /* l4_cfg -> smartreflex_iva */
5716 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5717         .master         = &omap44xx_l4_cfg_hwmod,
5718         .slave          = &omap44xx_smartreflex_iva_hwmod,
5719         .clk            = "l4_div_ck",
5720         .addr           = omap44xx_smartreflex_iva_addrs,
5721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5722 };
5723
5724 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5725         {
5726                 .pa_start       = 0x4a0d9000,
5727                 .pa_end         = 0x4a0d903f,
5728                 .flags          = ADDR_TYPE_RT
5729         },
5730         { }
5731 };
5732
5733 /* l4_cfg -> smartreflex_mpu */
5734 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5735         .master         = &omap44xx_l4_cfg_hwmod,
5736         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5737         .clk            = "l4_div_ck",
5738         .addr           = omap44xx_smartreflex_mpu_addrs,
5739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5740 };
5741
5742 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5743         {
5744                 .pa_start       = 0x4a0f6000,
5745                 .pa_end         = 0x4a0f6fff,
5746                 .flags          = ADDR_TYPE_RT
5747         },
5748         { }
5749 };
5750
5751 /* l4_cfg -> spinlock */
5752 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5753         .master         = &omap44xx_l4_cfg_hwmod,
5754         .slave          = &omap44xx_spinlock_hwmod,
5755         .clk            = "l4_div_ck",
5756         .addr           = omap44xx_spinlock_addrs,
5757         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5758 };
5759
5760 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5761         {
5762                 .pa_start       = 0x4a318000,
5763                 .pa_end         = 0x4a31807f,
5764                 .flags          = ADDR_TYPE_RT
5765         },
5766         { }
5767 };
5768
5769 /* l4_wkup -> timer1 */
5770 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5771         .master         = &omap44xx_l4_wkup_hwmod,
5772         .slave          = &omap44xx_timer1_hwmod,
5773         .clk            = "l4_wkup_clk_mux_ck",
5774         .addr           = omap44xx_timer1_addrs,
5775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5776 };
5777
5778 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5779         {
5780                 .pa_start       = 0x48032000,
5781                 .pa_end         = 0x4803207f,
5782                 .flags          = ADDR_TYPE_RT
5783         },
5784         { }
5785 };
5786
5787 /* l4_per -> timer2 */
5788 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5789         .master         = &omap44xx_l4_per_hwmod,
5790         .slave          = &omap44xx_timer2_hwmod,
5791         .clk            = "l4_div_ck",
5792         .addr           = omap44xx_timer2_addrs,
5793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5794 };
5795
5796 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5797         {
5798                 .pa_start       = 0x48034000,
5799                 .pa_end         = 0x4803407f,
5800                 .flags          = ADDR_TYPE_RT
5801         },
5802         { }
5803 };
5804
5805 /* l4_per -> timer3 */
5806 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5807         .master         = &omap44xx_l4_per_hwmod,
5808         .slave          = &omap44xx_timer3_hwmod,
5809         .clk            = "l4_div_ck",
5810         .addr           = omap44xx_timer3_addrs,
5811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5812 };
5813
5814 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5815         {
5816                 .pa_start       = 0x48036000,
5817                 .pa_end         = 0x4803607f,
5818                 .flags          = ADDR_TYPE_RT
5819         },
5820         { }
5821 };
5822
5823 /* l4_per -> timer4 */
5824 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5825         .master         = &omap44xx_l4_per_hwmod,
5826         .slave          = &omap44xx_timer4_hwmod,
5827         .clk            = "l4_div_ck",
5828         .addr           = omap44xx_timer4_addrs,
5829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5830 };
5831
5832 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5833         {
5834                 .pa_start       = 0x40138000,
5835                 .pa_end         = 0x4013807f,
5836                 .flags          = ADDR_TYPE_RT
5837         },
5838         { }
5839 };
5840
5841 /* l4_abe -> timer5 */
5842 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5843         .master         = &omap44xx_l4_abe_hwmod,
5844         .slave          = &omap44xx_timer5_hwmod,
5845         .clk            = "ocp_abe_iclk",
5846         .addr           = omap44xx_timer5_addrs,
5847         .user           = OCP_USER_MPU,
5848 };
5849
5850 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5851         {
5852                 .pa_start       = 0x49038000,
5853                 .pa_end         = 0x4903807f,
5854                 .flags          = ADDR_TYPE_RT
5855         },
5856         { }
5857 };
5858
5859 /* l4_abe -> timer5 (dma) */
5860 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5861         .master         = &omap44xx_l4_abe_hwmod,
5862         .slave          = &omap44xx_timer5_hwmod,
5863         .clk            = "ocp_abe_iclk",
5864         .addr           = omap44xx_timer5_dma_addrs,
5865         .user           = OCP_USER_SDMA,
5866 };
5867
5868 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5869         {
5870                 .pa_start       = 0x4013a000,
5871                 .pa_end         = 0x4013a07f,
5872                 .flags          = ADDR_TYPE_RT
5873         },
5874         { }
5875 };
5876
5877 /* l4_abe -> timer6 */
5878 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5879         .master         = &omap44xx_l4_abe_hwmod,
5880         .slave          = &omap44xx_timer6_hwmod,
5881         .clk            = "ocp_abe_iclk",
5882         .addr           = omap44xx_timer6_addrs,
5883         .user           = OCP_USER_MPU,
5884 };
5885
5886 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5887         {
5888                 .pa_start       = 0x4903a000,
5889                 .pa_end         = 0x4903a07f,
5890                 .flags          = ADDR_TYPE_RT
5891         },
5892         { }
5893 };
5894
5895 /* l4_abe -> timer6 (dma) */
5896 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5897         .master         = &omap44xx_l4_abe_hwmod,
5898         .slave          = &omap44xx_timer6_hwmod,
5899         .clk            = "ocp_abe_iclk",
5900         .addr           = omap44xx_timer6_dma_addrs,
5901         .user           = OCP_USER_SDMA,
5902 };
5903
5904 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5905         {
5906                 .pa_start       = 0x4013c000,
5907                 .pa_end         = 0x4013c07f,
5908                 .flags          = ADDR_TYPE_RT
5909         },
5910         { }
5911 };
5912
5913 /* l4_abe -> timer7 */
5914 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5915         .master         = &omap44xx_l4_abe_hwmod,
5916         .slave          = &omap44xx_timer7_hwmod,
5917         .clk            = "ocp_abe_iclk",
5918         .addr           = omap44xx_timer7_addrs,
5919         .user           = OCP_USER_MPU,
5920 };
5921
5922 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5923         {
5924                 .pa_start       = 0x4903c000,
5925                 .pa_end         = 0x4903c07f,
5926                 .flags          = ADDR_TYPE_RT
5927         },
5928         { }
5929 };
5930
5931 /* l4_abe -> timer7 (dma) */
5932 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5933         .master         = &omap44xx_l4_abe_hwmod,
5934         .slave          = &omap44xx_timer7_hwmod,
5935         .clk            = "ocp_abe_iclk",
5936         .addr           = omap44xx_timer7_dma_addrs,
5937         .user           = OCP_USER_SDMA,
5938 };
5939
5940 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5941         {
5942                 .pa_start       = 0x4013e000,
5943                 .pa_end         = 0x4013e07f,
5944                 .flags          = ADDR_TYPE_RT
5945         },
5946         { }
5947 };
5948
5949 /* l4_abe -> timer8 */
5950 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5951         .master         = &omap44xx_l4_abe_hwmod,
5952         .slave          = &omap44xx_timer8_hwmod,
5953         .clk            = "ocp_abe_iclk",
5954         .addr           = omap44xx_timer8_addrs,
5955         .user           = OCP_USER_MPU,
5956 };
5957
5958 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5959         {
5960                 .pa_start       = 0x4903e000,
5961                 .pa_end         = 0x4903e07f,
5962                 .flags          = ADDR_TYPE_RT
5963         },
5964         { }
5965 };
5966
5967 /* l4_abe -> timer8 (dma) */
5968 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5969         .master         = &omap44xx_l4_abe_hwmod,
5970         .slave          = &omap44xx_timer8_hwmod,
5971         .clk            = "ocp_abe_iclk",
5972         .addr           = omap44xx_timer8_dma_addrs,
5973         .user           = OCP_USER_SDMA,
5974 };
5975
5976 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5977         {
5978                 .pa_start       = 0x4803e000,
5979                 .pa_end         = 0x4803e07f,
5980                 .flags          = ADDR_TYPE_RT
5981         },
5982         { }
5983 };
5984
5985 /* l4_per -> timer9 */
5986 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5987         .master         = &omap44xx_l4_per_hwmod,
5988         .slave          = &omap44xx_timer9_hwmod,
5989         .clk            = "l4_div_ck",
5990         .addr           = omap44xx_timer9_addrs,
5991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5992 };
5993
5994 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5995         {
5996                 .pa_start       = 0x48086000,
5997                 .pa_end         = 0x4808607f,
5998                 .flags          = ADDR_TYPE_RT
5999         },
6000         { }
6001 };
6002
6003 /* l4_per -> timer10 */
6004 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6005         .master         = &omap44xx_l4_per_hwmod,
6006         .slave          = &omap44xx_timer10_hwmod,
6007         .clk            = "l4_div_ck",
6008         .addr           = omap44xx_timer10_addrs,
6009         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6010 };
6011
6012 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6013         {
6014                 .pa_start       = 0x48088000,
6015                 .pa_end         = 0x4808807f,
6016                 .flags          = ADDR_TYPE_RT
6017         },
6018         { }
6019 };
6020
6021 /* l4_per -> timer11 */
6022 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6023         .master         = &omap44xx_l4_per_hwmod,
6024         .slave          = &omap44xx_timer11_hwmod,
6025         .clk            = "l4_div_ck",
6026         .addr           = omap44xx_timer11_addrs,
6027         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6028 };
6029
6030 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6031         {
6032                 .pa_start       = 0x4806a000,
6033                 .pa_end         = 0x4806a0ff,
6034                 .flags          = ADDR_TYPE_RT
6035         },
6036         { }
6037 };
6038
6039 /* l4_per -> uart1 */
6040 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6041         .master         = &omap44xx_l4_per_hwmod,
6042         .slave          = &omap44xx_uart1_hwmod,
6043         .clk            = "l4_div_ck",
6044         .addr           = omap44xx_uart1_addrs,
6045         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6046 };
6047
6048 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6049         {
6050                 .pa_start       = 0x4806c000,
6051                 .pa_end         = 0x4806c0ff,
6052                 .flags          = ADDR_TYPE_RT
6053         },
6054         { }
6055 };
6056
6057 /* l4_per -> uart2 */
6058 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6059         .master         = &omap44xx_l4_per_hwmod,
6060         .slave          = &omap44xx_uart2_hwmod,
6061         .clk            = "l4_div_ck",
6062         .addr           = omap44xx_uart2_addrs,
6063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6064 };
6065
6066 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6067         {
6068                 .pa_start       = 0x48020000,
6069                 .pa_end         = 0x480200ff,
6070                 .flags          = ADDR_TYPE_RT
6071         },
6072         { }
6073 };
6074
6075 /* l4_per -> uart3 */
6076 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6077         .master         = &omap44xx_l4_per_hwmod,
6078         .slave          = &omap44xx_uart3_hwmod,
6079         .clk            = "l4_div_ck",
6080         .addr           = omap44xx_uart3_addrs,
6081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6082 };
6083
6084 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6085         {
6086                 .pa_start       = 0x4806e000,
6087                 .pa_end         = 0x4806e0ff,
6088                 .flags          = ADDR_TYPE_RT
6089         },
6090         { }
6091 };
6092
6093 /* l4_per -> uart4 */
6094 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6095         .master         = &omap44xx_l4_per_hwmod,
6096         .slave          = &omap44xx_uart4_hwmod,
6097         .clk            = "l4_div_ck",
6098         .addr           = omap44xx_uart4_addrs,
6099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6100 };
6101
6102 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6103         {
6104                 .pa_start       = 0x4a0a9000,
6105                 .pa_end         = 0x4a0a93ff,
6106                 .flags          = ADDR_TYPE_RT
6107         },
6108         { }
6109 };
6110
6111 /* l4_cfg -> usb_host_fs */
6112 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6113         .master         = &omap44xx_l4_cfg_hwmod,
6114         .slave          = &omap44xx_usb_host_fs_hwmod,
6115         .clk            = "l4_div_ck",
6116         .addr           = omap44xx_usb_host_fs_addrs,
6117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6118 };
6119
6120 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6121         {
6122                 .name           = "uhh",
6123                 .pa_start       = 0x4a064000,
6124                 .pa_end         = 0x4a0647ff,
6125                 .flags          = ADDR_TYPE_RT
6126         },
6127         {
6128                 .name           = "ohci",
6129                 .pa_start       = 0x4a064800,
6130                 .pa_end         = 0x4a064bff,
6131         },
6132         {
6133                 .name           = "ehci",
6134                 .pa_start       = 0x4a064c00,
6135                 .pa_end         = 0x4a064fff,
6136         },
6137         {}
6138 };
6139
6140 /* l4_cfg -> usb_host_hs */
6141 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6142         .master         = &omap44xx_l4_cfg_hwmod,
6143         .slave          = &omap44xx_usb_host_hs_hwmod,
6144         .clk            = "l4_div_ck",
6145         .addr           = omap44xx_usb_host_hs_addrs,
6146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6147 };
6148
6149 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6150         {
6151                 .pa_start       = 0x4a0ab000,
6152                 .pa_end         = 0x4a0ab7ff,
6153                 .flags          = ADDR_TYPE_RT
6154         },
6155         {
6156                 /* XXX: Remove this once control module driver is in place */
6157                 .pa_start       = 0x4a00233c,
6158                 .pa_end         = 0x4a00233f,
6159                 .flags          = ADDR_TYPE_RT
6160         },
6161         { }
6162 };
6163
6164 /* l4_cfg -> usb_otg_hs */
6165 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6166         .master         = &omap44xx_l4_cfg_hwmod,
6167         .slave          = &omap44xx_usb_otg_hs_hwmod,
6168         .clk            = "l4_div_ck",
6169         .addr           = omap44xx_usb_otg_hs_addrs,
6170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6171 };
6172
6173 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6174         {
6175                 .name           = "tll",
6176                 .pa_start       = 0x4a062000,
6177                 .pa_end         = 0x4a063fff,
6178                 .flags          = ADDR_TYPE_RT
6179         },
6180         {}
6181 };
6182
6183 /* l4_cfg -> usb_tll_hs */
6184 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6185         .master         = &omap44xx_l4_cfg_hwmod,
6186         .slave          = &omap44xx_usb_tll_hs_hwmod,
6187         .clk            = "l4_div_ck",
6188         .addr           = omap44xx_usb_tll_hs_addrs,
6189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6190 };
6191
6192 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6193         {
6194                 .pa_start       = 0x4a314000,
6195                 .pa_end         = 0x4a31407f,
6196                 .flags          = ADDR_TYPE_RT
6197         },
6198         { }
6199 };
6200
6201 /* l4_wkup -> wd_timer2 */
6202 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6203         .master         = &omap44xx_l4_wkup_hwmod,
6204         .slave          = &omap44xx_wd_timer2_hwmod,
6205         .clk            = "l4_wkup_clk_mux_ck",
6206         .addr           = omap44xx_wd_timer2_addrs,
6207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6208 };
6209
6210 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6211         {
6212                 .pa_start       = 0x40130000,
6213                 .pa_end         = 0x4013007f,
6214                 .flags          = ADDR_TYPE_RT
6215         },
6216         { }
6217 };
6218
6219 /* l4_abe -> wd_timer3 */
6220 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6221         .master         = &omap44xx_l4_abe_hwmod,
6222         .slave          = &omap44xx_wd_timer3_hwmod,
6223         .clk            = "ocp_abe_iclk",
6224         .addr           = omap44xx_wd_timer3_addrs,
6225         .user           = OCP_USER_MPU,
6226 };
6227
6228 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6229         {
6230                 .pa_start       = 0x49030000,
6231                 .pa_end         = 0x4903007f,
6232                 .flags          = ADDR_TYPE_RT
6233         },
6234         { }
6235 };
6236
6237 /* l4_abe -> wd_timer3 (dma) */
6238 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6239         .master         = &omap44xx_l4_abe_hwmod,
6240         .slave          = &omap44xx_wd_timer3_hwmod,
6241         .clk            = "ocp_abe_iclk",
6242         .addr           = omap44xx_wd_timer3_dma_addrs,
6243         .user           = OCP_USER_SDMA,
6244 };
6245
6246 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6247         &omap44xx_c2c__c2c_target_fw,
6248         &omap44xx_l4_cfg__c2c_target_fw,
6249         &omap44xx_l3_main_1__dmm,
6250         &omap44xx_mpu__dmm,
6251         &omap44xx_c2c__emif_fw,
6252         &omap44xx_dmm__emif_fw,
6253         &omap44xx_l4_cfg__emif_fw,
6254         &omap44xx_iva__l3_instr,
6255         &omap44xx_l3_main_3__l3_instr,
6256         &omap44xx_ocp_wp_noc__l3_instr,
6257         &omap44xx_dsp__l3_main_1,
6258         &omap44xx_dss__l3_main_1,
6259         &omap44xx_l3_main_2__l3_main_1,
6260         &omap44xx_l4_cfg__l3_main_1,
6261         &omap44xx_mmc1__l3_main_1,
6262         &omap44xx_mmc2__l3_main_1,
6263         &omap44xx_mpu__l3_main_1,
6264         &omap44xx_c2c_target_fw__l3_main_2,
6265         &omap44xx_debugss__l3_main_2,
6266         &omap44xx_dma_system__l3_main_2,
6267         &omap44xx_fdif__l3_main_2,
6268         &omap44xx_gpu__l3_main_2,
6269         &omap44xx_hsi__l3_main_2,
6270         &omap44xx_ipu__l3_main_2,
6271         &omap44xx_iss__l3_main_2,
6272         &omap44xx_iva__l3_main_2,
6273         &omap44xx_l3_main_1__l3_main_2,
6274         &omap44xx_l4_cfg__l3_main_2,
6275         /* &omap44xx_usb_host_fs__l3_main_2, */
6276         &omap44xx_usb_host_hs__l3_main_2,
6277         &omap44xx_usb_otg_hs__l3_main_2,
6278         &omap44xx_l3_main_1__l3_main_3,
6279         &omap44xx_l3_main_2__l3_main_3,
6280         &omap44xx_l4_cfg__l3_main_3,
6281         /* &omap44xx_aess__l4_abe, */
6282         &omap44xx_dsp__l4_abe,
6283         &omap44xx_l3_main_1__l4_abe,
6284         &omap44xx_mpu__l4_abe,
6285         &omap44xx_l3_main_1__l4_cfg,
6286         &omap44xx_l3_main_2__l4_per,
6287         &omap44xx_l4_cfg__l4_wkup,
6288         &omap44xx_mpu__mpu_private,
6289         &omap44xx_l4_cfg__ocp_wp_noc,
6290         /* &omap44xx_l4_abe__aess, */
6291         /* &omap44xx_l4_abe__aess_dma, */
6292         &omap44xx_l3_main_2__c2c,
6293         &omap44xx_l4_wkup__counter_32k,
6294         &omap44xx_l4_cfg__ctrl_module_core,
6295         &omap44xx_l4_cfg__ctrl_module_pad_core,
6296         &omap44xx_l4_wkup__ctrl_module_wkup,
6297         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6298         &omap44xx_l3_instr__debugss,
6299         &omap44xx_l4_cfg__dma_system,
6300         &omap44xx_l4_abe__dmic,
6301         &omap44xx_l4_abe__dmic_dma,
6302         &omap44xx_dsp__iva,
6303         /* &omap44xx_dsp__sl2if, */
6304         &omap44xx_l4_cfg__dsp,
6305         &omap44xx_l3_main_2__dss,
6306         &omap44xx_l4_per__dss,
6307         &omap44xx_l3_main_2__dss_dispc,
6308         &omap44xx_l4_per__dss_dispc,
6309         &omap44xx_l3_main_2__dss_dsi1,
6310         &omap44xx_l4_per__dss_dsi1,
6311         &omap44xx_l3_main_2__dss_dsi2,
6312         &omap44xx_l4_per__dss_dsi2,
6313         &omap44xx_l3_main_2__dss_hdmi,
6314         &omap44xx_l4_per__dss_hdmi,
6315         &omap44xx_l3_main_2__dss_rfbi,
6316         &omap44xx_l4_per__dss_rfbi,
6317         &omap44xx_l3_main_2__dss_venc,
6318         &omap44xx_l4_per__dss_venc,
6319         &omap44xx_l4_per__elm,
6320         &omap44xx_emif_fw__emif1,
6321         &omap44xx_emif_fw__emif2,
6322         &omap44xx_l4_cfg__fdif,
6323         &omap44xx_l4_wkup__gpio1,
6324         &omap44xx_l4_per__gpio2,
6325         &omap44xx_l4_per__gpio3,
6326         &omap44xx_l4_per__gpio4,
6327         &omap44xx_l4_per__gpio5,
6328         &omap44xx_l4_per__gpio6,
6329         &omap44xx_l3_main_2__gpmc,
6330         &omap44xx_l3_main_2__gpu,
6331         &omap44xx_l4_per__hdq1w,
6332         &omap44xx_l4_cfg__hsi,
6333         &omap44xx_l4_per__i2c1,
6334         &omap44xx_l4_per__i2c2,
6335         &omap44xx_l4_per__i2c3,
6336         &omap44xx_l4_per__i2c4,
6337         &omap44xx_l3_main_2__ipu,
6338         &omap44xx_l3_main_2__iss,
6339         /* &omap44xx_iva__sl2if, */
6340         &omap44xx_l3_main_2__iva,
6341         &omap44xx_l4_wkup__kbd,
6342         &omap44xx_l4_cfg__mailbox,
6343         &omap44xx_l4_abe__mcasp,
6344         &omap44xx_l4_abe__mcasp_dma,
6345         &omap44xx_l4_abe__mcbsp1,
6346         &omap44xx_l4_abe__mcbsp1_dma,
6347         &omap44xx_l4_abe__mcbsp2,
6348         &omap44xx_l4_abe__mcbsp2_dma,
6349         &omap44xx_l4_abe__mcbsp3,
6350         &omap44xx_l4_abe__mcbsp3_dma,
6351         &omap44xx_l4_per__mcbsp4,
6352         &omap44xx_l4_abe__mcpdm,
6353         &omap44xx_l4_abe__mcpdm_dma,
6354         &omap44xx_l4_per__mcspi1,
6355         &omap44xx_l4_per__mcspi2,
6356         &omap44xx_l4_per__mcspi3,
6357         &omap44xx_l4_per__mcspi4,
6358         &omap44xx_l4_per__mmc1,
6359         &omap44xx_l4_per__mmc2,
6360         &omap44xx_l4_per__mmc3,
6361         &omap44xx_l4_per__mmc4,
6362         &omap44xx_l4_per__mmc5,
6363         &omap44xx_l3_main_2__mmu_ipu,
6364         &omap44xx_l4_cfg__mmu_dsp,
6365         &omap44xx_l3_main_2__ocmc_ram,
6366         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6367         &omap44xx_mpu_private__prcm_mpu,
6368         &omap44xx_l4_wkup__cm_core_aon,
6369         &omap44xx_l4_cfg__cm_core,
6370         &omap44xx_l4_wkup__prm,
6371         &omap44xx_l4_wkup__scrm,
6372         /* &omap44xx_l3_main_2__sl2if, */
6373         &omap44xx_l4_abe__slimbus1,
6374         &omap44xx_l4_abe__slimbus1_dma,
6375         &omap44xx_l4_per__slimbus2,
6376         &omap44xx_l4_cfg__smartreflex_core,
6377         &omap44xx_l4_cfg__smartreflex_iva,
6378         &omap44xx_l4_cfg__smartreflex_mpu,
6379         &omap44xx_l4_cfg__spinlock,
6380         &omap44xx_l4_wkup__timer1,
6381         &omap44xx_l4_per__timer2,
6382         &omap44xx_l4_per__timer3,
6383         &omap44xx_l4_per__timer4,
6384         &omap44xx_l4_abe__timer5,
6385         &omap44xx_l4_abe__timer5_dma,
6386         &omap44xx_l4_abe__timer6,
6387         &omap44xx_l4_abe__timer6_dma,
6388         &omap44xx_l4_abe__timer7,
6389         &omap44xx_l4_abe__timer7_dma,
6390         &omap44xx_l4_abe__timer8,
6391         &omap44xx_l4_abe__timer8_dma,
6392         &omap44xx_l4_per__timer9,
6393         &omap44xx_l4_per__timer10,
6394         &omap44xx_l4_per__timer11,
6395         &omap44xx_l4_per__uart1,
6396         &omap44xx_l4_per__uart2,
6397         &omap44xx_l4_per__uart3,
6398         &omap44xx_l4_per__uart4,
6399         /* &omap44xx_l4_cfg__usb_host_fs, */
6400         &omap44xx_l4_cfg__usb_host_hs,
6401         &omap44xx_l4_cfg__usb_otg_hs,
6402         &omap44xx_l4_cfg__usb_tll_hs,
6403         &omap44xx_l4_wkup__wd_timer2,
6404         &omap44xx_l4_abe__wd_timer3,
6405         &omap44xx_l4_abe__wd_timer3_dma,
6406         NULL,
6407 };
6408
6409 int __init omap44xx_hwmod_init(void)
6410 {
6411         omap_hwmod_init();
6412         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6413 }
6414