arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm1_44xx.h"
  31 #include "cm2_44xx.h"
  32 #include "prm44xx.h"
  33 #include "prm-regbits-44xx.h"
  34 #include "wd_timer.h"
  35
  36 /* Base offset for all OMAP4 interrupts external to MPUSS */
  37 #define OMAP44XX_IRQ_GIC_START  32
  38
  39 /* Base offset for all OMAP4 dma requests */
  40 #define OMAP44XX_DMA_REQ_START  1
  41
  42 /* Backward references (IPs with Bus Master capability) */
  43 static struct omap_hwmod omap44xx_dma_system_hwmod;
  44 static struct omap_hwmod omap44xx_dmm_hwmod;
  45 static struct omap_hwmod omap44xx_dsp_hwmod;
  46 static struct omap_hwmod omap44xx_dss_hwmod;
  47 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  48 static struct omap_hwmod omap44xx_iva_hwmod;
  49 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  50 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  51 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  52 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  53 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  54 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  55 static struct omap_hwmod omap44xx_l4_per_hwmod;
  56 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  57 static struct omap_hwmod omap44xx_mpu_hwmod;
  58 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  59
  60 /*
  61  * Interconnects omap_hwmod structures
  62  * hwmods that compose the global OMAP interconnect
  63  */
  64
  65 /*
  66  * 'dmm' class
  67  * instance(s): dmm
  68  */
  69 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  70         .name   = "dmm",
  71 };
  72
  73 /* dmm interface data */
  74 /* l3_main_1 -> dmm */
  75 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  76         .master         = &omap44xx_l3_main_1_hwmod,
  77         .slave          = &omap44xx_dmm_hwmod,
  78         .clk            = "l3_div_ck",
  79         .user           = OCP_USER_SDMA,
  80 };
  81
  82 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  83         {
  84                 .pa_start       = 0x4e000000,
  85                 .pa_end         = 0x4e0007ff,
  86                 .flags          = ADDR_TYPE_RT
  87         },
  88 };
  89
  90 /* mpu -> dmm */
  91 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  92         .master         = &omap44xx_mpu_hwmod,
  93         .slave          = &omap44xx_dmm_hwmod,
  94         .clk            = "l3_div_ck",
  95         .addr           = omap44xx_dmm_addrs,
  96         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
  97         .user           = OCP_USER_MPU,
  98 };
  99
 100 /* dmm slave ports */
 101 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 102         &omap44xx_l3_main_1__dmm,
 103         &omap44xx_mpu__dmm,
 104 };
 105
 106 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 107         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 108 };
 109
 110 static struct omap_hwmod omap44xx_dmm_hwmod = {
 111         .name           = "dmm",
 112         .class          = &omap44xx_dmm_hwmod_class,
 113         .slaves         = omap44xx_dmm_slaves,
 114         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 115         .mpu_irqs       = omap44xx_dmm_irqs,
 116         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 117         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 118 };
 119
 120 /*
 121  * 'emif_fw' class
 122  * instance(s): emif_fw
 123  */
 124 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 125         .name   = "emif_fw",
 126 };
 127
 128 /* emif_fw interface data */
 129 /* dmm -> emif_fw */
 130 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 131         .master         = &omap44xx_dmm_hwmod,
 132         .slave          = &omap44xx_emif_fw_hwmod,
 133         .clk            = "l3_div_ck",
 134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 135 };
 136
 137 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 138         {
 139                 .pa_start       = 0x4a20c000,
 140                 .pa_end         = 0x4a20c0ff,
 141                 .flags          = ADDR_TYPE_RT
 142         },
 143 };
 144
 145 /* l4_cfg -> emif_fw */
 146 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 147         .master         = &omap44xx_l4_cfg_hwmod,
 148         .slave          = &omap44xx_emif_fw_hwmod,
 149         .clk            = "l4_div_ck",
 150         .addr           = omap44xx_emif_fw_addrs,
 151         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 152         .user           = OCP_USER_MPU,
 153 };
 154
 155 /* emif_fw slave ports */
 156 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 157         &omap44xx_dmm__emif_fw,
 158         &omap44xx_l4_cfg__emif_fw,
 159 };
 160
 161 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 162         .name           = "emif_fw",
 163         .class          = &omap44xx_emif_fw_hwmod_class,
 164         .slaves         = omap44xx_emif_fw_slaves,
 165         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 166         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 167 };
 168
 169 /*
 170  * 'l3' class
 171  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 172  */
 173 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 174         .name   = "l3",
 175 };
 176
 177 /* l3_instr interface data */
 178 /* iva -> l3_instr */
 179 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 180         .master         = &omap44xx_iva_hwmod,
 181         .slave          = &omap44xx_l3_instr_hwmod,
 182         .clk            = "l3_div_ck",
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 /* l3_main_3 -> l3_instr */
 187 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 188         .master         = &omap44xx_l3_main_3_hwmod,
 189         .slave          = &omap44xx_l3_instr_hwmod,
 190         .clk            = "l3_div_ck",
 191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 192 };
 193
 194 /* l3_instr slave ports */
 195 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 196         &omap44xx_iva__l3_instr,
 197         &omap44xx_l3_main_3__l3_instr,
 198 };
 199
 200 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 201         .name           = "l3_instr",
 202         .class          = &omap44xx_l3_hwmod_class,
 203         .slaves         = omap44xx_l3_instr_slaves,
 204         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 205         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 206 };
 207
 208 /* l3_main_1 interface data */
 209 /* dsp -> l3_main_1 */
 210 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 211         .master         = &omap44xx_dsp_hwmod,
 212         .slave          = &omap44xx_l3_main_1_hwmod,
 213         .clk            = "l3_div_ck",
 214         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 215 };
 216
 217 /* dss -> l3_main_1 */
 218 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 219         .master         = &omap44xx_dss_hwmod,
 220         .slave          = &omap44xx_l3_main_1_hwmod,
 221         .clk            = "l3_div_ck",
 222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 223 };
 224
 225 /* l3_main_2 -> l3_main_1 */
 226 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 227         .master         = &omap44xx_l3_main_2_hwmod,
 228         .slave          = &omap44xx_l3_main_1_hwmod,
 229         .clk            = "l3_div_ck",
 230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 231 };
 232
 233 /* l4_cfg -> l3_main_1 */
 234 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 235         .master         = &omap44xx_l4_cfg_hwmod,
 236         .slave          = &omap44xx_l3_main_1_hwmod,
 237         .clk            = "l4_div_ck",
 238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 239 };
 240
 241 /* mpu -> l3_main_1 */
 242 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 243         .master         = &omap44xx_mpu_hwmod,
 244         .slave          = &omap44xx_l3_main_1_hwmod,
 245         .clk            = "l3_div_ck",
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* l3_main_1 slave ports */
 250 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 251         &omap44xx_dsp__l3_main_1,
 252         &omap44xx_dss__l3_main_1,
 253         &omap44xx_l3_main_2__l3_main_1,
 254         &omap44xx_l4_cfg__l3_main_1,
 255         &omap44xx_mpu__l3_main_1,
 256 };
 257
 258 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 259         .name           = "l3_main_1",
 260         .class          = &omap44xx_l3_hwmod_class,
 261         .slaves         = omap44xx_l3_main_1_slaves,
 262         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 263         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 264 };
 265
 266 /* l3_main_2 interface data */
 267 /* dma_system -> l3_main_2 */
 268 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 269         .master         = &omap44xx_dma_system_hwmod,
 270         .slave          = &omap44xx_l3_main_2_hwmod,
 271         .clk            = "l3_div_ck",
 272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 273 };
 274
 275 /* iva -> l3_main_2 */
 276 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 277         .master         = &omap44xx_iva_hwmod,
 278         .slave          = &omap44xx_l3_main_2_hwmod,
 279         .clk            = "l3_div_ck",
 280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 281 };
 282
 283 /* l3_main_1 -> l3_main_2 */
 284 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 285         .master         = &omap44xx_l3_main_1_hwmod,
 286         .slave          = &omap44xx_l3_main_2_hwmod,
 287         .clk            = "l3_div_ck",
 288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 289 };
 290
 291 /* l4_cfg -> l3_main_2 */
 292 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 293         .master         = &omap44xx_l4_cfg_hwmod,
 294         .slave          = &omap44xx_l3_main_2_hwmod,
 295         .clk            = "l4_div_ck",
 296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 297 };
 298
 299 /* l3_main_2 slave ports */
 300 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 301         &omap44xx_dma_system__l3_main_2,
 302         &omap44xx_iva__l3_main_2,
 303         &omap44xx_l3_main_1__l3_main_2,
 304         &omap44xx_l4_cfg__l3_main_2,
 305 };
 306
 307 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 308         .name           = "l3_main_2",
 309         .class          = &omap44xx_l3_hwmod_class,
 310         .slaves         = omap44xx_l3_main_2_slaves,
 311         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 312         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 313 };
 314
 315 /* l3_main_3 interface data */
 316 /* l3_main_1 -> l3_main_3 */
 317 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 318         .master         = &omap44xx_l3_main_1_hwmod,
 319         .slave          = &omap44xx_l3_main_3_hwmod,
 320         .clk            = "l3_div_ck",
 321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 322 };
 323
 324 /* l3_main_2 -> l3_main_3 */
 325 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 326         .master         = &omap44xx_l3_main_2_hwmod,
 327         .slave          = &omap44xx_l3_main_3_hwmod,
 328         .clk            = "l3_div_ck",
 329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 330 };
 331
 332 /* l4_cfg -> l3_main_3 */
 333 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 334         .master         = &omap44xx_l4_cfg_hwmod,
 335         .slave          = &omap44xx_l3_main_3_hwmod,
 336         .clk            = "l4_div_ck",
 337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 338 };
 339
 340 /* l3_main_3 slave ports */
 341 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 342         &omap44xx_l3_main_1__l3_main_3,
 343         &omap44xx_l3_main_2__l3_main_3,
 344         &omap44xx_l4_cfg__l3_main_3,
 345 };
 346
 347 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 348         .name           = "l3_main_3",
 349         .class          = &omap44xx_l3_hwmod_class,
 350         .slaves         = omap44xx_l3_main_3_slaves,
 351         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 352         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 353 };
 354
 355 /*
 356  * 'l4' class
 357  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 358  */
 359 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 360         .name   = "l4",
 361 };
 362
 363 /* l4_abe interface data */
 364 /* dsp -> l4_abe */
 365 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 366         .master         = &omap44xx_dsp_hwmod,
 367         .slave          = &omap44xx_l4_abe_hwmod,
 368         .clk            = "ocp_abe_iclk",
 369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 370 };
 371
 372 /* l3_main_1 -> l4_abe */
 373 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 374         .master         = &omap44xx_l3_main_1_hwmod,
 375         .slave          = &omap44xx_l4_abe_hwmod,
 376         .clk            = "l3_div_ck",
 377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 378 };
 379
 380 /* mpu -> l4_abe */
 381 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 382         .master         = &omap44xx_mpu_hwmod,
 383         .slave          = &omap44xx_l4_abe_hwmod,
 384         .clk            = "ocp_abe_iclk",
 385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 386 };
 387
 388 /* l4_abe slave ports */
 389 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 390         &omap44xx_dsp__l4_abe,
 391         &omap44xx_l3_main_1__l4_abe,
 392         &omap44xx_mpu__l4_abe,
 393 };
 394
 395 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 396         .name           = "l4_abe",
 397         .class          = &omap44xx_l4_hwmod_class,
 398         .slaves         = omap44xx_l4_abe_slaves,
 399         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 400         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 401 };
 402
 403 /* l4_cfg interface data */
 404 /* l3_main_1 -> l4_cfg */
 405 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 406         .master         = &omap44xx_l3_main_1_hwmod,
 407         .slave          = &omap44xx_l4_cfg_hwmod,
 408         .clk            = "l3_div_ck",
 409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 410 };
 411
 412 /* l4_cfg slave ports */
 413 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 414         &omap44xx_l3_main_1__l4_cfg,
 415 };
 416
 417 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 418         .name           = "l4_cfg",
 419         .class          = &omap44xx_l4_hwmod_class,
 420         .slaves         = omap44xx_l4_cfg_slaves,
 421         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 422         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 423 };
 424
 425 /* l4_per interface data */
 426 /* l3_main_2 -> l4_per */
 427 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 428         .master         = &omap44xx_l3_main_2_hwmod,
 429         .slave          = &omap44xx_l4_per_hwmod,
 430         .clk            = "l3_div_ck",
 431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 432 };
 433
 434 /* l4_per slave ports */
 435 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 436         &omap44xx_l3_main_2__l4_per,
 437 };
 438
 439 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 440         .name           = "l4_per",
 441         .class          = &omap44xx_l4_hwmod_class,
 442         .slaves         = omap44xx_l4_per_slaves,
 443         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 444         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 445 };
 446
 447 /* l4_wkup interface data */
 448 /* l4_cfg -> l4_wkup */
 449 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 450         .master         = &omap44xx_l4_cfg_hwmod,
 451         .slave          = &omap44xx_l4_wkup_hwmod,
 452         .clk            = "l4_div_ck",
 453         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 454 };
 455
 456 /* l4_wkup slave ports */
 457 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 458         &omap44xx_l4_cfg__l4_wkup,
 459 };
 460
 461 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 462         .name           = "l4_wkup",
 463         .class          = &omap44xx_l4_hwmod_class,
 464         .slaves         = omap44xx_l4_wkup_slaves,
 465         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 466         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 467 };
 468
 469 /*
 470  * 'mpu_bus' class
 471  * instance(s): mpu_private
 472  */
 473 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 474         .name   = "mpu_bus",
 475 };
 476
 477 /* mpu_private interface data */
 478 /* mpu -> mpu_private */
 479 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 480         .master         = &omap44xx_mpu_hwmod,
 481         .slave          = &omap44xx_mpu_private_hwmod,
 482         .clk            = "l3_div_ck",
 483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 484 };
 485
 486 /* mpu_private slave ports */
 487 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 488         &omap44xx_mpu__mpu_private,
 489 };
 490
 491 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 492         .name           = "mpu_private",
 493         .class          = &omap44xx_mpu_bus_hwmod_class,
 494         .slaves         = omap44xx_mpu_private_slaves,
 495         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 496         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 497 };
 498
 499 /*
 500  * Modules omap_hwmod structures
 501  *
 502  * The following IPs are excluded for the moment because:
 503  * - They do not need an explicit SW control using omap_hwmod API.
 504  * - They still need to be validated with the driver
 505  *   properly adapted to omap_hwmod / omap_device
 506  *
 507  *  aess
 508  *  bandgap
 509  *  c2c
 510  *  c2c_target_fw
 511  *  cm_core
 512  *  cm_core_aon
 513  *  counter_32k
 514  *  ctrl_module_core
 515  *  ctrl_module_pad_core
 516  *  ctrl_module_pad_wkup
 517  *  ctrl_module_wkup
 518  *  debugss
 519  *  efuse_ctrl_cust
 520  *  efuse_ctrl_std
 521  *  elm
 522  *  emif1
 523  *  emif2
 524  *  fdif
 525  *  gpmc
 526  *  gpu
 527  *  hdq1w
 528  *  hsi
 529  *  ipu
 530  *  iss
 531  *  kbd
 532  *  mcasp
 533  *  mcbsp1
 534  *  mcbsp2
 535  *  mcbsp3
 536  *  mcbsp4
 537  *  mcpdm
 538  *  mmc1
 539  *  mmc2
 540  *  mmc3
 541  *  mmc4
 542  *  mmc5
 543  *  mpu_c0
 544  *  mpu_c1
 545  *  ocmc_ram
 546  *  ocp2scp_usb_phy
 547  *  ocp_wp_noc
 548  *  prcm
 549  *  prcm_mpu
 550  *  prm
 551  *  scrm
 552  *  sl2if
 553  *  slimbus1
 554  *  slimbus2
 555  *  usb_host_fs
 556  *  usb_host_hs
 557  *  usb_otg_hs
 558  *  usb_phy_cm
 559  *  usb_tll_hs
 560  *  usim
 561  */
 562
 563 /*
 564  * 'dma' class
 565  * dma controller for data exchange between memory to memory (i.e. internal or
 566  * external memory) and gp peripherals to memory or memory to gp peripherals
 567  */
 568
 569 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 570         .rev_offs       = 0x0000,
 571         .sysc_offs      = 0x002c,
 572         .syss_offs      = 0x0028,
 573         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 574                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 575                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 576                            SYSS_HAS_RESET_STATUS),
 577         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 578                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 579         .sysc_fields    = &omap_hwmod_sysc_type1,
 580 };
 581
 582 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 583         .name   = "dma",
 584         .sysc   = &omap44xx_dma_sysc,
 585 };
 586
 587 /* dma dev_attr */
 588 static struct omap_dma_dev_attr dma_dev_attr = {
 589         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 590                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 591         .lch_count      = 32,
 592 };
 593
 594 /* dma_system */
 595 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 596         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 597         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 598         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 599         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 600 };
 601
 602 /* dma_system master ports */
 603 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 604         &omap44xx_dma_system__l3_main_2,
 605 };
 606
 607 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 608         {
 609                 .pa_start       = 0x4a056000,
 610                 .pa_end         = 0x4a0560ff,
 611                 .flags          = ADDR_TYPE_RT
 612         },
 613 };
 614
 615 /* l4_cfg -> dma_system */
 616 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 617         .master         = &omap44xx_l4_cfg_hwmod,
 618         .slave          = &omap44xx_dma_system_hwmod,
 619         .clk            = "l4_div_ck",
 620         .addr           = omap44xx_dma_system_addrs,
 621         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
 622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 623 };
 624
 625 /* dma_system slave ports */
 626 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 627         &omap44xx_l4_cfg__dma_system,
 628 };
 629
 630 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 631         .name           = "dma_system",
 632         .class          = &omap44xx_dma_hwmod_class,
 633         .mpu_irqs       = omap44xx_dma_system_irqs,
 634         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
 635         .main_clk       = "l3_div_ck",
 636         .prcm = {
 637                 .omap4 = {
 638                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 639                 },
 640         },
 641         .dev_attr       = &dma_dev_attr,
 642         .slaves         = omap44xx_dma_system_slaves,
 643         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 644         .masters        = omap44xx_dma_system_masters,
 645         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 646         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 647 };
 648
 649 /*
 650  * 'dmic' class
 651  * digital microphone controller
 652  */
 653
 654 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 655         .rev_offs       = 0x0000,
 656         .sysc_offs      = 0x0010,
 657         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 658                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 659         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 660                            SIDLE_SMART_WKUP),
 661         .sysc_fields    = &omap_hwmod_sysc_type2,
 662 };
 663
 664 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 665         .name   = "dmic",
 666         .sysc   = &omap44xx_dmic_sysc,
 667 };
 668
 669 /* dmic */
 670 static struct omap_hwmod omap44xx_dmic_hwmod;
 671 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 672         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 673 };
 674
 675 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 676         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 677 };
 678
 679 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 680         {
 681                 .pa_start       = 0x4012e000,
 682                 .pa_end         = 0x4012e07f,
 683                 .flags          = ADDR_TYPE_RT
 684         },
 685 };
 686
 687 /* l4_abe -> dmic */
 688 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 689         .master         = &omap44xx_l4_abe_hwmod,
 690         .slave          = &omap44xx_dmic_hwmod,
 691         .clk            = "ocp_abe_iclk",
 692         .addr           = omap44xx_dmic_addrs,
 693         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
 694         .user           = OCP_USER_MPU,
 695 };
 696
 697 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 698         {
 699                 .pa_start       = 0x4902e000,
 700                 .pa_end         = 0x4902e07f,
 701                 .flags          = ADDR_TYPE_RT
 702         },
 703 };
 704
 705 /* l4_abe -> dmic (dma) */
 706 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 707         .master         = &omap44xx_l4_abe_hwmod,
 708         .slave          = &omap44xx_dmic_hwmod,
 709         .clk            = "ocp_abe_iclk",
 710         .addr           = omap44xx_dmic_dma_addrs,
 711         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
 712         .user           = OCP_USER_SDMA,
 713 };
 714
 715 /* dmic slave ports */
 716 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 717         &omap44xx_l4_abe__dmic,
 718         &omap44xx_l4_abe__dmic_dma,
 719 };
 720
 721 static struct omap_hwmod omap44xx_dmic_hwmod = {
 722         .name           = "dmic",
 723         .class          = &omap44xx_dmic_hwmod_class,
 724         .mpu_irqs       = omap44xx_dmic_irqs,
 725         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
 726         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 727         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
 728         .main_clk       = "dmic_fck",
 729         .prcm           = {
 730                 .omap4 = {
 731                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 732                 },
 733         },
 734         .slaves         = omap44xx_dmic_slaves,
 735         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
 736         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 737 };
 738
 739 /*
 740  * 'dsp' class
 741  * dsp sub-system
 742  */
 743
 744 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 745         .name   = "dsp",
 746 };
 747
 748 /* dsp */
 749 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 750         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 751 };
 752
 753 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 754         { .name = "mmu_cache", .rst_shift = 1 },
 755 };
 756
 757 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 758         { .name = "dsp", .rst_shift = 0 },
 759 };
 760
 761 /* dsp -> iva */
 762 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 763         .master         = &omap44xx_dsp_hwmod,
 764         .slave          = &omap44xx_iva_hwmod,
 765         .clk            = "dpll_iva_m5x2_ck",
 766 };
 767
 768 /* dsp master ports */
 769 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
 770         &omap44xx_dsp__l3_main_1,
 771         &omap44xx_dsp__l4_abe,
 772         &omap44xx_dsp__iva,
 773 };
 774
 775 /* l4_cfg -> dsp */
 776 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
 777         .master         = &omap44xx_l4_cfg_hwmod,
 778         .slave          = &omap44xx_dsp_hwmod,
 779         .clk            = "l4_div_ck",
 780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 781 };
 782
 783 /* dsp slave ports */
 784 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
 785         &omap44xx_l4_cfg__dsp,
 786 };
 787
 788 /* Pseudo hwmod for reset control purpose only */
 789 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
 790         .name           = "dsp_c0",
 791         .class          = &omap44xx_dsp_hwmod_class,
 792         .flags          = HWMOD_INIT_NO_RESET,
 793         .rst_lines      = omap44xx_dsp_c0_resets,
 794         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
 795         .prcm = {
 796                 .omap4 = {
 797                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 798                 },
 799         },
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 801 };
 802
 803 static struct omap_hwmod omap44xx_dsp_hwmod = {
 804         .name           = "dsp",
 805         .class          = &omap44xx_dsp_hwmod_class,
 806         .mpu_irqs       = omap44xx_dsp_irqs,
 807         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
 808         .rst_lines      = omap44xx_dsp_resets,
 809         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 810         .main_clk       = "dsp_fck",
 811         .prcm = {
 812                 .omap4 = {
 813                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 814                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 815                 },
 816         },
 817         .slaves         = omap44xx_dsp_slaves,
 818         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
 819         .masters        = omap44xx_dsp_masters,
 820         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
 821         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 822 };
 823
 824 /*
 825  * 'dss' class
 826  * display sub-system
 827  */
 828
 829 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 830         .rev_offs       = 0x0000,
 831         .syss_offs      = 0x0014,
 832         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 833 };
 834
 835 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 836         .name   = "dss",
 837         .sysc   = &omap44xx_dss_sysc,
 838 };
 839
 840 /* dss */
 841 /* dss master ports */
 842 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
 843         &omap44xx_dss__l3_main_1,
 844 };
 845
 846 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
 847         {
 848                 .pa_start       = 0x58000000,
 849                 .pa_end         = 0x5800007f,
 850                 .flags          = ADDR_TYPE_RT
 851         },
 852 };
 853
 854 /* l3_main_2 -> dss */
 855 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
 856         .master         = &omap44xx_l3_main_2_hwmod,
 857         .slave          = &omap44xx_dss_hwmod,
 858         .clk            = "l3_div_ck",
 859         .addr           = omap44xx_dss_dma_addrs,
 860         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
 861         .user           = OCP_USER_SDMA,
 862 };
 863
 864 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
 865         {
 866                 .pa_start       = 0x48040000,
 867                 .pa_end         = 0x4804007f,
 868                 .flags          = ADDR_TYPE_RT
 869         },
 870 };
 871
 872 /* l4_per -> dss */
 873 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
 874         .master         = &omap44xx_l4_per_hwmod,
 875         .slave          = &omap44xx_dss_hwmod,
 876         .clk            = "l4_div_ck",
 877         .addr           = omap44xx_dss_addrs,
 878         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
 879         .user           = OCP_USER_MPU,
 880 };
 881
 882 /* dss slave ports */
 883 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
 884         &omap44xx_l3_main_2__dss,
 885         &omap44xx_l4_per__dss,
 886 };
 887
 888 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 889         { .role = "sys_clk", .clk = "dss_sys_clk" },
 890         { .role = "tv_clk", .clk = "dss_tv_clk" },
 891         { .role = "dss_clk", .clk = "dss_dss_clk" },
 892         { .role = "video_clk", .clk = "dss_48mhz_clk" },
 893 };
 894
 895 static struct omap_hwmod omap44xx_dss_hwmod = {
 896         .name           = "dss_core",
 897         .class          = &omap44xx_dss_hwmod_class,
 898         .main_clk       = "dss_fck",
 899         .prcm = {
 900                 .omap4 = {
 901                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
 902                 },
 903         },
 904         .opt_clks       = dss_opt_clks,
 905         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 906         .slaves         = omap44xx_dss_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
 908         .masters        = omap44xx_dss_masters,
 909         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
 910         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 911 };
 912
 913 /*
 914  * 'dispc' class
 915  * display controller
 916  */
 917
 918 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 919         .rev_offs       = 0x0000,
 920         .sysc_offs      = 0x0010,
 921         .syss_offs      = 0x0014,
 922         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 923                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 924                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 925                            SYSS_HAS_RESET_STATUS),
 926         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 927                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 928         .sysc_fields    = &omap_hwmod_sysc_type1,
 929 };
 930
 931 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 932         .name   = "dispc",
 933         .sysc   = &omap44xx_dispc_sysc,
 934 };
 935
 936 /* dss_dispc */
 937 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
 938 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 939         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 940 };
 941
 942 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 943         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 944 };
 945
 946 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
 947         {
 948                 .pa_start       = 0x58001000,
 949                 .pa_end         = 0x58001fff,
 950                 .flags          = ADDR_TYPE_RT
 951         },
 952 };
 953
 954 /* l3_main_2 -> dss_dispc */
 955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
 956         .master         = &omap44xx_l3_main_2_hwmod,
 957         .slave          = &omap44xx_dss_dispc_hwmod,
 958         .clk            = "l3_div_ck",
 959         .addr           = omap44xx_dss_dispc_dma_addrs,
 960         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
 961         .user           = OCP_USER_SDMA,
 962 };
 963
 964 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
 965         {
 966                 .pa_start       = 0x48041000,
 967                 .pa_end         = 0x48041fff,
 968                 .flags          = ADDR_TYPE_RT
 969         },
 970 };
 971
 972 /* l4_per -> dss_dispc */
 973 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
 974         .master         = &omap44xx_l4_per_hwmod,
 975         .slave          = &omap44xx_dss_dispc_hwmod,
 976         .clk            = "l4_div_ck",
 977         .addr           = omap44xx_dss_dispc_addrs,
 978         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
 979         .user           = OCP_USER_MPU,
 980 };
 981
 982 /* dss_dispc slave ports */
 983 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
 984         &omap44xx_l3_main_2__dss_dispc,
 985         &omap44xx_l4_per__dss_dispc,
 986 };
 987
 988 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 989         .name           = "dss_dispc",
 990         .class          = &omap44xx_dispc_hwmod_class,
 991         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 992         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
 993         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 994         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
 995         .main_clk       = "dss_fck",
 996         .prcm = {
 997                 .omap4 = {
 998                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
 999                 },
1000         },
1001         .slaves         = omap44xx_dss_dispc_slaves,
1002         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1003         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1004 };
1005
1006 /*
1007  * 'dsi' class
1008  * display serial interface controller
1009  */
1010
1011 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1012         .rev_offs       = 0x0000,
1013         .sysc_offs      = 0x0010,
1014         .syss_offs      = 0x0014,
1015         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1016                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1017                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1018         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1019         .sysc_fields    = &omap_hwmod_sysc_type1,
1020 };
1021
1022 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1023         .name   = "dsi",
1024         .sysc   = &omap44xx_dsi_sysc,
1025 };
1026
1027 /* dss_dsi1 */
1028 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1029 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1030         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1031 };
1032
1033 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1034         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1035 };
1036
1037 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1038         {
1039                 .pa_start       = 0x58004000,
1040                 .pa_end         = 0x580041ff,
1041                 .flags          = ADDR_TYPE_RT
1042         },
1043 };
1044
1045 /* l3_main_2 -> dss_dsi1 */
1046 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1047         .master         = &omap44xx_l3_main_2_hwmod,
1048         .slave          = &omap44xx_dss_dsi1_hwmod,
1049         .clk            = "l3_div_ck",
1050         .addr           = omap44xx_dss_dsi1_dma_addrs,
1051         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1052         .user           = OCP_USER_SDMA,
1053 };
1054
1055 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1056         {
1057                 .pa_start       = 0x48044000,
1058                 .pa_end         = 0x480441ff,
1059                 .flags          = ADDR_TYPE_RT
1060         },
1061 };
1062
1063 /* l4_per -> dss_dsi1 */
1064 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1065         .master         = &omap44xx_l4_per_hwmod,
1066         .slave          = &omap44xx_dss_dsi1_hwmod,
1067         .clk            = "l4_div_ck",
1068         .addr           = omap44xx_dss_dsi1_addrs,
1069         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1070         .user           = OCP_USER_MPU,
1071 };
1072
1073 /* dss_dsi1 slave ports */
1074 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1075         &omap44xx_l3_main_2__dss_dsi1,
1076         &omap44xx_l4_per__dss_dsi1,
1077 };
1078
1079 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1080         .name           = "dss_dsi1",
1081         .class          = &omap44xx_dsi_hwmod_class,
1082         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1083         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1084         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1085         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1086         .main_clk       = "dss_fck",
1087         .prcm = {
1088                 .omap4 = {
1089                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1090                 },
1091         },
1092         .slaves         = omap44xx_dss_dsi1_slaves,
1093         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1094         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1095 };
1096
1097 /* dss_dsi2 */
1098 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1099 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1100         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1101 };
1102
1103 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1104         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1105 };
1106
1107 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1108         {
1109                 .pa_start       = 0x58005000,
1110                 .pa_end         = 0x580051ff,
1111                 .flags          = ADDR_TYPE_RT
1112         },
1113 };
1114
1115 /* l3_main_2 -> dss_dsi2 */
1116 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1117         .master         = &omap44xx_l3_main_2_hwmod,
1118         .slave          = &omap44xx_dss_dsi2_hwmod,
1119         .clk            = "l3_div_ck",
1120         .addr           = omap44xx_dss_dsi2_dma_addrs,
1121         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1122         .user           = OCP_USER_SDMA,
1123 };
1124
1125 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1126         {
1127                 .pa_start       = 0x48045000,
1128                 .pa_end         = 0x480451ff,
1129                 .flags          = ADDR_TYPE_RT
1130         },
1131 };
1132
1133 /* l4_per -> dss_dsi2 */
1134 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1135         .master         = &omap44xx_l4_per_hwmod,
1136         .slave          = &omap44xx_dss_dsi2_hwmod,
1137         .clk            = "l4_div_ck",
1138         .addr           = omap44xx_dss_dsi2_addrs,
1139         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1140         .user           = OCP_USER_MPU,
1141 };
1142
1143 /* dss_dsi2 slave ports */
1144 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1145         &omap44xx_l3_main_2__dss_dsi2,
1146         &omap44xx_l4_per__dss_dsi2,
1147 };
1148
1149 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1150         .name           = "dss_dsi2",
1151         .class          = &omap44xx_dsi_hwmod_class,
1152         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1153         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1154         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1155         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1156         .main_clk       = "dss_fck",
1157         .prcm = {
1158                 .omap4 = {
1159                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1160                 },
1161         },
1162         .slaves         = omap44xx_dss_dsi2_slaves,
1163         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1164         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1165 };
1166
1167 /*
1168  * 'hdmi' class
1169  * hdmi controller
1170  */
1171
1172 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1173         .rev_offs       = 0x0000,
1174         .sysc_offs      = 0x0010,
1175         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1176                            SYSC_HAS_SOFTRESET),
1177         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1178                            SIDLE_SMART_WKUP),
1179         .sysc_fields    = &omap_hwmod_sysc_type2,
1180 };
1181
1182 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1183         .name   = "hdmi",
1184         .sysc   = &omap44xx_hdmi_sysc,
1185 };
1186
1187 /* dss_hdmi */
1188 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1189 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1190         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1191 };
1192
1193 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1194         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1195 };
1196
1197 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1198         {
1199                 .pa_start       = 0x58006000,
1200                 .pa_end         = 0x58006fff,
1201                 .flags          = ADDR_TYPE_RT
1202         },
1203 };
1204
1205 /* l3_main_2 -> dss_hdmi */
1206 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1207         .master         = &omap44xx_l3_main_2_hwmod,
1208         .slave          = &omap44xx_dss_hdmi_hwmod,
1209         .clk            = "l3_div_ck",
1210         .addr           = omap44xx_dss_hdmi_dma_addrs,
1211         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1212         .user           = OCP_USER_SDMA,
1213 };
1214
1215 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1216         {
1217                 .pa_start       = 0x48046000,
1218                 .pa_end         = 0x48046fff,
1219                 .flags          = ADDR_TYPE_RT
1220         },
1221 };
1222
1223 /* l4_per -> dss_hdmi */
1224 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1225         .master         = &omap44xx_l4_per_hwmod,
1226         .slave          = &omap44xx_dss_hdmi_hwmod,
1227         .clk            = "l4_div_ck",
1228         .addr           = omap44xx_dss_hdmi_addrs,
1229         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1230         .user           = OCP_USER_MPU,
1231 };
1232
1233 /* dss_hdmi slave ports */
1234 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1235         &omap44xx_l3_main_2__dss_hdmi,
1236         &omap44xx_l4_per__dss_hdmi,
1237 };
1238
1239 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1240         .name           = "dss_hdmi",
1241         .class          = &omap44xx_hdmi_hwmod_class,
1242         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1243         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1244         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1245         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1246         .main_clk       = "dss_fck",
1247         .prcm = {
1248                 .omap4 = {
1249                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1250                 },
1251         },
1252         .slaves         = omap44xx_dss_hdmi_slaves,
1253         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1254         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1255 };
1256
1257 /*
1258  * 'rfbi' class
1259  * remote frame buffer interface
1260  */
1261
1262 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1263         .rev_offs       = 0x0000,
1264         .sysc_offs      = 0x0010,
1265         .syss_offs      = 0x0014,
1266         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1267                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1268         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1269         .sysc_fields    = &omap_hwmod_sysc_type1,
1270 };
1271
1272 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1273         .name   = "rfbi",
1274         .sysc   = &omap44xx_rfbi_sysc,
1275 };
1276
1277 /* dss_rfbi */
1278 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1279 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1280         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1281 };
1282
1283 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1284         {
1285                 .pa_start       = 0x58002000,
1286                 .pa_end         = 0x580020ff,
1287                 .flags          = ADDR_TYPE_RT
1288         },
1289 };
1290
1291 /* l3_main_2 -> dss_rfbi */
1292 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1293         .master         = &omap44xx_l3_main_2_hwmod,
1294         .slave          = &omap44xx_dss_rfbi_hwmod,
1295         .clk            = "l3_div_ck",
1296         .addr           = omap44xx_dss_rfbi_dma_addrs,
1297         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1298         .user           = OCP_USER_SDMA,
1299 };
1300
1301 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1302         {
1303                 .pa_start       = 0x48042000,
1304                 .pa_end         = 0x480420ff,
1305                 .flags          = ADDR_TYPE_RT
1306         },
1307 };
1308
1309 /* l4_per -> dss_rfbi */
1310 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1311         .master         = &omap44xx_l4_per_hwmod,
1312         .slave          = &omap44xx_dss_rfbi_hwmod,
1313         .clk            = "l4_div_ck",
1314         .addr           = omap44xx_dss_rfbi_addrs,
1315         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1316         .user           = OCP_USER_MPU,
1317 };
1318
1319 /* dss_rfbi slave ports */
1320 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1321         &omap44xx_l3_main_2__dss_rfbi,
1322         &omap44xx_l4_per__dss_rfbi,
1323 };
1324
1325 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1326         .name           = "dss_rfbi",
1327         .class          = &omap44xx_rfbi_hwmod_class,
1328         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1329         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1330         .main_clk       = "dss_fck",
1331         .prcm = {
1332                 .omap4 = {
1333                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1334                 },
1335         },
1336         .slaves         = omap44xx_dss_rfbi_slaves,
1337         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1338         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1339 };
1340
1341 /*
1342  * 'venc' class
1343  * video encoder
1344  */
1345
1346 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1347         .name   = "venc",
1348 };
1349
1350 /* dss_venc */
1351 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1352 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1353         {
1354                 .pa_start       = 0x58003000,
1355                 .pa_end         = 0x580030ff,
1356                 .flags          = ADDR_TYPE_RT
1357         },
1358 };
1359
1360 /* l3_main_2 -> dss_venc */
1361 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1362         .master         = &omap44xx_l3_main_2_hwmod,
1363         .slave          = &omap44xx_dss_venc_hwmod,
1364         .clk            = "l3_div_ck",
1365         .addr           = omap44xx_dss_venc_dma_addrs,
1366         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1367         .user           = OCP_USER_SDMA,
1368 };
1369
1370 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1371         {
1372                 .pa_start       = 0x48043000,
1373                 .pa_end         = 0x480430ff,
1374                 .flags          = ADDR_TYPE_RT
1375         },
1376 };
1377
1378 /* l4_per -> dss_venc */
1379 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1380         .master         = &omap44xx_l4_per_hwmod,
1381         .slave          = &omap44xx_dss_venc_hwmod,
1382         .clk            = "l4_div_ck",
1383         .addr           = omap44xx_dss_venc_addrs,
1384         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1385         .user           = OCP_USER_MPU,
1386 };
1387
1388 /* dss_venc slave ports */
1389 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1390         &omap44xx_l3_main_2__dss_venc,
1391         &omap44xx_l4_per__dss_venc,
1392 };
1393
1394 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1395         .name           = "dss_venc",
1396         .class          = &omap44xx_venc_hwmod_class,
1397         .main_clk       = "dss_fck",
1398         .prcm = {
1399                 .omap4 = {
1400                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1401                 },
1402         },
1403         .slaves         = omap44xx_dss_venc_slaves,
1404         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1405         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1406 };
1407
1408 /*
1409  * 'gpio' class
1410  * general purpose io module
1411  */
1412
1413 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1414         .rev_offs       = 0x0000,
1415         .sysc_offs      = 0x0010,
1416         .syss_offs      = 0x0114,
1417         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1418                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1419                            SYSS_HAS_RESET_STATUS),
1420         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1421                            SIDLE_SMART_WKUP),
1422         .sysc_fields    = &omap_hwmod_sysc_type1,
1423 };
1424
1425 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1426         .name   = "gpio",
1427         .sysc   = &omap44xx_gpio_sysc,
1428         .rev    = 2,
1429 };
1430
1431 /* gpio dev_attr */
1432 static struct omap_gpio_dev_attr gpio_dev_attr = {
1433         .bank_width     = 32,
1434         .dbck_flag      = true,
1435 };
1436
1437 /* gpio1 */
1438 static struct omap_hwmod omap44xx_gpio1_hwmod;
1439 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1440         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1441 };
1442
1443 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1444         {
1445                 .pa_start       = 0x4a310000,
1446                 .pa_end         = 0x4a3101ff,
1447                 .flags          = ADDR_TYPE_RT
1448         },
1449 };
1450
1451 /* l4_wkup -> gpio1 */
1452 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1453         .master         = &omap44xx_l4_wkup_hwmod,
1454         .slave          = &omap44xx_gpio1_hwmod,
1455         .clk            = "l4_wkup_clk_mux_ck",
1456         .addr           = omap44xx_gpio1_addrs,
1457         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1459 };
1460
1461 /* gpio1 slave ports */
1462 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1463         &omap44xx_l4_wkup__gpio1,
1464 };
1465
1466 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1467         { .role = "dbclk", .clk = "gpio1_dbclk" },
1468 };
1469
1470 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1471         .name           = "gpio1",
1472         .class          = &omap44xx_gpio_hwmod_class,
1473         .mpu_irqs       = omap44xx_gpio1_irqs,
1474         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1475         .main_clk       = "gpio1_ick",
1476         .prcm = {
1477                 .omap4 = {
1478                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1479                 },
1480         },
1481         .opt_clks       = gpio1_opt_clks,
1482         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1483         .dev_attr       = &gpio_dev_attr,
1484         .slaves         = omap44xx_gpio1_slaves,
1485         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1486         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1487 };
1488
1489 /* gpio2 */
1490 static struct omap_hwmod omap44xx_gpio2_hwmod;
1491 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1492         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1493 };
1494
1495 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1496         {
1497                 .pa_start       = 0x48055000,
1498                 .pa_end         = 0x480551ff,
1499                 .flags          = ADDR_TYPE_RT
1500         },
1501 };
1502
1503 /* l4_per -> gpio2 */
1504 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1505         .master         = &omap44xx_l4_per_hwmod,
1506         .slave          = &omap44xx_gpio2_hwmod,
1507         .clk            = "l4_div_ck",
1508         .addr           = omap44xx_gpio2_addrs,
1509         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1510         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1511 };
1512
1513 /* gpio2 slave ports */
1514 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1515         &omap44xx_l4_per__gpio2,
1516 };
1517
1518 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1519         { .role = "dbclk", .clk = "gpio2_dbclk" },
1520 };
1521
1522 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1523         .name           = "gpio2",
1524         .class          = &omap44xx_gpio_hwmod_class,
1525         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1526         .mpu_irqs       = omap44xx_gpio2_irqs,
1527         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1528         .main_clk       = "gpio2_ick",
1529         .prcm = {
1530                 .omap4 = {
1531                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1532                 },
1533         },
1534         .opt_clks       = gpio2_opt_clks,
1535         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1536         .dev_attr       = &gpio_dev_attr,
1537         .slaves         = omap44xx_gpio2_slaves,
1538         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1539         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1540 };
1541
1542 /* gpio3 */
1543 static struct omap_hwmod omap44xx_gpio3_hwmod;
1544 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1545         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1546 };
1547
1548 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1549         {
1550                 .pa_start       = 0x48057000,
1551                 .pa_end         = 0x480571ff,
1552                 .flags          = ADDR_TYPE_RT
1553         },
1554 };
1555
1556 /* l4_per -> gpio3 */
1557 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1558         .master         = &omap44xx_l4_per_hwmod,
1559         .slave          = &omap44xx_gpio3_hwmod,
1560         .clk            = "l4_div_ck",
1561         .addr           = omap44xx_gpio3_addrs,
1562         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1563         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1564 };
1565
1566 /* gpio3 slave ports */
1567 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1568         &omap44xx_l4_per__gpio3,
1569 };
1570
1571 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1572         { .role = "dbclk", .clk = "gpio3_dbclk" },
1573 };
1574
1575 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1576         .name           = "gpio3",
1577         .class          = &omap44xx_gpio_hwmod_class,
1578         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1579         .mpu_irqs       = omap44xx_gpio3_irqs,
1580         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1581         .main_clk       = "gpio3_ick",
1582         .prcm = {
1583                 .omap4 = {
1584                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1585                 },
1586         },
1587         .opt_clks       = gpio3_opt_clks,
1588         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1589         .dev_attr       = &gpio_dev_attr,
1590         .slaves         = omap44xx_gpio3_slaves,
1591         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1592         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1593 };
1594
1595 /* gpio4 */
1596 static struct omap_hwmod omap44xx_gpio4_hwmod;
1597 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1598         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1599 };
1600
1601 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1602         {
1603                 .pa_start       = 0x48059000,
1604                 .pa_end         = 0x480591ff,
1605                 .flags          = ADDR_TYPE_RT
1606         },
1607 };
1608
1609 /* l4_per -> gpio4 */
1610 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1611         .master         = &omap44xx_l4_per_hwmod,
1612         .slave          = &omap44xx_gpio4_hwmod,
1613         .clk            = "l4_div_ck",
1614         .addr           = omap44xx_gpio4_addrs,
1615         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1617 };
1618
1619 /* gpio4 slave ports */
1620 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1621         &omap44xx_l4_per__gpio4,
1622 };
1623
1624 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1625         { .role = "dbclk", .clk = "gpio4_dbclk" },
1626 };
1627
1628 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1629         .name           = "gpio4",
1630         .class          = &omap44xx_gpio_hwmod_class,
1631         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1632         .mpu_irqs       = omap44xx_gpio4_irqs,
1633         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1634         .main_clk       = "gpio4_ick",
1635         .prcm = {
1636                 .omap4 = {
1637                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1638                 },
1639         },
1640         .opt_clks       = gpio4_opt_clks,
1641         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1642         .dev_attr       = &gpio_dev_attr,
1643         .slaves         = omap44xx_gpio4_slaves,
1644         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1645         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1646 };
1647
1648 /* gpio5 */
1649 static struct omap_hwmod omap44xx_gpio5_hwmod;
1650 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1651         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1652 };
1653
1654 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1655         {
1656                 .pa_start       = 0x4805b000,
1657                 .pa_end         = 0x4805b1ff,
1658                 .flags          = ADDR_TYPE_RT
1659         },
1660 };
1661
1662 /* l4_per -> gpio5 */
1663 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1664         .master         = &omap44xx_l4_per_hwmod,
1665         .slave          = &omap44xx_gpio5_hwmod,
1666         .clk            = "l4_div_ck",
1667         .addr           = omap44xx_gpio5_addrs,
1668         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1669         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1670 };
1671
1672 /* gpio5 slave ports */
1673 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1674         &omap44xx_l4_per__gpio5,
1675 };
1676
1677 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1678         { .role = "dbclk", .clk = "gpio5_dbclk" },
1679 };
1680
1681 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1682         .name           = "gpio5",
1683         .class          = &omap44xx_gpio_hwmod_class,
1684         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1685         .mpu_irqs       = omap44xx_gpio5_irqs,
1686         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1687         .main_clk       = "gpio5_ick",
1688         .prcm = {
1689                 .omap4 = {
1690                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1691                 },
1692         },
1693         .opt_clks       = gpio5_opt_clks,
1694         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1695         .dev_attr       = &gpio_dev_attr,
1696         .slaves         = omap44xx_gpio5_slaves,
1697         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1698         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1699 };
1700
1701 /* gpio6 */
1702 static struct omap_hwmod omap44xx_gpio6_hwmod;
1703 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1704         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1705 };
1706
1707 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1708         {
1709                 .pa_start       = 0x4805d000,
1710                 .pa_end         = 0x4805d1ff,
1711                 .flags          = ADDR_TYPE_RT
1712         },
1713 };
1714
1715 /* l4_per -> gpio6 */
1716 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1717         .master         = &omap44xx_l4_per_hwmod,
1718         .slave          = &omap44xx_gpio6_hwmod,
1719         .clk            = "l4_div_ck",
1720         .addr           = omap44xx_gpio6_addrs,
1721         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1723 };
1724
1725 /* gpio6 slave ports */
1726 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1727         &omap44xx_l4_per__gpio6,
1728 };
1729
1730 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1731         { .role = "dbclk", .clk = "gpio6_dbclk" },
1732 };
1733
1734 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1735         .name           = "gpio6",
1736         .class          = &omap44xx_gpio_hwmod_class,
1737         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1738         .mpu_irqs       = omap44xx_gpio6_irqs,
1739         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1740         .main_clk       = "gpio6_ick",
1741         .prcm = {
1742                 .omap4 = {
1743                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1744                 },
1745         },
1746         .opt_clks       = gpio6_opt_clks,
1747         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1748         .dev_attr       = &gpio_dev_attr,
1749         .slaves         = omap44xx_gpio6_slaves,
1750         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1751         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1752 };
1753
1754 /*
1755  * 'i2c' class
1756  * multimaster high-speed i2c controller
1757  */
1758
1759 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1760         .sysc_offs      = 0x0010,
1761         .syss_offs      = 0x0090,
1762         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1763                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1764                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1765         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1766                            SIDLE_SMART_WKUP),
1767         .sysc_fields    = &omap_hwmod_sysc_type1,
1768 };
1769
1770 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1771         .name   = "i2c",
1772         .sysc   = &omap44xx_i2c_sysc,
1773 };
1774
1775 /* i2c1 */
1776 static struct omap_hwmod omap44xx_i2c1_hwmod;
1777 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1778         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1779 };
1780
1781 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1782         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1783         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1784 };
1785
1786 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1787         {
1788                 .pa_start       = 0x48070000,
1789                 .pa_end         = 0x480700ff,
1790                 .flags          = ADDR_TYPE_RT
1791         },
1792 };
1793
1794 /* l4_per -> i2c1 */
1795 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1796         .master         = &omap44xx_l4_per_hwmod,
1797         .slave          = &omap44xx_i2c1_hwmod,
1798         .clk            = "l4_div_ck",
1799         .addr           = omap44xx_i2c1_addrs,
1800         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
1801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1802 };
1803
1804 /* i2c1 slave ports */
1805 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1806         &omap44xx_l4_per__i2c1,
1807 };
1808
1809 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1810         .name           = "i2c1",
1811         .class          = &omap44xx_i2c_hwmod_class,
1812         .flags          = HWMOD_INIT_NO_RESET,
1813         .mpu_irqs       = omap44xx_i2c1_irqs,
1814         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
1815         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1816         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1817         .main_clk       = "i2c1_fck",
1818         .prcm = {
1819                 .omap4 = {
1820                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1821                 },
1822         },
1823         .slaves         = omap44xx_i2c1_slaves,
1824         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
1825         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1826 };
1827
1828 /* i2c2 */
1829 static struct omap_hwmod omap44xx_i2c2_hwmod;
1830 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1831         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1832 };
1833
1834 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1835         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1836         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1837 };
1838
1839 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1840         {
1841                 .pa_start       = 0x48072000,
1842                 .pa_end         = 0x480720ff,
1843                 .flags          = ADDR_TYPE_RT
1844         },
1845 };
1846
1847 /* l4_per -> i2c2 */
1848 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1849         .master         = &omap44xx_l4_per_hwmod,
1850         .slave          = &omap44xx_i2c2_hwmod,
1851         .clk            = "l4_div_ck",
1852         .addr           = omap44xx_i2c2_addrs,
1853         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
1854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1855 };
1856
1857 /* i2c2 slave ports */
1858 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1859         &omap44xx_l4_per__i2c2,
1860 };
1861
1862 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1863         .name           = "i2c2",
1864         .class          = &omap44xx_i2c_hwmod_class,
1865         .flags          = HWMOD_INIT_NO_RESET,
1866         .mpu_irqs       = omap44xx_i2c2_irqs,
1867         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
1868         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1869         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1870         .main_clk       = "i2c2_fck",
1871         .prcm = {
1872                 .omap4 = {
1873                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1874                 },
1875         },
1876         .slaves         = omap44xx_i2c2_slaves,
1877         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
1878         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1879 };
1880
1881 /* i2c3 */
1882 static struct omap_hwmod omap44xx_i2c3_hwmod;
1883 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1884         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1885 };
1886
1887 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1888         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1889         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1890 };
1891
1892 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1893         {
1894                 .pa_start       = 0x48060000,
1895                 .pa_end         = 0x480600ff,
1896                 .flags          = ADDR_TYPE_RT
1897         },
1898 };
1899
1900 /* l4_per -> i2c3 */
1901 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
1902         .master         = &omap44xx_l4_per_hwmod,
1903         .slave          = &omap44xx_i2c3_hwmod,
1904         .clk            = "l4_div_ck",
1905         .addr           = omap44xx_i2c3_addrs,
1906         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
1907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1908 };
1909
1910 /* i2c3 slave ports */
1911 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1912         &omap44xx_l4_per__i2c3,
1913 };
1914
1915 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1916         .name           = "i2c3",
1917         .class          = &omap44xx_i2c_hwmod_class,
1918         .flags          = HWMOD_INIT_NO_RESET,
1919         .mpu_irqs       = omap44xx_i2c3_irqs,
1920         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
1921         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1922         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1923         .main_clk       = "i2c3_fck",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1927                 },
1928         },
1929         .slaves         = omap44xx_i2c3_slaves,
1930         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
1931         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1932 };
1933
1934 /* i2c4 */
1935 static struct omap_hwmod omap44xx_i2c4_hwmod;
1936 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1937         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1938 };
1939
1940 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1941         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1942         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1943 };
1944
1945 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
1946         {
1947                 .pa_start       = 0x48350000,
1948                 .pa_end         = 0x483500ff,
1949                 .flags          = ADDR_TYPE_RT
1950         },
1951 };
1952
1953 /* l4_per -> i2c4 */
1954 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1955         .master         = &omap44xx_l4_per_hwmod,
1956         .slave          = &omap44xx_i2c4_hwmod,
1957         .clk            = "l4_div_ck",
1958         .addr           = omap44xx_i2c4_addrs,
1959         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
1960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1961 };
1962
1963 /* i2c4 slave ports */
1964 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1965         &omap44xx_l4_per__i2c4,
1966 };
1967
1968 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1969         .name           = "i2c4",
1970         .class          = &omap44xx_i2c_hwmod_class,
1971         .flags          = HWMOD_INIT_NO_RESET,
1972         .mpu_irqs       = omap44xx_i2c4_irqs,
1973         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
1974         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1975         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1976         .main_clk       = "i2c4_fck",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1980                 },
1981         },
1982         .slaves         = omap44xx_i2c4_slaves,
1983         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
1984         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1985 };
1986
1987 /*
1988  * 'iva' class
1989  * multi-standard video encoder/decoder hardware accelerator
1990  */
1991
1992 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1993         .name   = "iva",
1994 };
1995
1996 /* iva */
1997 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1998         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1999         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2000         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2001 };
2002
2003 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2004         { .name = "logic", .rst_shift = 2 },
2005 };
2006
2007 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2008         { .name = "seq0", .rst_shift = 0 },
2009 };
2010
2011 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2012         { .name = "seq1", .rst_shift = 1 },
2013 };
2014
2015 /* iva master ports */
2016 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2017         &omap44xx_iva__l3_main_2,
2018         &omap44xx_iva__l3_instr,
2019 };
2020
2021 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2022         {
2023                 .pa_start       = 0x5a000000,
2024                 .pa_end         = 0x5a07ffff,
2025                 .flags          = ADDR_TYPE_RT
2026         },
2027 };
2028
2029 /* l3_main_2 -> iva */
2030 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2031         .master         = &omap44xx_l3_main_2_hwmod,
2032         .slave          = &omap44xx_iva_hwmod,
2033         .clk            = "l3_div_ck",
2034         .addr           = omap44xx_iva_addrs,
2035         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
2036         .user           = OCP_USER_MPU,
2037 };
2038
2039 /* iva slave ports */
2040 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2041         &omap44xx_dsp__iva,
2042         &omap44xx_l3_main_2__iva,
2043 };
2044
2045 /* Pseudo hwmod for reset control purpose only */
2046 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2047         .name           = "iva_seq0",
2048         .class          = &omap44xx_iva_hwmod_class,
2049         .flags          = HWMOD_INIT_NO_RESET,
2050         .rst_lines      = omap44xx_iva_seq0_resets,
2051         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2052         .prcm = {
2053                 .omap4 = {
2054                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2055                 },
2056         },
2057         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2058 };
2059
2060 /* Pseudo hwmod for reset control purpose only */
2061 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2062         .name           = "iva_seq1",
2063         .class          = &omap44xx_iva_hwmod_class,
2064         .flags          = HWMOD_INIT_NO_RESET,
2065         .rst_lines      = omap44xx_iva_seq1_resets,
2066         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2067         .prcm = {
2068                 .omap4 = {
2069                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2070                 },
2071         },
2072         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2073 };
2074
2075 static struct omap_hwmod omap44xx_iva_hwmod = {
2076         .name           = "iva",
2077         .class          = &omap44xx_iva_hwmod_class,
2078         .mpu_irqs       = omap44xx_iva_irqs,
2079         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
2080         .rst_lines      = omap44xx_iva_resets,
2081         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2082         .main_clk       = "iva_fck",
2083         .prcm = {
2084                 .omap4 = {
2085                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2086                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2087                 },
2088         },
2089         .slaves         = omap44xx_iva_slaves,
2090         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2091         .masters        = omap44xx_iva_masters,
2092         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2093         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2094 };
2095
2096 /*
2097  * 'mailbox' class
2098  * mailbox module allowing communication between the on-chip processors using a
2099  * queued mailbox-interrupt mechanism.
2100  */
2101
2102 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2103         .rev_offs       = 0x0000,
2104         .sysc_offs      = 0x0010,
2105         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2106                            SYSC_HAS_SOFTRESET),
2107         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2108         .sysc_fields    = &omap_hwmod_sysc_type2,
2109 };
2110
2111 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2112         .name   = "mailbox",
2113         .sysc   = &omap44xx_mailbox_sysc,
2114 };
2115
2116 /* mailbox */
2117 static struct omap_hwmod omap44xx_mailbox_hwmod;
2118 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2119         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2120 };
2121
2122 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2123         {
2124                 .pa_start       = 0x4a0f4000,
2125                 .pa_end         = 0x4a0f41ff,
2126                 .flags          = ADDR_TYPE_RT
2127         },
2128 };
2129
2130 /* l4_cfg -> mailbox */
2131 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2132         .master         = &omap44xx_l4_cfg_hwmod,
2133         .slave          = &omap44xx_mailbox_hwmod,
2134         .clk            = "l4_div_ck",
2135         .addr           = omap44xx_mailbox_addrs,
2136         .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
2137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2138 };
2139
2140 /* mailbox slave ports */
2141 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2142         &omap44xx_l4_cfg__mailbox,
2143 };
2144
2145 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2146         .name           = "mailbox",
2147         .class          = &omap44xx_mailbox_hwmod_class,
2148         .mpu_irqs       = omap44xx_mailbox_irqs,
2149         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
2150         .prcm           = {
2151                 .omap4 = {
2152                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2153                 },
2154         },
2155         .slaves         = omap44xx_mailbox_slaves,
2156         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2157         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2158 };
2159
2160 /*
2161  * 'mcspi' class
2162  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2163  * bus
2164  */
2165
2166 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2167         .rev_offs       = 0x0000,
2168         .sysc_offs      = 0x0010,
2169         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2170                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2171         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2172                            SIDLE_SMART_WKUP),
2173         .sysc_fields    = &omap_hwmod_sysc_type2,
2174 };
2175
2176 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2177         .name   = "mcspi",
2178         .sysc   = &omap44xx_mcspi_sysc,
2179 };
2180
2181 /* mcspi1 */
2182 static struct omap_hwmod omap44xx_mcspi1_hwmod;
2183 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2184         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2185 };
2186
2187 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2188         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2189         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2190         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2191         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2192         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2193         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2194         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2195         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2196 };
2197
2198 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
2199         {
2200                 .pa_start       = 0x48098000,
2201                 .pa_end         = 0x480981ff,
2202                 .flags          = ADDR_TYPE_RT
2203         },
2204 };
2205
2206 /* l4_per -> mcspi1 */
2207 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
2208         .master         = &omap44xx_l4_per_hwmod,
2209         .slave          = &omap44xx_mcspi1_hwmod,
2210         .clk            = "l4_div_ck",
2211         .addr           = omap44xx_mcspi1_addrs,
2212         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* mcspi1 slave ports */
2217 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
2218         &omap44xx_l4_per__mcspi1,
2219 };
2220
2221 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2222         .name           = "mcspi1",
2223         .class          = &omap44xx_mcspi_hwmod_class,
2224         .mpu_irqs       = omap44xx_mcspi1_irqs,
2225         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
2226         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2227         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
2228         .main_clk       = "mcspi1_fck",
2229         .prcm = {
2230                 .omap4 = {
2231                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2232                 },
2233         },
2234         .slaves         = omap44xx_mcspi1_slaves,
2235         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
2236         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2237 };
2238
2239 /* mcspi2 */
2240 static struct omap_hwmod omap44xx_mcspi2_hwmod;
2241 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2242         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2243 };
2244
2245 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2246         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2247         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2248         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2249         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2250 };
2251
2252 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
2253         {
2254                 .pa_start       = 0x4809a000,
2255                 .pa_end         = 0x4809a1ff,
2256                 .flags          = ADDR_TYPE_RT
2257         },
2258 };
2259
2260 /* l4_per -> mcspi2 */
2261 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
2262         .master         = &omap44xx_l4_per_hwmod,
2263         .slave          = &omap44xx_mcspi2_hwmod,
2264         .clk            = "l4_div_ck",
2265         .addr           = omap44xx_mcspi2_addrs,
2266         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
2267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2268 };
2269
2270 /* mcspi2 slave ports */
2271 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
2272         &omap44xx_l4_per__mcspi2,
2273 };
2274
2275 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2276         .name           = "mcspi2",
2277         .class          = &omap44xx_mcspi_hwmod_class,
2278         .mpu_irqs       = omap44xx_mcspi2_irqs,
2279         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
2280         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2281         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
2282         .main_clk       = "mcspi2_fck",
2283         .prcm = {
2284                 .omap4 = {
2285                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2286                 },
2287         },
2288         .slaves         = omap44xx_mcspi2_slaves,
2289         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
2290         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2291 };
2292
2293 /* mcspi3 */
2294 static struct omap_hwmod omap44xx_mcspi3_hwmod;
2295 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2296         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2297 };
2298
2299 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2300         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2301         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2302         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2303         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2304 };
2305
2306 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
2307         {
2308                 .pa_start       = 0x480b8000,
2309                 .pa_end         = 0x480b81ff,
2310                 .flags          = ADDR_TYPE_RT
2311         },
2312 };
2313
2314 /* l4_per -> mcspi3 */
2315 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
2316         .master         = &omap44xx_l4_per_hwmod,
2317         .slave          = &omap44xx_mcspi3_hwmod,
2318         .clk            = "l4_div_ck",
2319         .addr           = omap44xx_mcspi3_addrs,
2320         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
2321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2322 };
2323
2324 /* mcspi3 slave ports */
2325 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
2326         &omap44xx_l4_per__mcspi3,
2327 };
2328
2329 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2330         .name           = "mcspi3",
2331         .class          = &omap44xx_mcspi_hwmod_class,
2332         .mpu_irqs       = omap44xx_mcspi3_irqs,
2333         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
2334         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2335         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
2336         .main_clk       = "mcspi3_fck",
2337         .prcm = {
2338                 .omap4 = {
2339                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2340                 },
2341         },
2342         .slaves         = omap44xx_mcspi3_slaves,
2343         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
2344         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2345 };
2346
2347 /* mcspi4 */
2348 static struct omap_hwmod omap44xx_mcspi4_hwmod;
2349 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2350         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2351 };
2352
2353 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2354         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2355         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2356 };
2357
2358 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
2359         {
2360                 .pa_start       = 0x480ba000,
2361                 .pa_end         = 0x480ba1ff,
2362                 .flags          = ADDR_TYPE_RT
2363         },
2364 };
2365
2366 /* l4_per -> mcspi4 */
2367 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
2368         .master         = &omap44xx_l4_per_hwmod,
2369         .slave          = &omap44xx_mcspi4_hwmod,
2370         .clk            = "l4_div_ck",
2371         .addr           = omap44xx_mcspi4_addrs,
2372         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
2373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2374 };
2375
2376 /* mcspi4 slave ports */
2377 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
2378         &omap44xx_l4_per__mcspi4,
2379 };
2380
2381 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2382         .name           = "mcspi4",
2383         .class          = &omap44xx_mcspi_hwmod_class,
2384         .mpu_irqs       = omap44xx_mcspi4_irqs,
2385         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
2386         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2387         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
2388         .main_clk       = "mcspi4_fck",
2389         .prcm = {
2390                 .omap4 = {
2391                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2392                 },
2393         },
2394         .slaves         = omap44xx_mcspi4_slaves,
2395         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
2396         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2397 };
2398
2399 /*
2400  * 'mpu' class
2401  * mpu sub-system
2402  */
2403
2404 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2405         .name   = "mpu",
2406 };
2407
2408 /* mpu */
2409 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2410         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2411         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2412         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2413 };
2414
2415 /* mpu master ports */
2416 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
2417         &omap44xx_mpu__l3_main_1,
2418         &omap44xx_mpu__l4_abe,
2419         &omap44xx_mpu__dmm,
2420 };
2421
2422 static struct omap_hwmod omap44xx_mpu_hwmod = {
2423         .name           = "mpu",
2424         .class          = &omap44xx_mpu_hwmod_class,
2425         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
2426         .mpu_irqs       = omap44xx_mpu_irqs,
2427         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
2428         .main_clk       = "dpll_mpu_m2_ck",
2429         .prcm = {
2430                 .omap4 = {
2431                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
2432                 },
2433         },
2434         .masters        = omap44xx_mpu_masters,
2435         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
2436         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2437 };
2438
2439 /*
2440  * 'smartreflex' class
2441  * smartreflex module (monitor silicon performance and outputs a measure of
2442  * performance error)
2443  */
2444
2445 /* The IP is not compliant to type1 / type2 scheme */
2446 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2447         .sidle_shift    = 24,
2448         .enwkup_shift   = 26,
2449 };
2450
2451 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2452         .sysc_offs      = 0x0038,
2453         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2454         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2455                            SIDLE_SMART_WKUP),
2456         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2457 };
2458
2459 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2460         .name   = "smartreflex",
2461         .sysc   = &omap44xx_smartreflex_sysc,
2462         .rev    = 2,
2463 };
2464
2465 /* smartreflex_core */
2466 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
2467 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2468         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2469 };
2470
2471 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
2472         {
2473                 .pa_start       = 0x4a0dd000,
2474                 .pa_end         = 0x4a0dd03f,
2475                 .flags          = ADDR_TYPE_RT
2476         },
2477 };
2478
2479 /* l4_cfg -> smartreflex_core */
2480 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
2481         .master         = &omap44xx_l4_cfg_hwmod,
2482         .slave          = &omap44xx_smartreflex_core_hwmod,
2483         .clk            = "l4_div_ck",
2484         .addr           = omap44xx_smartreflex_core_addrs,
2485         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
2486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 /* smartreflex_core slave ports */
2490 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
2491         &omap44xx_l4_cfg__smartreflex_core,
2492 };
2493
2494 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2495         .name           = "smartreflex_core",
2496         .class          = &omap44xx_smartreflex_hwmod_class,
2497         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2498         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
2499         .main_clk       = "smartreflex_core_fck",
2500         .vdd_name       = "core",
2501         .prcm = {
2502                 .omap4 = {
2503                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2504                 },
2505         },
2506         .slaves         = omap44xx_smartreflex_core_slaves,
2507         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
2508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2509 };
2510
2511 /* smartreflex_iva */
2512 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
2513 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2514         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2515 };
2516
2517 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
2518         {
2519                 .pa_start       = 0x4a0db000,
2520                 .pa_end         = 0x4a0db03f,
2521                 .flags          = ADDR_TYPE_RT
2522         },
2523 };
2524
2525 /* l4_cfg -> smartreflex_iva */
2526 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
2527         .master         = &omap44xx_l4_cfg_hwmod,
2528         .slave          = &omap44xx_smartreflex_iva_hwmod,
2529         .clk            = "l4_div_ck",
2530         .addr           = omap44xx_smartreflex_iva_addrs,
2531         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
2532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2533 };
2534
2535 /* smartreflex_iva slave ports */
2536 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
2537         &omap44xx_l4_cfg__smartreflex_iva,
2538 };
2539
2540 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2541         .name           = "smartreflex_iva",
2542         .class          = &omap44xx_smartreflex_hwmod_class,
2543         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2544         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
2545         .main_clk       = "smartreflex_iva_fck",
2546         .vdd_name       = "iva",
2547         .prcm = {
2548                 .omap4 = {
2549                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2550                 },
2551         },
2552         .slaves         = omap44xx_smartreflex_iva_slaves,
2553         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
2554         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2555 };
2556
2557 /* smartreflex_mpu */
2558 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
2559 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2560         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2561 };
2562
2563 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
2564         {
2565                 .pa_start       = 0x4a0d9000,
2566                 .pa_end         = 0x4a0d903f,
2567                 .flags          = ADDR_TYPE_RT
2568         },
2569 };
2570
2571 /* l4_cfg -> smartreflex_mpu */
2572 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
2573         .master         = &omap44xx_l4_cfg_hwmod,
2574         .slave          = &omap44xx_smartreflex_mpu_hwmod,
2575         .clk            = "l4_div_ck",
2576         .addr           = omap44xx_smartreflex_mpu_addrs,
2577         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
2578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581 /* smartreflex_mpu slave ports */
2582 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
2583         &omap44xx_l4_cfg__smartreflex_mpu,
2584 };
2585
2586 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2587         .name           = "smartreflex_mpu",
2588         .class          = &omap44xx_smartreflex_hwmod_class,
2589         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2590         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
2591         .main_clk       = "smartreflex_mpu_fck",
2592         .vdd_name       = "mpu",
2593         .prcm = {
2594                 .omap4 = {
2595                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2596                 },
2597         },
2598         .slaves         = omap44xx_smartreflex_mpu_slaves,
2599         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
2600         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2601 };
2602
2603 /*
2604  * 'spinlock' class
2605  * spinlock provides hardware assistance for synchronizing the processes
2606  * running on multiple processors
2607  */
2608
2609 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2610         .rev_offs       = 0x0000,
2611         .sysc_offs      = 0x0010,
2612         .syss_offs      = 0x0014,
2613         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2614                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2615                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2616         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2617                            SIDLE_SMART_WKUP),
2618         .sysc_fields    = &omap_hwmod_sysc_type1,
2619 };
2620
2621 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2622         .name   = "spinlock",
2623         .sysc   = &omap44xx_spinlock_sysc,
2624 };
2625
2626 /* spinlock */
2627 static struct omap_hwmod omap44xx_spinlock_hwmod;
2628 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
2629         {
2630                 .pa_start       = 0x4a0f6000,
2631                 .pa_end         = 0x4a0f6fff,
2632                 .flags          = ADDR_TYPE_RT
2633         },
2634 };
2635
2636 /* l4_cfg -> spinlock */
2637 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
2638         .master         = &omap44xx_l4_cfg_hwmod,
2639         .slave          = &omap44xx_spinlock_hwmod,
2640         .clk            = "l4_div_ck",
2641         .addr           = omap44xx_spinlock_addrs,
2642         .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
2643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2644 };
2645
2646 /* spinlock slave ports */
2647 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
2648         &omap44xx_l4_cfg__spinlock,
2649 };
2650
2651 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2652         .name           = "spinlock",
2653         .class          = &omap44xx_spinlock_hwmod_class,
2654         .prcm = {
2655                 .omap4 = {
2656                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
2657                 },
2658         },
2659         .slaves         = omap44xx_spinlock_slaves,
2660         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
2661         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2662 };
2663
2664 /*
2665  * 'timer' class
2666  * general purpose timer module with accurate 1ms tick
2667  * This class contains several variants: ['timer_1ms', 'timer']
2668  */
2669
2670 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2671         .rev_offs       = 0x0000,
2672         .sysc_offs      = 0x0010,
2673         .syss_offs      = 0x0014,
2674         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2675                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2676                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2677                            SYSS_HAS_RESET_STATUS),
2678         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2679         .sysc_fields    = &omap_hwmod_sysc_type1,
2680 };
2681
2682 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2683         .name   = "timer",
2684         .sysc   = &omap44xx_timer_1ms_sysc,
2685 };
2686
2687 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2688         .rev_offs       = 0x0000,
2689         .sysc_offs      = 0x0010,
2690         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2691                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2692         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2693                            SIDLE_SMART_WKUP),
2694         .sysc_fields    = &omap_hwmod_sysc_type2,
2695 };
2696
2697 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2698         .name   = "timer",
2699         .sysc   = &omap44xx_timer_sysc,
2700 };
2701
2702 /* timer1 */
2703 static struct omap_hwmod omap44xx_timer1_hwmod;
2704 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2705         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2706 };
2707
2708 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
2709         {
2710                 .pa_start       = 0x4a318000,
2711                 .pa_end         = 0x4a31807f,
2712                 .flags          = ADDR_TYPE_RT
2713         },
2714 };
2715
2716 /* l4_wkup -> timer1 */
2717 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
2718         .master         = &omap44xx_l4_wkup_hwmod,
2719         .slave          = &omap44xx_timer1_hwmod,
2720         .clk            = "l4_wkup_clk_mux_ck",
2721         .addr           = omap44xx_timer1_addrs,
2722         .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
2723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2724 };
2725
2726 /* timer1 slave ports */
2727 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
2728         &omap44xx_l4_wkup__timer1,
2729 };
2730
2731 static struct omap_hwmod omap44xx_timer1_hwmod = {
2732         .name           = "timer1",
2733         .class          = &omap44xx_timer_1ms_hwmod_class,
2734         .mpu_irqs       = omap44xx_timer1_irqs,
2735         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
2736         .main_clk       = "timer1_fck",
2737         .prcm = {
2738                 .omap4 = {
2739                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2740                 },
2741         },
2742         .slaves         = omap44xx_timer1_slaves,
2743         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
2744         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2745 };
2746
2747 /* timer2 */
2748 static struct omap_hwmod omap44xx_timer2_hwmod;
2749 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2750         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2751 };
2752
2753 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
2754         {
2755                 .pa_start       = 0x48032000,
2756                 .pa_end         = 0x4803207f,
2757                 .flags          = ADDR_TYPE_RT
2758         },
2759 };
2760
2761 /* l4_per -> timer2 */
2762 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
2763         .master         = &omap44xx_l4_per_hwmod,
2764         .slave          = &omap44xx_timer2_hwmod,
2765         .clk            = "l4_div_ck",
2766         .addr           = omap44xx_timer2_addrs,
2767         .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
2768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2769 };
2770
2771 /* timer2 slave ports */
2772 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
2773         &omap44xx_l4_per__timer2,
2774 };
2775
2776 static struct omap_hwmod omap44xx_timer2_hwmod = {
2777         .name           = "timer2",
2778         .class          = &omap44xx_timer_1ms_hwmod_class,
2779         .mpu_irqs       = omap44xx_timer2_irqs,
2780         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
2781         .main_clk       = "timer2_fck",
2782         .prcm = {
2783                 .omap4 = {
2784                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2785                 },
2786         },
2787         .slaves         = omap44xx_timer2_slaves,
2788         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
2789         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2790 };
2791
2792 /* timer3 */
2793 static struct omap_hwmod omap44xx_timer3_hwmod;
2794 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2795         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2796 };
2797
2798 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
2799         {
2800                 .pa_start       = 0x48034000,
2801                 .pa_end         = 0x4803407f,
2802                 .flags          = ADDR_TYPE_RT
2803         },
2804 };
2805
2806 /* l4_per -> timer3 */
2807 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
2808         .master         = &omap44xx_l4_per_hwmod,
2809         .slave          = &omap44xx_timer3_hwmod,
2810         .clk            = "l4_div_ck",
2811         .addr           = omap44xx_timer3_addrs,
2812         .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
2813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /* timer3 slave ports */
2817 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
2818         &omap44xx_l4_per__timer3,
2819 };
2820
2821 static struct omap_hwmod omap44xx_timer3_hwmod = {
2822         .name           = "timer3",
2823         .class          = &omap44xx_timer_hwmod_class,
2824         .mpu_irqs       = omap44xx_timer3_irqs,
2825         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
2826         .main_clk       = "timer3_fck",
2827         .prcm = {
2828                 .omap4 = {
2829                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2830                 },
2831         },
2832         .slaves         = omap44xx_timer3_slaves,
2833         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
2834         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2835 };
2836
2837 /* timer4 */
2838 static struct omap_hwmod omap44xx_timer4_hwmod;
2839 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2840         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2841 };
2842
2843 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
2844         {
2845                 .pa_start       = 0x48036000,
2846                 .pa_end         = 0x4803607f,
2847                 .flags          = ADDR_TYPE_RT
2848         },
2849 };
2850
2851 /* l4_per -> timer4 */
2852 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
2853         .master         = &omap44xx_l4_per_hwmod,
2854         .slave          = &omap44xx_timer4_hwmod,
2855         .clk            = "l4_div_ck",
2856         .addr           = omap44xx_timer4_addrs,
2857         .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
2858         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2859 };
2860
2861 /* timer4 slave ports */
2862 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
2863         &omap44xx_l4_per__timer4,
2864 };
2865
2866 static struct omap_hwmod omap44xx_timer4_hwmod = {
2867         .name           = "timer4",
2868         .class          = &omap44xx_timer_hwmod_class,
2869         .mpu_irqs       = omap44xx_timer4_irqs,
2870         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
2871         .main_clk       = "timer4_fck",
2872         .prcm = {
2873                 .omap4 = {
2874                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2875                 },
2876         },
2877         .slaves         = omap44xx_timer4_slaves,
2878         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
2879         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2880 };
2881
2882 /* timer5 */
2883 static struct omap_hwmod omap44xx_timer5_hwmod;
2884 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2885         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2886 };
2887
2888 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
2889         {
2890                 .pa_start       = 0x40138000,
2891                 .pa_end         = 0x4013807f,
2892                 .flags          = ADDR_TYPE_RT
2893         },
2894 };
2895
2896 /* l4_abe -> timer5 */
2897 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
2898         .master         = &omap44xx_l4_abe_hwmod,
2899         .slave          = &omap44xx_timer5_hwmod,
2900         .clk            = "ocp_abe_iclk",
2901         .addr           = omap44xx_timer5_addrs,
2902         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
2903         .user           = OCP_USER_MPU,
2904 };
2905
2906 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
2907         {
2908                 .pa_start       = 0x49038000,
2909                 .pa_end         = 0x4903807f,
2910                 .flags          = ADDR_TYPE_RT
2911         },
2912 };
2913
2914 /* l4_abe -> timer5 (dma) */
2915 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
2916         .master         = &omap44xx_l4_abe_hwmod,
2917         .slave          = &omap44xx_timer5_hwmod,
2918         .clk            = "ocp_abe_iclk",
2919         .addr           = omap44xx_timer5_dma_addrs,
2920         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
2921         .user           = OCP_USER_SDMA,
2922 };
2923
2924 /* timer5 slave ports */
2925 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
2926         &omap44xx_l4_abe__timer5,
2927         &omap44xx_l4_abe__timer5_dma,
2928 };
2929
2930 static struct omap_hwmod omap44xx_timer5_hwmod = {
2931         .name           = "timer5",
2932         .class          = &omap44xx_timer_hwmod_class,
2933         .mpu_irqs       = omap44xx_timer5_irqs,
2934         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
2935         .main_clk       = "timer5_fck",
2936         .prcm = {
2937                 .omap4 = {
2938                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2939                 },
2940         },
2941         .slaves         = omap44xx_timer5_slaves,
2942         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
2943         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2944 };
2945
2946 /* timer6 */
2947 static struct omap_hwmod omap44xx_timer6_hwmod;
2948 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
2949         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
2950 };
2951
2952 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
2953         {
2954                 .pa_start       = 0x4013a000,
2955                 .pa_end         = 0x4013a07f,
2956                 .flags          = ADDR_TYPE_RT
2957         },
2958 };
2959
2960 /* l4_abe -> timer6 */
2961 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
2962         .master         = &omap44xx_l4_abe_hwmod,
2963         .slave          = &omap44xx_timer6_hwmod,
2964         .clk            = "ocp_abe_iclk",
2965         .addr           = omap44xx_timer6_addrs,
2966         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
2967         .user           = OCP_USER_MPU,
2968 };
2969
2970 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
2971         {
2972                 .pa_start       = 0x4903a000,
2973                 .pa_end         = 0x4903a07f,
2974                 .flags          = ADDR_TYPE_RT
2975         },
2976 };
2977
2978 /* l4_abe -> timer6 (dma) */
2979 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
2980         .master         = &omap44xx_l4_abe_hwmod,
2981         .slave          = &omap44xx_timer6_hwmod,
2982         .clk            = "ocp_abe_iclk",
2983         .addr           = omap44xx_timer6_dma_addrs,
2984         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
2985         .user           = OCP_USER_SDMA,
2986 };
2987
2988 /* timer6 slave ports */
2989 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
2990         &omap44xx_l4_abe__timer6,
2991         &omap44xx_l4_abe__timer6_dma,
2992 };
2993
2994 static struct omap_hwmod omap44xx_timer6_hwmod = {
2995         .name           = "timer6",
2996         .class          = &omap44xx_timer_hwmod_class,
2997         .mpu_irqs       = omap44xx_timer6_irqs,
2998         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
2999         .main_clk       = "timer6_fck",
3000         .prcm = {
3001                 .omap4 = {
3002                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
3003                 },
3004         },
3005         .slaves         = omap44xx_timer6_slaves,
3006         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
3007         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3008 };
3009
3010 /* timer7 */
3011 static struct omap_hwmod omap44xx_timer7_hwmod;
3012 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3013         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3014 };
3015
3016 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
3017         {
3018                 .pa_start       = 0x4013c000,
3019                 .pa_end         = 0x4013c07f,
3020                 .flags          = ADDR_TYPE_RT
3021         },
3022 };
3023
3024 /* l4_abe -> timer7 */
3025 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
3026         .master         = &omap44xx_l4_abe_hwmod,
3027         .slave          = &omap44xx_timer7_hwmod,
3028         .clk            = "ocp_abe_iclk",
3029         .addr           = omap44xx_timer7_addrs,
3030         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
3031         .user           = OCP_USER_MPU,
3032 };
3033
3034 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
3035         {
3036                 .pa_start       = 0x4903c000,
3037                 .pa_end         = 0x4903c07f,
3038                 .flags          = ADDR_TYPE_RT
3039         },
3040 };
3041
3042 /* l4_abe -> timer7 (dma) */
3043 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
3044         .master         = &omap44xx_l4_abe_hwmod,
3045         .slave          = &omap44xx_timer7_hwmod,
3046         .clk            = "ocp_abe_iclk",
3047         .addr           = omap44xx_timer7_dma_addrs,
3048         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
3049         .user           = OCP_USER_SDMA,
3050 };
3051
3052 /* timer7 slave ports */
3053 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
3054         &omap44xx_l4_abe__timer7,
3055         &omap44xx_l4_abe__timer7_dma,
3056 };
3057
3058 static struct omap_hwmod omap44xx_timer7_hwmod = {
3059         .name           = "timer7",
3060         .class          = &omap44xx_timer_hwmod_class,
3061         .mpu_irqs       = omap44xx_timer7_irqs,
3062         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
3063         .main_clk       = "timer7_fck",
3064         .prcm = {
3065                 .omap4 = {
3066                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
3067                 },
3068         },
3069         .slaves         = omap44xx_timer7_slaves,
3070         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
3071         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3072 };
3073
3074 /* timer8 */
3075 static struct omap_hwmod omap44xx_timer8_hwmod;
3076 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3077         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3078 };
3079
3080 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
3081         {
3082                 .pa_start       = 0x4013e000,
3083                 .pa_end         = 0x4013e07f,
3084                 .flags          = ADDR_TYPE_RT
3085         },
3086 };
3087
3088 /* l4_abe -> timer8 */
3089 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
3090         .master         = &omap44xx_l4_abe_hwmod,
3091         .slave          = &omap44xx_timer8_hwmod,
3092         .clk            = "ocp_abe_iclk",
3093         .addr           = omap44xx_timer8_addrs,
3094         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
3095         .user           = OCP_USER_MPU,
3096 };
3097
3098 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
3099         {
3100                 .pa_start       = 0x4903e000,
3101                 .pa_end         = 0x4903e07f,
3102                 .flags          = ADDR_TYPE_RT
3103         },
3104 };
3105
3106 /* l4_abe -> timer8 (dma) */
3107 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
3108         .master         = &omap44xx_l4_abe_hwmod,
3109         .slave          = &omap44xx_timer8_hwmod,
3110         .clk            = "ocp_abe_iclk",
3111         .addr           = omap44xx_timer8_dma_addrs,
3112         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
3113         .user           = OCP_USER_SDMA,
3114 };
3115
3116 /* timer8 slave ports */
3117 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
3118         &omap44xx_l4_abe__timer8,
3119         &omap44xx_l4_abe__timer8_dma,
3120 };
3121
3122 static struct omap_hwmod omap44xx_timer8_hwmod = {
3123         .name           = "timer8",
3124         .class          = &omap44xx_timer_hwmod_class,
3125         .mpu_irqs       = omap44xx_timer8_irqs,
3126         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
3127         .main_clk       = "timer8_fck",
3128         .prcm = {
3129                 .omap4 = {
3130                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
3131                 },
3132         },
3133         .slaves         = omap44xx_timer8_slaves,
3134         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
3135         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3136 };
3137
3138 /* timer9 */
3139 static struct omap_hwmod omap44xx_timer9_hwmod;
3140 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3141         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3142 };
3143
3144 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
3145         {
3146                 .pa_start       = 0x4803e000,
3147                 .pa_end         = 0x4803e07f,
3148                 .flags          = ADDR_TYPE_RT
3149         },
3150 };
3151
3152 /* l4_per -> timer9 */
3153 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
3154         .master         = &omap44xx_l4_per_hwmod,
3155         .slave          = &omap44xx_timer9_hwmod,
3156         .clk            = "l4_div_ck",
3157         .addr           = omap44xx_timer9_addrs,
3158         .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
3159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3160 };
3161
3162 /* timer9 slave ports */
3163 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
3164         &omap44xx_l4_per__timer9,
3165 };
3166
3167 static struct omap_hwmod omap44xx_timer9_hwmod = {
3168         .name           = "timer9",
3169         .class          = &omap44xx_timer_hwmod_class,
3170         .mpu_irqs       = omap44xx_timer9_irqs,
3171         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
3172         .main_clk       = "timer9_fck",
3173         .prcm = {
3174                 .omap4 = {
3175                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
3176                 },
3177         },
3178         .slaves         = omap44xx_timer9_slaves,
3179         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
3180         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3181 };
3182
3183 /* timer10 */
3184 static struct omap_hwmod omap44xx_timer10_hwmod;
3185 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3186         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3187 };
3188
3189 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
3190         {
3191                 .pa_start       = 0x48086000,
3192                 .pa_end         = 0x4808607f,
3193                 .flags          = ADDR_TYPE_RT
3194         },
3195 };
3196
3197 /* l4_per -> timer10 */
3198 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
3199         .master         = &omap44xx_l4_per_hwmod,
3200         .slave          = &omap44xx_timer10_hwmod,
3201         .clk            = "l4_div_ck",
3202         .addr           = omap44xx_timer10_addrs,
3203         .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
3204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3205 };
3206
3207 /* timer10 slave ports */
3208 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
3209         &omap44xx_l4_per__timer10,
3210 };
3211
3212 static struct omap_hwmod omap44xx_timer10_hwmod = {
3213         .name           = "timer10",
3214         .class          = &omap44xx_timer_1ms_hwmod_class,
3215         .mpu_irqs       = omap44xx_timer10_irqs,
3216         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
3217         .main_clk       = "timer10_fck",
3218         .prcm = {
3219                 .omap4 = {
3220                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
3221                 },
3222         },
3223         .slaves         = omap44xx_timer10_slaves,
3224         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
3225         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3226 };
3227
3228 /* timer11 */
3229 static struct omap_hwmod omap44xx_timer11_hwmod;
3230 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3231         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3232 };
3233
3234 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
3235         {
3236                 .pa_start       = 0x48088000,
3237                 .pa_end         = 0x4808807f,
3238                 .flags          = ADDR_TYPE_RT
3239         },
3240 };
3241
3242 /* l4_per -> timer11 */
3243 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
3244         .master         = &omap44xx_l4_per_hwmod,
3245         .slave          = &omap44xx_timer11_hwmod,
3246         .clk            = "l4_div_ck",
3247         .addr           = omap44xx_timer11_addrs,
3248         .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
3249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3250 };
3251
3252 /* timer11 slave ports */
3253 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
3254         &omap44xx_l4_per__timer11,
3255 };
3256
3257 static struct omap_hwmod omap44xx_timer11_hwmod = {
3258         .name           = "timer11",
3259         .class          = &omap44xx_timer_hwmod_class,
3260         .mpu_irqs       = omap44xx_timer11_irqs,
3261         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
3262         .main_clk       = "timer11_fck",
3263         .prcm = {
3264                 .omap4 = {
3265                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
3266                 },
3267         },
3268         .slaves         = omap44xx_timer11_slaves,
3269         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
3270         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3271 };
3272
3273 /*
3274  * 'uart' class
3275  * universal asynchronous receiver/transmitter (uart)
3276  */
3277
3278 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3279         .rev_offs       = 0x0050,
3280         .sysc_offs      = 0x0054,
3281         .syss_offs      = 0x0058,
3282         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3283                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3284                            SYSS_HAS_RESET_STATUS),
3285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3286                            SIDLE_SMART_WKUP),
3287         .sysc_fields    = &omap_hwmod_sysc_type1,
3288 };
3289
3290 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3291         .name   = "uart",
3292         .sysc   = &omap44xx_uart_sysc,
3293 };
3294
3295 /* uart1 */
3296 static struct omap_hwmod omap44xx_uart1_hwmod;
3297 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3298         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3299 };
3300
3301 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3302         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3303         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3304 };
3305
3306 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
3307         {
3308                 .pa_start       = 0x4806a000,
3309                 .pa_end         = 0x4806a0ff,
3310                 .flags          = ADDR_TYPE_RT
3311         },
3312 };
3313
3314 /* l4_per -> uart1 */
3315 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
3316         .master         = &omap44xx_l4_per_hwmod,
3317         .slave          = &omap44xx_uart1_hwmod,
3318         .clk            = "l4_div_ck",
3319         .addr           = omap44xx_uart1_addrs,
3320         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
3321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 /* uart1 slave ports */
3325 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
3326         &omap44xx_l4_per__uart1,
3327 };
3328
3329 static struct omap_hwmod omap44xx_uart1_hwmod = {
3330         .name           = "uart1",
3331         .class          = &omap44xx_uart_hwmod_class,
3332         .mpu_irqs       = omap44xx_uart1_irqs,
3333         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
3334         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3335         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
3336         .main_clk       = "uart1_fck",
3337         .prcm = {
3338                 .omap4 = {
3339                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
3340                 },
3341         },
3342         .slaves         = omap44xx_uart1_slaves,
3343         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
3344         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3345 };
3346
3347 /* uart2 */
3348 static struct omap_hwmod omap44xx_uart2_hwmod;
3349 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3350         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3351 };
3352
3353 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3354         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3355         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3356 };
3357
3358 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
3359         {
3360                 .pa_start       = 0x4806c000,
3361                 .pa_end         = 0x4806c0ff,
3362                 .flags          = ADDR_TYPE_RT
3363         },
3364 };
3365
3366 /* l4_per -> uart2 */
3367 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
3368         .master         = &omap44xx_l4_per_hwmod,
3369         .slave          = &omap44xx_uart2_hwmod,
3370         .clk            = "l4_div_ck",
3371         .addr           = omap44xx_uart2_addrs,
3372         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
3373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3374 };
3375
3376 /* uart2 slave ports */
3377 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
3378         &omap44xx_l4_per__uart2,
3379 };
3380
3381 static struct omap_hwmod omap44xx_uart2_hwmod = {
3382         .name           = "uart2",
3383         .class          = &omap44xx_uart_hwmod_class,
3384         .mpu_irqs       = omap44xx_uart2_irqs,
3385         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
3386         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3387         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
3388         .main_clk       = "uart2_fck",
3389         .prcm = {
3390                 .omap4 = {
3391                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
3392                 },
3393         },
3394         .slaves         = omap44xx_uart2_slaves,
3395         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
3396         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3397 };
3398
3399 /* uart3 */
3400 static struct omap_hwmod omap44xx_uart3_hwmod;
3401 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3402         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3403 };
3404
3405 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3406         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3407         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3408 };
3409
3410 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
3411         {
3412                 .pa_start       = 0x48020000,
3413                 .pa_end         = 0x480200ff,
3414                 .flags          = ADDR_TYPE_RT
3415         },
3416 };
3417
3418 /* l4_per -> uart3 */
3419 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
3420         .master         = &omap44xx_l4_per_hwmod,
3421         .slave          = &omap44xx_uart3_hwmod,
3422         .clk            = "l4_div_ck",
3423         .addr           = omap44xx_uart3_addrs,
3424         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
3425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3426 };
3427
3428 /* uart3 slave ports */
3429 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
3430         &omap44xx_l4_per__uart3,
3431 };
3432
3433 static struct omap_hwmod omap44xx_uart3_hwmod = {
3434         .name           = "uart3",
3435         .class          = &omap44xx_uart_hwmod_class,
3436         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3437         .mpu_irqs       = omap44xx_uart3_irqs,
3438         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
3439         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3440         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
3441         .main_clk       = "uart3_fck",
3442         .prcm = {
3443                 .omap4 = {
3444                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
3445                 },
3446         },
3447         .slaves         = omap44xx_uart3_slaves,
3448         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
3449         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3450 };
3451
3452 /* uart4 */
3453 static struct omap_hwmod omap44xx_uart4_hwmod;
3454 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3455         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3456 };
3457
3458 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3459         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3460         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3461 };
3462
3463 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
3464         {
3465                 .pa_start       = 0x4806e000,
3466                 .pa_end         = 0x4806e0ff,
3467                 .flags          = ADDR_TYPE_RT
3468         },
3469 };
3470
3471 /* l4_per -> uart4 */
3472 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
3473         .master         = &omap44xx_l4_per_hwmod,
3474         .slave          = &omap44xx_uart4_hwmod,
3475         .clk            = "l4_div_ck",
3476         .addr           = omap44xx_uart4_addrs,
3477         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
3478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3479 };
3480
3481 /* uart4 slave ports */
3482 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
3483         &omap44xx_l4_per__uart4,
3484 };
3485
3486 static struct omap_hwmod omap44xx_uart4_hwmod = {
3487         .name           = "uart4",
3488         .class          = &omap44xx_uart_hwmod_class,
3489         .mpu_irqs       = omap44xx_uart4_irqs,
3490         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
3491         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3492         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
3493         .main_clk       = "uart4_fck",
3494         .prcm = {
3495                 .omap4 = {
3496                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
3497                 },
3498         },
3499         .slaves         = omap44xx_uart4_slaves,
3500         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
3501         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3502 };
3503
3504 /*
3505  * 'wd_timer' class
3506  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3507  * overflow condition
3508  */
3509
3510 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3511         .rev_offs       = 0x0000,
3512         .sysc_offs      = 0x0010,
3513         .syss_offs      = 0x0014,
3514         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3515                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3516         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3517                            SIDLE_SMART_WKUP),
3518         .sysc_fields    = &omap_hwmod_sysc_type1,
3519 };
3520
3521 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3522         .name           = "wd_timer",
3523         .sysc           = &omap44xx_wd_timer_sysc,
3524         .pre_shutdown   = &omap2_wd_timer_disable,
3525 };
3526
3527 /* wd_timer2 */
3528 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
3529 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3530         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3531 };
3532
3533 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
3534         {
3535                 .pa_start       = 0x4a314000,
3536                 .pa_end         = 0x4a31407f,
3537                 .flags          = ADDR_TYPE_RT
3538         },
3539 };
3540
3541 /* l4_wkup -> wd_timer2 */
3542 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
3543         .master         = &omap44xx_l4_wkup_hwmod,
3544         .slave          = &omap44xx_wd_timer2_hwmod,
3545         .clk            = "l4_wkup_clk_mux_ck",
3546         .addr           = omap44xx_wd_timer2_addrs,
3547         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
3548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3549 };
3550
3551 /* wd_timer2 slave ports */
3552 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
3553         &omap44xx_l4_wkup__wd_timer2,
3554 };
3555
3556 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3557         .name           = "wd_timer2",
3558         .class          = &omap44xx_wd_timer_hwmod_class,
3559         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3560         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
3561         .main_clk       = "wd_timer2_fck",
3562         .prcm = {
3563                 .omap4 = {
3564                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
3565                 },
3566         },
3567         .slaves         = omap44xx_wd_timer2_slaves,
3568         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
3569         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3570 };
3571
3572 /* wd_timer3 */
3573 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
3574 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3575         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3576 };
3577
3578 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
3579         {
3580                 .pa_start       = 0x40130000,
3581                 .pa_end         = 0x4013007f,
3582                 .flags          = ADDR_TYPE_RT
3583         },
3584 };
3585
3586 /* l4_abe -> wd_timer3 */
3587 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
3588         .master         = &omap44xx_l4_abe_hwmod,
3589         .slave          = &omap44xx_wd_timer3_hwmod,
3590         .clk            = "ocp_abe_iclk",
3591         .addr           = omap44xx_wd_timer3_addrs,
3592         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
3593         .user           = OCP_USER_MPU,
3594 };
3595
3596 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
3597         {
3598                 .pa_start       = 0x49030000,
3599                 .pa_end         = 0x4903007f,
3600                 .flags          = ADDR_TYPE_RT
3601         },
3602 };
3603
3604 /* l4_abe -> wd_timer3 (dma) */
3605 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
3606         .master         = &omap44xx_l4_abe_hwmod,
3607         .slave          = &omap44xx_wd_timer3_hwmod,
3608         .clk            = "ocp_abe_iclk",
3609         .addr           = omap44xx_wd_timer3_dma_addrs,
3610         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
3611         .user           = OCP_USER_SDMA,
3612 };
3613
3614 /* wd_timer3 slave ports */
3615 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
3616         &omap44xx_l4_abe__wd_timer3,
3617         &omap44xx_l4_abe__wd_timer3_dma,
3618 };
3619
3620 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3621         .name           = "wd_timer3",
3622         .class          = &omap44xx_wd_timer_hwmod_class,
3623         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3624         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
3625         .main_clk       = "wd_timer3_fck",
3626         .prcm = {
3627                 .omap4 = {
3628                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
3629                 },
3630         },
3631         .slaves         = omap44xx_wd_timer3_slaves,
3632         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
3633         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3634 };
3635
3636 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
3637
3638         /* dmm class */
3639         &omap44xx_dmm_hwmod,
3640
3641         /* emif_fw class */
3642         &omap44xx_emif_fw_hwmod,
3643
3644         /* l3 class */
3645         &omap44xx_l3_instr_hwmod,
3646         &omap44xx_l3_main_1_hwmod,
3647         &omap44xx_l3_main_2_hwmod,
3648         &omap44xx_l3_main_3_hwmod,
3649
3650         /* l4 class */
3651         &omap44xx_l4_abe_hwmod,
3652         &omap44xx_l4_cfg_hwmod,
3653         &omap44xx_l4_per_hwmod,
3654         &omap44xx_l4_wkup_hwmod,
3655
3656         /* mpu_bus class */
3657         &omap44xx_mpu_private_hwmod,
3658
3659         /* dma class */
3660         &omap44xx_dma_system_hwmod,
3661
3662         /* dmic class */
3663         &omap44xx_dmic_hwmod,
3664
3665         /* dsp class */
3666         &omap44xx_dsp_hwmod,
3667         &omap44xx_dsp_c0_hwmod,
3668
3669         /* dss class */
3670         &omap44xx_dss_hwmod,
3671         &omap44xx_dss_dispc_hwmod,
3672         &omap44xx_dss_dsi1_hwmod,
3673         &omap44xx_dss_dsi2_hwmod,
3674         &omap44xx_dss_hdmi_hwmod,
3675         &omap44xx_dss_rfbi_hwmod,
3676         &omap44xx_dss_venc_hwmod,
3677
3678         /* gpio class */
3679         &omap44xx_gpio1_hwmod,
3680         &omap44xx_gpio2_hwmod,
3681         &omap44xx_gpio3_hwmod,
3682         &omap44xx_gpio4_hwmod,
3683         &omap44xx_gpio5_hwmod,
3684         &omap44xx_gpio6_hwmod,
3685
3686         /* i2c class */
3687         &omap44xx_i2c1_hwmod,
3688         &omap44xx_i2c2_hwmod,
3689         &omap44xx_i2c3_hwmod,
3690         &omap44xx_i2c4_hwmod,
3691
3692         /* iva class */
3693         &omap44xx_iva_hwmod,
3694         &omap44xx_iva_seq0_hwmod,
3695         &omap44xx_iva_seq1_hwmod,
3696
3697         /* mailbox class */
3698         &omap44xx_mailbox_hwmod,
3699
3700         /* mcspi class */
3701         &omap44xx_mcspi1_hwmod,
3702         &omap44xx_mcspi2_hwmod,
3703         &omap44xx_mcspi3_hwmod,
3704         &omap44xx_mcspi4_hwmod,
3705
3706         /* mpu class */
3707         &omap44xx_mpu_hwmod,
3708
3709         /* smartreflex class */
3710         &omap44xx_smartreflex_core_hwmod,
3711         &omap44xx_smartreflex_iva_hwmod,
3712         &omap44xx_smartreflex_mpu_hwmod,
3713
3714         /* spinlock class */
3715         &omap44xx_spinlock_hwmod,
3716
3717         /* timer class */
3718         &omap44xx_timer1_hwmod,
3719         &omap44xx_timer2_hwmod,
3720         &omap44xx_timer3_hwmod,
3721         &omap44xx_timer4_hwmod,
3722         &omap44xx_timer5_hwmod,
3723         &omap44xx_timer6_hwmod,
3724         &omap44xx_timer7_hwmod,
3725         &omap44xx_timer8_hwmod,
3726         &omap44xx_timer9_hwmod,
3727         &omap44xx_timer10_hwmod,
3728         &omap44xx_timer11_hwmod,
3729
3730         /* uart class */
3731         &omap44xx_uart1_hwmod,
3732         &omap44xx_uart2_hwmod,
3733         &omap44xx_uart3_hwmod,
3734         &omap44xx_uart4_hwmod,
3735
3736         /* wd_timer class */
3737         &omap44xx_wd_timer2_hwmod,
3738         &omap44xx_wd_timer3_hwmod,
3739
3740         NULL,
3741 };
3742
3743 int __init omap44xx_hwmod_init(void)
3744 {
3745         return omap_hwmod_init(omap44xx_hwmods);
3746 }
3747