arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm1_44xx.h"
  31 #include "cm2_44xx.h"
  32 #include "prm44xx.h"
  33 #include "prm-regbits-44xx.h"
  34 #include "wd_timer.h"
  35
  36 /* Base offset for all OMAP4 interrupts external to MPUSS */
  37 #define OMAP44XX_IRQ_GIC_START  32
  38
  39 /* Base offset for all OMAP4 dma requests */
  40 #define OMAP44XX_DMA_REQ_START  1
  41
  42 /* Backward references (IPs with Bus Master capability) */
  43 static struct omap_hwmod omap44xx_dma_system_hwmod;
  44 static struct omap_hwmod omap44xx_dmm_hwmod;
  45 static struct omap_hwmod omap44xx_dsp_hwmod;
  46 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  47 static struct omap_hwmod omap44xx_iva_hwmod;
  48 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  49 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  50 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  51 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  52 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  53 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  54 static struct omap_hwmod omap44xx_l4_per_hwmod;
  55 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  56 static struct omap_hwmod omap44xx_mpu_hwmod;
  57 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  58
  59 /*
  60  * Interconnects omap_hwmod structures
  61  * hwmods that compose the global OMAP interconnect
  62  */
  63
  64 /*
  65  * 'dmm' class
  66  * instance(s): dmm
  67  */
  68 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  69         .name = "dmm",
  70 };
  71
  72 /* dmm interface data */
  73 /* l3_main_1 -> dmm */
  74 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  75         .master         = &omap44xx_l3_main_1_hwmod,
  76         .slave          = &omap44xx_dmm_hwmod,
  77         .clk            = "l3_div_ck",
  78         .user           = OCP_USER_SDMA,
  79 };
  80
  81 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  82         {
  83                 .pa_start       = 0x4e000000,
  84                 .pa_end         = 0x4e0007ff,
  85                 .flags          = ADDR_TYPE_RT
  86         },
  87 };
  88
  89 /* mpu -> dmm */
  90 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  91         .master         = &omap44xx_mpu_hwmod,
  92         .slave          = &omap44xx_dmm_hwmod,
  93         .clk            = "l3_div_ck",
  94         .addr           = omap44xx_dmm_addrs,
  95         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
  96         .user           = OCP_USER_MPU,
  97 };
  98
  99 /* dmm slave ports */
 100 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 101         &omap44xx_l3_main_1__dmm,
 102         &omap44xx_mpu__dmm,
 103 };
 104
 105 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 106         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 107 };
 108
 109 static struct omap_hwmod omap44xx_dmm_hwmod = {
 110         .name           = "dmm",
 111         .class          = &omap44xx_dmm_hwmod_class,
 112         .slaves         = omap44xx_dmm_slaves,
 113         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 114         .mpu_irqs       = omap44xx_dmm_irqs,
 115         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 116         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 117 };
 118
 119 /*
 120  * 'emif_fw' class
 121  * instance(s): emif_fw
 122  */
 123 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 124         .name = "emif_fw",
 125 };
 126
 127 /* emif_fw interface data */
 128 /* dmm -> emif_fw */
 129 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 130         .master         = &omap44xx_dmm_hwmod,
 131         .slave          = &omap44xx_emif_fw_hwmod,
 132         .clk            = "l3_div_ck",
 133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 134 };
 135
 136 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 137         {
 138                 .pa_start       = 0x4a20c000,
 139                 .pa_end         = 0x4a20c0ff,
 140                 .flags          = ADDR_TYPE_RT
 141         },
 142 };
 143
 144 /* l4_cfg -> emif_fw */
 145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 146         .master         = &omap44xx_l4_cfg_hwmod,
 147         .slave          = &omap44xx_emif_fw_hwmod,
 148         .clk            = "l4_div_ck",
 149         .addr           = omap44xx_emif_fw_addrs,
 150         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 151         .user           = OCP_USER_MPU,
 152 };
 153
 154 /* emif_fw slave ports */
 155 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 156         &omap44xx_dmm__emif_fw,
 157         &omap44xx_l4_cfg__emif_fw,
 158 };
 159
 160 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 161         .name           = "emif_fw",
 162         .class          = &omap44xx_emif_fw_hwmod_class,
 163         .slaves         = omap44xx_emif_fw_slaves,
 164         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 165         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 166 };
 167
 168 /*
 169  * 'l3' class
 170  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 171  */
 172 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 173         .name = "l3",
 174 };
 175
 176 /* l3_instr interface data */
 177 /* iva -> l3_instr */
 178 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 179         .master         = &omap44xx_iva_hwmod,
 180         .slave          = &omap44xx_l3_instr_hwmod,
 181         .clk            = "l3_div_ck",
 182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 183 };
 184
 185 /* l3_main_3 -> l3_instr */
 186 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 187         .master         = &omap44xx_l3_main_3_hwmod,
 188         .slave          = &omap44xx_l3_instr_hwmod,
 189         .clk            = "l3_div_ck",
 190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 191 };
 192
 193 /* l3_instr slave ports */
 194 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 195         &omap44xx_iva__l3_instr,
 196         &omap44xx_l3_main_3__l3_instr,
 197 };
 198
 199 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 200         .name           = "l3_instr",
 201         .class          = &omap44xx_l3_hwmod_class,
 202         .slaves         = omap44xx_l3_instr_slaves,
 203         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 204         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 205 };
 206
 207 /* l3_main_1 interface data */
 208 /* dsp -> l3_main_1 */
 209 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 210         .master         = &omap44xx_dsp_hwmod,
 211         .slave          = &omap44xx_l3_main_1_hwmod,
 212         .clk            = "l3_div_ck",
 213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 214 };
 215
 216 /* l3_main_2 -> l3_main_1 */
 217 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 218         .master         = &omap44xx_l3_main_2_hwmod,
 219         .slave          = &omap44xx_l3_main_1_hwmod,
 220         .clk            = "l3_div_ck",
 221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 222 };
 223
 224 /* l4_cfg -> l3_main_1 */
 225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 226         .master         = &omap44xx_l4_cfg_hwmod,
 227         .slave          = &omap44xx_l3_main_1_hwmod,
 228         .clk            = "l4_div_ck",
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* mpu -> l3_main_1 */
 233 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 234         .master         = &omap44xx_mpu_hwmod,
 235         .slave          = &omap44xx_l3_main_1_hwmod,
 236         .clk            = "l3_div_ck",
 237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 238 };
 239
 240 /* l3_main_1 slave ports */
 241 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 242         &omap44xx_dsp__l3_main_1,
 243         &omap44xx_l3_main_2__l3_main_1,
 244         &omap44xx_l4_cfg__l3_main_1,
 245         &omap44xx_mpu__l3_main_1,
 246 };
 247
 248 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 249         .name           = "l3_main_1",
 250         .class          = &omap44xx_l3_hwmod_class,
 251         .slaves         = omap44xx_l3_main_1_slaves,
 252         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 253         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 254 };
 255
 256 /* l3_main_2 interface data */
 257 /* iva -> l3_main_2 */
 258 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 259         .master         = &omap44xx_iva_hwmod,
 260         .slave          = &omap44xx_l3_main_2_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* l3_main_1 -> l3_main_2 */
 266 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 267         .master         = &omap44xx_l3_main_1_hwmod,
 268         .slave          = &omap44xx_l3_main_2_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 /* dma_system -> l3_main_2 */
 274 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 275         .master         = &omap44xx_dma_system_hwmod,
 276         .slave          = &omap44xx_l3_main_2_hwmod,
 277         .clk            = "l3_div_ck",
 278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 279 };
 280
 281 /* l4_cfg -> l3_main_2 */
 282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 283         .master         = &omap44xx_l4_cfg_hwmod,
 284         .slave          = &omap44xx_l3_main_2_hwmod,
 285         .clk            = "l4_div_ck",
 286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 287 };
 288
 289 /* l3_main_2 slave ports */
 290 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 291         &omap44xx_dma_system__l3_main_2,
 292         &omap44xx_iva__l3_main_2,
 293         &omap44xx_l3_main_1__l3_main_2,
 294         &omap44xx_l4_cfg__l3_main_2,
 295 };
 296
 297 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 298         .name           = "l3_main_2",
 299         .class          = &omap44xx_l3_hwmod_class,
 300         .slaves         = omap44xx_l3_main_2_slaves,
 301         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 302         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 303 };
 304
 305 /* l3_main_3 interface data */
 306 /* l3_main_1 -> l3_main_3 */
 307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 308         .master         = &omap44xx_l3_main_1_hwmod,
 309         .slave          = &omap44xx_l3_main_3_hwmod,
 310         .clk            = "l3_div_ck",
 311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 312 };
 313
 314 /* l3_main_2 -> l3_main_3 */
 315 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 316         .master         = &omap44xx_l3_main_2_hwmod,
 317         .slave          = &omap44xx_l3_main_3_hwmod,
 318         .clk            = "l3_div_ck",
 319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 320 };
 321
 322 /* l4_cfg -> l3_main_3 */
 323 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 324         .master         = &omap44xx_l4_cfg_hwmod,
 325         .slave          = &omap44xx_l3_main_3_hwmod,
 326         .clk            = "l4_div_ck",
 327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 328 };
 329
 330 /* l3_main_3 slave ports */
 331 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 332         &omap44xx_l3_main_1__l3_main_3,
 333         &omap44xx_l3_main_2__l3_main_3,
 334         &omap44xx_l4_cfg__l3_main_3,
 335 };
 336
 337 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 338         .name           = "l3_main_3",
 339         .class          = &omap44xx_l3_hwmod_class,
 340         .slaves         = omap44xx_l3_main_3_slaves,
 341         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 342         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 343 };
 344
 345 /*
 346  * 'l4' class
 347  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 348  */
 349 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 350         .name = "l4",
 351 };
 352
 353 /* l4_abe interface data */
 354 /* dsp -> l4_abe */
 355 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 356         .master         = &omap44xx_dsp_hwmod,
 357         .slave          = &omap44xx_l4_abe_hwmod,
 358         .clk            = "ocp_abe_iclk",
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 /* l3_main_1 -> l4_abe */
 363 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 364         .master         = &omap44xx_l3_main_1_hwmod,
 365         .slave          = &omap44xx_l4_abe_hwmod,
 366         .clk            = "l3_div_ck",
 367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 368 };
 369
 370 /* mpu -> l4_abe */
 371 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 372         .master         = &omap44xx_mpu_hwmod,
 373         .slave          = &omap44xx_l4_abe_hwmod,
 374         .clk            = "ocp_abe_iclk",
 375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 376 };
 377
 378 /* l4_abe slave ports */
 379 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 380         &omap44xx_dsp__l4_abe,
 381         &omap44xx_l3_main_1__l4_abe,
 382         &omap44xx_mpu__l4_abe,
 383 };
 384
 385 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 386         .name           = "l4_abe",
 387         .class          = &omap44xx_l4_hwmod_class,
 388         .slaves         = omap44xx_l4_abe_slaves,
 389         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 390         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 391 };
 392
 393 /* l4_cfg interface data */
 394 /* l3_main_1 -> l4_cfg */
 395 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 396         .master         = &omap44xx_l3_main_1_hwmod,
 397         .slave          = &omap44xx_l4_cfg_hwmod,
 398         .clk            = "l3_div_ck",
 399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 400 };
 401
 402 /* l4_cfg slave ports */
 403 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 404         &omap44xx_l3_main_1__l4_cfg,
 405 };
 406
 407 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 408         .name           = "l4_cfg",
 409         .class          = &omap44xx_l4_hwmod_class,
 410         .slaves         = omap44xx_l4_cfg_slaves,
 411         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 413 };
 414
 415 /* l4_per interface data */
 416 /* l3_main_2 -> l4_per */
 417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 418         .master         = &omap44xx_l3_main_2_hwmod,
 419         .slave          = &omap44xx_l4_per_hwmod,
 420         .clk            = "l3_div_ck",
 421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 422 };
 423
 424 /* l4_per slave ports */
 425 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 426         &omap44xx_l3_main_2__l4_per,
 427 };
 428
 429 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 430         .name           = "l4_per",
 431         .class          = &omap44xx_l4_hwmod_class,
 432         .slaves         = omap44xx_l4_per_slaves,
 433         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 435 };
 436
 437 /* l4_wkup interface data */
 438 /* l4_cfg -> l4_wkup */
 439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 440         .master         = &omap44xx_l4_cfg_hwmod,
 441         .slave          = &omap44xx_l4_wkup_hwmod,
 442         .clk            = "l4_div_ck",
 443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 444 };
 445
 446 /* l4_wkup slave ports */
 447 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 448         &omap44xx_l4_cfg__l4_wkup,
 449 };
 450
 451 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 452         .name           = "l4_wkup",
 453         .class          = &omap44xx_l4_hwmod_class,
 454         .slaves         = omap44xx_l4_wkup_slaves,
 455         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 456         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 457 };
 458
 459 /*
 460  * 'mpu_bus' class
 461  * instance(s): mpu_private
 462  */
 463 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 464         .name = "mpu_bus",
 465 };
 466
 467 /* mpu_private interface data */
 468 /* mpu -> mpu_private */
 469 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 470         .master         = &omap44xx_mpu_hwmod,
 471         .slave          = &omap44xx_mpu_private_hwmod,
 472         .clk            = "l3_div_ck",
 473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 474 };
 475
 476 /* mpu_private slave ports */
 477 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 478         &omap44xx_mpu__mpu_private,
 479 };
 480
 481 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 482         .name           = "mpu_private",
 483         .class          = &omap44xx_mpu_bus_hwmod_class,
 484         .slaves         = omap44xx_mpu_private_slaves,
 485         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 486         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 487 };
 488
 489 /*
 490  * Modules omap_hwmod structures
 491  *
 492  * The following IPs are excluded for the moment because:
 493  * - They do not need an explicit SW control using omap_hwmod API.
 494  * - They still need to be validated with the driver
 495  *   properly adapted to omap_hwmod / omap_device
 496  *
 497  *  aess
 498  *  bandgap
 499  *  c2c
 500  *  c2c_target_fw
 501  *  cm_core
 502  *  cm_core_aon
 503  *  counter_32k
 504  *  ctrl_module_core
 505  *  ctrl_module_pad_core
 506  *  ctrl_module_pad_wkup
 507  *  ctrl_module_wkup
 508  *  debugss
 509  *  dma_system
 510  *  dmic
 511  *  dss
 512  *  dss_dispc
 513  *  dss_dsi1
 514  *  dss_dsi2
 515  *  dss_hdmi
 516  *  dss_rfbi
 517  *  dss_venc
 518  *  efuse_ctrl_cust
 519  *  efuse_ctrl_std
 520  *  elm
 521  *  emif1
 522  *  emif2
 523  *  fdif
 524  *  gpmc
 525  *  gpu
 526  *  hdq1w
 527  *  hsi
 528  *  ipu
 529  *  iss
 530  *  kbd
 531  *  mailbox
 532  *  mcasp
 533  *  mcbsp1
 534  *  mcbsp2
 535  *  mcbsp3
 536  *  mcbsp4
 537  *  mcpdm
 538  *  mcspi1
 539  *  mcspi2
 540  *  mcspi3
 541  *  mcspi4
 542  *  mmc1
 543  *  mmc2
 544  *  mmc3
 545  *  mmc4
 546  *  mmc5
 547  *  mpu_c0
 548  *  mpu_c1
 549  *  ocmc_ram
 550  *  ocp2scp_usb_phy
 551  *  ocp_wp_noc
 552  *  prcm
 553  *  prcm_mpu
 554  *  prm
 555  *  scrm
 556  *  sl2if
 557  *  slimbus1
 558  *  slimbus2
 559  *  smartreflex_core
 560  *  smartreflex_iva
 561  *  smartreflex_mpu
 562  *  spinlock
 563  *  timer1
 564  *  timer10
 565  *  timer11
 566  *  timer2
 567  *  timer3
 568  *  timer4
 569  *  timer5
 570  *  timer6
 571  *  timer7
 572  *  timer8
 573  *  timer9
 574  *  usb_host_fs
 575  *  usb_host_hs
 576  *  usb_otg_hs
 577  *  usb_phy_cm
 578  *  usb_tll_hs
 579  *  usim
 580  */
 581
 582 /*
 583  * 'dsp' class
 584  * dsp sub-system
 585  */
 586
 587 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 588         .name = "dsp",
 589 };
 590
 591 /* dsp */
 592 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 593         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 594 };
 595
 596 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 597         { .name = "mmu_cache", .rst_shift = 1 },
 598 };
 599
 600 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 601         { .name = "dsp", .rst_shift = 0 },
 602 };
 603
 604 /* dsp -> iva */
 605 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 606         .master         = &omap44xx_dsp_hwmod,
 607         .slave          = &omap44xx_iva_hwmod,
 608         .clk            = "dpll_iva_m5x2_ck",
 609 };
 610
 611 /* dsp master ports */
 612 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
 613         &omap44xx_dsp__l3_main_1,
 614         &omap44xx_dsp__l4_abe,
 615         &omap44xx_dsp__iva,
 616 };
 617
 618 /* l4_cfg -> dsp */
 619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
 620         .master         = &omap44xx_l4_cfg_hwmod,
 621         .slave          = &omap44xx_dsp_hwmod,
 622         .clk            = "l4_div_ck",
 623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 624 };
 625
 626 /* dsp slave ports */
 627 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
 628         &omap44xx_l4_cfg__dsp,
 629 };
 630
 631 /* Pseudo hwmod for reset control purpose only */
 632 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
 633         .name           = "dsp_c0",
 634         .class          = &omap44xx_dsp_hwmod_class,
 635         .flags          = HWMOD_INIT_NO_RESET,
 636         .rst_lines      = omap44xx_dsp_c0_resets,
 637         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
 638         .prcm = {
 639                 .omap4 = {
 640                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 641                 },
 642         },
 643         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 644 };
 645
 646 static struct omap_hwmod omap44xx_dsp_hwmod = {
 647         .name           = "dsp",
 648         .class          = &omap44xx_dsp_hwmod_class,
 649         .mpu_irqs       = omap44xx_dsp_irqs,
 650         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
 651         .rst_lines      = omap44xx_dsp_resets,
 652         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 653         .main_clk       = "dsp_fck",
 654         .prcm = {
 655                 .omap4 = {
 656                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 657                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 658                 },
 659         },
 660         .slaves         = omap44xx_dsp_slaves,
 661         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
 662         .masters        = omap44xx_dsp_masters,
 663         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
 664         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 665 };
 666
 667 /*
 668  * 'gpio' class
 669  * general purpose io module
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
 673         .rev_offs       = 0x0000,
 674         .sysc_offs      = 0x0010,
 675         .syss_offs      = 0x0114,
 676         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 677                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 678                            SYSS_HAS_RESET_STATUS),
 679         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 680         .sysc_fields    = &omap_hwmod_sysc_type1,
 681 };
 682
 683 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
 684         .name = "gpio",
 685         .sysc = &omap44xx_gpio_sysc,
 686         .rev = 2,
 687 };
 688
 689 /* gpio dev_attr */
 690 static struct omap_gpio_dev_attr gpio_dev_attr = {
 691         .bank_width = 32,
 692         .dbck_flag = true,
 693 };
 694
 695 /* gpio1 */
 696 static struct omap_hwmod omap44xx_gpio1_hwmod;
 697 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
 698         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
 699 };
 700
 701 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
 702         {
 703                 .pa_start       = 0x4a310000,
 704                 .pa_end         = 0x4a3101ff,
 705                 .flags          = ADDR_TYPE_RT
 706         },
 707 };
 708
 709 /* l4_wkup -> gpio1 */
 710 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
 711         .master         = &omap44xx_l4_wkup_hwmod,
 712         .slave          = &omap44xx_gpio1_hwmod,
 713         .addr           = omap44xx_gpio1_addrs,
 714         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
 715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 716 };
 717
 718 /* gpio1 slave ports */
 719 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
 720         &omap44xx_l4_wkup__gpio1,
 721 };
 722
 723 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 724         { .role = "dbclk", .clk = "sys_32k_ck" },
 725 };
 726
 727 static struct omap_hwmod omap44xx_gpio1_hwmod = {
 728         .name           = "gpio1",
 729         .class          = &omap44xx_gpio_hwmod_class,
 730         .mpu_irqs       = omap44xx_gpio1_irqs,
 731         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
 732         .main_clk       = "gpio1_ick",
 733         .prcm = {
 734                 .omap4 = {
 735                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
 736                 },
 737         },
 738         .opt_clks       = gpio1_opt_clks,
 739         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 740         .dev_attr       = &gpio_dev_attr,
 741         .slaves         = omap44xx_gpio1_slaves,
 742         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
 743         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 744 };
 745
 746 /* gpio2 */
 747 static struct omap_hwmod omap44xx_gpio2_hwmod;
 748 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
 749         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
 750 };
 751
 752 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
 753         {
 754                 .pa_start       = 0x48055000,
 755                 .pa_end         = 0x480551ff,
 756                 .flags          = ADDR_TYPE_RT
 757         },
 758 };
 759
 760 /* l4_per -> gpio2 */
 761 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
 762         .master         = &omap44xx_l4_per_hwmod,
 763         .slave          = &omap44xx_gpio2_hwmod,
 764         .addr           = omap44xx_gpio2_addrs,
 765         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
 766         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 767 };
 768
 769 /* gpio2 slave ports */
 770 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
 771         &omap44xx_l4_per__gpio2,
 772 };
 773
 774 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 775         { .role = "dbclk", .clk = "sys_32k_ck" },
 776 };
 777
 778 static struct omap_hwmod omap44xx_gpio2_hwmod = {
 779         .name           = "gpio2",
 780         .class          = &omap44xx_gpio_hwmod_class,
 781         .mpu_irqs       = omap44xx_gpio2_irqs,
 782         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
 783         .main_clk       = "gpio2_ick",
 784         .prcm = {
 785                 .omap4 = {
 786                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
 787                 },
 788         },
 789         .opt_clks       = gpio2_opt_clks,
 790         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 791         .dev_attr       = &gpio_dev_attr,
 792         .slaves         = omap44xx_gpio2_slaves,
 793         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
 794         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 795 };
 796
 797 /* gpio3 */
 798 static struct omap_hwmod omap44xx_gpio3_hwmod;
 799 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
 800         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
 801 };
 802
 803 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
 804         {
 805                 .pa_start       = 0x48057000,
 806                 .pa_end         = 0x480571ff,
 807                 .flags          = ADDR_TYPE_RT
 808         },
 809 };
 810
 811 /* l4_per -> gpio3 */
 812 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
 813         .master         = &omap44xx_l4_per_hwmod,
 814         .slave          = &omap44xx_gpio3_hwmod,
 815         .addr           = omap44xx_gpio3_addrs,
 816         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
 817         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 818 };
 819
 820 /* gpio3 slave ports */
 821 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
 822         &omap44xx_l4_per__gpio3,
 823 };
 824
 825 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 826         { .role = "dbclk", .clk = "sys_32k_ck" },
 827 };
 828
 829 static struct omap_hwmod omap44xx_gpio3_hwmod = {
 830         .name           = "gpio3",
 831         .class          = &omap44xx_gpio_hwmod_class,
 832         .mpu_irqs       = omap44xx_gpio3_irqs,
 833         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
 834         .main_clk       = "gpio3_ick",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
 838                 },
 839         },
 840         .opt_clks       = gpio3_opt_clks,
 841         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 842         .dev_attr       = &gpio_dev_attr,
 843         .slaves         = omap44xx_gpio3_slaves,
 844         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
 845         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 846 };
 847
 848 /* gpio4 */
 849 static struct omap_hwmod omap44xx_gpio4_hwmod;
 850 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
 851         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
 852 };
 853
 854 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
 855         {
 856                 .pa_start       = 0x48059000,
 857                 .pa_end         = 0x480591ff,
 858                 .flags          = ADDR_TYPE_RT
 859         },
 860 };
 861
 862 /* l4_per -> gpio4 */
 863 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
 864         .master         = &omap44xx_l4_per_hwmod,
 865         .slave          = &omap44xx_gpio4_hwmod,
 866         .addr           = omap44xx_gpio4_addrs,
 867         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
 868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 869 };
 870
 871 /* gpio4 slave ports */
 872 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
 873         &omap44xx_l4_per__gpio4,
 874 };
 875
 876 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 877         { .role = "dbclk", .clk = "sys_32k_ck" },
 878 };
 879
 880 static struct omap_hwmod omap44xx_gpio4_hwmod = {
 881         .name           = "gpio4",
 882         .class          = &omap44xx_gpio_hwmod_class,
 883         .mpu_irqs       = omap44xx_gpio4_irqs,
 884         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
 885         .main_clk       = "gpio4_ick",
 886         .prcm = {
 887                 .omap4 = {
 888                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
 889                 },
 890         },
 891         .opt_clks       = gpio4_opt_clks,
 892         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 893         .dev_attr       = &gpio_dev_attr,
 894         .slaves         = omap44xx_gpio4_slaves,
 895         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
 896         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 897 };
 898
 899 /* gpio5 */
 900 static struct omap_hwmod omap44xx_gpio5_hwmod;
 901 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
 902         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
 903 };
 904
 905 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
 906         {
 907                 .pa_start       = 0x4805b000,
 908                 .pa_end         = 0x4805b1ff,
 909                 .flags          = ADDR_TYPE_RT
 910         },
 911 };
 912
 913 /* l4_per -> gpio5 */
 914 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
 915         .master         = &omap44xx_l4_per_hwmod,
 916         .slave          = &omap44xx_gpio5_hwmod,
 917         .addr           = omap44xx_gpio5_addrs,
 918         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
 919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 920 };
 921
 922 /* gpio5 slave ports */
 923 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
 924         &omap44xx_l4_per__gpio5,
 925 };
 926
 927 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 928         { .role = "dbclk", .clk = "sys_32k_ck" },
 929 };
 930
 931 static struct omap_hwmod omap44xx_gpio5_hwmod = {
 932         .name           = "gpio5",
 933         .class          = &omap44xx_gpio_hwmod_class,
 934         .mpu_irqs       = omap44xx_gpio5_irqs,
 935         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
 936         .main_clk       = "gpio5_ick",
 937         .prcm = {
 938                 .omap4 = {
 939                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
 940                 },
 941         },
 942         .opt_clks       = gpio5_opt_clks,
 943         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 944         .dev_attr       = &gpio_dev_attr,
 945         .slaves         = omap44xx_gpio5_slaves,
 946         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
 947         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 948 };
 949
 950 /* gpio6 */
 951 static struct omap_hwmod omap44xx_gpio6_hwmod;
 952 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
 953         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
 954 };
 955
 956 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
 957         {
 958                 .pa_start       = 0x4805d000,
 959                 .pa_end         = 0x4805d1ff,
 960                 .flags          = ADDR_TYPE_RT
 961         },
 962 };
 963
 964 /* l4_per -> gpio6 */
 965 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
 966         .master         = &omap44xx_l4_per_hwmod,
 967         .slave          = &omap44xx_gpio6_hwmod,
 968         .addr           = omap44xx_gpio6_addrs,
 969         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
 970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 971 };
 972
 973 /* gpio6 slave ports */
 974 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
 975         &omap44xx_l4_per__gpio6,
 976 };
 977
 978 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 979         { .role = "dbclk", .clk = "sys_32k_ck" },
 980 };
 981
 982 static struct omap_hwmod omap44xx_gpio6_hwmod = {
 983         .name           = "gpio6",
 984         .class          = &omap44xx_gpio_hwmod_class,
 985         .mpu_irqs       = omap44xx_gpio6_irqs,
 986         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
 987         .main_clk       = "gpio6_ick",
 988         .prcm = {
 989                 .omap4 = {
 990                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
 991                 },
 992         },
 993         .opt_clks       = gpio6_opt_clks,
 994         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 995         .dev_attr       = &gpio_dev_attr,
 996         .slaves         = omap44xx_gpio6_slaves,
 997         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
 998         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 999 };
1000
1001 /*
1002  * 'i2c' class
1003  * multimaster high-speed i2c controller
1004  */
1005
1006 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1007         .sysc_offs      = 0x0010,
1008         .syss_offs      = 0x0090,
1009         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1010                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1011                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1012         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1013         .sysc_fields    = &omap_hwmod_sysc_type1,
1014 };
1015
1016 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1017         .name = "i2c",
1018         .sysc = &omap44xx_i2c_sysc,
1019 };
1020
1021 /* i2c1 */
1022 static struct omap_hwmod omap44xx_i2c1_hwmod;
1023 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1024         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1025 };
1026
1027 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1028         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1029         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1030 };
1031
1032 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1033         {
1034                 .pa_start       = 0x48070000,
1035                 .pa_end         = 0x480700ff,
1036                 .flags          = ADDR_TYPE_RT
1037         },
1038 };
1039
1040 /* l4_per -> i2c1 */
1041 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1042         .master         = &omap44xx_l4_per_hwmod,
1043         .slave          = &omap44xx_i2c1_hwmod,
1044         .clk            = "l4_div_ck",
1045         .addr           = omap44xx_i2c1_addrs,
1046         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
1047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1048 };
1049
1050 /* i2c1 slave ports */
1051 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1052         &omap44xx_l4_per__i2c1,
1053 };
1054
1055 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1056         .name           = "i2c1",
1057         .class          = &omap44xx_i2c_hwmod_class,
1058         .flags          = HWMOD_INIT_NO_RESET,
1059         .mpu_irqs       = omap44xx_i2c1_irqs,
1060         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
1061         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1062         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1063         .main_clk       = "i2c1_fck",
1064         .prcm = {
1065                 .omap4 = {
1066                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1067                 },
1068         },
1069         .slaves         = omap44xx_i2c1_slaves,
1070         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
1071         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1072 };
1073
1074 /* i2c2 */
1075 static struct omap_hwmod omap44xx_i2c2_hwmod;
1076 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1077         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1078 };
1079
1080 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1081         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1082         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1083 };
1084
1085 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1086         {
1087                 .pa_start       = 0x48072000,
1088                 .pa_end         = 0x480720ff,
1089                 .flags          = ADDR_TYPE_RT
1090         },
1091 };
1092
1093 /* l4_per -> i2c2 */
1094 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1095         .master         = &omap44xx_l4_per_hwmod,
1096         .slave          = &omap44xx_i2c2_hwmod,
1097         .clk            = "l4_div_ck",
1098         .addr           = omap44xx_i2c2_addrs,
1099         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
1100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1101 };
1102
1103 /* i2c2 slave ports */
1104 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1105         &omap44xx_l4_per__i2c2,
1106 };
1107
1108 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1109         .name           = "i2c2",
1110         .class          = &omap44xx_i2c_hwmod_class,
1111         .flags          = HWMOD_INIT_NO_RESET,
1112         .mpu_irqs       = omap44xx_i2c2_irqs,
1113         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
1114         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1115         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1116         .main_clk       = "i2c2_fck",
1117         .prcm = {
1118                 .omap4 = {
1119                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1120                 },
1121         },
1122         .slaves         = omap44xx_i2c2_slaves,
1123         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
1124         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1125 };
1126
1127 /* i2c3 */
1128 static struct omap_hwmod omap44xx_i2c3_hwmod;
1129 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1130         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1131 };
1132
1133 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1134         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1135         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1136 };
1137
1138 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1139         {
1140                 .pa_start       = 0x48060000,
1141                 .pa_end         = 0x480600ff,
1142                 .flags          = ADDR_TYPE_RT
1143         },
1144 };
1145
1146 /* l4_per -> i2c3 */
1147 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
1148         .master         = &omap44xx_l4_per_hwmod,
1149         .slave          = &omap44xx_i2c3_hwmod,
1150         .clk            = "l4_div_ck",
1151         .addr           = omap44xx_i2c3_addrs,
1152         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
1153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1154 };
1155
1156 /* i2c3 slave ports */
1157 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1158         &omap44xx_l4_per__i2c3,
1159 };
1160
1161 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1162         .name           = "i2c3",
1163         .class          = &omap44xx_i2c_hwmod_class,
1164         .flags          = HWMOD_INIT_NO_RESET,
1165         .mpu_irqs       = omap44xx_i2c3_irqs,
1166         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
1167         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1168         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1169         .main_clk       = "i2c3_fck",
1170         .prcm = {
1171                 .omap4 = {
1172                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1173                 },
1174         },
1175         .slaves         = omap44xx_i2c3_slaves,
1176         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
1177         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1178 };
1179
1180 /* i2c4 */
1181 static struct omap_hwmod omap44xx_i2c4_hwmod;
1182 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1183         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1184 };
1185
1186 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1187         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1188         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1189 };
1190
1191 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
1192         {
1193                 .pa_start       = 0x48350000,
1194                 .pa_end         = 0x483500ff,
1195                 .flags          = ADDR_TYPE_RT
1196         },
1197 };
1198
1199 /* l4_per -> i2c4 */
1200 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1201         .master         = &omap44xx_l4_per_hwmod,
1202         .slave          = &omap44xx_i2c4_hwmod,
1203         .clk            = "l4_div_ck",
1204         .addr           = omap44xx_i2c4_addrs,
1205         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
1206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1207 };
1208
1209 /* i2c4 slave ports */
1210 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1211         &omap44xx_l4_per__i2c4,
1212 };
1213
1214 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1215         .name           = "i2c4",
1216         .class          = &omap44xx_i2c_hwmod_class,
1217         .flags          = HWMOD_INIT_NO_RESET,
1218         .mpu_irqs       = omap44xx_i2c4_irqs,
1219         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
1220         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1221         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1222         .main_clk       = "i2c4_fck",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1226                 },
1227         },
1228         .slaves         = omap44xx_i2c4_slaves,
1229         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
1230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1231 };
1232
1233 /*
1234  * 'iva' class
1235  * multi-standard video encoder/decoder hardware accelerator
1236  */
1237
1238 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1239         .name = "iva",
1240 };
1241
1242 /* iva */
1243 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1244         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1245         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1246         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1247 };
1248
1249 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1250         { .name = "logic", .rst_shift = 2 },
1251 };
1252
1253 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1254         { .name = "seq0", .rst_shift = 0 },
1255 };
1256
1257 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1258         { .name = "seq1", .rst_shift = 1 },
1259 };
1260
1261 /* iva master ports */
1262 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1263         &omap44xx_iva__l3_main_2,
1264         &omap44xx_iva__l3_instr,
1265 };
1266
1267 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1268         {
1269                 .pa_start       = 0x5a000000,
1270                 .pa_end         = 0x5a07ffff,
1271                 .flags          = ADDR_TYPE_RT
1272         },
1273 };
1274
1275 /* l3_main_2 -> iva */
1276 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1277         .master         = &omap44xx_l3_main_2_hwmod,
1278         .slave          = &omap44xx_iva_hwmod,
1279         .clk            = "l3_div_ck",
1280         .addr           = omap44xx_iva_addrs,
1281         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
1282         .user           = OCP_USER_MPU,
1283 };
1284
1285 /* iva slave ports */
1286 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1287         &omap44xx_dsp__iva,
1288         &omap44xx_l3_main_2__iva,
1289 };
1290
1291 /* Pseudo hwmod for reset control purpose only */
1292 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1293         .name           = "iva_seq0",
1294         .class          = &omap44xx_iva_hwmod_class,
1295         .flags          = HWMOD_INIT_NO_RESET,
1296         .rst_lines      = omap44xx_iva_seq0_resets,
1297         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1298         .prcm = {
1299                 .omap4 = {
1300                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1301                 },
1302         },
1303         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1304 };
1305
1306 /* Pseudo hwmod for reset control purpose only */
1307 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1308         .name           = "iva_seq1",
1309         .class          = &omap44xx_iva_hwmod_class,
1310         .flags          = HWMOD_INIT_NO_RESET,
1311         .rst_lines      = omap44xx_iva_seq1_resets,
1312         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1313         .prcm = {
1314                 .omap4 = {
1315                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1316                 },
1317         },
1318         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1319 };
1320
1321 static struct omap_hwmod omap44xx_iva_hwmod = {
1322         .name           = "iva",
1323         .class          = &omap44xx_iva_hwmod_class,
1324         .mpu_irqs       = omap44xx_iva_irqs,
1325         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
1326         .rst_lines      = omap44xx_iva_resets,
1327         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1328         .main_clk       = "iva_fck",
1329         .prcm = {
1330                 .omap4 = {
1331                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1332                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1333                 },
1334         },
1335         .slaves         = omap44xx_iva_slaves,
1336         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
1337         .masters        = omap44xx_iva_masters,
1338         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
1339         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1340 };
1341
1342 /*
1343  * 'mpu' class
1344  * mpu sub-system
1345  */
1346
1347 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1348         .name = "mpu",
1349 };
1350
1351 /* mpu */
1352 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
1353         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
1354         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
1355         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
1356 };
1357
1358 /* mpu master ports */
1359 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
1360         &omap44xx_mpu__l3_main_1,
1361         &omap44xx_mpu__l4_abe,
1362         &omap44xx_mpu__dmm,
1363 };
1364
1365 static struct omap_hwmod omap44xx_mpu_hwmod = {
1366         .name           = "mpu",
1367         .class          = &omap44xx_mpu_hwmod_class,
1368         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1369         .mpu_irqs       = omap44xx_mpu_irqs,
1370         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
1371         .main_clk       = "dpll_mpu_m2_ck",
1372         .prcm = {
1373                 .omap4 = {
1374                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
1375                 },
1376         },
1377         .masters        = omap44xx_mpu_masters,
1378         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
1379         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1380 };
1381
1382 /*
1383  * 'uart' class
1384  * universal asynchronous receiver/transmitter (uart)
1385  */
1386
1387 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
1388         .rev_offs       = 0x0050,
1389         .sysc_offs      = 0x0054,
1390         .syss_offs      = 0x0058,
1391         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1392                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1393                            SYSS_HAS_RESET_STATUS),
1394         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1395         .sysc_fields    = &omap_hwmod_sysc_type1,
1396 };
1397
1398 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
1399         .name = "uart",
1400         .sysc = &omap44xx_uart_sysc,
1401 };
1402
1403 /* uart1 */
1404 static struct omap_hwmod omap44xx_uart1_hwmod;
1405 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
1406         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
1407 };
1408
1409 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
1410         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
1411         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
1412 };
1413
1414 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
1415         {
1416                 .pa_start       = 0x4806a000,
1417                 .pa_end         = 0x4806a0ff,
1418                 .flags          = ADDR_TYPE_RT
1419         },
1420 };
1421
1422 /* l4_per -> uart1 */
1423 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
1424         .master         = &omap44xx_l4_per_hwmod,
1425         .slave          = &omap44xx_uart1_hwmod,
1426         .clk            = "l4_div_ck",
1427         .addr           = omap44xx_uart1_addrs,
1428         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
1429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1430 };
1431
1432 /* uart1 slave ports */
1433 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
1434         &omap44xx_l4_per__uart1,
1435 };
1436
1437 static struct omap_hwmod omap44xx_uart1_hwmod = {
1438         .name           = "uart1",
1439         .class          = &omap44xx_uart_hwmod_class,
1440         .mpu_irqs       = omap44xx_uart1_irqs,
1441         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
1442         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
1443         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
1444         .main_clk       = "uart1_fck",
1445         .prcm = {
1446                 .omap4 = {
1447                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
1448                 },
1449         },
1450         .slaves         = omap44xx_uart1_slaves,
1451         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
1452         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1453 };
1454
1455 /* uart2 */
1456 static struct omap_hwmod omap44xx_uart2_hwmod;
1457 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
1458         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
1459 };
1460
1461 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
1462         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
1463         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
1464 };
1465
1466 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
1467         {
1468                 .pa_start       = 0x4806c000,
1469                 .pa_end         = 0x4806c0ff,
1470                 .flags          = ADDR_TYPE_RT
1471         },
1472 };
1473
1474 /* l4_per -> uart2 */
1475 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
1476         .master         = &omap44xx_l4_per_hwmod,
1477         .slave          = &omap44xx_uart2_hwmod,
1478         .clk            = "l4_div_ck",
1479         .addr           = omap44xx_uart2_addrs,
1480         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
1481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1482 };
1483
1484 /* uart2 slave ports */
1485 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
1486         &omap44xx_l4_per__uart2,
1487 };
1488
1489 static struct omap_hwmod omap44xx_uart2_hwmod = {
1490         .name           = "uart2",
1491         .class          = &omap44xx_uart_hwmod_class,
1492         .mpu_irqs       = omap44xx_uart2_irqs,
1493         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
1494         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
1495         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
1496         .main_clk       = "uart2_fck",
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
1500                 },
1501         },
1502         .slaves         = omap44xx_uart2_slaves,
1503         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
1504         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1505 };
1506
1507 /* uart3 */
1508 static struct omap_hwmod omap44xx_uart3_hwmod;
1509 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
1510         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
1511 };
1512
1513 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
1514         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
1515         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
1516 };
1517
1518 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
1519         {
1520                 .pa_start       = 0x48020000,
1521                 .pa_end         = 0x480200ff,
1522                 .flags          = ADDR_TYPE_RT
1523         },
1524 };
1525
1526 /* l4_per -> uart3 */
1527 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
1528         .master         = &omap44xx_l4_per_hwmod,
1529         .slave          = &omap44xx_uart3_hwmod,
1530         .clk            = "l4_div_ck",
1531         .addr           = omap44xx_uart3_addrs,
1532         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
1533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1534 };
1535
1536 /* uart3 slave ports */
1537 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
1538         &omap44xx_l4_per__uart3,
1539 };
1540
1541 static struct omap_hwmod omap44xx_uart3_hwmod = {
1542         .name           = "uart3",
1543         .class          = &omap44xx_uart_hwmod_class,
1544         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1545         .mpu_irqs       = omap44xx_uart3_irqs,
1546         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
1547         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
1548         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
1549         .main_clk       = "uart3_fck",
1550         .prcm = {
1551                 .omap4 = {
1552                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
1553                 },
1554         },
1555         .slaves         = omap44xx_uart3_slaves,
1556         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
1557         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1558 };
1559
1560 /* uart4 */
1561 static struct omap_hwmod omap44xx_uart4_hwmod;
1562 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
1563         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
1564 };
1565
1566 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
1567         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
1568         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
1569 };
1570
1571 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
1572         {
1573                 .pa_start       = 0x4806e000,
1574                 .pa_end         = 0x4806e0ff,
1575                 .flags          = ADDR_TYPE_RT
1576         },
1577 };
1578
1579 /* l4_per -> uart4 */
1580 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1581         .master         = &omap44xx_l4_per_hwmod,
1582         .slave          = &omap44xx_uart4_hwmod,
1583         .clk            = "l4_div_ck",
1584         .addr           = omap44xx_uart4_addrs,
1585         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
1586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1587 };
1588
1589 /* uart4 slave ports */
1590 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1591         &omap44xx_l4_per__uart4,
1592 };
1593
1594 static struct omap_hwmod omap44xx_uart4_hwmod = {
1595         .name           = "uart4",
1596         .class          = &omap44xx_uart_hwmod_class,
1597         .mpu_irqs       = omap44xx_uart4_irqs,
1598         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
1599         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
1600         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1601         .main_clk       = "uart4_fck",
1602         .prcm = {
1603                 .omap4 = {
1604                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1605                 },
1606         },
1607         .slaves         = omap44xx_uart4_slaves,
1608         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
1609         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1610 };
1611
1612 /*
1613  * 'wd_timer' class
1614  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1615  * overflow condition
1616  */
1617
1618 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
1619         .rev_offs       = 0x0000,
1620         .sysc_offs      = 0x0010,
1621         .syss_offs      = 0x0014,
1622         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1623                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1624         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1625         .sysc_fields    = &omap_hwmod_sysc_type1,
1626 };
1627
1628 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
1629         .name           = "wd_timer",
1630         .sysc           = &omap44xx_wd_timer_sysc,
1631         .pre_shutdown   = &omap2_wd_timer_disable
1632 };
1633
1634 /* wd_timer2 */
1635 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
1636 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
1637         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
1638 };
1639
1640 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
1641         {
1642                 .pa_start       = 0x4a314000,
1643                 .pa_end         = 0x4a31407f,
1644                 .flags          = ADDR_TYPE_RT
1645         },
1646 };
1647
1648 /* l4_wkup -> wd_timer2 */
1649 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
1650         .master         = &omap44xx_l4_wkup_hwmod,
1651         .slave          = &omap44xx_wd_timer2_hwmod,
1652         .clk            = "l4_wkup_clk_mux_ck",
1653         .addr           = omap44xx_wd_timer2_addrs,
1654         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
1655         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1656 };
1657
1658 /* wd_timer2 slave ports */
1659 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
1660         &omap44xx_l4_wkup__wd_timer2,
1661 };
1662
1663 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
1664         .name           = "wd_timer2",
1665         .class          = &omap44xx_wd_timer_hwmod_class,
1666         .mpu_irqs       = omap44xx_wd_timer2_irqs,
1667         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
1668         .main_clk       = "wd_timer2_fck",
1669         .prcm = {
1670                 .omap4 = {
1671                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
1672                 },
1673         },
1674         .slaves         = omap44xx_wd_timer2_slaves,
1675         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
1676         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1677 };
1678
1679 /* wd_timer3 */
1680 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
1681 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
1682         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
1683 };
1684
1685 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
1686         {
1687                 .pa_start       = 0x40130000,
1688                 .pa_end         = 0x4013007f,
1689                 .flags          = ADDR_TYPE_RT
1690         },
1691 };
1692
1693 /* l4_abe -> wd_timer3 */
1694 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
1695         .master         = &omap44xx_l4_abe_hwmod,
1696         .slave          = &omap44xx_wd_timer3_hwmod,
1697         .clk            = "ocp_abe_iclk",
1698         .addr           = omap44xx_wd_timer3_addrs,
1699         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
1700         .user           = OCP_USER_MPU,
1701 };
1702
1703 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
1704         {
1705                 .pa_start       = 0x49030000,
1706                 .pa_end         = 0x4903007f,
1707                 .flags          = ADDR_TYPE_RT
1708         },
1709 };
1710
1711 /* l4_abe -> wd_timer3 (dma) */
1712 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
1713         .master         = &omap44xx_l4_abe_hwmod,
1714         .slave          = &omap44xx_wd_timer3_hwmod,
1715         .clk            = "ocp_abe_iclk",
1716         .addr           = omap44xx_wd_timer3_dma_addrs,
1717         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1718         .user           = OCP_USER_SDMA,
1719 };
1720
1721 /* wd_timer3 slave ports */
1722 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1723         &omap44xx_l4_abe__wd_timer3,
1724         &omap44xx_l4_abe__wd_timer3_dma,
1725 };
1726
1727 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1728         .name           = "wd_timer3",
1729         .class          = &omap44xx_wd_timer_hwmod_class,
1730         .mpu_irqs       = omap44xx_wd_timer3_irqs,
1731         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1732         .main_clk       = "wd_timer3_fck",
1733         .prcm = {
1734                 .omap4 = {
1735                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1736                 },
1737         },
1738         .slaves         = omap44xx_wd_timer3_slaves,
1739         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1740         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1741 };
1742
1743
1744 /*
1745  * 'dma' class
1746  * dma controller for data exchange between memory to memory (i.e. internal or
1747  * external memory) and gp peripherals to memory or memory to gp peripherals
1748  */
1749
1750 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
1751         .rev_offs       = 0x0000,
1752         .sysc_offs      = 0x002c,
1753         .syss_offs      = 0x0028,
1754         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1755                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1756                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1757                            SYSS_HAS_RESET_STATUS),
1758         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1759                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1760         .sysc_fields    = &omap_hwmod_sysc_type1,
1761 };
1762
1763 /* dma attributes */
1764 static struct omap_dma_dev_attr dma_dev_attr = {
1765         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1766                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1767         .lch_count = 32,
1768 };
1769
1770 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
1771         .name   = "dma",
1772         .sysc   = &omap44xx_dma_sysc,
1773 };
1774
1775 /* dma_system */
1776 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
1777         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
1778         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
1779         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
1780         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
1781 };
1782
1783 /* dma_system master ports */
1784 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
1785         &omap44xx_dma_system__l3_main_2,
1786 };
1787
1788 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
1789         {
1790                 .pa_start       = 0x4a056000,
1791                 .pa_end         = 0x4a0560ff,
1792                 .flags          = ADDR_TYPE_RT
1793         },
1794 };
1795
1796 /* l4_cfg -> dma_system */
1797 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
1798         .master         = &omap44xx_l4_cfg_hwmod,
1799         .slave          = &omap44xx_dma_system_hwmod,
1800         .clk            = "l4_div_ck",
1801         .addr           = omap44xx_dma_system_addrs,
1802         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
1803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1804 };
1805
1806 /* dma_system slave ports */
1807 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
1808         &omap44xx_l4_cfg__dma_system,
1809 };
1810
1811 static struct omap_hwmod omap44xx_dma_system_hwmod = {
1812         .name           = "dma_system",
1813         .class          = &omap44xx_dma_hwmod_class,
1814         .mpu_irqs       = omap44xx_dma_system_irqs,
1815         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
1816         .main_clk       = "l3_div_ck",
1817         .prcm = {
1818                 .omap4 = {
1819                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
1820                 },
1821         },
1822         .slaves         = omap44xx_dma_system_slaves,
1823         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
1824         .masters        = omap44xx_dma_system_masters,
1825         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
1826         .dev_attr       = &dma_dev_attr,
1827         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1828 };
1829
1830 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1831         /* dmm class */
1832         &omap44xx_dmm_hwmod,
1833
1834         /* emif_fw class */
1835         &omap44xx_emif_fw_hwmod,
1836
1837         /* l3 class */
1838         &omap44xx_l3_instr_hwmod,
1839         &omap44xx_l3_main_1_hwmod,
1840         &omap44xx_l3_main_2_hwmod,
1841         &omap44xx_l3_main_3_hwmod,
1842
1843         /* l4 class */
1844         &omap44xx_l4_abe_hwmod,
1845         &omap44xx_l4_cfg_hwmod,
1846         &omap44xx_l4_per_hwmod,
1847         &omap44xx_l4_wkup_hwmod,
1848
1849         /* dma class */
1850         &omap44xx_dma_system_hwmod,
1851
1852         /* mpu_bus class */
1853         &omap44xx_mpu_private_hwmod,
1854
1855         /* dsp class */
1856         &omap44xx_dsp_hwmod,
1857         &omap44xx_dsp_c0_hwmod,
1858
1859         /* gpio class */
1860         &omap44xx_gpio1_hwmod,
1861         &omap44xx_gpio2_hwmod,
1862         &omap44xx_gpio3_hwmod,
1863         &omap44xx_gpio4_hwmod,
1864         &omap44xx_gpio5_hwmod,
1865         &omap44xx_gpio6_hwmod,
1866
1867         /* i2c class */
1868         &omap44xx_i2c1_hwmod,
1869         &omap44xx_i2c2_hwmod,
1870         &omap44xx_i2c3_hwmod,
1871         &omap44xx_i2c4_hwmod,
1872
1873         /* iva class */
1874         &omap44xx_iva_hwmod,
1875         &omap44xx_iva_seq0_hwmod,
1876         &omap44xx_iva_seq1_hwmod,
1877
1878         /* mpu class */
1879         &omap44xx_mpu_hwmod,
1880
1881         /* uart class */
1882         &omap44xx_uart1_hwmod,
1883         &omap44xx_uart2_hwmod,
1884         &omap44xx_uart3_hwmod,
1885         &omap44xx_uart4_hwmod,
1886
1887         /* wd_timer class */
1888         &omap44xx_wd_timer2_hwmod,
1889         &omap44xx_wd_timer3_hwmod,
1890
1891         NULL,
1892 };
1893
1894 int __init omap44xx_hwmod_init(void)
1895 {
1896         return omap_hwmod_init(omap44xx_hwmods);
1897 }
1898