2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
25 #include <plat/gpio.h>
28 #include "omap_hwmod_common_data.h"
33 #include "prm-regbits-44xx.h"
36 /* Base offset for all OMAP4 interrupts external to MPUSS */
37 #define OMAP44XX_IRQ_GIC_START 32
39 /* Base offset for all OMAP4 dma requests */
40 #define OMAP44XX_DMA_REQ_START 1
42 /* Backward references (IPs with Bus Master capability) */
43 static struct omap_hwmod omap44xx_dma_system_hwmod;
44 static struct omap_hwmod omap44xx_dmm_hwmod;
45 static struct omap_hwmod omap44xx_dsp_hwmod;
46 static struct omap_hwmod omap44xx_emif_fw_hwmod;
47 static struct omap_hwmod omap44xx_iva_hwmod;
48 static struct omap_hwmod omap44xx_l3_instr_hwmod;
49 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
50 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
51 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
52 static struct omap_hwmod omap44xx_l4_abe_hwmod;
53 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
54 static struct omap_hwmod omap44xx_l4_per_hwmod;
55 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
56 static struct omap_hwmod omap44xx_mpu_hwmod;
57 static struct omap_hwmod omap44xx_mpu_private_hwmod;
60 * Interconnects omap_hwmod structures
61 * hwmods that compose the global OMAP interconnect
68 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
72 /* dmm interface data */
73 /* l3_main_1 -> dmm */
74 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
75 .master = &omap44xx_l3_main_1_hwmod,
76 .slave = &omap44xx_dmm_hwmod,
78 .user = OCP_USER_SDMA,
81 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
83 .pa_start = 0x4e000000,
90 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
91 .master = &omap44xx_mpu_hwmod,
92 .slave = &omap44xx_dmm_hwmod,
94 .addr = omap44xx_dmm_addrs,
95 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
100 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
101 &omap44xx_l3_main_1__dmm,
105 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
106 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
109 static struct omap_hwmod omap44xx_dmm_hwmod = {
111 .class = &omap44xx_dmm_hwmod_class,
112 .slaves = omap44xx_dmm_slaves,
113 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
114 .mpu_irqs = omap44xx_dmm_irqs,
115 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
121 * instance(s): emif_fw
123 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
127 /* emif_fw interface data */
129 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
130 .master = &omap44xx_dmm_hwmod,
131 .slave = &omap44xx_emif_fw_hwmod,
133 .user = OCP_USER_MPU | OCP_USER_SDMA,
136 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
138 .pa_start = 0x4a20c000,
139 .pa_end = 0x4a20c0ff,
140 .flags = ADDR_TYPE_RT
144 /* l4_cfg -> emif_fw */
145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
146 .master = &omap44xx_l4_cfg_hwmod,
147 .slave = &omap44xx_emif_fw_hwmod,
149 .addr = omap44xx_emif_fw_addrs,
150 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
151 .user = OCP_USER_MPU,
154 /* emif_fw slave ports */
155 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
156 &omap44xx_dmm__emif_fw,
157 &omap44xx_l4_cfg__emif_fw,
160 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
162 .class = &omap44xx_emif_fw_hwmod_class,
163 .slaves = omap44xx_emif_fw_slaves,
164 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
170 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
172 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
176 /* l3_instr interface data */
177 /* iva -> l3_instr */
178 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
179 .master = &omap44xx_iva_hwmod,
180 .slave = &omap44xx_l3_instr_hwmod,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
185 /* l3_main_3 -> l3_instr */
186 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
187 .master = &omap44xx_l3_main_3_hwmod,
188 .slave = &omap44xx_l3_instr_hwmod,
190 .user = OCP_USER_MPU | OCP_USER_SDMA,
193 /* l3_instr slave ports */
194 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
195 &omap44xx_iva__l3_instr,
196 &omap44xx_l3_main_3__l3_instr,
199 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
201 .class = &omap44xx_l3_hwmod_class,
202 .slaves = omap44xx_l3_instr_slaves,
203 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
204 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
207 /* l3_main_1 interface data */
208 /* dsp -> l3_main_1 */
209 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
210 .master = &omap44xx_dsp_hwmod,
211 .slave = &omap44xx_l3_main_1_hwmod,
213 .user = OCP_USER_MPU | OCP_USER_SDMA,
216 /* l3_main_2 -> l3_main_1 */
217 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
218 .master = &omap44xx_l3_main_2_hwmod,
219 .slave = &omap44xx_l3_main_1_hwmod,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
224 /* l4_cfg -> l3_main_1 */
225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
226 .master = &omap44xx_l4_cfg_hwmod,
227 .slave = &omap44xx_l3_main_1_hwmod,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 /* mpu -> l3_main_1 */
233 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
234 .master = &omap44xx_mpu_hwmod,
235 .slave = &omap44xx_l3_main_1_hwmod,
237 .user = OCP_USER_MPU | OCP_USER_SDMA,
240 /* l3_main_1 slave ports */
241 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
242 &omap44xx_dsp__l3_main_1,
243 &omap44xx_l3_main_2__l3_main_1,
244 &omap44xx_l4_cfg__l3_main_1,
245 &omap44xx_mpu__l3_main_1,
248 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
250 .class = &omap44xx_l3_hwmod_class,
251 .slaves = omap44xx_l3_main_1_slaves,
252 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
256 /* l3_main_2 interface data */
257 /* iva -> l3_main_2 */
258 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
259 .master = &omap44xx_iva_hwmod,
260 .slave = &omap44xx_l3_main_2_hwmod,
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 /* l3_main_1 -> l3_main_2 */
266 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
267 .master = &omap44xx_l3_main_1_hwmod,
268 .slave = &omap44xx_l3_main_2_hwmod,
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
273 /* dma_system -> l3_main_2 */
274 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
275 .master = &omap44xx_dma_system_hwmod,
276 .slave = &omap44xx_l3_main_2_hwmod,
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
281 /* l4_cfg -> l3_main_2 */
282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
283 .master = &omap44xx_l4_cfg_hwmod,
284 .slave = &omap44xx_l3_main_2_hwmod,
286 .user = OCP_USER_MPU | OCP_USER_SDMA,
289 /* l3_main_2 slave ports */
290 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
291 &omap44xx_dma_system__l3_main_2,
292 &omap44xx_iva__l3_main_2,
293 &omap44xx_l3_main_1__l3_main_2,
294 &omap44xx_l4_cfg__l3_main_2,
297 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
299 .class = &omap44xx_l3_hwmod_class,
300 .slaves = omap44xx_l3_main_2_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
305 /* l3_main_3 interface data */
306 /* l3_main_1 -> l3_main_3 */
307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
308 .master = &omap44xx_l3_main_1_hwmod,
309 .slave = &omap44xx_l3_main_3_hwmod,
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
314 /* l3_main_2 -> l3_main_3 */
315 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
316 .master = &omap44xx_l3_main_2_hwmod,
317 .slave = &omap44xx_l3_main_3_hwmod,
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
322 /* l4_cfg -> l3_main_3 */
323 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
324 .master = &omap44xx_l4_cfg_hwmod,
325 .slave = &omap44xx_l3_main_3_hwmod,
327 .user = OCP_USER_MPU | OCP_USER_SDMA,
330 /* l3_main_3 slave ports */
331 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
332 &omap44xx_l3_main_1__l3_main_3,
333 &omap44xx_l3_main_2__l3_main_3,
334 &omap44xx_l4_cfg__l3_main_3,
337 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
339 .class = &omap44xx_l3_hwmod_class,
340 .slaves = omap44xx_l3_main_3_slaves,
341 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
342 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
347 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
349 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
353 /* l4_abe interface data */
355 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
356 .master = &omap44xx_dsp_hwmod,
357 .slave = &omap44xx_l4_abe_hwmod,
358 .clk = "ocp_abe_iclk",
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
362 /* l3_main_1 -> l4_abe */
363 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
364 .master = &omap44xx_l3_main_1_hwmod,
365 .slave = &omap44xx_l4_abe_hwmod,
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
371 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
372 .master = &omap44xx_mpu_hwmod,
373 .slave = &omap44xx_l4_abe_hwmod,
374 .clk = "ocp_abe_iclk",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 /* l4_abe slave ports */
379 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
380 &omap44xx_dsp__l4_abe,
381 &omap44xx_l3_main_1__l4_abe,
382 &omap44xx_mpu__l4_abe,
385 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
387 .class = &omap44xx_l4_hwmod_class,
388 .slaves = omap44xx_l4_abe_slaves,
389 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
390 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
393 /* l4_cfg interface data */
394 /* l3_main_1 -> l4_cfg */
395 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
396 .master = &omap44xx_l3_main_1_hwmod,
397 .slave = &omap44xx_l4_cfg_hwmod,
399 .user = OCP_USER_MPU | OCP_USER_SDMA,
402 /* l4_cfg slave ports */
403 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
404 &omap44xx_l3_main_1__l4_cfg,
407 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
409 .class = &omap44xx_l4_hwmod_class,
410 .slaves = omap44xx_l4_cfg_slaves,
411 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
415 /* l4_per interface data */
416 /* l3_main_2 -> l4_per */
417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
418 .master = &omap44xx_l3_main_2_hwmod,
419 .slave = &omap44xx_l4_per_hwmod,
421 .user = OCP_USER_MPU | OCP_USER_SDMA,
424 /* l4_per slave ports */
425 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
426 &omap44xx_l3_main_2__l4_per,
429 static struct omap_hwmod omap44xx_l4_per_hwmod = {
431 .class = &omap44xx_l4_hwmod_class,
432 .slaves = omap44xx_l4_per_slaves,
433 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
437 /* l4_wkup interface data */
438 /* l4_cfg -> l4_wkup */
439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
440 .master = &omap44xx_l4_cfg_hwmod,
441 .slave = &omap44xx_l4_wkup_hwmod,
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
446 /* l4_wkup slave ports */
447 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
448 &omap44xx_l4_cfg__l4_wkup,
451 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
453 .class = &omap44xx_l4_hwmod_class,
454 .slaves = omap44xx_l4_wkup_slaves,
455 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
461 * instance(s): mpu_private
463 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
467 /* mpu_private interface data */
468 /* mpu -> mpu_private */
469 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
470 .master = &omap44xx_mpu_hwmod,
471 .slave = &omap44xx_mpu_private_hwmod,
473 .user = OCP_USER_MPU | OCP_USER_SDMA,
476 /* mpu_private slave ports */
477 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
478 &omap44xx_mpu__mpu_private,
481 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
482 .name = "mpu_private",
483 .class = &omap44xx_mpu_bus_hwmod_class,
484 .slaves = omap44xx_mpu_private_slaves,
485 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
486 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
490 * Modules omap_hwmod structures
492 * The following IPs are excluded for the moment because:
493 * - They do not need an explicit SW control using omap_hwmod API.
494 * - They still need to be validated with the driver
495 * properly adapted to omap_hwmod / omap_device
505 * ctrl_module_pad_core
506 * ctrl_module_pad_wkup
587 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
592 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
593 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
596 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
597 { .name = "mmu_cache", .rst_shift = 1 },
600 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
601 { .name = "dsp", .rst_shift = 0 },
605 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
606 .master = &omap44xx_dsp_hwmod,
607 .slave = &omap44xx_iva_hwmod,
608 .clk = "dpll_iva_m5x2_ck",
611 /* dsp master ports */
612 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
613 &omap44xx_dsp__l3_main_1,
614 &omap44xx_dsp__l4_abe,
619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
620 .master = &omap44xx_l4_cfg_hwmod,
621 .slave = &omap44xx_dsp_hwmod,
623 .user = OCP_USER_MPU | OCP_USER_SDMA,
626 /* dsp slave ports */
627 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
628 &omap44xx_l4_cfg__dsp,
631 /* Pseudo hwmod for reset control purpose only */
632 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
634 .class = &omap44xx_dsp_hwmod_class,
635 .flags = HWMOD_INIT_NO_RESET,
636 .rst_lines = omap44xx_dsp_c0_resets,
637 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
640 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
643 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
646 static struct omap_hwmod omap44xx_dsp_hwmod = {
648 .class = &omap44xx_dsp_hwmod_class,
649 .mpu_irqs = omap44xx_dsp_irqs,
650 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
651 .rst_lines = omap44xx_dsp_resets,
652 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
653 .main_clk = "dsp_fck",
656 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
657 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
660 .slaves = omap44xx_dsp_slaves,
661 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
662 .masters = omap44xx_dsp_masters,
663 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
664 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
669 * general purpose io module
672 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
676 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
677 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
678 SYSS_HAS_RESET_STATUS),
679 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
680 .sysc_fields = &omap_hwmod_sysc_type1,
683 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
685 .sysc = &omap44xx_gpio_sysc,
690 static struct omap_gpio_dev_attr gpio_dev_attr = {
696 static struct omap_hwmod omap44xx_gpio1_hwmod;
697 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
698 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
701 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
703 .pa_start = 0x4a310000,
704 .pa_end = 0x4a3101ff,
705 .flags = ADDR_TYPE_RT
709 /* l4_wkup -> gpio1 */
710 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
711 .master = &omap44xx_l4_wkup_hwmod,
712 .slave = &omap44xx_gpio1_hwmod,
713 .addr = omap44xx_gpio1_addrs,
714 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
715 .user = OCP_USER_MPU | OCP_USER_SDMA,
718 /* gpio1 slave ports */
719 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
720 &omap44xx_l4_wkup__gpio1,
723 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
724 { .role = "dbclk", .clk = "sys_32k_ck" },
727 static struct omap_hwmod omap44xx_gpio1_hwmod = {
729 .class = &omap44xx_gpio_hwmod_class,
730 .mpu_irqs = omap44xx_gpio1_irqs,
731 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
732 .main_clk = "gpio1_ick",
735 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
738 .opt_clks = gpio1_opt_clks,
739 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
740 .dev_attr = &gpio_dev_attr,
741 .slaves = omap44xx_gpio1_slaves,
742 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
743 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
747 static struct omap_hwmod omap44xx_gpio2_hwmod;
748 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
749 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
752 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
754 .pa_start = 0x48055000,
755 .pa_end = 0x480551ff,
756 .flags = ADDR_TYPE_RT
760 /* l4_per -> gpio2 */
761 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
762 .master = &omap44xx_l4_per_hwmod,
763 .slave = &omap44xx_gpio2_hwmod,
764 .addr = omap44xx_gpio2_addrs,
765 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
766 .user = OCP_USER_MPU | OCP_USER_SDMA,
769 /* gpio2 slave ports */
770 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
771 &omap44xx_l4_per__gpio2,
774 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
775 { .role = "dbclk", .clk = "sys_32k_ck" },
778 static struct omap_hwmod omap44xx_gpio2_hwmod = {
780 .class = &omap44xx_gpio_hwmod_class,
781 .mpu_irqs = omap44xx_gpio2_irqs,
782 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
783 .main_clk = "gpio2_ick",
786 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
789 .opt_clks = gpio2_opt_clks,
790 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
791 .dev_attr = &gpio_dev_attr,
792 .slaves = omap44xx_gpio2_slaves,
793 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
794 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
798 static struct omap_hwmod omap44xx_gpio3_hwmod;
799 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
800 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
803 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
805 .pa_start = 0x48057000,
806 .pa_end = 0x480571ff,
807 .flags = ADDR_TYPE_RT
811 /* l4_per -> gpio3 */
812 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
813 .master = &omap44xx_l4_per_hwmod,
814 .slave = &omap44xx_gpio3_hwmod,
815 .addr = omap44xx_gpio3_addrs,
816 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
817 .user = OCP_USER_MPU | OCP_USER_SDMA,
820 /* gpio3 slave ports */
821 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
822 &omap44xx_l4_per__gpio3,
825 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
826 { .role = "dbclk", .clk = "sys_32k_ck" },
829 static struct omap_hwmod omap44xx_gpio3_hwmod = {
831 .class = &omap44xx_gpio_hwmod_class,
832 .mpu_irqs = omap44xx_gpio3_irqs,
833 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
834 .main_clk = "gpio3_ick",
837 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
840 .opt_clks = gpio3_opt_clks,
841 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
842 .dev_attr = &gpio_dev_attr,
843 .slaves = omap44xx_gpio3_slaves,
844 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
845 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
849 static struct omap_hwmod omap44xx_gpio4_hwmod;
850 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
851 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
854 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
856 .pa_start = 0x48059000,
857 .pa_end = 0x480591ff,
858 .flags = ADDR_TYPE_RT
862 /* l4_per -> gpio4 */
863 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
864 .master = &omap44xx_l4_per_hwmod,
865 .slave = &omap44xx_gpio4_hwmod,
866 .addr = omap44xx_gpio4_addrs,
867 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
868 .user = OCP_USER_MPU | OCP_USER_SDMA,
871 /* gpio4 slave ports */
872 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
873 &omap44xx_l4_per__gpio4,
876 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
877 { .role = "dbclk", .clk = "sys_32k_ck" },
880 static struct omap_hwmod omap44xx_gpio4_hwmod = {
882 .class = &omap44xx_gpio_hwmod_class,
883 .mpu_irqs = omap44xx_gpio4_irqs,
884 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
885 .main_clk = "gpio4_ick",
888 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
891 .opt_clks = gpio4_opt_clks,
892 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
893 .dev_attr = &gpio_dev_attr,
894 .slaves = omap44xx_gpio4_slaves,
895 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
896 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
900 static struct omap_hwmod omap44xx_gpio5_hwmod;
901 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
902 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
905 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
907 .pa_start = 0x4805b000,
908 .pa_end = 0x4805b1ff,
909 .flags = ADDR_TYPE_RT
913 /* l4_per -> gpio5 */
914 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
915 .master = &omap44xx_l4_per_hwmod,
916 .slave = &omap44xx_gpio5_hwmod,
917 .addr = omap44xx_gpio5_addrs,
918 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
919 .user = OCP_USER_MPU | OCP_USER_SDMA,
922 /* gpio5 slave ports */
923 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
924 &omap44xx_l4_per__gpio5,
927 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
928 { .role = "dbclk", .clk = "sys_32k_ck" },
931 static struct omap_hwmod omap44xx_gpio5_hwmod = {
933 .class = &omap44xx_gpio_hwmod_class,
934 .mpu_irqs = omap44xx_gpio5_irqs,
935 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
936 .main_clk = "gpio5_ick",
939 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
942 .opt_clks = gpio5_opt_clks,
943 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
944 .dev_attr = &gpio_dev_attr,
945 .slaves = omap44xx_gpio5_slaves,
946 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
947 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
951 static struct omap_hwmod omap44xx_gpio6_hwmod;
952 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
953 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
956 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
958 .pa_start = 0x4805d000,
959 .pa_end = 0x4805d1ff,
960 .flags = ADDR_TYPE_RT
964 /* l4_per -> gpio6 */
965 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
966 .master = &omap44xx_l4_per_hwmod,
967 .slave = &omap44xx_gpio6_hwmod,
968 .addr = omap44xx_gpio6_addrs,
969 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
970 .user = OCP_USER_MPU | OCP_USER_SDMA,
973 /* gpio6 slave ports */
974 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
975 &omap44xx_l4_per__gpio6,
978 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
979 { .role = "dbclk", .clk = "sys_32k_ck" },
982 static struct omap_hwmod omap44xx_gpio6_hwmod = {
984 .class = &omap44xx_gpio_hwmod_class,
985 .mpu_irqs = omap44xx_gpio6_irqs,
986 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
987 .main_clk = "gpio6_ick",
990 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
993 .opt_clks = gpio6_opt_clks,
994 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
995 .dev_attr = &gpio_dev_attr,
996 .slaves = omap44xx_gpio6_slaves,
997 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
998 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1003 * multimaster high-speed i2c controller
1006 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1007 .sysc_offs = 0x0010,
1008 .syss_offs = 0x0090,
1009 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1010 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1011 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1012 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1013 .sysc_fields = &omap_hwmod_sysc_type1,
1016 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1018 .sysc = &omap44xx_i2c_sysc,
1022 static struct omap_hwmod omap44xx_i2c1_hwmod;
1023 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1024 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1027 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1028 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1029 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1032 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1034 .pa_start = 0x48070000,
1035 .pa_end = 0x480700ff,
1036 .flags = ADDR_TYPE_RT
1040 /* l4_per -> i2c1 */
1041 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1042 .master = &omap44xx_l4_per_hwmod,
1043 .slave = &omap44xx_i2c1_hwmod,
1045 .addr = omap44xx_i2c1_addrs,
1046 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
1047 .user = OCP_USER_MPU | OCP_USER_SDMA,
1050 /* i2c1 slave ports */
1051 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1052 &omap44xx_l4_per__i2c1,
1055 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1057 .class = &omap44xx_i2c_hwmod_class,
1058 .flags = HWMOD_INIT_NO_RESET,
1059 .mpu_irqs = omap44xx_i2c1_irqs,
1060 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
1061 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1062 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1063 .main_clk = "i2c1_fck",
1066 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1069 .slaves = omap44xx_i2c1_slaves,
1070 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
1071 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1075 static struct omap_hwmod omap44xx_i2c2_hwmod;
1076 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1077 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1080 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1081 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1082 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1085 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1087 .pa_start = 0x48072000,
1088 .pa_end = 0x480720ff,
1089 .flags = ADDR_TYPE_RT
1093 /* l4_per -> i2c2 */
1094 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1095 .master = &omap44xx_l4_per_hwmod,
1096 .slave = &omap44xx_i2c2_hwmod,
1098 .addr = omap44xx_i2c2_addrs,
1099 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
1100 .user = OCP_USER_MPU | OCP_USER_SDMA,
1103 /* i2c2 slave ports */
1104 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1105 &omap44xx_l4_per__i2c2,
1108 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1110 .class = &omap44xx_i2c_hwmod_class,
1111 .flags = HWMOD_INIT_NO_RESET,
1112 .mpu_irqs = omap44xx_i2c2_irqs,
1113 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
1114 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1115 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1116 .main_clk = "i2c2_fck",
1119 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1122 .slaves = omap44xx_i2c2_slaves,
1123 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
1124 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1128 static struct omap_hwmod omap44xx_i2c3_hwmod;
1129 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1130 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1133 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1134 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1135 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1138 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1140 .pa_start = 0x48060000,
1141 .pa_end = 0x480600ff,
1142 .flags = ADDR_TYPE_RT
1146 /* l4_per -> i2c3 */
1147 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
1148 .master = &omap44xx_l4_per_hwmod,
1149 .slave = &omap44xx_i2c3_hwmod,
1151 .addr = omap44xx_i2c3_addrs,
1152 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
1153 .user = OCP_USER_MPU | OCP_USER_SDMA,
1156 /* i2c3 slave ports */
1157 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1158 &omap44xx_l4_per__i2c3,
1161 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1163 .class = &omap44xx_i2c_hwmod_class,
1164 .flags = HWMOD_INIT_NO_RESET,
1165 .mpu_irqs = omap44xx_i2c3_irqs,
1166 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
1167 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1168 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1169 .main_clk = "i2c3_fck",
1172 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1175 .slaves = omap44xx_i2c3_slaves,
1176 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
1177 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1181 static struct omap_hwmod omap44xx_i2c4_hwmod;
1182 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1183 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1186 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1187 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1188 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1191 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
1193 .pa_start = 0x48350000,
1194 .pa_end = 0x483500ff,
1195 .flags = ADDR_TYPE_RT
1199 /* l4_per -> i2c4 */
1200 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1201 .master = &omap44xx_l4_per_hwmod,
1202 .slave = &omap44xx_i2c4_hwmod,
1204 .addr = omap44xx_i2c4_addrs,
1205 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
1206 .user = OCP_USER_MPU | OCP_USER_SDMA,
1209 /* i2c4 slave ports */
1210 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1211 &omap44xx_l4_per__i2c4,
1214 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1216 .class = &omap44xx_i2c_hwmod_class,
1217 .flags = HWMOD_INIT_NO_RESET,
1218 .mpu_irqs = omap44xx_i2c4_irqs,
1219 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
1220 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1221 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1222 .main_clk = "i2c4_fck",
1225 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1228 .slaves = omap44xx_i2c4_slaves,
1229 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
1230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1235 * multi-standard video encoder/decoder hardware accelerator
1238 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1243 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1244 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1245 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1246 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1249 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1250 { .name = "logic", .rst_shift = 2 },
1253 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1254 { .name = "seq0", .rst_shift = 0 },
1257 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1258 { .name = "seq1", .rst_shift = 1 },
1261 /* iva master ports */
1262 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1263 &omap44xx_iva__l3_main_2,
1264 &omap44xx_iva__l3_instr,
1267 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1269 .pa_start = 0x5a000000,
1270 .pa_end = 0x5a07ffff,
1271 .flags = ADDR_TYPE_RT
1275 /* l3_main_2 -> iva */
1276 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1277 .master = &omap44xx_l3_main_2_hwmod,
1278 .slave = &omap44xx_iva_hwmod,
1280 .addr = omap44xx_iva_addrs,
1281 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
1282 .user = OCP_USER_MPU,
1285 /* iva slave ports */
1286 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1288 &omap44xx_l3_main_2__iva,
1291 /* Pseudo hwmod for reset control purpose only */
1292 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1294 .class = &omap44xx_iva_hwmod_class,
1295 .flags = HWMOD_INIT_NO_RESET,
1296 .rst_lines = omap44xx_iva_seq0_resets,
1297 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1300 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1303 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1306 /* Pseudo hwmod for reset control purpose only */
1307 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1309 .class = &omap44xx_iva_hwmod_class,
1310 .flags = HWMOD_INIT_NO_RESET,
1311 .rst_lines = omap44xx_iva_seq1_resets,
1312 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1315 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1321 static struct omap_hwmod omap44xx_iva_hwmod = {
1323 .class = &omap44xx_iva_hwmod_class,
1324 .mpu_irqs = omap44xx_iva_irqs,
1325 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
1326 .rst_lines = omap44xx_iva_resets,
1327 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1328 .main_clk = "iva_fck",
1331 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1332 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1335 .slaves = omap44xx_iva_slaves,
1336 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
1337 .masters = omap44xx_iva_masters,
1338 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
1339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1347 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1352 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
1353 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
1354 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
1355 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
1358 /* mpu master ports */
1359 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
1360 &omap44xx_mpu__l3_main_1,
1361 &omap44xx_mpu__l4_abe,
1365 static struct omap_hwmod omap44xx_mpu_hwmod = {
1367 .class = &omap44xx_mpu_hwmod_class,
1368 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1369 .mpu_irqs = omap44xx_mpu_irqs,
1370 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
1371 .main_clk = "dpll_mpu_m2_ck",
1374 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
1377 .masters = omap44xx_mpu_masters,
1378 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
1379 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1384 * universal asynchronous receiver/transmitter (uart)
1387 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
1389 .sysc_offs = 0x0054,
1390 .syss_offs = 0x0058,
1391 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1392 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1393 SYSS_HAS_RESET_STATUS),
1394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1395 .sysc_fields = &omap_hwmod_sysc_type1,
1398 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
1400 .sysc = &omap44xx_uart_sysc,
1404 static struct omap_hwmod omap44xx_uart1_hwmod;
1405 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
1406 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
1409 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
1410 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
1411 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
1414 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
1416 .pa_start = 0x4806a000,
1417 .pa_end = 0x4806a0ff,
1418 .flags = ADDR_TYPE_RT
1422 /* l4_per -> uart1 */
1423 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
1424 .master = &omap44xx_l4_per_hwmod,
1425 .slave = &omap44xx_uart1_hwmod,
1427 .addr = omap44xx_uart1_addrs,
1428 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
1429 .user = OCP_USER_MPU | OCP_USER_SDMA,
1432 /* uart1 slave ports */
1433 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
1434 &omap44xx_l4_per__uart1,
1437 static struct omap_hwmod omap44xx_uart1_hwmod = {
1439 .class = &omap44xx_uart_hwmod_class,
1440 .mpu_irqs = omap44xx_uart1_irqs,
1441 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
1442 .sdma_reqs = omap44xx_uart1_sdma_reqs,
1443 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
1444 .main_clk = "uart1_fck",
1447 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
1450 .slaves = omap44xx_uart1_slaves,
1451 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
1452 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1456 static struct omap_hwmod omap44xx_uart2_hwmod;
1457 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
1458 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
1461 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
1462 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
1463 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
1466 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
1468 .pa_start = 0x4806c000,
1469 .pa_end = 0x4806c0ff,
1470 .flags = ADDR_TYPE_RT
1474 /* l4_per -> uart2 */
1475 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
1476 .master = &omap44xx_l4_per_hwmod,
1477 .slave = &omap44xx_uart2_hwmod,
1479 .addr = omap44xx_uart2_addrs,
1480 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
1481 .user = OCP_USER_MPU | OCP_USER_SDMA,
1484 /* uart2 slave ports */
1485 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
1486 &omap44xx_l4_per__uart2,
1489 static struct omap_hwmod omap44xx_uart2_hwmod = {
1491 .class = &omap44xx_uart_hwmod_class,
1492 .mpu_irqs = omap44xx_uart2_irqs,
1493 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
1494 .sdma_reqs = omap44xx_uart2_sdma_reqs,
1495 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
1496 .main_clk = "uart2_fck",
1499 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
1502 .slaves = omap44xx_uart2_slaves,
1503 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
1504 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1508 static struct omap_hwmod omap44xx_uart3_hwmod;
1509 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
1510 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
1513 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
1514 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
1515 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
1518 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
1520 .pa_start = 0x48020000,
1521 .pa_end = 0x480200ff,
1522 .flags = ADDR_TYPE_RT
1526 /* l4_per -> uart3 */
1527 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
1528 .master = &omap44xx_l4_per_hwmod,
1529 .slave = &omap44xx_uart3_hwmod,
1531 .addr = omap44xx_uart3_addrs,
1532 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
1533 .user = OCP_USER_MPU | OCP_USER_SDMA,
1536 /* uart3 slave ports */
1537 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
1538 &omap44xx_l4_per__uart3,
1541 static struct omap_hwmod omap44xx_uart3_hwmod = {
1543 .class = &omap44xx_uart_hwmod_class,
1544 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1545 .mpu_irqs = omap44xx_uart3_irqs,
1546 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
1547 .sdma_reqs = omap44xx_uart3_sdma_reqs,
1548 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
1549 .main_clk = "uart3_fck",
1552 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
1555 .slaves = omap44xx_uart3_slaves,
1556 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
1557 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1561 static struct omap_hwmod omap44xx_uart4_hwmod;
1562 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
1563 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
1566 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
1567 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
1568 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
1571 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
1573 .pa_start = 0x4806e000,
1574 .pa_end = 0x4806e0ff,
1575 .flags = ADDR_TYPE_RT
1579 /* l4_per -> uart4 */
1580 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1581 .master = &omap44xx_l4_per_hwmod,
1582 .slave = &omap44xx_uart4_hwmod,
1584 .addr = omap44xx_uart4_addrs,
1585 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
1586 .user = OCP_USER_MPU | OCP_USER_SDMA,
1589 /* uart4 slave ports */
1590 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1591 &omap44xx_l4_per__uart4,
1594 static struct omap_hwmod omap44xx_uart4_hwmod = {
1596 .class = &omap44xx_uart_hwmod_class,
1597 .mpu_irqs = omap44xx_uart4_irqs,
1598 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
1599 .sdma_reqs = omap44xx_uart4_sdma_reqs,
1600 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1601 .main_clk = "uart4_fck",
1604 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1607 .slaves = omap44xx_uart4_slaves,
1608 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
1609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1614 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1615 * overflow condition
1618 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
1620 .sysc_offs = 0x0010,
1621 .syss_offs = 0x0014,
1622 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1623 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1624 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1625 .sysc_fields = &omap_hwmod_sysc_type1,
1628 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
1630 .sysc = &omap44xx_wd_timer_sysc,
1631 .pre_shutdown = &omap2_wd_timer_disable
1635 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
1636 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
1637 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
1640 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
1642 .pa_start = 0x4a314000,
1643 .pa_end = 0x4a31407f,
1644 .flags = ADDR_TYPE_RT
1648 /* l4_wkup -> wd_timer2 */
1649 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
1650 .master = &omap44xx_l4_wkup_hwmod,
1651 .slave = &omap44xx_wd_timer2_hwmod,
1652 .clk = "l4_wkup_clk_mux_ck",
1653 .addr = omap44xx_wd_timer2_addrs,
1654 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
1655 .user = OCP_USER_MPU | OCP_USER_SDMA,
1658 /* wd_timer2 slave ports */
1659 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
1660 &omap44xx_l4_wkup__wd_timer2,
1663 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
1664 .name = "wd_timer2",
1665 .class = &omap44xx_wd_timer_hwmod_class,
1666 .mpu_irqs = omap44xx_wd_timer2_irqs,
1667 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
1668 .main_clk = "wd_timer2_fck",
1671 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
1674 .slaves = omap44xx_wd_timer2_slaves,
1675 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
1676 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1680 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
1681 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
1682 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
1685 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
1687 .pa_start = 0x40130000,
1688 .pa_end = 0x4013007f,
1689 .flags = ADDR_TYPE_RT
1693 /* l4_abe -> wd_timer3 */
1694 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
1695 .master = &omap44xx_l4_abe_hwmod,
1696 .slave = &omap44xx_wd_timer3_hwmod,
1697 .clk = "ocp_abe_iclk",
1698 .addr = omap44xx_wd_timer3_addrs,
1699 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
1700 .user = OCP_USER_MPU,
1703 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
1705 .pa_start = 0x49030000,
1706 .pa_end = 0x4903007f,
1707 .flags = ADDR_TYPE_RT
1711 /* l4_abe -> wd_timer3 (dma) */
1712 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
1713 .master = &omap44xx_l4_abe_hwmod,
1714 .slave = &omap44xx_wd_timer3_hwmod,
1715 .clk = "ocp_abe_iclk",
1716 .addr = omap44xx_wd_timer3_dma_addrs,
1717 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1718 .user = OCP_USER_SDMA,
1721 /* wd_timer3 slave ports */
1722 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1723 &omap44xx_l4_abe__wd_timer3,
1724 &omap44xx_l4_abe__wd_timer3_dma,
1727 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1728 .name = "wd_timer3",
1729 .class = &omap44xx_wd_timer_hwmod_class,
1730 .mpu_irqs = omap44xx_wd_timer3_irqs,
1731 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1732 .main_clk = "wd_timer3_fck",
1735 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1738 .slaves = omap44xx_wd_timer3_slaves,
1739 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1740 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1746 * dma controller for data exchange between memory to memory (i.e. internal or
1747 * external memory) and gp peripherals to memory or memory to gp peripherals
1750 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
1752 .sysc_offs = 0x002c,
1753 .syss_offs = 0x0028,
1754 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1755 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1756 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1757 SYSS_HAS_RESET_STATUS),
1758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1759 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1760 .sysc_fields = &omap_hwmod_sysc_type1,
1763 /* dma attributes */
1764 static struct omap_dma_dev_attr dma_dev_attr = {
1765 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1766 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1770 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
1772 .sysc = &omap44xx_dma_sysc,
1776 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
1777 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
1778 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
1779 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
1780 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
1783 /* dma_system master ports */
1784 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
1785 &omap44xx_dma_system__l3_main_2,
1788 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
1790 .pa_start = 0x4a056000,
1791 .pa_end = 0x4a0560ff,
1792 .flags = ADDR_TYPE_RT
1796 /* l4_cfg -> dma_system */
1797 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
1798 .master = &omap44xx_l4_cfg_hwmod,
1799 .slave = &omap44xx_dma_system_hwmod,
1801 .addr = omap44xx_dma_system_addrs,
1802 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
1803 .user = OCP_USER_MPU | OCP_USER_SDMA,
1806 /* dma_system slave ports */
1807 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
1808 &omap44xx_l4_cfg__dma_system,
1811 static struct omap_hwmod omap44xx_dma_system_hwmod = {
1812 .name = "dma_system",
1813 .class = &omap44xx_dma_hwmod_class,
1814 .mpu_irqs = omap44xx_dma_system_irqs,
1815 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
1816 .main_clk = "l3_div_ck",
1819 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
1822 .slaves = omap44xx_dma_system_slaves,
1823 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
1824 .masters = omap44xx_dma_system_masters,
1825 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
1826 .dev_attr = &dma_dev_attr,
1827 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1830 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1832 &omap44xx_dmm_hwmod,
1835 &omap44xx_emif_fw_hwmod,
1838 &omap44xx_l3_instr_hwmod,
1839 &omap44xx_l3_main_1_hwmod,
1840 &omap44xx_l3_main_2_hwmod,
1841 &omap44xx_l3_main_3_hwmod,
1844 &omap44xx_l4_abe_hwmod,
1845 &omap44xx_l4_cfg_hwmod,
1846 &omap44xx_l4_per_hwmod,
1847 &omap44xx_l4_wkup_hwmod,
1850 &omap44xx_dma_system_hwmod,
1853 &omap44xx_mpu_private_hwmod,
1856 &omap44xx_dsp_hwmod,
1857 &omap44xx_dsp_c0_hwmod,
1860 &omap44xx_gpio1_hwmod,
1861 &omap44xx_gpio2_hwmod,
1862 &omap44xx_gpio3_hwmod,
1863 &omap44xx_gpio4_hwmod,
1864 &omap44xx_gpio5_hwmod,
1865 &omap44xx_gpio6_hwmod,
1868 &omap44xx_i2c1_hwmod,
1869 &omap44xx_i2c2_hwmod,
1870 &omap44xx_i2c3_hwmod,
1871 &omap44xx_i2c4_hwmod,
1874 &omap44xx_iva_hwmod,
1875 &omap44xx_iva_seq0_hwmod,
1876 &omap44xx_iva_seq1_hwmod,
1879 &omap44xx_mpu_hwmod,
1882 &omap44xx_uart1_hwmod,
1883 &omap44xx_uart2_hwmod,
1884 &omap44xx_uart3_hwmod,
1885 &omap44xx_uart4_hwmod,
1887 /* wd_timer class */
1888 &omap44xx_wd_timer2_hwmod,
1889 &omap44xx_wd_timer3_hwmod,
1894 int __init omap44xx_hwmod_init(void)
1896 return omap_hwmod_init(omap44xx_hwmods);