arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                 },
 208         },
 209 };
 210
 211 /* l4_cfg */
 212 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213         .name           = "l4_cfg",
 214         .class          = &omap44xx_l4_hwmod_class,
 215         .clkdm_name     = "l4_cfg_clkdm",
 216         .prcm = {
 217                 .omap4 = {
 218                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220                 },
 221         },
 222 };
 223
 224 /* l4_per */
 225 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226         .name           = "l4_per",
 227         .class          = &omap44xx_l4_hwmod_class,
 228         .clkdm_name     = "l4_per_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233                 },
 234         },
 235 };
 236
 237 /* l4_wkup */
 238 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239         .name           = "l4_wkup",
 240         .class          = &omap44xx_l4_hwmod_class,
 241         .clkdm_name     = "l4_wkup_clkdm",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'mpu_bus' class
 252  * instance(s): mpu_private
 253  */
 254 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255         .name   = "mpu_bus",
 256 };
 257
 258 /* mpu_private */
 259 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260         .name           = "mpu_private",
 261         .class          = &omap44xx_mpu_bus_hwmod_class,
 262         .clkdm_name     = "mpuss_clkdm",
 263 };
 264
 265 /*
 266  * 'ocp_wp_noc' class
 267  * instance(s): ocp_wp_noc
 268  */
 269 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270         .name   = "ocp_wp_noc",
 271 };
 272
 273 /* ocp_wp_noc */
 274 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275         .name           = "ocp_wp_noc",
 276         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 277         .clkdm_name     = "l3_instr_clkdm",
 278         .prcm = {
 279                 .omap4 = {
 280                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282                         .modulemode   = MODULEMODE_HWCTRL,
 283                 },
 284         },
 285 };
 286
 287 /*
 288  * Modules omap_hwmod structures
 289  *
 290  * The following IPs are excluded for the moment because:
 291  * - They do not need an explicit SW control using omap_hwmod API.
 292  * - They still need to be validated with the driver
 293  *   properly adapted to omap_hwmod / omap_device
 294  *
 295  * usim
 296  */
 297
 298 /*
 299  * 'aess' class
 300  * audio engine sub system
 301  */
 302
 303 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 304         .rev_offs       = 0x0000,
 305         .sysc_offs      = 0x0010,
 306         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 308                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 309                            MSTANDBY_SMART_WKUP),
 310         .sysc_fields    = &omap_hwmod_sysc_type2,
 311 };
 312
 313 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 314         .name   = "aess",
 315         .sysc   = &omap44xx_aess_sysc,
 316 };
 317
 318 /* aess */
 319 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 320         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 321         { .irq = -1 }
 322 };
 323
 324 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 325         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 326         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 327         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 328         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 329         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 330         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 331         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 332         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 333         { .dma_req = -1 }
 334 };
 335
 336 static struct omap_hwmod omap44xx_aess_hwmod = {
 337         .name           = "aess",
 338         .class          = &omap44xx_aess_hwmod_class,
 339         .clkdm_name     = "abe_clkdm",
 340         .mpu_irqs       = omap44xx_aess_irqs,
 341         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 342         .main_clk       = "aess_fck",
 343         .prcm = {
 344                 .omap4 = {
 345                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 346                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 347                         .modulemode   = MODULEMODE_SWCTRL,
 348                 },
 349         },
 350 };
 351
 352 /*
 353  * 'c2c' class
 354  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 355  * soc
 356  */
 357
 358 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 359         .name   = "c2c",
 360 };
 361
 362 /* c2c */
 363 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 364         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 365         { .irq = -1 }
 366 };
 367
 368 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 369         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 370         { .dma_req = -1 }
 371 };
 372
 373 static struct omap_hwmod omap44xx_c2c_hwmod = {
 374         .name           = "c2c",
 375         .class          = &omap44xx_c2c_hwmod_class,
 376         .clkdm_name     = "d2d_clkdm",
 377         .mpu_irqs       = omap44xx_c2c_irqs,
 378         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 382                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 383                 },
 384         },
 385 };
 386
 387 /*
 388  * 'counter' class
 389  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 390  */
 391
 392 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 393         .rev_offs       = 0x0000,
 394         .sysc_offs      = 0x0004,
 395         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 396         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 397         .sysc_fields    = &omap_hwmod_sysc_type1,
 398 };
 399
 400 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 401         .name   = "counter",
 402         .sysc   = &omap44xx_counter_sysc,
 403 };
 404
 405 /* counter_32k */
 406 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 407         .name           = "counter_32k",
 408         .class          = &omap44xx_counter_hwmod_class,
 409         .clkdm_name     = "l4_wkup_clkdm",
 410         .flags          = HWMOD_SWSUP_SIDLE,
 411         .main_clk       = "sys_32k_ck",
 412         .prcm = {
 413                 .omap4 = {
 414                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 415                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 416                 },
 417         },
 418 };
 419
 420 /*
 421  * 'ctrl_module' class
 422  * attila core control module + core pad control module + wkup pad control
 423  * module + attila wkup control module
 424  */
 425
 426 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 427         .rev_offs       = 0x0000,
 428         .sysc_offs      = 0x0010,
 429         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 430         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 431                            SIDLE_SMART_WKUP),
 432         .sysc_fields    = &omap_hwmod_sysc_type2,
 433 };
 434
 435 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 436         .name   = "ctrl_module",
 437         .sysc   = &omap44xx_ctrl_module_sysc,
 438 };
 439
 440 /* ctrl_module_core */
 441 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 442         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 443         { .irq = -1 }
 444 };
 445
 446 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 447         .name           = "ctrl_module_core",
 448         .class          = &omap44xx_ctrl_module_hwmod_class,
 449         .clkdm_name     = "l4_cfg_clkdm",
 450         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 451 };
 452
 453 /* ctrl_module_pad_core */
 454 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 455         .name           = "ctrl_module_pad_core",
 456         .class          = &omap44xx_ctrl_module_hwmod_class,
 457         .clkdm_name     = "l4_cfg_clkdm",
 458 };
 459
 460 /* ctrl_module_wkup */
 461 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 462         .name           = "ctrl_module_wkup",
 463         .class          = &omap44xx_ctrl_module_hwmod_class,
 464         .clkdm_name     = "l4_wkup_clkdm",
 465 };
 466
 467 /* ctrl_module_pad_wkup */
 468 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 469         .name           = "ctrl_module_pad_wkup",
 470         .class          = &omap44xx_ctrl_module_hwmod_class,
 471         .clkdm_name     = "l4_wkup_clkdm",
 472 };
 473
 474 /*
 475  * 'debugss' class
 476  * debug and emulation sub system
 477  */
 478
 479 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 480         .name   = "debugss",
 481 };
 482
 483 /* debugss */
 484 static struct omap_hwmod omap44xx_debugss_hwmod = {
 485         .name           = "debugss",
 486         .class          = &omap44xx_debugss_hwmod_class,
 487         .clkdm_name     = "emu_sys_clkdm",
 488         .main_clk       = "trace_clk_div_ck",
 489         .prcm = {
 490                 .omap4 = {
 491                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 492                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 493                 },
 494         },
 495 };
 496
 497 /*
 498  * 'dma' class
 499  * dma controller for data exchange between memory to memory (i.e. internal or
 500  * external memory) and gp peripherals to memory or memory to gp peripherals
 501  */
 502
 503 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 504         .rev_offs       = 0x0000,
 505         .sysc_offs      = 0x002c,
 506         .syss_offs      = 0x0028,
 507         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 508                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 509                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 510                            SYSS_HAS_RESET_STATUS),
 511         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 512                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 513         .sysc_fields    = &omap_hwmod_sysc_type1,
 514 };
 515
 516 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 517         .name   = "dma",
 518         .sysc   = &omap44xx_dma_sysc,
 519 };
 520
 521 /* dma dev_attr */
 522 static struct omap_dma_dev_attr dma_dev_attr = {
 523         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 524                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 525         .lch_count      = 32,
 526 };
 527
 528 /* dma_system */
 529 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 530         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 531         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 532         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 533         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 534         { .irq = -1 }
 535 };
 536
 537 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 538         .name           = "dma_system",
 539         .class          = &omap44xx_dma_hwmod_class,
 540         .clkdm_name     = "l3_dma_clkdm",
 541         .mpu_irqs       = omap44xx_dma_system_irqs,
 542         .main_clk       = "l3_div_ck",
 543         .prcm = {
 544                 .omap4 = {
 545                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 546                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 547                 },
 548         },
 549         .dev_attr       = &dma_dev_attr,
 550 };
 551
 552 /*
 553  * 'dmic' class
 554  * digital microphone controller
 555  */
 556
 557 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 558         .rev_offs       = 0x0000,
 559         .sysc_offs      = 0x0010,
 560         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 561                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 562         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 563                            SIDLE_SMART_WKUP),
 564         .sysc_fields    = &omap_hwmod_sysc_type2,
 565 };
 566
 567 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 568         .name   = "dmic",
 569         .sysc   = &omap44xx_dmic_sysc,
 570 };
 571
 572 /* dmic */
 573 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 574         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 575         { .irq = -1 }
 576 };
 577
 578 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 579         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 580         { .dma_req = -1 }
 581 };
 582
 583 static struct omap_hwmod omap44xx_dmic_hwmod = {
 584         .name           = "dmic",
 585         .class          = &omap44xx_dmic_hwmod_class,
 586         .clkdm_name     = "abe_clkdm",
 587         .mpu_irqs       = omap44xx_dmic_irqs,
 588         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 589         .main_clk       = "dmic_fck",
 590         .prcm = {
 591                 .omap4 = {
 592                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 593                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 594                         .modulemode   = MODULEMODE_SWCTRL,
 595                 },
 596         },
 597 };
 598
 599 /*
 600  * 'dsp' class
 601  * dsp sub-system
 602  */
 603
 604 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 605         .name   = "dsp",
 606 };
 607
 608 /* dsp */
 609 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 610         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 611         { .irq = -1 }
 612 };
 613
 614 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 615         { .name = "dsp", .rst_shift = 0 },
 616         { .name = "mmu_cache", .rst_shift = 1 },
 617 };
 618
 619 static struct omap_hwmod omap44xx_dsp_hwmod = {
 620         .name           = "dsp",
 621         .class          = &omap44xx_dsp_hwmod_class,
 622         .clkdm_name     = "tesla_clkdm",
 623         .mpu_irqs       = omap44xx_dsp_irqs,
 624         .rst_lines      = omap44xx_dsp_resets,
 625         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 626         .main_clk       = "dsp_fck",
 627         .prcm = {
 628                 .omap4 = {
 629                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 630                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 631                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 632                         .modulemode   = MODULEMODE_HWCTRL,
 633                 },
 634         },
 635 };
 636
 637 /*
 638  * 'dss' class
 639  * display sub-system
 640  */
 641
 642 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 643         .rev_offs       = 0x0000,
 644         .syss_offs      = 0x0014,
 645         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 646 };
 647
 648 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 649         .name   = "dss",
 650         .sysc   = &omap44xx_dss_sysc,
 651         .reset  = omap_dss_reset,
 652 };
 653
 654 /* dss */
 655 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 656         { .role = "sys_clk", .clk = "dss_sys_clk" },
 657         { .role = "tv_clk", .clk = "dss_tv_clk" },
 658         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 659 };
 660
 661 static struct omap_hwmod omap44xx_dss_hwmod = {
 662         .name           = "dss_core",
 663         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 664         .class          = &omap44xx_dss_hwmod_class,
 665         .clkdm_name     = "l3_dss_clkdm",
 666         .main_clk       = "dss_dss_clk",
 667         .prcm = {
 668                 .omap4 = {
 669                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 670                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 671                 },
 672         },
 673         .opt_clks       = dss_opt_clks,
 674         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 675 };
 676
 677 /*
 678  * 'dispc' class
 679  * display controller
 680  */
 681
 682 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 683         .rev_offs       = 0x0000,
 684         .sysc_offs      = 0x0010,
 685         .syss_offs      = 0x0014,
 686         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 687                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 688                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 689                            SYSS_HAS_RESET_STATUS),
 690         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 691                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 692         .sysc_fields    = &omap_hwmod_sysc_type1,
 693 };
 694
 695 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 696         .name   = "dispc",
 697         .sysc   = &omap44xx_dispc_sysc,
 698 };
 699
 700 /* dss_dispc */
 701 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 702         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 703         { .irq = -1 }
 704 };
 705
 706 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 707         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 708         { .dma_req = -1 }
 709 };
 710
 711 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 712         .manager_count          = 3,
 713         .has_framedonetv_irq    = 1
 714 };
 715
 716 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 717         .name           = "dss_dispc",
 718         .class          = &omap44xx_dispc_hwmod_class,
 719         .clkdm_name     = "l3_dss_clkdm",
 720         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 721         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 722         .main_clk       = "dss_dss_clk",
 723         .prcm = {
 724                 .omap4 = {
 725                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 726                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 727                 },
 728         },
 729         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 730 };
 731
 732 /*
 733  * 'dsi' class
 734  * display serial interface controller
 735  */
 736
 737 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 738         .rev_offs       = 0x0000,
 739         .sysc_offs      = 0x0010,
 740         .syss_offs      = 0x0014,
 741         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 742                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 743                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 744         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 745         .sysc_fields    = &omap_hwmod_sysc_type1,
 746 };
 747
 748 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 749         .name   = "dsi",
 750         .sysc   = &omap44xx_dsi_sysc,
 751 };
 752
 753 /* dss_dsi1 */
 754 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 755         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 756         { .irq = -1 }
 757 };
 758
 759 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 760         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 761         { .dma_req = -1 }
 762 };
 763
 764 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 765         { .role = "sys_clk", .clk = "dss_sys_clk" },
 766 };
 767
 768 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 769         .name           = "dss_dsi1",
 770         .class          = &omap44xx_dsi_hwmod_class,
 771         .clkdm_name     = "l3_dss_clkdm",
 772         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 773         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 774         .main_clk       = "dss_dss_clk",
 775         .prcm = {
 776                 .omap4 = {
 777                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 778                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 779                 },
 780         },
 781         .opt_clks       = dss_dsi1_opt_clks,
 782         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 783 };
 784
 785 /* dss_dsi2 */
 786 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 787         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 788         { .irq = -1 }
 789 };
 790
 791 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 792         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 793         { .dma_req = -1 }
 794 };
 795
 796 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 797         { .role = "sys_clk", .clk = "dss_sys_clk" },
 798 };
 799
 800 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 801         .name           = "dss_dsi2",
 802         .class          = &omap44xx_dsi_hwmod_class,
 803         .clkdm_name     = "l3_dss_clkdm",
 804         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 805         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 806         .main_clk       = "dss_dss_clk",
 807         .prcm = {
 808                 .omap4 = {
 809                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 810                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 811                 },
 812         },
 813         .opt_clks       = dss_dsi2_opt_clks,
 814         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 815 };
 816
 817 /*
 818  * 'hdmi' class
 819  * hdmi controller
 820  */
 821
 822 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 823         .rev_offs       = 0x0000,
 824         .sysc_offs      = 0x0010,
 825         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 826                            SYSC_HAS_SOFTRESET),
 827         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 828                            SIDLE_SMART_WKUP),
 829         .sysc_fields    = &omap_hwmod_sysc_type2,
 830 };
 831
 832 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 833         .name   = "hdmi",
 834         .sysc   = &omap44xx_hdmi_sysc,
 835 };
 836
 837 /* dss_hdmi */
 838 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 839         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 840         { .irq = -1 }
 841 };
 842
 843 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 844         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 845         { .dma_req = -1 }
 846 };
 847
 848 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 849         { .role = "sys_clk", .clk = "dss_sys_clk" },
 850 };
 851
 852 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 853         .name           = "dss_hdmi",
 854         .class          = &omap44xx_hdmi_hwmod_class,
 855         .clkdm_name     = "l3_dss_clkdm",
 856         /*
 857          * HDMI audio requires to use no-idle mode. Hence,
 858          * set idle mode by software.
 859          */
 860         .flags          = HWMOD_SWSUP_SIDLE,
 861         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 862         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 863         .main_clk       = "dss_48mhz_clk",
 864         .prcm = {
 865                 .omap4 = {
 866                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 867                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 868                 },
 869         },
 870         .opt_clks       = dss_hdmi_opt_clks,
 871         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 872 };
 873
 874 /*
 875  * 'rfbi' class
 876  * remote frame buffer interface
 877  */
 878
 879 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 880         .rev_offs       = 0x0000,
 881         .sysc_offs      = 0x0010,
 882         .syss_offs      = 0x0014,
 883         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 884                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 885         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 886         .sysc_fields    = &omap_hwmod_sysc_type1,
 887 };
 888
 889 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 890         .name   = "rfbi",
 891         .sysc   = &omap44xx_rfbi_sysc,
 892 };
 893
 894 /* dss_rfbi */
 895 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 896         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 897         { .dma_req = -1 }
 898 };
 899
 900 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 901         { .role = "ick", .clk = "dss_fck" },
 902 };
 903
 904 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 905         .name           = "dss_rfbi",
 906         .class          = &omap44xx_rfbi_hwmod_class,
 907         .clkdm_name     = "l3_dss_clkdm",
 908         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 909         .main_clk       = "dss_dss_clk",
 910         .prcm = {
 911                 .omap4 = {
 912                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 913                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 914                 },
 915         },
 916         .opt_clks       = dss_rfbi_opt_clks,
 917         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 918 };
 919
 920 /*
 921  * 'venc' class
 922  * video encoder
 923  */
 924
 925 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 926         .name   = "venc",
 927 };
 928
 929 /* dss_venc */
 930 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 931         .name           = "dss_venc",
 932         .class          = &omap44xx_venc_hwmod_class,
 933         .clkdm_name     = "l3_dss_clkdm",
 934         .main_clk       = "dss_tv_clk",
 935         .prcm = {
 936                 .omap4 = {
 937                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 938                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 939                 },
 940         },
 941 };
 942
 943 /*
 944  * 'elm' class
 945  * bch error location module
 946  */
 947
 948 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 949         .rev_offs       = 0x0000,
 950         .sysc_offs      = 0x0010,
 951         .syss_offs      = 0x0014,
 952         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 953                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 954                            SYSS_HAS_RESET_STATUS),
 955         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 956         .sysc_fields    = &omap_hwmod_sysc_type1,
 957 };
 958
 959 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 960         .name   = "elm",
 961         .sysc   = &omap44xx_elm_sysc,
 962 };
 963
 964 /* elm */
 965 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 966         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 967         { .irq = -1 }
 968 };
 969
 970 static struct omap_hwmod omap44xx_elm_hwmod = {
 971         .name           = "elm",
 972         .class          = &omap44xx_elm_hwmod_class,
 973         .clkdm_name     = "l4_per_clkdm",
 974         .mpu_irqs       = omap44xx_elm_irqs,
 975         .prcm = {
 976                 .omap4 = {
 977                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 978                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 979                 },
 980         },
 981 };
 982
 983 /*
 984  * 'emif' class
 985  * external memory interface no1
 986  */
 987
 988 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 989         .rev_offs       = 0x0000,
 990 };
 991
 992 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 993         .name   = "emif",
 994         .sysc   = &omap44xx_emif_sysc,
 995 };
 996
 997 /* emif1 */
 998 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 999         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1000         { .irq = -1 }
1001 };
1002
1003 static struct omap_hwmod omap44xx_emif1_hwmod = {
1004         .name           = "emif1",
1005         .class          = &omap44xx_emif_hwmod_class,
1006         .clkdm_name     = "l3_emif_clkdm",
1007         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1008         .mpu_irqs       = omap44xx_emif1_irqs,
1009         .main_clk       = "ddrphy_ck",
1010         .prcm = {
1011                 .omap4 = {
1012                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1013                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1014                         .modulemode   = MODULEMODE_HWCTRL,
1015                 },
1016         },
1017 };
1018
1019 /* emif2 */
1020 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1021         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1022         { .irq = -1 }
1023 };
1024
1025 static struct omap_hwmod omap44xx_emif2_hwmod = {
1026         .name           = "emif2",
1027         .class          = &omap44xx_emif_hwmod_class,
1028         .clkdm_name     = "l3_emif_clkdm",
1029         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030         .mpu_irqs       = omap44xx_emif2_irqs,
1031         .main_clk       = "ddrphy_ck",
1032         .prcm = {
1033                 .omap4 = {
1034                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1035                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1036                         .modulemode   = MODULEMODE_HWCTRL,
1037                 },
1038         },
1039 };
1040
1041 /*
1042  * 'fdif' class
1043  * face detection hw accelerator module
1044  */
1045
1046 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1047         .rev_offs       = 0x0000,
1048         .sysc_offs      = 0x0010,
1049         /*
1050          * FDIF needs 100 OCP clk cycles delay after a softreset before
1051          * accessing sysconfig again.
1052          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1053          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1054          *
1055          * TODO: Indicate errata when available.
1056          */
1057         .srst_udelay    = 2,
1058         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1059                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1060         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1061                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1062         .sysc_fields    = &omap_hwmod_sysc_type2,
1063 };
1064
1065 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1066         .name   = "fdif",
1067         .sysc   = &omap44xx_fdif_sysc,
1068 };
1069
1070 /* fdif */
1071 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1072         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1073         { .irq = -1 }
1074 };
1075
1076 static struct omap_hwmod omap44xx_fdif_hwmod = {
1077         .name           = "fdif",
1078         .class          = &omap44xx_fdif_hwmod_class,
1079         .clkdm_name     = "iss_clkdm",
1080         .mpu_irqs       = omap44xx_fdif_irqs,
1081         .main_clk       = "fdif_fck",
1082         .prcm = {
1083                 .omap4 = {
1084                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1085                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1086                         .modulemode   = MODULEMODE_SWCTRL,
1087                 },
1088         },
1089 };
1090
1091 /*
1092  * 'gpio' class
1093  * general purpose io module
1094  */
1095
1096 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1097         .rev_offs       = 0x0000,
1098         .sysc_offs      = 0x0010,
1099         .syss_offs      = 0x0114,
1100         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1101                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1102                            SYSS_HAS_RESET_STATUS),
1103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1104                            SIDLE_SMART_WKUP),
1105         .sysc_fields    = &omap_hwmod_sysc_type1,
1106 };
1107
1108 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1109         .name   = "gpio",
1110         .sysc   = &omap44xx_gpio_sysc,
1111         .rev    = 2,
1112 };
1113
1114 /* gpio dev_attr */
1115 static struct omap_gpio_dev_attr gpio_dev_attr = {
1116         .bank_width     = 32,
1117         .dbck_flag      = true,
1118 };
1119
1120 /* gpio1 */
1121 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1122         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1123         { .irq = -1 }
1124 };
1125
1126 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1127         { .role = "dbclk", .clk = "gpio1_dbclk" },
1128 };
1129
1130 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1131         .name           = "gpio1",
1132         .class          = &omap44xx_gpio_hwmod_class,
1133         .clkdm_name     = "l4_wkup_clkdm",
1134         .mpu_irqs       = omap44xx_gpio1_irqs,
1135         .main_clk       = "gpio1_ick",
1136         .prcm = {
1137                 .omap4 = {
1138                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1139                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1140                         .modulemode   = MODULEMODE_HWCTRL,
1141                 },
1142         },
1143         .opt_clks       = gpio1_opt_clks,
1144         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1145         .dev_attr       = &gpio_dev_attr,
1146 };
1147
1148 /* gpio2 */
1149 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1150         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1151         { .irq = -1 }
1152 };
1153
1154 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1155         { .role = "dbclk", .clk = "gpio2_dbclk" },
1156 };
1157
1158 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1159         .name           = "gpio2",
1160         .class          = &omap44xx_gpio_hwmod_class,
1161         .clkdm_name     = "l4_per_clkdm",
1162         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1163         .mpu_irqs       = omap44xx_gpio2_irqs,
1164         .main_clk       = "gpio2_ick",
1165         .prcm = {
1166                 .omap4 = {
1167                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .opt_clks       = gpio2_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1174         .dev_attr       = &gpio_dev_attr,
1175 };
1176
1177 /* gpio3 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1179         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1180         { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio3_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1188         .name           = "gpio3",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .mpu_irqs       = omap44xx_gpio3_irqs,
1193         .main_clk       = "gpio3_ick",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio3_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio4 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1208         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1209         { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio4_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1217         .name           = "gpio4",
1218         .class          = &omap44xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4_per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .mpu_irqs       = omap44xx_gpio4_irqs,
1222         .main_clk       = "gpio4_ick",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1226                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1227                         .modulemode   = MODULEMODE_HWCTRL,
1228                 },
1229         },
1230         .opt_clks       = gpio4_opt_clks,
1231         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1232         .dev_attr       = &gpio_dev_attr,
1233 };
1234
1235 /* gpio5 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1237         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1238         { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1242         { .role = "dbclk", .clk = "gpio5_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1246         .name           = "gpio5",
1247         .class          = &omap44xx_gpio_hwmod_class,
1248         .clkdm_name     = "l4_per_clkdm",
1249         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250         .mpu_irqs       = omap44xx_gpio5_irqs,
1251         .main_clk       = "gpio5_ick",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1256                         .modulemode   = MODULEMODE_HWCTRL,
1257                 },
1258         },
1259         .opt_clks       = gpio5_opt_clks,
1260         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1261         .dev_attr       = &gpio_dev_attr,
1262 };
1263
1264 /* gpio6 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1266         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1267         { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1271         { .role = "dbclk", .clk = "gpio6_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1275         .name           = "gpio6",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .clkdm_name     = "l4_per_clkdm",
1278         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279         .mpu_irqs       = omap44xx_gpio6_irqs,
1280         .main_clk       = "gpio6_ick",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_HWCTRL,
1286                 },
1287         },
1288         .opt_clks       = gpio6_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1290         .dev_attr       = &gpio_dev_attr,
1291 };
1292
1293 /*
1294  * 'gpmc' class
1295  * general purpose memory controller
1296  */
1297
1298 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1299         .rev_offs       = 0x0000,
1300         .sysc_offs      = 0x0010,
1301         .syss_offs      = 0x0014,
1302         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1303                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1304         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1305         .sysc_fields    = &omap_hwmod_sysc_type1,
1306 };
1307
1308 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1309         .name   = "gpmc",
1310         .sysc   = &omap44xx_gpmc_sysc,
1311 };
1312
1313 /* gpmc */
1314 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1315         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1316         { .irq = -1 }
1317 };
1318
1319 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1320         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1321         { .dma_req = -1 }
1322 };
1323
1324 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1325         .name           = "gpmc",
1326         .class          = &omap44xx_gpmc_hwmod_class,
1327         .clkdm_name     = "l3_2_clkdm",
1328         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1329         .mpu_irqs       = omap44xx_gpmc_irqs,
1330         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1331         .prcm = {
1332                 .omap4 = {
1333                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1334                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1335                         .modulemode   = MODULEMODE_HWCTRL,
1336                 },
1337         },
1338 };
1339
1340 /*
1341  * 'gpu' class
1342  * 2d/3d graphics accelerator
1343  */
1344
1345 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1346         .rev_offs       = 0x1fc00,
1347         .sysc_offs      = 0x1fc10,
1348         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1349         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352         .sysc_fields    = &omap_hwmod_sysc_type2,
1353 };
1354
1355 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1356         .name   = "gpu",
1357         .sysc   = &omap44xx_gpu_sysc,
1358 };
1359
1360 /* gpu */
1361 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1362         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1363         { .irq = -1 }
1364 };
1365
1366 static struct omap_hwmod omap44xx_gpu_hwmod = {
1367         .name           = "gpu",
1368         .class          = &omap44xx_gpu_hwmod_class,
1369         .clkdm_name     = "l3_gfx_clkdm",
1370         .mpu_irqs       = omap44xx_gpu_irqs,
1371         .main_clk       = "gpu_fck",
1372         .prcm = {
1373                 .omap4 = {
1374                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1375                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1376                         .modulemode   = MODULEMODE_SWCTRL,
1377                 },
1378         },
1379 };
1380
1381 /*
1382  * 'hdq1w' class
1383  * hdq / 1-wire serial interface controller
1384  */
1385
1386 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1387         .rev_offs       = 0x0000,
1388         .sysc_offs      = 0x0014,
1389         .syss_offs      = 0x0018,
1390         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1391                            SYSS_HAS_RESET_STATUS),
1392         .sysc_fields    = &omap_hwmod_sysc_type1,
1393 };
1394
1395 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1396         .name   = "hdq1w",
1397         .sysc   = &omap44xx_hdq1w_sysc,
1398 };
1399
1400 /* hdq1w */
1401 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1402         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1403         { .irq = -1 }
1404 };
1405
1406 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1407         .name           = "hdq1w",
1408         .class          = &omap44xx_hdq1w_hwmod_class,
1409         .clkdm_name     = "l4_per_clkdm",
1410         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1411         .mpu_irqs       = omap44xx_hdq1w_irqs,
1412         .main_clk       = "hdq1w_fck",
1413         .prcm = {
1414                 .omap4 = {
1415                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1416                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1417                         .modulemode   = MODULEMODE_SWCTRL,
1418                 },
1419         },
1420 };
1421
1422 /*
1423  * 'hsi' class
1424  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1425  * serial if)
1426  */
1427
1428 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1429         .rev_offs       = 0x0000,
1430         .sysc_offs      = 0x0010,
1431         .syss_offs      = 0x0014,
1432         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1433                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1434                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1435         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1436                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1437                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1438         .sysc_fields    = &omap_hwmod_sysc_type1,
1439 };
1440
1441 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1442         .name   = "hsi",
1443         .sysc   = &omap44xx_hsi_sysc,
1444 };
1445
1446 /* hsi */
1447 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1448         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1449         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1450         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1451         { .irq = -1 }
1452 };
1453
1454 static struct omap_hwmod omap44xx_hsi_hwmod = {
1455         .name           = "hsi",
1456         .class          = &omap44xx_hsi_hwmod_class,
1457         .clkdm_name     = "l3_init_clkdm",
1458         .mpu_irqs       = omap44xx_hsi_irqs,
1459         .main_clk       = "hsi_fck",
1460         .prcm = {
1461                 .omap4 = {
1462                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1463                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1464                         .modulemode   = MODULEMODE_HWCTRL,
1465                 },
1466         },
1467 };
1468
1469 /*
1470  * 'i2c' class
1471  * multimaster high-speed i2c controller
1472  */
1473
1474 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1475         .sysc_offs      = 0x0010,
1476         .syss_offs      = 0x0090,
1477         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1478                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1479                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1480         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1481                            SIDLE_SMART_WKUP),
1482         .clockact       = CLOCKACT_TEST_ICLK,
1483         .sysc_fields    = &omap_hwmod_sysc_type1,
1484 };
1485
1486 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1487         .name   = "i2c",
1488         .sysc   = &omap44xx_i2c_sysc,
1489         .rev    = OMAP_I2C_IP_VERSION_2,
1490         .reset  = &omap_i2c_reset,
1491 };
1492
1493 static struct omap_i2c_dev_attr i2c_dev_attr = {
1494         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1495                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1496 };
1497
1498 /* i2c1 */
1499 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1500         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1501         { .irq = -1 }
1502 };
1503
1504 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1505         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1506         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1507         { .dma_req = -1 }
1508 };
1509
1510 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1511         .name           = "i2c1",
1512         .class          = &omap44xx_i2c_hwmod_class,
1513         .clkdm_name     = "l4_per_clkdm",
1514         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1515         .mpu_irqs       = omap44xx_i2c1_irqs,
1516         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1517         .main_clk       = "i2c1_fck",
1518         .prcm = {
1519                 .omap4 = {
1520                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1521                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1522                         .modulemode   = MODULEMODE_SWCTRL,
1523                 },
1524         },
1525         .dev_attr       = &i2c_dev_attr,
1526 };
1527
1528 /* i2c2 */
1529 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1530         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1531         { .irq = -1 }
1532 };
1533
1534 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1535         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1536         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1537         { .dma_req = -1 }
1538 };
1539
1540 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1541         .name           = "i2c2",
1542         .class          = &omap44xx_i2c_hwmod_class,
1543         .clkdm_name     = "l4_per_clkdm",
1544         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1545         .mpu_irqs       = omap44xx_i2c2_irqs,
1546         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1547         .main_clk       = "i2c2_fck",
1548         .prcm = {
1549                 .omap4 = {
1550                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1551                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1552                         .modulemode   = MODULEMODE_SWCTRL,
1553                 },
1554         },
1555         .dev_attr       = &i2c_dev_attr,
1556 };
1557
1558 /* i2c3 */
1559 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1560         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1561         { .irq = -1 }
1562 };
1563
1564 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1565         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1566         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1567         { .dma_req = -1 }
1568 };
1569
1570 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1571         .name           = "i2c3",
1572         .class          = &omap44xx_i2c_hwmod_class,
1573         .clkdm_name     = "l4_per_clkdm",
1574         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1575         .mpu_irqs       = omap44xx_i2c3_irqs,
1576         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1577         .main_clk       = "i2c3_fck",
1578         .prcm = {
1579                 .omap4 = {
1580                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1581                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1582                         .modulemode   = MODULEMODE_SWCTRL,
1583                 },
1584         },
1585         .dev_attr       = &i2c_dev_attr,
1586 };
1587
1588 /* i2c4 */
1589 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1590         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1591         { .irq = -1 }
1592 };
1593
1594 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1595         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1596         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1597         { .dma_req = -1 }
1598 };
1599
1600 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1601         .name           = "i2c4",
1602         .class          = &omap44xx_i2c_hwmod_class,
1603         .clkdm_name     = "l4_per_clkdm",
1604         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1605         .mpu_irqs       = omap44xx_i2c4_irqs,
1606         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1607         .main_clk       = "i2c4_fck",
1608         .prcm = {
1609                 .omap4 = {
1610                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1611                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1612                         .modulemode   = MODULEMODE_SWCTRL,
1613                 },
1614         },
1615         .dev_attr       = &i2c_dev_attr,
1616 };
1617
1618 /*
1619  * 'ipu' class
1620  * imaging processor unit
1621  */
1622
1623 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1624         .name   = "ipu",
1625 };
1626
1627 /* ipu */
1628 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1629         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1630         { .irq = -1 }
1631 };
1632
1633 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1634         { .name = "cpu0", .rst_shift = 0 },
1635         { .name = "cpu1", .rst_shift = 1 },
1636         { .name = "mmu_cache", .rst_shift = 2 },
1637 };
1638
1639 static struct omap_hwmod omap44xx_ipu_hwmod = {
1640         .name           = "ipu",
1641         .class          = &omap44xx_ipu_hwmod_class,
1642         .clkdm_name     = "ducati_clkdm",
1643         .mpu_irqs       = omap44xx_ipu_irqs,
1644         .rst_lines      = omap44xx_ipu_resets,
1645         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1646         .main_clk       = "ipu_fck",
1647         .prcm = {
1648                 .omap4 = {
1649                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1650                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1651                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1652                         .modulemode   = MODULEMODE_HWCTRL,
1653                 },
1654         },
1655 };
1656
1657 /*
1658  * 'iss' class
1659  * external images sensor pixel data processor
1660  */
1661
1662 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1663         .rev_offs       = 0x0000,
1664         .sysc_offs      = 0x0010,
1665         /*
1666          * ISS needs 100 OCP clk cycles delay after a softreset before
1667          * accessing sysconfig again.
1668          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1669          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1670          *
1671          * TODO: Indicate errata when available.
1672          */
1673         .srst_udelay    = 2,
1674         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1675                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1676         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1677                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1678                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1679         .sysc_fields    = &omap_hwmod_sysc_type2,
1680 };
1681
1682 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1683         .name   = "iss",
1684         .sysc   = &omap44xx_iss_sysc,
1685 };
1686
1687 /* iss */
1688 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1689         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1690         { .irq = -1 }
1691 };
1692
1693 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1694         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1695         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1696         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1697         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1698         { .dma_req = -1 }
1699 };
1700
1701 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1702         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1703 };
1704
1705 static struct omap_hwmod omap44xx_iss_hwmod = {
1706         .name           = "iss",
1707         .class          = &omap44xx_iss_hwmod_class,
1708         .clkdm_name     = "iss_clkdm",
1709         .mpu_irqs       = omap44xx_iss_irqs,
1710         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1711         .main_clk       = "iss_fck",
1712         .prcm = {
1713                 .omap4 = {
1714                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1715                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1716                         .modulemode   = MODULEMODE_SWCTRL,
1717                 },
1718         },
1719         .opt_clks       = iss_opt_clks,
1720         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1721 };
1722
1723 /*
1724  * 'iva' class
1725  * multi-standard video encoder/decoder hardware accelerator
1726  */
1727
1728 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1729         .name   = "iva",
1730 };
1731
1732 /* iva */
1733 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1734         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1735         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1736         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1737         { .irq = -1 }
1738 };
1739
1740 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1741         { .name = "seq0", .rst_shift = 0 },
1742         { .name = "seq1", .rst_shift = 1 },
1743         { .name = "logic", .rst_shift = 2 },
1744 };
1745
1746 static struct omap_hwmod omap44xx_iva_hwmod = {
1747         .name           = "iva",
1748         .class          = &omap44xx_iva_hwmod_class,
1749         .clkdm_name     = "ivahd_clkdm",
1750         .mpu_irqs       = omap44xx_iva_irqs,
1751         .rst_lines      = omap44xx_iva_resets,
1752         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1753         .main_clk       = "iva_fck",
1754         .prcm = {
1755                 .omap4 = {
1756                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1757                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1758                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1759                         .modulemode   = MODULEMODE_HWCTRL,
1760                 },
1761         },
1762 };
1763
1764 /*
1765  * 'kbd' class
1766  * keyboard controller
1767  */
1768
1769 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1770         .rev_offs       = 0x0000,
1771         .sysc_offs      = 0x0010,
1772         .syss_offs      = 0x0014,
1773         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1774                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1775                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1776                            SYSS_HAS_RESET_STATUS),
1777         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1778         .sysc_fields    = &omap_hwmod_sysc_type1,
1779 };
1780
1781 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1782         .name   = "kbd",
1783         .sysc   = &omap44xx_kbd_sysc,
1784 };
1785
1786 /* kbd */
1787 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1788         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1789         { .irq = -1 }
1790 };
1791
1792 static struct omap_hwmod omap44xx_kbd_hwmod = {
1793         .name           = "kbd",
1794         .class          = &omap44xx_kbd_hwmod_class,
1795         .clkdm_name     = "l4_wkup_clkdm",
1796         .mpu_irqs       = omap44xx_kbd_irqs,
1797         .main_clk       = "kbd_fck",
1798         .prcm = {
1799                 .omap4 = {
1800                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1801                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1802                         .modulemode   = MODULEMODE_SWCTRL,
1803                 },
1804         },
1805 };
1806
1807 /*
1808  * 'mailbox' class
1809  * mailbox module allowing communication between the on-chip processors using a
1810  * queued mailbox-interrupt mechanism.
1811  */
1812
1813 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1814         .rev_offs       = 0x0000,
1815         .sysc_offs      = 0x0010,
1816         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1817                            SYSC_HAS_SOFTRESET),
1818         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1819         .sysc_fields    = &omap_hwmod_sysc_type2,
1820 };
1821
1822 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1823         .name   = "mailbox",
1824         .sysc   = &omap44xx_mailbox_sysc,
1825 };
1826
1827 /* mailbox */
1828 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1829         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1830         { .irq = -1 }
1831 };
1832
1833 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1834         .name           = "mailbox",
1835         .class          = &omap44xx_mailbox_hwmod_class,
1836         .clkdm_name     = "l4_cfg_clkdm",
1837         .mpu_irqs       = omap44xx_mailbox_irqs,
1838         .prcm = {
1839                 .omap4 = {
1840                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1841                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1842                 },
1843         },
1844 };
1845
1846 /*
1847  * 'mcasp' class
1848  * multi-channel audio serial port controller
1849  */
1850
1851 /* The IP is not compliant to type1 / type2 scheme */
1852 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1853         .sidle_shift    = 0,
1854 };
1855
1856 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1857         .sysc_offs      = 0x0004,
1858         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860                            SIDLE_SMART_WKUP),
1861         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1862 };
1863
1864 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1865         .name   = "mcasp",
1866         .sysc   = &omap44xx_mcasp_sysc,
1867 };
1868
1869 /* mcasp */
1870 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1871         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1872         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1873         { .irq = -1 }
1874 };
1875
1876 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1877         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1878         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1879         { .dma_req = -1 }
1880 };
1881
1882 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1883         .name           = "mcasp",
1884         .class          = &omap44xx_mcasp_hwmod_class,
1885         .clkdm_name     = "abe_clkdm",
1886         .mpu_irqs       = omap44xx_mcasp_irqs,
1887         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1888         .main_clk       = "mcasp_fck",
1889         .prcm = {
1890                 .omap4 = {
1891                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1892                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1893                         .modulemode   = MODULEMODE_SWCTRL,
1894                 },
1895         },
1896 };
1897
1898 /*
1899  * 'mcbsp' class
1900  * multi channel buffered serial port controller
1901  */
1902
1903 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1904         .sysc_offs      = 0x008c,
1905         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1906                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1907         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1908         .sysc_fields    = &omap_hwmod_sysc_type1,
1909 };
1910
1911 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1912         .name   = "mcbsp",
1913         .sysc   = &omap44xx_mcbsp_sysc,
1914         .rev    = MCBSP_CONFIG_TYPE4,
1915 };
1916
1917 /* mcbsp1 */
1918 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1919         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1920         { .irq = -1 }
1921 };
1922
1923 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1924         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1925         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1926         { .dma_req = -1 }
1927 };
1928
1929 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1930         { .role = "pad_fck", .clk = "pad_clks_ck" },
1931         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1932 };
1933
1934 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1935         .name           = "mcbsp1",
1936         .class          = &omap44xx_mcbsp_hwmod_class,
1937         .clkdm_name     = "abe_clkdm",
1938         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1939         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1940         .main_clk       = "mcbsp1_fck",
1941         .prcm = {
1942                 .omap4 = {
1943                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1944                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1945                         .modulemode   = MODULEMODE_SWCTRL,
1946                 },
1947         },
1948         .opt_clks       = mcbsp1_opt_clks,
1949         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1950 };
1951
1952 /* mcbsp2 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1954         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1970         .name           = "mcbsp2",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp2_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
1975         .main_clk       = "mcbsp2_fck",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp2_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1985 };
1986
1987 /* mcbsp3 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1989         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2005         .name           = "mcbsp3",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2010         .main_clk       = "mcbsp3_fck",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp3_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2020 };
2021
2022 /* mcbsp4 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2024         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2040         .name           = "mcbsp4",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "l4_per_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2045         .main_clk       = "mcbsp4_fck",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp4_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2055 };
2056
2057 /*
2058  * 'mcpdm' class
2059  * multi channel pdm controller (proprietary interface with phoenix power
2060  * ic)
2061  */
2062
2063 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2064         .rev_offs       = 0x0000,
2065         .sysc_offs      = 0x0010,
2066         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2067                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2069                            SIDLE_SMART_WKUP),
2070         .sysc_fields    = &omap_hwmod_sysc_type2,
2071 };
2072
2073 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2074         .name   = "mcpdm",
2075         .sysc   = &omap44xx_mcpdm_sysc,
2076 };
2077
2078 /* mcpdm */
2079 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2080         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2081         { .irq = -1 }
2082 };
2083
2084 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2085         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2086         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2087         { .dma_req = -1 }
2088 };
2089
2090 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2091         .name           = "mcpdm",
2092         .class          = &omap44xx_mcpdm_hwmod_class,
2093         .clkdm_name     = "abe_clkdm",
2094         .mpu_irqs       = omap44xx_mcpdm_irqs,
2095         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2096         .main_clk       = "mcpdm_fck",
2097         .prcm = {
2098                 .omap4 = {
2099                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2100                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2101                         .modulemode   = MODULEMODE_SWCTRL,
2102                 },
2103         },
2104 };
2105
2106 /*
2107  * 'mcspi' class
2108  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2109  * bus
2110  */
2111
2112 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2113         .rev_offs       = 0x0000,
2114         .sysc_offs      = 0x0010,
2115         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2116                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2117         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2118                            SIDLE_SMART_WKUP),
2119         .sysc_fields    = &omap_hwmod_sysc_type2,
2120 };
2121
2122 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2123         .name   = "mcspi",
2124         .sysc   = &omap44xx_mcspi_sysc,
2125         .rev    = OMAP4_MCSPI_REV,
2126 };
2127
2128 /* mcspi1 */
2129 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2130         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2131         { .irq = -1 }
2132 };
2133
2134 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2135         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2136         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2137         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2138         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2139         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2140         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2141         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2142         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2143         { .dma_req = -1 }
2144 };
2145
2146 /* mcspi1 dev_attr */
2147 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2148         .num_chipselect = 4,
2149 };
2150
2151 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2152         .name           = "mcspi1",
2153         .class          = &omap44xx_mcspi_hwmod_class,
2154         .clkdm_name     = "l4_per_clkdm",
2155         .mpu_irqs       = omap44xx_mcspi1_irqs,
2156         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2157         .main_clk       = "mcspi1_fck",
2158         .prcm = {
2159                 .omap4 = {
2160                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2161                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2162                         .modulemode   = MODULEMODE_SWCTRL,
2163                 },
2164         },
2165         .dev_attr       = &mcspi1_dev_attr,
2166 };
2167
2168 /* mcspi2 */
2169 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2170         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2171         { .irq = -1 }
2172 };
2173
2174 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2175         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2176         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2177         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2178         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2179         { .dma_req = -1 }
2180 };
2181
2182 /* mcspi2 dev_attr */
2183 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2184         .num_chipselect = 2,
2185 };
2186
2187 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2188         .name           = "mcspi2",
2189         .class          = &omap44xx_mcspi_hwmod_class,
2190         .clkdm_name     = "l4_per_clkdm",
2191         .mpu_irqs       = omap44xx_mcspi2_irqs,
2192         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2193         .main_clk       = "mcspi2_fck",
2194         .prcm = {
2195                 .omap4 = {
2196                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2197                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2198                         .modulemode   = MODULEMODE_SWCTRL,
2199                 },
2200         },
2201         .dev_attr       = &mcspi2_dev_attr,
2202 };
2203
2204 /* mcspi3 */
2205 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2206         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2207         { .irq = -1 }
2208 };
2209
2210 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2211         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2212         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2213         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2214         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2215         { .dma_req = -1 }
2216 };
2217
2218 /* mcspi3 dev_attr */
2219 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2220         .num_chipselect = 2,
2221 };
2222
2223 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2224         .name           = "mcspi3",
2225         .class          = &omap44xx_mcspi_hwmod_class,
2226         .clkdm_name     = "l4_per_clkdm",
2227         .mpu_irqs       = omap44xx_mcspi3_irqs,
2228         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2229         .main_clk       = "mcspi3_fck",
2230         .prcm = {
2231                 .omap4 = {
2232                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2233                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2234                         .modulemode   = MODULEMODE_SWCTRL,
2235                 },
2236         },
2237         .dev_attr       = &mcspi3_dev_attr,
2238 };
2239
2240 /* mcspi4 */
2241 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2242         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2243         { .irq = -1 }
2244 };
2245
2246 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2247         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2248         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2249         { .dma_req = -1 }
2250 };
2251
2252 /* mcspi4 dev_attr */
2253 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2254         .num_chipselect = 1,
2255 };
2256
2257 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2258         .name           = "mcspi4",
2259         .class          = &omap44xx_mcspi_hwmod_class,
2260         .clkdm_name     = "l4_per_clkdm",
2261         .mpu_irqs       = omap44xx_mcspi4_irqs,
2262         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2263         .main_clk       = "mcspi4_fck",
2264         .prcm = {
2265                 .omap4 = {
2266                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2267                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2268                         .modulemode   = MODULEMODE_SWCTRL,
2269                 },
2270         },
2271         .dev_attr       = &mcspi4_dev_attr,
2272 };
2273
2274 /*
2275  * 'mmc' class
2276  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2277  */
2278
2279 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2280         .rev_offs       = 0x0000,
2281         .sysc_offs      = 0x0010,
2282         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2283                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2284                            SYSC_HAS_SOFTRESET),
2285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2286                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2287                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2288         .sysc_fields    = &omap_hwmod_sysc_type2,
2289 };
2290
2291 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2292         .name   = "mmc",
2293         .sysc   = &omap44xx_mmc_sysc,
2294 };
2295
2296 /* mmc1 */
2297 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2298         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2299         { .irq = -1 }
2300 };
2301
2302 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2303         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2304         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2305         { .dma_req = -1 }
2306 };
2307
2308 /* mmc1 dev_attr */
2309 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2310         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2311 };
2312
2313 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2314         .name           = "mmc1",
2315         .class          = &omap44xx_mmc_hwmod_class,
2316         .clkdm_name     = "l3_init_clkdm",
2317         .mpu_irqs       = omap44xx_mmc1_irqs,
2318         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2319         .main_clk       = "mmc1_fck",
2320         .prcm = {
2321                 .omap4 = {
2322                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2323                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2324                         .modulemode   = MODULEMODE_SWCTRL,
2325                 },
2326         },
2327         .dev_attr       = &mmc1_dev_attr,
2328 };
2329
2330 /* mmc2 */
2331 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2332         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2333         { .irq = -1 }
2334 };
2335
2336 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2337         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2338         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2339         { .dma_req = -1 }
2340 };
2341
2342 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2343         .name           = "mmc2",
2344         .class          = &omap44xx_mmc_hwmod_class,
2345         .clkdm_name     = "l3_init_clkdm",
2346         .mpu_irqs       = omap44xx_mmc2_irqs,
2347         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2348         .main_clk       = "mmc2_fck",
2349         .prcm = {
2350                 .omap4 = {
2351                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2352                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2353                         .modulemode   = MODULEMODE_SWCTRL,
2354                 },
2355         },
2356 };
2357
2358 /* mmc3 */
2359 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2360         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2361         { .irq = -1 }
2362 };
2363
2364 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2365         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2366         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2367         { .dma_req = -1 }
2368 };
2369
2370 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2371         .name           = "mmc3",
2372         .class          = &omap44xx_mmc_hwmod_class,
2373         .clkdm_name     = "l4_per_clkdm",
2374         .mpu_irqs       = omap44xx_mmc3_irqs,
2375         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2376         .main_clk       = "mmc3_fck",
2377         .prcm = {
2378                 .omap4 = {
2379                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2380                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2381                         .modulemode   = MODULEMODE_SWCTRL,
2382                 },
2383         },
2384 };
2385
2386 /* mmc4 */
2387 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2388         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2389         { .irq = -1 }
2390 };
2391
2392 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2393         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2394         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2395         { .dma_req = -1 }
2396 };
2397
2398 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2399         .name           = "mmc4",
2400         .class          = &omap44xx_mmc_hwmod_class,
2401         .clkdm_name     = "l4_per_clkdm",
2402         .mpu_irqs       = omap44xx_mmc4_irqs,
2403         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2404         .main_clk       = "mmc4_fck",
2405         .prcm = {
2406                 .omap4 = {
2407                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2408                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2409                         .modulemode   = MODULEMODE_SWCTRL,
2410                 },
2411         },
2412 };
2413
2414 /* mmc5 */
2415 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2416         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2417         { .irq = -1 }
2418 };
2419
2420 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2421         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2422         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2423         { .dma_req = -1 }
2424 };
2425
2426 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2427         .name           = "mmc5",
2428         .class          = &omap44xx_mmc_hwmod_class,
2429         .clkdm_name     = "l4_per_clkdm",
2430         .mpu_irqs       = omap44xx_mmc5_irqs,
2431         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2432         .main_clk       = "mmc5_fck",
2433         .prcm = {
2434                 .omap4 = {
2435                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2436                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2437                         .modulemode   = MODULEMODE_SWCTRL,
2438                 },
2439         },
2440 };
2441
2442 /*
2443  * 'mpu' class
2444  * mpu sub-system
2445  */
2446
2447 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2448         .name   = "mpu",
2449 };
2450
2451 /* mpu */
2452 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2453         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2454         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2455         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2456         { .irq = -1 }
2457 };
2458
2459 static struct omap_hwmod omap44xx_mpu_hwmod = {
2460         .name           = "mpu",
2461         .class          = &omap44xx_mpu_hwmod_class,
2462         .clkdm_name     = "mpuss_clkdm",
2463         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2464         .mpu_irqs       = omap44xx_mpu_irqs,
2465         .main_clk       = "dpll_mpu_m2_ck",
2466         .prcm = {
2467                 .omap4 = {
2468                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2469                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2470                 },
2471         },
2472 };
2473
2474 /*
2475  * 'ocmc_ram' class
2476  * top-level core on-chip ram
2477  */
2478
2479 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2480         .name   = "ocmc_ram",
2481 };
2482
2483 /* ocmc_ram */
2484 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2485         .name           = "ocmc_ram",
2486         .class          = &omap44xx_ocmc_ram_hwmod_class,
2487         .clkdm_name     = "l3_2_clkdm",
2488         .prcm = {
2489                 .omap4 = {
2490                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2491                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2492                 },
2493         },
2494 };
2495
2496 /*
2497  * 'ocp2scp' class
2498  * bridge to transform ocp interface protocol to scp (serial control port)
2499  * protocol
2500  */
2501
2502 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2503         .name   = "ocp2scp",
2504 };
2505
2506 /* ocp2scp_usb_phy */
2507 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2508         { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2509 };
2510
2511 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2512         .name           = "ocp2scp_usb_phy",
2513         .class          = &omap44xx_ocp2scp_hwmod_class,
2514         .clkdm_name     = "l3_init_clkdm",
2515         .prcm = {
2516                 .omap4 = {
2517                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2518                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2519                         .modulemode   = MODULEMODE_HWCTRL,
2520                 },
2521         },
2522         .opt_clks       = ocp2scp_usb_phy_opt_clks,
2523         .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2524 };
2525
2526 /*
2527  * 'prcm' class
2528  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2529  * + clock manager 1 (in always on power domain) + local prm in mpu
2530  */
2531
2532 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2533         .name   = "prcm",
2534 };
2535
2536 /* prcm_mpu */
2537 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2538         .name           = "prcm_mpu",
2539         .class          = &omap44xx_prcm_hwmod_class,
2540         .clkdm_name     = "l4_wkup_clkdm",
2541 };
2542
2543 /* cm_core_aon */
2544 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2545         .name           = "cm_core_aon",
2546         .class          = &omap44xx_prcm_hwmod_class,
2547         .clkdm_name     = "cm_clkdm",
2548 };
2549
2550 /* cm_core */
2551 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2552         .name           = "cm_core",
2553         .class          = &omap44xx_prcm_hwmod_class,
2554         .clkdm_name     = "cm_clkdm",
2555 };
2556
2557 /* prm */
2558 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2559         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2560         { .irq = -1 }
2561 };
2562
2563 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2564         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2565         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2566 };
2567
2568 static struct omap_hwmod omap44xx_prm_hwmod = {
2569         .name           = "prm",
2570         .class          = &omap44xx_prcm_hwmod_class,
2571         .clkdm_name     = "prm_clkdm",
2572         .mpu_irqs       = omap44xx_prm_irqs,
2573         .rst_lines      = omap44xx_prm_resets,
2574         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2575 };
2576
2577 /*
2578  * 'scrm' class
2579  * system clock and reset manager
2580  */
2581
2582 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2583         .name   = "scrm",
2584 };
2585
2586 /* scrm */
2587 static struct omap_hwmod omap44xx_scrm_hwmod = {
2588         .name           = "scrm",
2589         .class          = &omap44xx_scrm_hwmod_class,
2590         .clkdm_name     = "l4_wkup_clkdm",
2591 };
2592
2593 /*
2594  * 'sl2if' class
2595  * shared level 2 memory interface
2596  */
2597
2598 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2599         .name   = "sl2if",
2600 };
2601
2602 /* sl2if */
2603 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2604         .name           = "sl2if",
2605         .class          = &omap44xx_sl2if_hwmod_class,
2606         .clkdm_name     = "ivahd_clkdm",
2607         .prcm = {
2608                 .omap4 = {
2609                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2610                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2611                         .modulemode   = MODULEMODE_HWCTRL,
2612                 },
2613         },
2614 };
2615
2616 /*
2617  * 'slimbus' class
2618  * bidirectional, multi-drop, multi-channel two-line serial interface between
2619  * the device and external components
2620  */
2621
2622 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2623         .rev_offs       = 0x0000,
2624         .sysc_offs      = 0x0010,
2625         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2626                            SYSC_HAS_SOFTRESET),
2627         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2628                            SIDLE_SMART_WKUP),
2629         .sysc_fields    = &omap_hwmod_sysc_type2,
2630 };
2631
2632 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2633         .name   = "slimbus",
2634         .sysc   = &omap44xx_slimbus_sysc,
2635 };
2636
2637 /* slimbus1 */
2638 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2639         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2640         { .irq = -1 }
2641 };
2642
2643 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2644         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2645         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2646         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2647         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2648         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2649         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2650         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2651         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2652         { .dma_req = -1 }
2653 };
2654
2655 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2656         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2657         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2658         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2659         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2660 };
2661
2662 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2663         .name           = "slimbus1",
2664         .class          = &omap44xx_slimbus_hwmod_class,
2665         .clkdm_name     = "abe_clkdm",
2666         .mpu_irqs       = omap44xx_slimbus1_irqs,
2667         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2668         .prcm = {
2669                 .omap4 = {
2670                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2671                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2672                         .modulemode   = MODULEMODE_SWCTRL,
2673                 },
2674         },
2675         .opt_clks       = slimbus1_opt_clks,
2676         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2677 };
2678
2679 /* slimbus2 */
2680 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2681         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2682         { .irq = -1 }
2683 };
2684
2685 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2686         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2687         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2688         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2689         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2690         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2691         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2692         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2693         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2694         { .dma_req = -1 }
2695 };
2696
2697 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2698         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2699         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2700         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2701 };
2702
2703 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2704         .name           = "slimbus2",
2705         .class          = &omap44xx_slimbus_hwmod_class,
2706         .clkdm_name     = "l4_per_clkdm",
2707         .mpu_irqs       = omap44xx_slimbus2_irqs,
2708         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2709         .prcm = {
2710                 .omap4 = {
2711                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2712                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2713                         .modulemode   = MODULEMODE_SWCTRL,
2714                 },
2715         },
2716         .opt_clks       = slimbus2_opt_clks,
2717         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2718 };
2719
2720 /*
2721  * 'smartreflex' class
2722  * smartreflex module (monitor silicon performance and outputs a measure of
2723  * performance error)
2724  */
2725
2726 /* The IP is not compliant to type1 / type2 scheme */
2727 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2728         .sidle_shift    = 24,
2729         .enwkup_shift   = 26,
2730 };
2731
2732 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2733         .sysc_offs      = 0x0038,
2734         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2736                            SIDLE_SMART_WKUP),
2737         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2738 };
2739
2740 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2741         .name   = "smartreflex",
2742         .sysc   = &omap44xx_smartreflex_sysc,
2743         .rev    = 2,
2744 };
2745
2746 /* smartreflex_core */
2747 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2748         .sensor_voltdm_name   = "core",
2749 };
2750
2751 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2752         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2753         { .irq = -1 }
2754 };
2755
2756 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2757         .name           = "smartreflex_core",
2758         .class          = &omap44xx_smartreflex_hwmod_class,
2759         .clkdm_name     = "l4_ao_clkdm",
2760         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2761
2762         .main_clk       = "smartreflex_core_fck",
2763         .prcm = {
2764                 .omap4 = {
2765                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2766                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2767                         .modulemode   = MODULEMODE_SWCTRL,
2768                 },
2769         },
2770         .dev_attr       = &smartreflex_core_dev_attr,
2771 };
2772
2773 /* smartreflex_iva */
2774 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2775         .sensor_voltdm_name     = "iva",
2776 };
2777
2778 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2779         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2780         { .irq = -1 }
2781 };
2782
2783 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2784         .name           = "smartreflex_iva",
2785         .class          = &omap44xx_smartreflex_hwmod_class,
2786         .clkdm_name     = "l4_ao_clkdm",
2787         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2788         .main_clk       = "smartreflex_iva_fck",
2789         .prcm = {
2790                 .omap4 = {
2791                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2792                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2793                         .modulemode   = MODULEMODE_SWCTRL,
2794                 },
2795         },
2796         .dev_attr       = &smartreflex_iva_dev_attr,
2797 };
2798
2799 /* smartreflex_mpu */
2800 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2801         .sensor_voltdm_name     = "mpu",
2802 };
2803
2804 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2805         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2806         { .irq = -1 }
2807 };
2808
2809 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2810         .name           = "smartreflex_mpu",
2811         .class          = &omap44xx_smartreflex_hwmod_class,
2812         .clkdm_name     = "l4_ao_clkdm",
2813         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
2814         .main_clk       = "smartreflex_mpu_fck",
2815         .prcm = {
2816                 .omap4 = {
2817                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2818                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2819                         .modulemode   = MODULEMODE_SWCTRL,
2820                 },
2821         },
2822         .dev_attr       = &smartreflex_mpu_dev_attr,
2823 };
2824
2825 /*
2826  * 'spinlock' class
2827  * spinlock provides hardware assistance for synchronizing the processes
2828  * running on multiple processors
2829  */
2830
2831 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2832         .rev_offs       = 0x0000,
2833         .sysc_offs      = 0x0010,
2834         .syss_offs      = 0x0014,
2835         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2836                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2837                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2838         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2839                            SIDLE_SMART_WKUP),
2840         .sysc_fields    = &omap_hwmod_sysc_type1,
2841 };
2842
2843 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2844         .name   = "spinlock",
2845         .sysc   = &omap44xx_spinlock_sysc,
2846 };
2847
2848 /* spinlock */
2849 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2850         .name           = "spinlock",
2851         .class          = &omap44xx_spinlock_hwmod_class,
2852         .clkdm_name     = "l4_cfg_clkdm",
2853         .prcm = {
2854                 .omap4 = {
2855                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2856                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2857                 },
2858         },
2859 };
2860
2861 /*
2862  * 'timer' class
2863  * general purpose timer module with accurate 1ms tick
2864  * This class contains several variants: ['timer_1ms', 'timer']
2865  */
2866
2867 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2868         .rev_offs       = 0x0000,
2869         .sysc_offs      = 0x0010,
2870         .syss_offs      = 0x0014,
2871         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2872                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2873                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2874                            SYSS_HAS_RESET_STATUS),
2875         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2876         .sysc_fields    = &omap_hwmod_sysc_type1,
2877 };
2878
2879 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2880         .name   = "timer",
2881         .sysc   = &omap44xx_timer_1ms_sysc,
2882 };
2883
2884 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2885         .rev_offs       = 0x0000,
2886         .sysc_offs      = 0x0010,
2887         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2888                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2889         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2890                            SIDLE_SMART_WKUP),
2891         .sysc_fields    = &omap_hwmod_sysc_type2,
2892 };
2893
2894 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2895         .name   = "timer",
2896         .sysc   = &omap44xx_timer_sysc,
2897 };
2898
2899 /* always-on timers dev attribute */
2900 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2901         .timer_capability       = OMAP_TIMER_ALWON,
2902 };
2903
2904 /* pwm timers dev attribute */
2905 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2906         .timer_capability       = OMAP_TIMER_HAS_PWM,
2907 };
2908
2909 /* timer1 */
2910 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2911         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2912         { .irq = -1 }
2913 };
2914
2915 static struct omap_hwmod omap44xx_timer1_hwmod = {
2916         .name           = "timer1",
2917         .class          = &omap44xx_timer_1ms_hwmod_class,
2918         .clkdm_name     = "l4_wkup_clkdm",
2919         .mpu_irqs       = omap44xx_timer1_irqs,
2920         .main_clk       = "timer1_fck",
2921         .prcm = {
2922                 .omap4 = {
2923                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2924                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2925                         .modulemode   = MODULEMODE_SWCTRL,
2926                 },
2927         },
2928         .dev_attr       = &capability_alwon_dev_attr,
2929 };
2930
2931 /* timer2 */
2932 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2933         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2934         { .irq = -1 }
2935 };
2936
2937 static struct omap_hwmod omap44xx_timer2_hwmod = {
2938         .name           = "timer2",
2939         .class          = &omap44xx_timer_1ms_hwmod_class,
2940         .clkdm_name     = "l4_per_clkdm",
2941         .mpu_irqs       = omap44xx_timer2_irqs,
2942         .main_clk       = "timer2_fck",
2943         .prcm = {
2944                 .omap4 = {
2945                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2946                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2947                         .modulemode   = MODULEMODE_SWCTRL,
2948                 },
2949         },
2950 };
2951
2952 /* timer3 */
2953 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2954         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2955         { .irq = -1 }
2956 };
2957
2958 static struct omap_hwmod omap44xx_timer3_hwmod = {
2959         .name           = "timer3",
2960         .class          = &omap44xx_timer_hwmod_class,
2961         .clkdm_name     = "l4_per_clkdm",
2962         .mpu_irqs       = omap44xx_timer3_irqs,
2963         .main_clk       = "timer3_fck",
2964         .prcm = {
2965                 .omap4 = {
2966                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2967                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2968                         .modulemode   = MODULEMODE_SWCTRL,
2969                 },
2970         },
2971 };
2972
2973 /* timer4 */
2974 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2975         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2976         { .irq = -1 }
2977 };
2978
2979 static struct omap_hwmod omap44xx_timer4_hwmod = {
2980         .name           = "timer4",
2981         .class          = &omap44xx_timer_hwmod_class,
2982         .clkdm_name     = "l4_per_clkdm",
2983         .mpu_irqs       = omap44xx_timer4_irqs,
2984         .main_clk       = "timer4_fck",
2985         .prcm = {
2986                 .omap4 = {
2987                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2988                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2989                         .modulemode   = MODULEMODE_SWCTRL,
2990                 },
2991         },
2992 };
2993
2994 /* timer5 */
2995 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2996         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2997         { .irq = -1 }
2998 };
2999
3000 static struct omap_hwmod omap44xx_timer5_hwmod = {
3001         .name           = "timer5",
3002         .class          = &omap44xx_timer_hwmod_class,
3003         .clkdm_name     = "abe_clkdm",
3004         .mpu_irqs       = omap44xx_timer5_irqs,
3005         .main_clk       = "timer5_fck",
3006         .prcm = {
3007                 .omap4 = {
3008                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3009                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3010                         .modulemode   = MODULEMODE_SWCTRL,
3011                 },
3012         },
3013 };
3014
3015 /* timer6 */
3016 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3017         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3018         { .irq = -1 }
3019 };
3020
3021 static struct omap_hwmod omap44xx_timer6_hwmod = {
3022         .name           = "timer6",
3023         .class          = &omap44xx_timer_hwmod_class,
3024         .clkdm_name     = "abe_clkdm",
3025         .mpu_irqs       = omap44xx_timer6_irqs,
3026
3027         .main_clk       = "timer6_fck",
3028         .prcm = {
3029                 .omap4 = {
3030                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3031                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3032                         .modulemode   = MODULEMODE_SWCTRL,
3033                 },
3034         },
3035 };
3036
3037 /* timer7 */
3038 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3039         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3040         { .irq = -1 }
3041 };
3042
3043 static struct omap_hwmod omap44xx_timer7_hwmod = {
3044         .name           = "timer7",
3045         .class          = &omap44xx_timer_hwmod_class,
3046         .clkdm_name     = "abe_clkdm",
3047         .mpu_irqs       = omap44xx_timer7_irqs,
3048         .main_clk       = "timer7_fck",
3049         .prcm = {
3050                 .omap4 = {
3051                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3052                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3053                         .modulemode   = MODULEMODE_SWCTRL,
3054                 },
3055         },
3056 };
3057
3058 /* timer8 */
3059 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3060         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3061         { .irq = -1 }
3062 };
3063
3064 static struct omap_hwmod omap44xx_timer8_hwmod = {
3065         .name           = "timer8",
3066         .class          = &omap44xx_timer_hwmod_class,
3067         .clkdm_name     = "abe_clkdm",
3068         .mpu_irqs       = omap44xx_timer8_irqs,
3069         .main_clk       = "timer8_fck",
3070         .prcm = {
3071                 .omap4 = {
3072                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3073                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3074                         .modulemode   = MODULEMODE_SWCTRL,
3075                 },
3076         },
3077         .dev_attr       = &capability_pwm_dev_attr,
3078 };
3079
3080 /* timer9 */
3081 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3082         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3083         { .irq = -1 }
3084 };
3085
3086 static struct omap_hwmod omap44xx_timer9_hwmod = {
3087         .name           = "timer9",
3088         .class          = &omap44xx_timer_hwmod_class,
3089         .clkdm_name     = "l4_per_clkdm",
3090         .mpu_irqs       = omap44xx_timer9_irqs,
3091         .main_clk       = "timer9_fck",
3092         .prcm = {
3093                 .omap4 = {
3094                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3095                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3096                         .modulemode   = MODULEMODE_SWCTRL,
3097                 },
3098         },
3099         .dev_attr       = &capability_pwm_dev_attr,
3100 };
3101
3102 /* timer10 */
3103 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3104         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3105         { .irq = -1 }
3106 };
3107
3108 static struct omap_hwmod omap44xx_timer10_hwmod = {
3109         .name           = "timer10",
3110         .class          = &omap44xx_timer_1ms_hwmod_class,
3111         .clkdm_name     = "l4_per_clkdm",
3112         .mpu_irqs       = omap44xx_timer10_irqs,
3113         .main_clk       = "timer10_fck",
3114         .prcm = {
3115                 .omap4 = {
3116                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3117                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3118                         .modulemode   = MODULEMODE_SWCTRL,
3119                 },
3120         },
3121         .dev_attr       = &capability_pwm_dev_attr,
3122 };
3123
3124 /* timer11 */
3125 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3126         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3127         { .irq = -1 }
3128 };
3129
3130 static struct omap_hwmod omap44xx_timer11_hwmod = {
3131         .name           = "timer11",
3132         .class          = &omap44xx_timer_hwmod_class,
3133         .clkdm_name     = "l4_per_clkdm",
3134         .mpu_irqs       = omap44xx_timer11_irqs,
3135         .main_clk       = "timer11_fck",
3136         .prcm = {
3137                 .omap4 = {
3138                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3139                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3140                         .modulemode   = MODULEMODE_SWCTRL,
3141                 },
3142         },
3143         .dev_attr       = &capability_pwm_dev_attr,
3144 };
3145
3146 /*
3147  * 'uart' class
3148  * universal asynchronous receiver/transmitter (uart)
3149  */
3150
3151 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3152         .rev_offs       = 0x0050,
3153         .sysc_offs      = 0x0054,
3154         .syss_offs      = 0x0058,
3155         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3156                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3157                            SYSS_HAS_RESET_STATUS),
3158         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3159                            SIDLE_SMART_WKUP),
3160         .sysc_fields    = &omap_hwmod_sysc_type1,
3161 };
3162
3163 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3164         .name   = "uart",
3165         .sysc   = &omap44xx_uart_sysc,
3166 };
3167
3168 /* uart1 */
3169 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3170         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3171         { .irq = -1 }
3172 };
3173
3174 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3175         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3176         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3177         { .dma_req = -1 }
3178 };
3179
3180 static struct omap_hwmod omap44xx_uart1_hwmod = {
3181         .name           = "uart1",
3182         .class          = &omap44xx_uart_hwmod_class,
3183         .clkdm_name     = "l4_per_clkdm",
3184         .mpu_irqs       = omap44xx_uart1_irqs,
3185         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3186         .main_clk       = "uart1_fck",
3187         .prcm = {
3188                 .omap4 = {
3189                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3190                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3191                         .modulemode   = MODULEMODE_SWCTRL,
3192                 },
3193         },
3194 };
3195
3196 /* uart2 */
3197 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3198         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3199         { .irq = -1 }
3200 };
3201
3202 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3203         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3204         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3205         { .dma_req = -1 }
3206 };
3207
3208 static struct omap_hwmod omap44xx_uart2_hwmod = {
3209         .name           = "uart2",
3210         .class          = &omap44xx_uart_hwmod_class,
3211         .clkdm_name     = "l4_per_clkdm",
3212         .mpu_irqs       = omap44xx_uart2_irqs,
3213         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3214         .main_clk       = "uart2_fck",
3215         .prcm = {
3216                 .omap4 = {
3217                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3218                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3219                         .modulemode   = MODULEMODE_SWCTRL,
3220                 },
3221         },
3222 };
3223
3224 /* uart3 */
3225 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3226         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3227         { .irq = -1 }
3228 };
3229
3230 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3231         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3232         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3233         { .dma_req = -1 }
3234 };
3235
3236 static struct omap_hwmod omap44xx_uart3_hwmod = {
3237         .name           = "uart3",
3238         .class          = &omap44xx_uart_hwmod_class,
3239         .clkdm_name     = "l4_per_clkdm",
3240         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3241         .mpu_irqs       = omap44xx_uart3_irqs,
3242         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3243         .main_clk       = "uart3_fck",
3244         .prcm = {
3245                 .omap4 = {
3246                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3247                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3248                         .modulemode   = MODULEMODE_SWCTRL,
3249                 },
3250         },
3251 };
3252
3253 /* uart4 */
3254 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3255         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3256         { .irq = -1 }
3257 };
3258
3259 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3260         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3261         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3262         { .dma_req = -1 }
3263 };
3264
3265 static struct omap_hwmod omap44xx_uart4_hwmod = {
3266         .name           = "uart4",
3267         .class          = &omap44xx_uart_hwmod_class,
3268         .clkdm_name     = "l4_per_clkdm",
3269         .mpu_irqs       = omap44xx_uart4_irqs,
3270         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3271         .main_clk       = "uart4_fck",
3272         .prcm = {
3273                 .omap4 = {
3274                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3275                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3276                         .modulemode   = MODULEMODE_SWCTRL,
3277                 },
3278         },
3279 };
3280
3281 /*
3282  * 'usb_host_fs' class
3283  * full-speed usb host controller
3284  */
3285
3286 /* The IP is not compliant to type1 / type2 scheme */
3287 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3288         .midle_shift    = 4,
3289         .sidle_shift    = 2,
3290         .srst_shift     = 1,
3291 };
3292
3293 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3294         .rev_offs       = 0x0000,
3295         .sysc_offs      = 0x0210,
3296         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3297                            SYSC_HAS_SOFTRESET),
3298         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3299                            SIDLE_SMART_WKUP),
3300         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3301 };
3302
3303 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3304         .name   = "usb_host_fs",
3305         .sysc   = &omap44xx_usb_host_fs_sysc,
3306 };
3307
3308 /* usb_host_fs */
3309 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3310         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3311         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3312         { .irq = -1 }
3313 };
3314
3315 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3316         .name           = "usb_host_fs",
3317         .class          = &omap44xx_usb_host_fs_hwmod_class,
3318         .clkdm_name     = "l3_init_clkdm",
3319         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3320         .main_clk       = "usb_host_fs_fck",
3321         .prcm = {
3322                 .omap4 = {
3323                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3324                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3325                         .modulemode   = MODULEMODE_SWCTRL,
3326                 },
3327         },
3328 };
3329
3330 /*
3331  * 'usb_host_hs' class
3332  * high-speed multi-port usb host controller
3333  */
3334
3335 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3336         .rev_offs       = 0x0000,
3337         .sysc_offs      = 0x0010,
3338         .syss_offs      = 0x0014,
3339         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3340                            SYSC_HAS_SOFTRESET),
3341         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3342                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3343                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3344         .sysc_fields    = &omap_hwmod_sysc_type2,
3345 };
3346
3347 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3348         .name   = "usb_host_hs",
3349         .sysc   = &omap44xx_usb_host_hs_sysc,
3350 };
3351
3352 /* usb_host_hs */
3353 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3354         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3355         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3356         { .irq = -1 }
3357 };
3358
3359 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3360         .name           = "usb_host_hs",
3361         .class          = &omap44xx_usb_host_hs_hwmod_class,
3362         .clkdm_name     = "l3_init_clkdm",
3363         .main_clk       = "usb_host_hs_fck",
3364         .prcm = {
3365                 .omap4 = {
3366                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3367                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3368                         .modulemode   = MODULEMODE_SWCTRL,
3369                 },
3370         },
3371         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3372
3373         /*
3374          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3375          * id: i660
3376          *
3377          * Description:
3378          * In the following configuration :
3379          * - USBHOST module is set to smart-idle mode
3380          * - PRCM asserts idle_req to the USBHOST module ( This typically
3381          *   happens when the system is going to a low power mode : all ports
3382          *   have been suspended, the master part of the USBHOST module has
3383          *   entered the standby state, and SW has cut the functional clocks)
3384          * - an USBHOST interrupt occurs before the module is able to answer
3385          *   idle_ack, typically a remote wakeup IRQ.
3386          * Then the USB HOST module will enter a deadlock situation where it
3387          * is no more accessible nor functional.
3388          *
3389          * Workaround:
3390          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3391          */
3392
3393         /*
3394          * Errata: USB host EHCI may stall when entering smart-standby mode
3395          * Id: i571
3396          *
3397          * Description:
3398          * When the USBHOST module is set to smart-standby mode, and when it is
3399          * ready to enter the standby state (i.e. all ports are suspended and
3400          * all attached devices are in suspend mode), then it can wrongly assert
3401          * the Mstandby signal too early while there are still some residual OCP
3402          * transactions ongoing. If this condition occurs, the internal state
3403          * machine may go to an undefined state and the USB link may be stuck
3404          * upon the next resume.
3405          *
3406          * Workaround:
3407          * Don't use smart standby; use only force standby,
3408          * hence HWMOD_SWSUP_MSTANDBY
3409          */
3410
3411         /*
3412          * During system boot; If the hwmod framework resets the module
3413          * the module will have smart idle settings; which can lead to deadlock
3414          * (above Errata Id:i660); so, dont reset the module during boot;
3415          * Use HWMOD_INIT_NO_RESET.
3416          */
3417
3418         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3419                           HWMOD_INIT_NO_RESET,
3420 };
3421
3422 /*
3423  * 'usb_otg_hs' class
3424  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3425  */
3426
3427 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3428         .rev_offs       = 0x0400,
3429         .sysc_offs      = 0x0404,
3430         .syss_offs      = 0x0408,
3431         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3432                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3433                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3434         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3435                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3436                            MSTANDBY_SMART),
3437         .sysc_fields    = &omap_hwmod_sysc_type1,
3438 };
3439
3440 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3441         .name   = "usb_otg_hs",
3442         .sysc   = &omap44xx_usb_otg_hs_sysc,
3443 };
3444
3445 /* usb_otg_hs */
3446 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3447         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3448         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3449         { .irq = -1 }
3450 };
3451
3452 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3453         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3454 };
3455
3456 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3457         .name           = "usb_otg_hs",
3458         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3459         .clkdm_name     = "l3_init_clkdm",
3460         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3461         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3462         .main_clk       = "usb_otg_hs_ick",
3463         .prcm = {
3464                 .omap4 = {
3465                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3466                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3467                         .modulemode   = MODULEMODE_HWCTRL,
3468                 },
3469         },
3470         .opt_clks       = usb_otg_hs_opt_clks,
3471         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3472 };
3473
3474 /*
3475  * 'usb_tll_hs' class
3476  * usb_tll_hs module is the adapter on the usb_host_hs ports
3477  */
3478
3479 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3480         .rev_offs       = 0x0000,
3481         .sysc_offs      = 0x0010,
3482         .syss_offs      = 0x0014,
3483         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3484                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3485                            SYSC_HAS_AUTOIDLE),
3486         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3487         .sysc_fields    = &omap_hwmod_sysc_type1,
3488 };
3489
3490 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3491         .name   = "usb_tll_hs",
3492         .sysc   = &omap44xx_usb_tll_hs_sysc,
3493 };
3494
3495 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3496         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3497         { .irq = -1 }
3498 };
3499
3500 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3501         .name           = "usb_tll_hs",
3502         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3503         .clkdm_name     = "l3_init_clkdm",
3504         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3505         .main_clk       = "usb_tll_hs_ick",
3506         .prcm = {
3507                 .omap4 = {
3508                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3509                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3510                         .modulemode   = MODULEMODE_HWCTRL,
3511                 },
3512         },
3513 };
3514
3515 /*
3516  * 'wd_timer' class
3517  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3518  * overflow condition
3519  */
3520
3521 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3522         .rev_offs       = 0x0000,
3523         .sysc_offs      = 0x0010,
3524         .syss_offs      = 0x0014,
3525         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3526                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3527         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3528                            SIDLE_SMART_WKUP),
3529         .sysc_fields    = &omap_hwmod_sysc_type1,
3530 };
3531
3532 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3533         .name           = "wd_timer",
3534         .sysc           = &omap44xx_wd_timer_sysc,
3535         .pre_shutdown   = &omap2_wd_timer_disable,
3536         .reset          = &omap2_wd_timer_reset,
3537 };
3538
3539 /* wd_timer2 */
3540 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3541         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3542         { .irq = -1 }
3543 };
3544
3545 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3546         .name           = "wd_timer2",
3547         .class          = &omap44xx_wd_timer_hwmod_class,
3548         .clkdm_name     = "l4_wkup_clkdm",
3549         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3550         .main_clk       = "wd_timer2_fck",
3551         .prcm = {
3552                 .omap4 = {
3553                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3554                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3555                         .modulemode   = MODULEMODE_SWCTRL,
3556                 },
3557         },
3558 };
3559
3560 /* wd_timer3 */
3561 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3562         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3563         { .irq = -1 }
3564 };
3565
3566 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3567         .name           = "wd_timer3",
3568         .class          = &omap44xx_wd_timer_hwmod_class,
3569         .clkdm_name     = "abe_clkdm",
3570         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3571         .main_clk       = "wd_timer3_fck",
3572         .prcm = {
3573                 .omap4 = {
3574                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3575                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3576                         .modulemode   = MODULEMODE_SWCTRL,
3577                 },
3578         },
3579 };
3580
3581
3582 /*
3583  * interfaces
3584  */
3585
3586 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3587         {
3588                 .pa_start       = 0x4a204000,
3589                 .pa_end         = 0x4a2040ff,
3590                 .flags          = ADDR_TYPE_RT
3591         },
3592         { }
3593 };
3594
3595 /* c2c -> c2c_target_fw */
3596 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3597         .master         = &omap44xx_c2c_hwmod,
3598         .slave          = &omap44xx_c2c_target_fw_hwmod,
3599         .clk            = "div_core_ck",
3600         .addr           = omap44xx_c2c_target_fw_addrs,
3601         .user           = OCP_USER_MPU,
3602 };
3603
3604 /* l4_cfg -> c2c_target_fw */
3605 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3606         .master         = &omap44xx_l4_cfg_hwmod,
3607         .slave          = &omap44xx_c2c_target_fw_hwmod,
3608         .clk            = "l4_div_ck",
3609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3610 };
3611
3612 /* l3_main_1 -> dmm */
3613 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3614         .master         = &omap44xx_l3_main_1_hwmod,
3615         .slave          = &omap44xx_dmm_hwmod,
3616         .clk            = "l3_div_ck",
3617         .user           = OCP_USER_SDMA,
3618 };
3619
3620 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3621         {
3622                 .pa_start       = 0x4e000000,
3623                 .pa_end         = 0x4e0007ff,
3624                 .flags          = ADDR_TYPE_RT
3625         },
3626         { }
3627 };
3628
3629 /* mpu -> dmm */
3630 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3631         .master         = &omap44xx_mpu_hwmod,
3632         .slave          = &omap44xx_dmm_hwmod,
3633         .clk            = "l3_div_ck",
3634         .addr           = omap44xx_dmm_addrs,
3635         .user           = OCP_USER_MPU,
3636 };
3637
3638 /* c2c -> emif_fw */
3639 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3640         .master         = &omap44xx_c2c_hwmod,
3641         .slave          = &omap44xx_emif_fw_hwmod,
3642         .clk            = "div_core_ck",
3643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3644 };
3645
3646 /* dmm -> emif_fw */
3647 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3648         .master         = &omap44xx_dmm_hwmod,
3649         .slave          = &omap44xx_emif_fw_hwmod,
3650         .clk            = "l3_div_ck",
3651         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3652 };
3653
3654 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3655         {
3656                 .pa_start       = 0x4a20c000,
3657                 .pa_end         = 0x4a20c0ff,
3658                 .flags          = ADDR_TYPE_RT
3659         },
3660         { }
3661 };
3662
3663 /* l4_cfg -> emif_fw */
3664 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3665         .master         = &omap44xx_l4_cfg_hwmod,
3666         .slave          = &omap44xx_emif_fw_hwmod,
3667         .clk            = "l4_div_ck",
3668         .addr           = omap44xx_emif_fw_addrs,
3669         .user           = OCP_USER_MPU,
3670 };
3671
3672 /* iva -> l3_instr */
3673 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3674         .master         = &omap44xx_iva_hwmod,
3675         .slave          = &omap44xx_l3_instr_hwmod,
3676         .clk            = "l3_div_ck",
3677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3678 };
3679
3680 /* l3_main_3 -> l3_instr */
3681 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3682         .master         = &omap44xx_l3_main_3_hwmod,
3683         .slave          = &omap44xx_l3_instr_hwmod,
3684         .clk            = "l3_div_ck",
3685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3686 };
3687
3688 /* ocp_wp_noc -> l3_instr */
3689 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3690         .master         = &omap44xx_ocp_wp_noc_hwmod,
3691         .slave          = &omap44xx_l3_instr_hwmod,
3692         .clk            = "l3_div_ck",
3693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3694 };
3695
3696 /* dsp -> l3_main_1 */
3697 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3698         .master         = &omap44xx_dsp_hwmod,
3699         .slave          = &omap44xx_l3_main_1_hwmod,
3700         .clk            = "l3_div_ck",
3701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3702 };
3703
3704 /* dss -> l3_main_1 */
3705 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3706         .master         = &omap44xx_dss_hwmod,
3707         .slave          = &omap44xx_l3_main_1_hwmod,
3708         .clk            = "l3_div_ck",
3709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3710 };
3711
3712 /* l3_main_2 -> l3_main_1 */
3713 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3714         .master         = &omap44xx_l3_main_2_hwmod,
3715         .slave          = &omap44xx_l3_main_1_hwmod,
3716         .clk            = "l3_div_ck",
3717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3718 };
3719
3720 /* l4_cfg -> l3_main_1 */
3721 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3722         .master         = &omap44xx_l4_cfg_hwmod,
3723         .slave          = &omap44xx_l3_main_1_hwmod,
3724         .clk            = "l4_div_ck",
3725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3726 };
3727
3728 /* mmc1 -> l3_main_1 */
3729 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3730         .master         = &omap44xx_mmc1_hwmod,
3731         .slave          = &omap44xx_l3_main_1_hwmod,
3732         .clk            = "l3_div_ck",
3733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3734 };
3735
3736 /* mmc2 -> l3_main_1 */
3737 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3738         .master         = &omap44xx_mmc2_hwmod,
3739         .slave          = &omap44xx_l3_main_1_hwmod,
3740         .clk            = "l3_div_ck",
3741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3742 };
3743
3744 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3745         {
3746                 .pa_start       = 0x44000000,
3747                 .pa_end         = 0x44000fff,
3748                 .flags          = ADDR_TYPE_RT
3749         },
3750         { }
3751 };
3752
3753 /* mpu -> l3_main_1 */
3754 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3755         .master         = &omap44xx_mpu_hwmod,
3756         .slave          = &omap44xx_l3_main_1_hwmod,
3757         .clk            = "l3_div_ck",
3758         .addr           = omap44xx_l3_main_1_addrs,
3759         .user           = OCP_USER_MPU,
3760 };
3761
3762 /* c2c_target_fw -> l3_main_2 */
3763 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3764         .master         = &omap44xx_c2c_target_fw_hwmod,
3765         .slave          = &omap44xx_l3_main_2_hwmod,
3766         .clk            = "l3_div_ck",
3767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3768 };
3769
3770 /* debugss -> l3_main_2 */
3771 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3772         .master         = &omap44xx_debugss_hwmod,
3773         .slave          = &omap44xx_l3_main_2_hwmod,
3774         .clk            = "dbgclk_mux_ck",
3775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3776 };
3777
3778 /* dma_system -> l3_main_2 */
3779 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3780         .master         = &omap44xx_dma_system_hwmod,
3781         .slave          = &omap44xx_l3_main_2_hwmod,
3782         .clk            = "l3_div_ck",
3783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3784 };
3785
3786 /* fdif -> l3_main_2 */
3787 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3788         .master         = &omap44xx_fdif_hwmod,
3789         .slave          = &omap44xx_l3_main_2_hwmod,
3790         .clk            = "l3_div_ck",
3791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3792 };
3793
3794 /* gpu -> l3_main_2 */
3795 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3796         .master         = &omap44xx_gpu_hwmod,
3797         .slave          = &omap44xx_l3_main_2_hwmod,
3798         .clk            = "l3_div_ck",
3799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3800 };
3801
3802 /* hsi -> l3_main_2 */
3803 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3804         .master         = &omap44xx_hsi_hwmod,
3805         .slave          = &omap44xx_l3_main_2_hwmod,
3806         .clk            = "l3_div_ck",
3807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3808 };
3809
3810 /* ipu -> l3_main_2 */
3811 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3812         .master         = &omap44xx_ipu_hwmod,
3813         .slave          = &omap44xx_l3_main_2_hwmod,
3814         .clk            = "l3_div_ck",
3815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3816 };
3817
3818 /* iss -> l3_main_2 */
3819 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3820         .master         = &omap44xx_iss_hwmod,
3821         .slave          = &omap44xx_l3_main_2_hwmod,
3822         .clk            = "l3_div_ck",
3823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3824 };
3825
3826 /* iva -> l3_main_2 */
3827 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3828         .master         = &omap44xx_iva_hwmod,
3829         .slave          = &omap44xx_l3_main_2_hwmod,
3830         .clk            = "l3_div_ck",
3831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3832 };
3833
3834 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3835         {
3836                 .pa_start       = 0x44800000,
3837                 .pa_end         = 0x44801fff,
3838                 .flags          = ADDR_TYPE_RT
3839         },
3840         { }
3841 };
3842
3843 /* l3_main_1 -> l3_main_2 */
3844 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3845         .master         = &omap44xx_l3_main_1_hwmod,
3846         .slave          = &omap44xx_l3_main_2_hwmod,
3847         .clk            = "l3_div_ck",
3848         .addr           = omap44xx_l3_main_2_addrs,
3849         .user           = OCP_USER_MPU,
3850 };
3851
3852 /* l4_cfg -> l3_main_2 */
3853 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3854         .master         = &omap44xx_l4_cfg_hwmod,
3855         .slave          = &omap44xx_l3_main_2_hwmod,
3856         .clk            = "l4_div_ck",
3857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3859
3860 /* usb_host_fs -> l3_main_2 */
3861 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3862         .master         = &omap44xx_usb_host_fs_hwmod,
3863         .slave          = &omap44xx_l3_main_2_hwmod,
3864         .clk            = "l3_div_ck",
3865         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3866 };
3867
3868 /* usb_host_hs -> l3_main_2 */
3869 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3870         .master         = &omap44xx_usb_host_hs_hwmod,
3871         .slave          = &omap44xx_l3_main_2_hwmod,
3872         .clk            = "l3_div_ck",
3873         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3874 };
3875
3876 /* usb_otg_hs -> l3_main_2 */
3877 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3878         .master         = &omap44xx_usb_otg_hs_hwmod,
3879         .slave          = &omap44xx_l3_main_2_hwmod,
3880         .clk            = "l3_div_ck",
3881         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3882 };
3883
3884 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3885         {
3886                 .pa_start       = 0x45000000,
3887                 .pa_end         = 0x45000fff,
3888                 .flags          = ADDR_TYPE_RT
3889         },
3890         { }
3891 };
3892
3893 /* l3_main_1 -> l3_main_3 */
3894 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3895         .master         = &omap44xx_l3_main_1_hwmod,
3896         .slave          = &omap44xx_l3_main_3_hwmod,
3897         .clk            = "l3_div_ck",
3898         .addr           = omap44xx_l3_main_3_addrs,
3899         .user           = OCP_USER_MPU,
3900 };
3901
3902 /* l3_main_2 -> l3_main_3 */
3903 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3904         .master         = &omap44xx_l3_main_2_hwmod,
3905         .slave          = &omap44xx_l3_main_3_hwmod,
3906         .clk            = "l3_div_ck",
3907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3908 };
3909
3910 /* l4_cfg -> l3_main_3 */
3911 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3912         .master         = &omap44xx_l4_cfg_hwmod,
3913         .slave          = &omap44xx_l3_main_3_hwmod,
3914         .clk            = "l4_div_ck",
3915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3916 };
3917
3918 /* aess -> l4_abe */
3919 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3920         .master         = &omap44xx_aess_hwmod,
3921         .slave          = &omap44xx_l4_abe_hwmod,
3922         .clk            = "ocp_abe_iclk",
3923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3924 };
3925
3926 /* dsp -> l4_abe */
3927 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3928         .master         = &omap44xx_dsp_hwmod,
3929         .slave          = &omap44xx_l4_abe_hwmod,
3930         .clk            = "ocp_abe_iclk",
3931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3932 };
3933
3934 /* l3_main_1 -> l4_abe */
3935 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3936         .master         = &omap44xx_l3_main_1_hwmod,
3937         .slave          = &omap44xx_l4_abe_hwmod,
3938         .clk            = "l3_div_ck",
3939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3940 };
3941
3942 /* mpu -> l4_abe */
3943 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3944         .master         = &omap44xx_mpu_hwmod,
3945         .slave          = &omap44xx_l4_abe_hwmod,
3946         .clk            = "ocp_abe_iclk",
3947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3948 };
3949
3950 /* l3_main_1 -> l4_cfg */
3951 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3952         .master         = &omap44xx_l3_main_1_hwmod,
3953         .slave          = &omap44xx_l4_cfg_hwmod,
3954         .clk            = "l3_div_ck",
3955         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3957
3958 /* l3_main_2 -> l4_per */
3959 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3960         .master         = &omap44xx_l3_main_2_hwmod,
3961         .slave          = &omap44xx_l4_per_hwmod,
3962         .clk            = "l3_div_ck",
3963         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3964 };
3965
3966 /* l4_cfg -> l4_wkup */
3967 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3968         .master         = &omap44xx_l4_cfg_hwmod,
3969         .slave          = &omap44xx_l4_wkup_hwmod,
3970         .clk            = "l4_div_ck",
3971         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3972 };
3973
3974 /* mpu -> mpu_private */
3975 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3976         .master         = &omap44xx_mpu_hwmod,
3977         .slave          = &omap44xx_mpu_private_hwmod,
3978         .clk            = "l3_div_ck",
3979         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3980 };
3981
3982 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3983         {
3984                 .pa_start       = 0x4a102000,
3985                 .pa_end         = 0x4a10207f,
3986                 .flags          = ADDR_TYPE_RT
3987         },
3988         { }
3989 };
3990
3991 /* l4_cfg -> ocp_wp_noc */
3992 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3993         .master         = &omap44xx_l4_cfg_hwmod,
3994         .slave          = &omap44xx_ocp_wp_noc_hwmod,
3995         .clk            = "l4_div_ck",
3996         .addr           = omap44xx_ocp_wp_noc_addrs,
3997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3998 };
3999
4000 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4001         {
4002                 .pa_start       = 0x401f1000,
4003                 .pa_end         = 0x401f13ff,
4004                 .flags          = ADDR_TYPE_RT
4005         },
4006         { }
4007 };
4008
4009 /* l4_abe -> aess */
4010 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4011         .master         = &omap44xx_l4_abe_hwmod,
4012         .slave          = &omap44xx_aess_hwmod,
4013         .clk            = "ocp_abe_iclk",
4014         .addr           = omap44xx_aess_addrs,
4015         .user           = OCP_USER_MPU,
4016 };
4017
4018 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4019         {
4020                 .pa_start       = 0x490f1000,
4021                 .pa_end         = 0x490f13ff,
4022                 .flags          = ADDR_TYPE_RT
4023         },
4024         { }
4025 };
4026
4027 /* l4_abe -> aess (dma) */
4028 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4029         .master         = &omap44xx_l4_abe_hwmod,
4030         .slave          = &omap44xx_aess_hwmod,
4031         .clk            = "ocp_abe_iclk",
4032         .addr           = omap44xx_aess_dma_addrs,
4033         .user           = OCP_USER_SDMA,
4034 };
4035
4036 /* l3_main_2 -> c2c */
4037 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4038         .master         = &omap44xx_l3_main_2_hwmod,
4039         .slave          = &omap44xx_c2c_hwmod,
4040         .clk            = "l3_div_ck",
4041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4045         {
4046                 .pa_start       = 0x4a304000,
4047                 .pa_end         = 0x4a30401f,
4048                 .flags          = ADDR_TYPE_RT
4049         },
4050         { }
4051 };
4052
4053 /* l4_wkup -> counter_32k */
4054 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4055         .master         = &omap44xx_l4_wkup_hwmod,
4056         .slave          = &omap44xx_counter_32k_hwmod,
4057         .clk            = "l4_wkup_clk_mux_ck",
4058         .addr           = omap44xx_counter_32k_addrs,
4059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4060 };
4061
4062 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4063         {
4064                 .pa_start       = 0x4a002000,
4065                 .pa_end         = 0x4a0027ff,
4066                 .flags          = ADDR_TYPE_RT
4067         },
4068         { }
4069 };
4070
4071 /* l4_cfg -> ctrl_module_core */
4072 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4073         .master         = &omap44xx_l4_cfg_hwmod,
4074         .slave          = &omap44xx_ctrl_module_core_hwmod,
4075         .clk            = "l4_div_ck",
4076         .addr           = omap44xx_ctrl_module_core_addrs,
4077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4078 };
4079
4080 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4081         {
4082                 .pa_start       = 0x4a100000,
4083                 .pa_end         = 0x4a1007ff,
4084                 .flags          = ADDR_TYPE_RT
4085         },
4086         { }
4087 };
4088
4089 /* l4_cfg -> ctrl_module_pad_core */
4090 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4091         .master         = &omap44xx_l4_cfg_hwmod,
4092         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4093         .clk            = "l4_div_ck",
4094         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4096 };
4097
4098 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4099         {
4100                 .pa_start       = 0x4a30c000,
4101                 .pa_end         = 0x4a30c7ff,
4102                 .flags          = ADDR_TYPE_RT
4103         },
4104         { }
4105 };
4106
4107 /* l4_wkup -> ctrl_module_wkup */
4108 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4109         .master         = &omap44xx_l4_wkup_hwmod,
4110         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4111         .clk            = "l4_wkup_clk_mux_ck",
4112         .addr           = omap44xx_ctrl_module_wkup_addrs,
4113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4114 };
4115
4116 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4117         {
4118                 .pa_start       = 0x4a31e000,
4119                 .pa_end         = 0x4a31e7ff,
4120                 .flags          = ADDR_TYPE_RT
4121         },
4122         { }
4123 };
4124
4125 /* l4_wkup -> ctrl_module_pad_wkup */
4126 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4127         .master         = &omap44xx_l4_wkup_hwmod,
4128         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4129         .clk            = "l4_wkup_clk_mux_ck",
4130         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4132 };
4133
4134 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4135         {
4136                 .pa_start       = 0x54160000,
4137                 .pa_end         = 0x54167fff,
4138                 .flags          = ADDR_TYPE_RT
4139         },
4140         { }
4141 };
4142
4143 /* l3_instr -> debugss */
4144 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4145         .master         = &omap44xx_l3_instr_hwmod,
4146         .slave          = &omap44xx_debugss_hwmod,
4147         .clk            = "l3_div_ck",
4148         .addr           = omap44xx_debugss_addrs,
4149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4150 };
4151
4152 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4153         {
4154                 .pa_start       = 0x4a056000,
4155                 .pa_end         = 0x4a056fff,
4156                 .flags          = ADDR_TYPE_RT
4157         },
4158         { }
4159 };
4160
4161 /* l4_cfg -> dma_system */
4162 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4163         .master         = &omap44xx_l4_cfg_hwmod,
4164         .slave          = &omap44xx_dma_system_hwmod,
4165         .clk            = "l4_div_ck",
4166         .addr           = omap44xx_dma_system_addrs,
4167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4168 };
4169
4170 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4171         {
4172                 .name           = "mpu",
4173                 .pa_start       = 0x4012e000,
4174                 .pa_end         = 0x4012e07f,
4175                 .flags          = ADDR_TYPE_RT
4176         },
4177         { }
4178 };
4179
4180 /* l4_abe -> dmic */
4181 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4182         .master         = &omap44xx_l4_abe_hwmod,
4183         .slave          = &omap44xx_dmic_hwmod,
4184         .clk            = "ocp_abe_iclk",
4185         .addr           = omap44xx_dmic_addrs,
4186         .user           = OCP_USER_MPU,
4187 };
4188
4189 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4190         {
4191                 .name           = "dma",
4192                 .pa_start       = 0x4902e000,
4193                 .pa_end         = 0x4902e07f,
4194                 .flags          = ADDR_TYPE_RT
4195         },
4196         { }
4197 };
4198
4199 /* l4_abe -> dmic (dma) */
4200 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4201         .master         = &omap44xx_l4_abe_hwmod,
4202         .slave          = &omap44xx_dmic_hwmod,
4203         .clk            = "ocp_abe_iclk",
4204         .addr           = omap44xx_dmic_dma_addrs,
4205         .user           = OCP_USER_SDMA,
4206 };
4207
4208 /* dsp -> iva */
4209 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4210         .master         = &omap44xx_dsp_hwmod,
4211         .slave          = &omap44xx_iva_hwmod,
4212         .clk            = "dpll_iva_m5x2_ck",
4213         .user           = OCP_USER_DSP,
4214 };
4215
4216 /* dsp -> sl2if */
4217 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4218         .master         = &omap44xx_dsp_hwmod,
4219         .slave          = &omap44xx_sl2if_hwmod,
4220         .clk            = "dpll_iva_m5x2_ck",
4221         .user           = OCP_USER_DSP,
4222 };
4223
4224 /* l4_cfg -> dsp */
4225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4226         .master         = &omap44xx_l4_cfg_hwmod,
4227         .slave          = &omap44xx_dsp_hwmod,
4228         .clk            = "l4_div_ck",
4229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4230 };
4231
4232 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4233         {
4234                 .pa_start       = 0x58000000,
4235                 .pa_end         = 0x5800007f,
4236                 .flags          = ADDR_TYPE_RT
4237         },
4238         { }
4239 };
4240
4241 /* l3_main_2 -> dss */
4242 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4243         .master         = &omap44xx_l3_main_2_hwmod,
4244         .slave          = &omap44xx_dss_hwmod,
4245         .clk            = "dss_fck",
4246         .addr           = omap44xx_dss_dma_addrs,
4247         .user           = OCP_USER_SDMA,
4248 };
4249
4250 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4251         {
4252                 .pa_start       = 0x48040000,
4253                 .pa_end         = 0x4804007f,
4254                 .flags          = ADDR_TYPE_RT
4255         },
4256         { }
4257 };
4258
4259 /* l4_per -> dss */
4260 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4261         .master         = &omap44xx_l4_per_hwmod,
4262         .slave          = &omap44xx_dss_hwmod,
4263         .clk            = "l4_div_ck",
4264         .addr           = omap44xx_dss_addrs,
4265         .user           = OCP_USER_MPU,
4266 };
4267
4268 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4269         {
4270                 .pa_start       = 0x58001000,
4271                 .pa_end         = 0x58001fff,
4272                 .flags          = ADDR_TYPE_RT
4273         },
4274         { }
4275 };
4276
4277 /* l3_main_2 -> dss_dispc */
4278 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4279         .master         = &omap44xx_l3_main_2_hwmod,
4280         .slave          = &omap44xx_dss_dispc_hwmod,
4281         .clk            = "dss_fck",
4282         .addr           = omap44xx_dss_dispc_dma_addrs,
4283         .user           = OCP_USER_SDMA,
4284 };
4285
4286 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4287         {
4288                 .pa_start       = 0x48041000,
4289                 .pa_end         = 0x48041fff,
4290                 .flags          = ADDR_TYPE_RT
4291         },
4292         { }
4293 };
4294
4295 /* l4_per -> dss_dispc */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4297         .master         = &omap44xx_l4_per_hwmod,
4298         .slave          = &omap44xx_dss_dispc_hwmod,
4299         .clk            = "l4_div_ck",
4300         .addr           = omap44xx_dss_dispc_addrs,
4301         .user           = OCP_USER_MPU,
4302 };
4303
4304 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4305         {
4306                 .pa_start       = 0x58004000,
4307                 .pa_end         = 0x580041ff,
4308                 .flags          = ADDR_TYPE_RT
4309         },
4310         { }
4311 };
4312
4313 /* l3_main_2 -> dss_dsi1 */
4314 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4315         .master         = &omap44xx_l3_main_2_hwmod,
4316         .slave          = &omap44xx_dss_dsi1_hwmod,
4317         .clk            = "dss_fck",
4318         .addr           = omap44xx_dss_dsi1_dma_addrs,
4319         .user           = OCP_USER_SDMA,
4320 };
4321
4322 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4323         {
4324                 .pa_start       = 0x48044000,
4325                 .pa_end         = 0x480441ff,
4326                 .flags          = ADDR_TYPE_RT
4327         },
4328         { }
4329 };
4330
4331 /* l4_per -> dss_dsi1 */
4332 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4333         .master         = &omap44xx_l4_per_hwmod,
4334         .slave          = &omap44xx_dss_dsi1_hwmod,
4335         .clk            = "l4_div_ck",
4336         .addr           = omap44xx_dss_dsi1_addrs,
4337         .user           = OCP_USER_MPU,
4338 };
4339
4340 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4341         {
4342                 .pa_start       = 0x58005000,
4343                 .pa_end         = 0x580051ff,
4344                 .flags          = ADDR_TYPE_RT
4345         },
4346         { }
4347 };
4348
4349 /* l3_main_2 -> dss_dsi2 */
4350 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4351         .master         = &omap44xx_l3_main_2_hwmod,
4352         .slave          = &omap44xx_dss_dsi2_hwmod,
4353         .clk            = "dss_fck",
4354         .addr           = omap44xx_dss_dsi2_dma_addrs,
4355         .user           = OCP_USER_SDMA,
4356 };
4357
4358 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4359         {
4360                 .pa_start       = 0x48045000,
4361                 .pa_end         = 0x480451ff,
4362                 .flags          = ADDR_TYPE_RT
4363         },
4364         { }
4365 };
4366
4367 /* l4_per -> dss_dsi2 */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4369         .master         = &omap44xx_l4_per_hwmod,
4370         .slave          = &omap44xx_dss_dsi2_hwmod,
4371         .clk            = "l4_div_ck",
4372         .addr           = omap44xx_dss_dsi2_addrs,
4373         .user           = OCP_USER_MPU,
4374 };
4375
4376 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4377         {
4378                 .pa_start       = 0x58006000,
4379                 .pa_end         = 0x58006fff,
4380                 .flags          = ADDR_TYPE_RT
4381         },
4382         { }
4383 };
4384
4385 /* l3_main_2 -> dss_hdmi */
4386 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4387         .master         = &omap44xx_l3_main_2_hwmod,
4388         .slave          = &omap44xx_dss_hdmi_hwmod,
4389         .clk            = "dss_fck",
4390         .addr           = omap44xx_dss_hdmi_dma_addrs,
4391         .user           = OCP_USER_SDMA,
4392 };
4393
4394 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4395         {
4396                 .pa_start       = 0x48046000,
4397                 .pa_end         = 0x48046fff,
4398                 .flags          = ADDR_TYPE_RT
4399         },
4400         { }
4401 };
4402
4403 /* l4_per -> dss_hdmi */
4404 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4405         .master         = &omap44xx_l4_per_hwmod,
4406         .slave          = &omap44xx_dss_hdmi_hwmod,
4407         .clk            = "l4_div_ck",
4408         .addr           = omap44xx_dss_hdmi_addrs,
4409         .user           = OCP_USER_MPU,
4410 };
4411
4412 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4413         {
4414                 .pa_start       = 0x58002000,
4415                 .pa_end         = 0x580020ff,
4416                 .flags          = ADDR_TYPE_RT
4417         },
4418         { }
4419 };
4420
4421 /* l3_main_2 -> dss_rfbi */
4422 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4423         .master         = &omap44xx_l3_main_2_hwmod,
4424         .slave          = &omap44xx_dss_rfbi_hwmod,
4425         .clk            = "dss_fck",
4426         .addr           = omap44xx_dss_rfbi_dma_addrs,
4427         .user           = OCP_USER_SDMA,
4428 };
4429
4430 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4431         {
4432                 .pa_start       = 0x48042000,
4433                 .pa_end         = 0x480420ff,
4434                 .flags          = ADDR_TYPE_RT
4435         },
4436         { }
4437 };
4438
4439 /* l4_per -> dss_rfbi */
4440 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4441         .master         = &omap44xx_l4_per_hwmod,
4442         .slave          = &omap44xx_dss_rfbi_hwmod,
4443         .clk            = "l4_div_ck",
4444         .addr           = omap44xx_dss_rfbi_addrs,
4445         .user           = OCP_USER_MPU,
4446 };
4447
4448 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4449         {
4450                 .pa_start       = 0x58003000,
4451                 .pa_end         = 0x580030ff,
4452                 .flags          = ADDR_TYPE_RT
4453         },
4454         { }
4455 };
4456
4457 /* l3_main_2 -> dss_venc */
4458 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4459         .master         = &omap44xx_l3_main_2_hwmod,
4460         .slave          = &omap44xx_dss_venc_hwmod,
4461         .clk            = "dss_fck",
4462         .addr           = omap44xx_dss_venc_dma_addrs,
4463         .user           = OCP_USER_SDMA,
4464 };
4465
4466 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4467         {
4468                 .pa_start       = 0x48043000,
4469                 .pa_end         = 0x480430ff,
4470                 .flags          = ADDR_TYPE_RT
4471         },
4472         { }
4473 };
4474
4475 /* l4_per -> dss_venc */
4476 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4477         .master         = &omap44xx_l4_per_hwmod,
4478         .slave          = &omap44xx_dss_venc_hwmod,
4479         .clk            = "l4_div_ck",
4480         .addr           = omap44xx_dss_venc_addrs,
4481         .user           = OCP_USER_MPU,
4482 };
4483
4484 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4485         {
4486                 .pa_start       = 0x48078000,
4487                 .pa_end         = 0x48078fff,
4488                 .flags          = ADDR_TYPE_RT
4489         },
4490         { }
4491 };
4492
4493 /* l4_per -> elm */
4494 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4495         .master         = &omap44xx_l4_per_hwmod,
4496         .slave          = &omap44xx_elm_hwmod,
4497         .clk            = "l4_div_ck",
4498         .addr           = omap44xx_elm_addrs,
4499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4500 };
4501
4502 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4503         {
4504                 .pa_start       = 0x4c000000,
4505                 .pa_end         = 0x4c0000ff,
4506                 .flags          = ADDR_TYPE_RT
4507         },
4508         { }
4509 };
4510
4511 /* emif_fw -> emif1 */
4512 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4513         .master         = &omap44xx_emif_fw_hwmod,
4514         .slave          = &omap44xx_emif1_hwmod,
4515         .clk            = "l3_div_ck",
4516         .addr           = omap44xx_emif1_addrs,
4517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4518 };
4519
4520 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4521         {
4522                 .pa_start       = 0x4d000000,
4523                 .pa_end         = 0x4d0000ff,
4524                 .flags          = ADDR_TYPE_RT
4525         },
4526         { }
4527 };
4528
4529 /* emif_fw -> emif2 */
4530 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4531         .master         = &omap44xx_emif_fw_hwmod,
4532         .slave          = &omap44xx_emif2_hwmod,
4533         .clk            = "l3_div_ck",
4534         .addr           = omap44xx_emif2_addrs,
4535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4536 };
4537
4538 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4539         {
4540                 .pa_start       = 0x4a10a000,
4541                 .pa_end         = 0x4a10a1ff,
4542                 .flags          = ADDR_TYPE_RT
4543         },
4544         { }
4545 };
4546
4547 /* l4_cfg -> fdif */
4548 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4549         .master         = &omap44xx_l4_cfg_hwmod,
4550         .slave          = &omap44xx_fdif_hwmod,
4551         .clk            = "l4_div_ck",
4552         .addr           = omap44xx_fdif_addrs,
4553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4554 };
4555
4556 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4557         {
4558                 .pa_start       = 0x4a310000,
4559                 .pa_end         = 0x4a3101ff,
4560                 .flags          = ADDR_TYPE_RT
4561         },
4562         { }
4563 };
4564
4565 /* l4_wkup -> gpio1 */
4566 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4567         .master         = &omap44xx_l4_wkup_hwmod,
4568         .slave          = &omap44xx_gpio1_hwmod,
4569         .clk            = "l4_wkup_clk_mux_ck",
4570         .addr           = omap44xx_gpio1_addrs,
4571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4572 };
4573
4574 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4575         {
4576                 .pa_start       = 0x48055000,
4577                 .pa_end         = 0x480551ff,
4578                 .flags          = ADDR_TYPE_RT
4579         },
4580         { }
4581 };
4582
4583 /* l4_per -> gpio2 */
4584 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4585         .master         = &omap44xx_l4_per_hwmod,
4586         .slave          = &omap44xx_gpio2_hwmod,
4587         .clk            = "l4_div_ck",
4588         .addr           = omap44xx_gpio2_addrs,
4589         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4590 };
4591
4592 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4593         {
4594                 .pa_start       = 0x48057000,
4595                 .pa_end         = 0x480571ff,
4596                 .flags          = ADDR_TYPE_RT
4597         },
4598         { }
4599 };
4600
4601 /* l4_per -> gpio3 */
4602 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4603         .master         = &omap44xx_l4_per_hwmod,
4604         .slave          = &omap44xx_gpio3_hwmod,
4605         .clk            = "l4_div_ck",
4606         .addr           = omap44xx_gpio3_addrs,
4607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4608 };
4609
4610 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4611         {
4612                 .pa_start       = 0x48059000,
4613                 .pa_end         = 0x480591ff,
4614                 .flags          = ADDR_TYPE_RT
4615         },
4616         { }
4617 };
4618
4619 /* l4_per -> gpio4 */
4620 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4621         .master         = &omap44xx_l4_per_hwmod,
4622         .slave          = &omap44xx_gpio4_hwmod,
4623         .clk            = "l4_div_ck",
4624         .addr           = omap44xx_gpio4_addrs,
4625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4626 };
4627
4628 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4629         {
4630                 .pa_start       = 0x4805b000,
4631                 .pa_end         = 0x4805b1ff,
4632                 .flags          = ADDR_TYPE_RT
4633         },
4634         { }
4635 };
4636
4637 /* l4_per -> gpio5 */
4638 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4639         .master         = &omap44xx_l4_per_hwmod,
4640         .slave          = &omap44xx_gpio5_hwmod,
4641         .clk            = "l4_div_ck",
4642         .addr           = omap44xx_gpio5_addrs,
4643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4644 };
4645
4646 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4647         {
4648                 .pa_start       = 0x4805d000,
4649                 .pa_end         = 0x4805d1ff,
4650                 .flags          = ADDR_TYPE_RT
4651         },
4652         { }
4653 };
4654
4655 /* l4_per -> gpio6 */
4656 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4657         .master         = &omap44xx_l4_per_hwmod,
4658         .slave          = &omap44xx_gpio6_hwmod,
4659         .clk            = "l4_div_ck",
4660         .addr           = omap44xx_gpio6_addrs,
4661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4662 };
4663
4664 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4665         {
4666                 .pa_start       = 0x50000000,
4667                 .pa_end         = 0x500003ff,
4668                 .flags          = ADDR_TYPE_RT
4669         },
4670         { }
4671 };
4672
4673 /* l3_main_2 -> gpmc */
4674 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4675         .master         = &omap44xx_l3_main_2_hwmod,
4676         .slave          = &omap44xx_gpmc_hwmod,
4677         .clk            = "l3_div_ck",
4678         .addr           = omap44xx_gpmc_addrs,
4679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4680 };
4681
4682 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4683         {
4684                 .pa_start       = 0x56000000,
4685                 .pa_end         = 0x5600ffff,
4686                 .flags          = ADDR_TYPE_RT
4687         },
4688         { }
4689 };
4690
4691 /* l3_main_2 -> gpu */
4692 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4693         .master         = &omap44xx_l3_main_2_hwmod,
4694         .slave          = &omap44xx_gpu_hwmod,
4695         .clk            = "l3_div_ck",
4696         .addr           = omap44xx_gpu_addrs,
4697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4698 };
4699
4700 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4701         {
4702                 .pa_start       = 0x480b2000,
4703                 .pa_end         = 0x480b201f,
4704                 .flags          = ADDR_TYPE_RT
4705         },
4706         { }
4707 };
4708
4709 /* l4_per -> hdq1w */
4710 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4711         .master         = &omap44xx_l4_per_hwmod,
4712         .slave          = &omap44xx_hdq1w_hwmod,
4713         .clk            = "l4_div_ck",
4714         .addr           = omap44xx_hdq1w_addrs,
4715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4716 };
4717
4718 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4719         {
4720                 .pa_start       = 0x4a058000,
4721                 .pa_end         = 0x4a05bfff,
4722                 .flags          = ADDR_TYPE_RT
4723         },
4724         { }
4725 };
4726
4727 /* l4_cfg -> hsi */
4728 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4729         .master         = &omap44xx_l4_cfg_hwmod,
4730         .slave          = &omap44xx_hsi_hwmod,
4731         .clk            = "l4_div_ck",
4732         .addr           = omap44xx_hsi_addrs,
4733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4734 };
4735
4736 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4737         {
4738                 .pa_start       = 0x48070000,
4739                 .pa_end         = 0x480700ff,
4740                 .flags          = ADDR_TYPE_RT
4741         },
4742         { }
4743 };
4744
4745 /* l4_per -> i2c1 */
4746 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4747         .master         = &omap44xx_l4_per_hwmod,
4748         .slave          = &omap44xx_i2c1_hwmod,
4749         .clk            = "l4_div_ck",
4750         .addr           = omap44xx_i2c1_addrs,
4751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4752 };
4753
4754 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4755         {
4756                 .pa_start       = 0x48072000,
4757                 .pa_end         = 0x480720ff,
4758                 .flags          = ADDR_TYPE_RT
4759         },
4760         { }
4761 };
4762
4763 /* l4_per -> i2c2 */
4764 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4765         .master         = &omap44xx_l4_per_hwmod,
4766         .slave          = &omap44xx_i2c2_hwmod,
4767         .clk            = "l4_div_ck",
4768         .addr           = omap44xx_i2c2_addrs,
4769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4770 };
4771
4772 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4773         {
4774                 .pa_start       = 0x48060000,
4775                 .pa_end         = 0x480600ff,
4776                 .flags          = ADDR_TYPE_RT
4777         },
4778         { }
4779 };
4780
4781 /* l4_per -> i2c3 */
4782 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4783         .master         = &omap44xx_l4_per_hwmod,
4784         .slave          = &omap44xx_i2c3_hwmod,
4785         .clk            = "l4_div_ck",
4786         .addr           = omap44xx_i2c3_addrs,
4787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4788 };
4789
4790 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4791         {
4792                 .pa_start       = 0x48350000,
4793                 .pa_end         = 0x483500ff,
4794                 .flags          = ADDR_TYPE_RT
4795         },
4796         { }
4797 };
4798
4799 /* l4_per -> i2c4 */
4800 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4801         .master         = &omap44xx_l4_per_hwmod,
4802         .slave          = &omap44xx_i2c4_hwmod,
4803         .clk            = "l4_div_ck",
4804         .addr           = omap44xx_i2c4_addrs,
4805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4806 };
4807
4808 /* l3_main_2 -> ipu */
4809 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4810         .master         = &omap44xx_l3_main_2_hwmod,
4811         .slave          = &omap44xx_ipu_hwmod,
4812         .clk            = "l3_div_ck",
4813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4814 };
4815
4816 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4817         {
4818                 .pa_start       = 0x52000000,
4819                 .pa_end         = 0x520000ff,
4820                 .flags          = ADDR_TYPE_RT
4821         },
4822         { }
4823 };
4824
4825 /* l3_main_2 -> iss */
4826 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4827         .master         = &omap44xx_l3_main_2_hwmod,
4828         .slave          = &omap44xx_iss_hwmod,
4829         .clk            = "l3_div_ck",
4830         .addr           = omap44xx_iss_addrs,
4831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4832 };
4833
4834 /* iva -> sl2if */
4835 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4836         .master         = &omap44xx_iva_hwmod,
4837         .slave          = &omap44xx_sl2if_hwmod,
4838         .clk            = "dpll_iva_m5x2_ck",
4839         .user           = OCP_USER_IVA,
4840 };
4841
4842 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4843         {
4844                 .pa_start       = 0x5a000000,
4845                 .pa_end         = 0x5a07ffff,
4846                 .flags          = ADDR_TYPE_RT
4847         },
4848         { }
4849 };
4850
4851 /* l3_main_2 -> iva */
4852 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4853         .master         = &omap44xx_l3_main_2_hwmod,
4854         .slave          = &omap44xx_iva_hwmod,
4855         .clk            = "l3_div_ck",
4856         .addr           = omap44xx_iva_addrs,
4857         .user           = OCP_USER_MPU,
4858 };
4859
4860 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4861         {
4862                 .pa_start       = 0x4a31c000,
4863                 .pa_end         = 0x4a31c07f,
4864                 .flags          = ADDR_TYPE_RT
4865         },
4866         { }
4867 };
4868
4869 /* l4_wkup -> kbd */
4870 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4871         .master         = &omap44xx_l4_wkup_hwmod,
4872         .slave          = &omap44xx_kbd_hwmod,
4873         .clk            = "l4_wkup_clk_mux_ck",
4874         .addr           = omap44xx_kbd_addrs,
4875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4876 };
4877
4878 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4879         {
4880                 .pa_start       = 0x4a0f4000,
4881                 .pa_end         = 0x4a0f41ff,
4882                 .flags          = ADDR_TYPE_RT
4883         },
4884         { }
4885 };
4886
4887 /* l4_cfg -> mailbox */
4888 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4889         .master         = &omap44xx_l4_cfg_hwmod,
4890         .slave          = &omap44xx_mailbox_hwmod,
4891         .clk            = "l4_div_ck",
4892         .addr           = omap44xx_mailbox_addrs,
4893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4894 };
4895
4896 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4897         {
4898                 .pa_start       = 0x40128000,
4899                 .pa_end         = 0x401283ff,
4900                 .flags          = ADDR_TYPE_RT
4901         },
4902         { }
4903 };
4904
4905 /* l4_abe -> mcasp */
4906 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4907         .master         = &omap44xx_l4_abe_hwmod,
4908         .slave          = &omap44xx_mcasp_hwmod,
4909         .clk            = "ocp_abe_iclk",
4910         .addr           = omap44xx_mcasp_addrs,
4911         .user           = OCP_USER_MPU,
4912 };
4913
4914 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4915         {
4916                 .pa_start       = 0x49028000,
4917                 .pa_end         = 0x490283ff,
4918                 .flags          = ADDR_TYPE_RT
4919         },
4920         { }
4921 };
4922
4923 /* l4_abe -> mcasp (dma) */
4924 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4925         .master         = &omap44xx_l4_abe_hwmod,
4926         .slave          = &omap44xx_mcasp_hwmod,
4927         .clk            = "ocp_abe_iclk",
4928         .addr           = omap44xx_mcasp_dma_addrs,
4929         .user           = OCP_USER_SDMA,
4930 };
4931
4932 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4933         {
4934                 .name           = "mpu",
4935                 .pa_start       = 0x40122000,
4936                 .pa_end         = 0x401220ff,
4937                 .flags          = ADDR_TYPE_RT
4938         },
4939         { }
4940 };
4941
4942 /* l4_abe -> mcbsp1 */
4943 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4944         .master         = &omap44xx_l4_abe_hwmod,
4945         .slave          = &omap44xx_mcbsp1_hwmod,
4946         .clk            = "ocp_abe_iclk",
4947         .addr           = omap44xx_mcbsp1_addrs,
4948         .user           = OCP_USER_MPU,
4949 };
4950
4951 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4952         {
4953                 .name           = "dma",
4954                 .pa_start       = 0x49022000,
4955                 .pa_end         = 0x490220ff,
4956                 .flags          = ADDR_TYPE_RT
4957         },
4958         { }
4959 };
4960
4961 /* l4_abe -> mcbsp1 (dma) */
4962 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4963         .master         = &omap44xx_l4_abe_hwmod,
4964         .slave          = &omap44xx_mcbsp1_hwmod,
4965         .clk            = "ocp_abe_iclk",
4966         .addr           = omap44xx_mcbsp1_dma_addrs,
4967         .user           = OCP_USER_SDMA,
4968 };
4969
4970 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4971         {
4972                 .name           = "mpu",
4973                 .pa_start       = 0x40124000,
4974                 .pa_end         = 0x401240ff,
4975                 .flags          = ADDR_TYPE_RT
4976         },
4977         { }
4978 };
4979
4980 /* l4_abe -> mcbsp2 */
4981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4982         .master         = &omap44xx_l4_abe_hwmod,
4983         .slave          = &omap44xx_mcbsp2_hwmod,
4984         .clk            = "ocp_abe_iclk",
4985         .addr           = omap44xx_mcbsp2_addrs,
4986         .user           = OCP_USER_MPU,
4987 };
4988
4989 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4990         {
4991                 .name           = "dma",
4992                 .pa_start       = 0x49024000,
4993                 .pa_end         = 0x490240ff,
4994                 .flags          = ADDR_TYPE_RT
4995         },
4996         { }
4997 };
4998
4999 /* l4_abe -> mcbsp2 (dma) */
5000 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5001         .master         = &omap44xx_l4_abe_hwmod,
5002         .slave          = &omap44xx_mcbsp2_hwmod,
5003         .clk            = "ocp_abe_iclk",
5004         .addr           = omap44xx_mcbsp2_dma_addrs,
5005         .user           = OCP_USER_SDMA,
5006 };
5007
5008 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5009         {
5010                 .name           = "mpu",
5011                 .pa_start       = 0x40126000,
5012                 .pa_end         = 0x401260ff,
5013                 .flags          = ADDR_TYPE_RT
5014         },
5015         { }
5016 };
5017
5018 /* l4_abe -> mcbsp3 */
5019 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5020         .master         = &omap44xx_l4_abe_hwmod,
5021         .slave          = &omap44xx_mcbsp3_hwmod,
5022         .clk            = "ocp_abe_iclk",
5023         .addr           = omap44xx_mcbsp3_addrs,
5024         .user           = OCP_USER_MPU,
5025 };
5026
5027 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5028         {
5029                 .name           = "dma",
5030                 .pa_start       = 0x49026000,
5031                 .pa_end         = 0x490260ff,
5032                 .flags          = ADDR_TYPE_RT
5033         },
5034         { }
5035 };
5036
5037 /* l4_abe -> mcbsp3 (dma) */
5038 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5039         .master         = &omap44xx_l4_abe_hwmod,
5040         .slave          = &omap44xx_mcbsp3_hwmod,
5041         .clk            = "ocp_abe_iclk",
5042         .addr           = omap44xx_mcbsp3_dma_addrs,
5043         .user           = OCP_USER_SDMA,
5044 };
5045
5046 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5047         {
5048                 .pa_start       = 0x48096000,
5049                 .pa_end         = 0x480960ff,
5050                 .flags          = ADDR_TYPE_RT
5051         },
5052         { }
5053 };
5054
5055 /* l4_per -> mcbsp4 */
5056 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5057         .master         = &omap44xx_l4_per_hwmod,
5058         .slave          = &omap44xx_mcbsp4_hwmod,
5059         .clk            = "l4_div_ck",
5060         .addr           = omap44xx_mcbsp4_addrs,
5061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5062 };
5063
5064 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5065         {
5066                 .pa_start       = 0x40132000,
5067                 .pa_end         = 0x4013207f,
5068                 .flags          = ADDR_TYPE_RT
5069         },
5070         { }
5071 };
5072
5073 /* l4_abe -> mcpdm */
5074 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5075         .master         = &omap44xx_l4_abe_hwmod,
5076         .slave          = &omap44xx_mcpdm_hwmod,
5077         .clk            = "ocp_abe_iclk",
5078         .addr           = omap44xx_mcpdm_addrs,
5079         .user           = OCP_USER_MPU,
5080 };
5081
5082 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5083         {
5084                 .pa_start       = 0x49032000,
5085                 .pa_end         = 0x4903207f,
5086                 .flags          = ADDR_TYPE_RT
5087         },
5088         { }
5089 };
5090
5091 /* l4_abe -> mcpdm (dma) */
5092 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5093         .master         = &omap44xx_l4_abe_hwmod,
5094         .slave          = &omap44xx_mcpdm_hwmod,
5095         .clk            = "ocp_abe_iclk",
5096         .addr           = omap44xx_mcpdm_dma_addrs,
5097         .user           = OCP_USER_SDMA,
5098 };
5099
5100 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5101         {
5102                 .pa_start       = 0x48098000,
5103                 .pa_end         = 0x480981ff,
5104                 .flags          = ADDR_TYPE_RT
5105         },
5106         { }
5107 };
5108
5109 /* l4_per -> mcspi1 */
5110 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5111         .master         = &omap44xx_l4_per_hwmod,
5112         .slave          = &omap44xx_mcspi1_hwmod,
5113         .clk            = "l4_div_ck",
5114         .addr           = omap44xx_mcspi1_addrs,
5115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5116 };
5117
5118 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5119         {
5120                 .pa_start       = 0x4809a000,
5121                 .pa_end         = 0x4809a1ff,
5122                 .flags          = ADDR_TYPE_RT
5123         },
5124         { }
5125 };
5126
5127 /* l4_per -> mcspi2 */
5128 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5129         .master         = &omap44xx_l4_per_hwmod,
5130         .slave          = &omap44xx_mcspi2_hwmod,
5131         .clk            = "l4_div_ck",
5132         .addr           = omap44xx_mcspi2_addrs,
5133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5134 };
5135
5136 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5137         {
5138                 .pa_start       = 0x480b8000,
5139                 .pa_end         = 0x480b81ff,
5140                 .flags          = ADDR_TYPE_RT
5141         },
5142         { }
5143 };
5144
5145 /* l4_per -> mcspi3 */
5146 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5147         .master         = &omap44xx_l4_per_hwmod,
5148         .slave          = &omap44xx_mcspi3_hwmod,
5149         .clk            = "l4_div_ck",
5150         .addr           = omap44xx_mcspi3_addrs,
5151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5152 };
5153
5154 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5155         {
5156                 .pa_start       = 0x480ba000,
5157                 .pa_end         = 0x480ba1ff,
5158                 .flags          = ADDR_TYPE_RT
5159         },
5160         { }
5161 };
5162
5163 /* l4_per -> mcspi4 */
5164 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5165         .master         = &omap44xx_l4_per_hwmod,
5166         .slave          = &omap44xx_mcspi4_hwmod,
5167         .clk            = "l4_div_ck",
5168         .addr           = omap44xx_mcspi4_addrs,
5169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5170 };
5171
5172 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5173         {
5174                 .pa_start       = 0x4809c000,
5175                 .pa_end         = 0x4809c3ff,
5176                 .flags          = ADDR_TYPE_RT
5177         },
5178         { }
5179 };
5180
5181 /* l4_per -> mmc1 */
5182 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5183         .master         = &omap44xx_l4_per_hwmod,
5184         .slave          = &omap44xx_mmc1_hwmod,
5185         .clk            = "l4_div_ck",
5186         .addr           = omap44xx_mmc1_addrs,
5187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5188 };
5189
5190 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5191         {
5192                 .pa_start       = 0x480b4000,
5193                 .pa_end         = 0x480b43ff,
5194                 .flags          = ADDR_TYPE_RT
5195         },
5196         { }
5197 };
5198
5199 /* l4_per -> mmc2 */
5200 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5201         .master         = &omap44xx_l4_per_hwmod,
5202         .slave          = &omap44xx_mmc2_hwmod,
5203         .clk            = "l4_div_ck",
5204         .addr           = omap44xx_mmc2_addrs,
5205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5206 };
5207
5208 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5209         {
5210                 .pa_start       = 0x480ad000,
5211                 .pa_end         = 0x480ad3ff,
5212                 .flags          = ADDR_TYPE_RT
5213         },
5214         { }
5215 };
5216
5217 /* l4_per -> mmc3 */
5218 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5219         .master         = &omap44xx_l4_per_hwmod,
5220         .slave          = &omap44xx_mmc3_hwmod,
5221         .clk            = "l4_div_ck",
5222         .addr           = omap44xx_mmc3_addrs,
5223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5224 };
5225
5226 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5227         {
5228                 .pa_start       = 0x480d1000,
5229                 .pa_end         = 0x480d13ff,
5230                 .flags          = ADDR_TYPE_RT
5231         },
5232         { }
5233 };
5234
5235 /* l4_per -> mmc4 */
5236 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5237         .master         = &omap44xx_l4_per_hwmod,
5238         .slave          = &omap44xx_mmc4_hwmod,
5239         .clk            = "l4_div_ck",
5240         .addr           = omap44xx_mmc4_addrs,
5241         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5242 };
5243
5244 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5245         {
5246                 .pa_start       = 0x480d5000,
5247                 .pa_end         = 0x480d53ff,
5248                 .flags          = ADDR_TYPE_RT
5249         },
5250         { }
5251 };
5252
5253 /* l4_per -> mmc5 */
5254 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5255         .master         = &omap44xx_l4_per_hwmod,
5256         .slave          = &omap44xx_mmc5_hwmod,
5257         .clk            = "l4_div_ck",
5258         .addr           = omap44xx_mmc5_addrs,
5259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5260 };
5261
5262 /* l3_main_2 -> ocmc_ram */
5263 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5264         .master         = &omap44xx_l3_main_2_hwmod,
5265         .slave          = &omap44xx_ocmc_ram_hwmod,
5266         .clk            = "l3_div_ck",
5267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5268 };
5269
5270 /* l4_cfg -> ocp2scp_usb_phy */
5271 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5272         .master         = &omap44xx_l4_cfg_hwmod,
5273         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5274         .clk            = "l4_div_ck",
5275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5276 };
5277
5278 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5279         {
5280                 .pa_start       = 0x48243000,
5281                 .pa_end         = 0x48243fff,
5282                 .flags          = ADDR_TYPE_RT
5283         },
5284         { }
5285 };
5286
5287 /* mpu_private -> prcm_mpu */
5288 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5289         .master         = &omap44xx_mpu_private_hwmod,
5290         .slave          = &omap44xx_prcm_mpu_hwmod,
5291         .clk            = "l3_div_ck",
5292         .addr           = omap44xx_prcm_mpu_addrs,
5293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5294 };
5295
5296 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5297         {
5298                 .pa_start       = 0x4a004000,
5299                 .pa_end         = 0x4a004fff,
5300                 .flags          = ADDR_TYPE_RT
5301         },
5302         { }
5303 };
5304
5305 /* l4_wkup -> cm_core_aon */
5306 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5307         .master         = &omap44xx_l4_wkup_hwmod,
5308         .slave          = &omap44xx_cm_core_aon_hwmod,
5309         .clk            = "l4_wkup_clk_mux_ck",
5310         .addr           = omap44xx_cm_core_aon_addrs,
5311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5312 };
5313
5314 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5315         {
5316                 .pa_start       = 0x4a008000,
5317                 .pa_end         = 0x4a009fff,
5318                 .flags          = ADDR_TYPE_RT
5319         },
5320         { }
5321 };
5322
5323 /* l4_cfg -> cm_core */
5324 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5325         .master         = &omap44xx_l4_cfg_hwmod,
5326         .slave          = &omap44xx_cm_core_hwmod,
5327         .clk            = "l4_div_ck",
5328         .addr           = omap44xx_cm_core_addrs,
5329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5330 };
5331
5332 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5333         {
5334                 .pa_start       = 0x4a306000,
5335                 .pa_end         = 0x4a307fff,
5336                 .flags          = ADDR_TYPE_RT
5337         },
5338         { }
5339 };
5340
5341 /* l4_wkup -> prm */
5342 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5343         .master         = &omap44xx_l4_wkup_hwmod,
5344         .slave          = &omap44xx_prm_hwmod,
5345         .clk            = "l4_wkup_clk_mux_ck",
5346         .addr           = omap44xx_prm_addrs,
5347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5348 };
5349
5350 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5351         {
5352                 .pa_start       = 0x4a30a000,
5353                 .pa_end         = 0x4a30a7ff,
5354                 .flags          = ADDR_TYPE_RT
5355         },
5356         { }
5357 };
5358
5359 /* l4_wkup -> scrm */
5360 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5361         .master         = &omap44xx_l4_wkup_hwmod,
5362         .slave          = &omap44xx_scrm_hwmod,
5363         .clk            = "l4_wkup_clk_mux_ck",
5364         .addr           = omap44xx_scrm_addrs,
5365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5366 };
5367
5368 /* l3_main_2 -> sl2if */
5369 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5370         .master         = &omap44xx_l3_main_2_hwmod,
5371         .slave          = &omap44xx_sl2if_hwmod,
5372         .clk            = "l3_div_ck",
5373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5374 };
5375
5376 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5377         {
5378                 .pa_start       = 0x4012c000,
5379                 .pa_end         = 0x4012c3ff,
5380                 .flags          = ADDR_TYPE_RT
5381         },
5382         { }
5383 };
5384
5385 /* l4_abe -> slimbus1 */
5386 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5387         .master         = &omap44xx_l4_abe_hwmod,
5388         .slave          = &omap44xx_slimbus1_hwmod,
5389         .clk            = "ocp_abe_iclk",
5390         .addr           = omap44xx_slimbus1_addrs,
5391         .user           = OCP_USER_MPU,
5392 };
5393
5394 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5395         {
5396                 .pa_start       = 0x4902c000,
5397                 .pa_end         = 0x4902c3ff,
5398                 .flags          = ADDR_TYPE_RT
5399         },
5400         { }
5401 };
5402
5403 /* l4_abe -> slimbus1 (dma) */
5404 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5405         .master         = &omap44xx_l4_abe_hwmod,
5406         .slave          = &omap44xx_slimbus1_hwmod,
5407         .clk            = "ocp_abe_iclk",
5408         .addr           = omap44xx_slimbus1_dma_addrs,
5409         .user           = OCP_USER_SDMA,
5410 };
5411
5412 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5413         {
5414                 .pa_start       = 0x48076000,
5415                 .pa_end         = 0x480763ff,
5416                 .flags          = ADDR_TYPE_RT
5417         },
5418         { }
5419 };
5420
5421 /* l4_per -> slimbus2 */
5422 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5423         .master         = &omap44xx_l4_per_hwmod,
5424         .slave          = &omap44xx_slimbus2_hwmod,
5425         .clk            = "l4_div_ck",
5426         .addr           = omap44xx_slimbus2_addrs,
5427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5428 };
5429
5430 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5431         {
5432                 .pa_start       = 0x4a0dd000,
5433                 .pa_end         = 0x4a0dd03f,
5434                 .flags          = ADDR_TYPE_RT
5435         },
5436         { }
5437 };
5438
5439 /* l4_cfg -> smartreflex_core */
5440 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5441         .master         = &omap44xx_l4_cfg_hwmod,
5442         .slave          = &omap44xx_smartreflex_core_hwmod,
5443         .clk            = "l4_div_ck",
5444         .addr           = omap44xx_smartreflex_core_addrs,
5445         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5446 };
5447
5448 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5449         {
5450                 .pa_start       = 0x4a0db000,
5451                 .pa_end         = 0x4a0db03f,
5452                 .flags          = ADDR_TYPE_RT
5453         },
5454         { }
5455 };
5456
5457 /* l4_cfg -> smartreflex_iva */
5458 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5459         .master         = &omap44xx_l4_cfg_hwmod,
5460         .slave          = &omap44xx_smartreflex_iva_hwmod,
5461         .clk            = "l4_div_ck",
5462         .addr           = omap44xx_smartreflex_iva_addrs,
5463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5464 };
5465
5466 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5467         {
5468                 .pa_start       = 0x4a0d9000,
5469                 .pa_end         = 0x4a0d903f,
5470                 .flags          = ADDR_TYPE_RT
5471         },
5472         { }
5473 };
5474
5475 /* l4_cfg -> smartreflex_mpu */
5476 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5477         .master         = &omap44xx_l4_cfg_hwmod,
5478         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5479         .clk            = "l4_div_ck",
5480         .addr           = omap44xx_smartreflex_mpu_addrs,
5481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5482 };
5483
5484 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5485         {
5486                 .pa_start       = 0x4a0f6000,
5487                 .pa_end         = 0x4a0f6fff,
5488                 .flags          = ADDR_TYPE_RT
5489         },
5490         { }
5491 };
5492
5493 /* l4_cfg -> spinlock */
5494 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5495         .master         = &omap44xx_l4_cfg_hwmod,
5496         .slave          = &omap44xx_spinlock_hwmod,
5497         .clk            = "l4_div_ck",
5498         .addr           = omap44xx_spinlock_addrs,
5499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5500 };
5501
5502 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5503         {
5504                 .pa_start       = 0x4a318000,
5505                 .pa_end         = 0x4a31807f,
5506                 .flags          = ADDR_TYPE_RT
5507         },
5508         { }
5509 };
5510
5511 /* l4_wkup -> timer1 */
5512 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5513         .master         = &omap44xx_l4_wkup_hwmod,
5514         .slave          = &omap44xx_timer1_hwmod,
5515         .clk            = "l4_wkup_clk_mux_ck",
5516         .addr           = omap44xx_timer1_addrs,
5517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5518 };
5519
5520 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5521         {
5522                 .pa_start       = 0x48032000,
5523                 .pa_end         = 0x4803207f,
5524                 .flags          = ADDR_TYPE_RT
5525         },
5526         { }
5527 };
5528
5529 /* l4_per -> timer2 */
5530 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5531         .master         = &omap44xx_l4_per_hwmod,
5532         .slave          = &omap44xx_timer2_hwmod,
5533         .clk            = "l4_div_ck",
5534         .addr           = omap44xx_timer2_addrs,
5535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5536 };
5537
5538 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5539         {
5540                 .pa_start       = 0x48034000,
5541                 .pa_end         = 0x4803407f,
5542                 .flags          = ADDR_TYPE_RT
5543         },
5544         { }
5545 };
5546
5547 /* l4_per -> timer3 */
5548 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5549         .master         = &omap44xx_l4_per_hwmod,
5550         .slave          = &omap44xx_timer3_hwmod,
5551         .clk            = "l4_div_ck",
5552         .addr           = omap44xx_timer3_addrs,
5553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5554 };
5555
5556 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5557         {
5558                 .pa_start       = 0x48036000,
5559                 .pa_end         = 0x4803607f,
5560                 .flags          = ADDR_TYPE_RT
5561         },
5562         { }
5563 };
5564
5565 /* l4_per -> timer4 */
5566 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5567         .master         = &omap44xx_l4_per_hwmod,
5568         .slave          = &omap44xx_timer4_hwmod,
5569         .clk            = "l4_div_ck",
5570         .addr           = omap44xx_timer4_addrs,
5571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5572 };
5573
5574 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5575         {
5576                 .pa_start       = 0x40138000,
5577                 .pa_end         = 0x4013807f,
5578                 .flags          = ADDR_TYPE_RT
5579         },
5580         { }
5581 };
5582
5583 /* l4_abe -> timer5 */
5584 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5585         .master         = &omap44xx_l4_abe_hwmod,
5586         .slave          = &omap44xx_timer5_hwmod,
5587         .clk            = "ocp_abe_iclk",
5588         .addr           = omap44xx_timer5_addrs,
5589         .user           = OCP_USER_MPU,
5590 };
5591
5592 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5593         {
5594                 .pa_start       = 0x49038000,
5595                 .pa_end         = 0x4903807f,
5596                 .flags          = ADDR_TYPE_RT
5597         },
5598         { }
5599 };
5600
5601 /* l4_abe -> timer5 (dma) */
5602 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5603         .master         = &omap44xx_l4_abe_hwmod,
5604         .slave          = &omap44xx_timer5_hwmod,
5605         .clk            = "ocp_abe_iclk",
5606         .addr           = omap44xx_timer5_dma_addrs,
5607         .user           = OCP_USER_SDMA,
5608 };
5609
5610 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5611         {
5612                 .pa_start       = 0x4013a000,
5613                 .pa_end         = 0x4013a07f,
5614                 .flags          = ADDR_TYPE_RT
5615         },
5616         { }
5617 };
5618
5619 /* l4_abe -> timer6 */
5620 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5621         .master         = &omap44xx_l4_abe_hwmod,
5622         .slave          = &omap44xx_timer6_hwmod,
5623         .clk            = "ocp_abe_iclk",
5624         .addr           = omap44xx_timer6_addrs,
5625         .user           = OCP_USER_MPU,
5626 };
5627
5628 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5629         {
5630                 .pa_start       = 0x4903a000,
5631                 .pa_end         = 0x4903a07f,
5632                 .flags          = ADDR_TYPE_RT
5633         },
5634         { }
5635 };
5636
5637 /* l4_abe -> timer6 (dma) */
5638 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5639         .master         = &omap44xx_l4_abe_hwmod,
5640         .slave          = &omap44xx_timer6_hwmod,
5641         .clk            = "ocp_abe_iclk",
5642         .addr           = omap44xx_timer6_dma_addrs,
5643         .user           = OCP_USER_SDMA,
5644 };
5645
5646 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5647         {
5648                 .pa_start       = 0x4013c000,
5649                 .pa_end         = 0x4013c07f,
5650                 .flags          = ADDR_TYPE_RT
5651         },
5652         { }
5653 };
5654
5655 /* l4_abe -> timer7 */
5656 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5657         .master         = &omap44xx_l4_abe_hwmod,
5658         .slave          = &omap44xx_timer7_hwmod,
5659         .clk            = "ocp_abe_iclk",
5660         .addr           = omap44xx_timer7_addrs,
5661         .user           = OCP_USER_MPU,
5662 };
5663
5664 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5665         {
5666                 .pa_start       = 0x4903c000,
5667                 .pa_end         = 0x4903c07f,
5668                 .flags          = ADDR_TYPE_RT
5669         },
5670         { }
5671 };
5672
5673 /* l4_abe -> timer7 (dma) */
5674 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5675         .master         = &omap44xx_l4_abe_hwmod,
5676         .slave          = &omap44xx_timer7_hwmod,
5677         .clk            = "ocp_abe_iclk",
5678         .addr           = omap44xx_timer7_dma_addrs,
5679         .user           = OCP_USER_SDMA,
5680 };
5681
5682 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5683         {
5684                 .pa_start       = 0x4013e000,
5685                 .pa_end         = 0x4013e07f,
5686                 .flags          = ADDR_TYPE_RT
5687         },
5688         { }
5689 };
5690
5691 /* l4_abe -> timer8 */
5692 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5693         .master         = &omap44xx_l4_abe_hwmod,
5694         .slave          = &omap44xx_timer8_hwmod,
5695         .clk            = "ocp_abe_iclk",
5696         .addr           = omap44xx_timer8_addrs,
5697         .user           = OCP_USER_MPU,
5698 };
5699
5700 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5701         {
5702                 .pa_start       = 0x4903e000,
5703                 .pa_end         = 0x4903e07f,
5704                 .flags          = ADDR_TYPE_RT
5705         },
5706         { }
5707 };
5708
5709 /* l4_abe -> timer8 (dma) */
5710 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5711         .master         = &omap44xx_l4_abe_hwmod,
5712         .slave          = &omap44xx_timer8_hwmod,
5713         .clk            = "ocp_abe_iclk",
5714         .addr           = omap44xx_timer8_dma_addrs,
5715         .user           = OCP_USER_SDMA,
5716 };
5717
5718 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5719         {
5720                 .pa_start       = 0x4803e000,
5721                 .pa_end         = 0x4803e07f,
5722                 .flags          = ADDR_TYPE_RT
5723         },
5724         { }
5725 };
5726
5727 /* l4_per -> timer9 */
5728 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5729         .master         = &omap44xx_l4_per_hwmod,
5730         .slave          = &omap44xx_timer9_hwmod,
5731         .clk            = "l4_div_ck",
5732         .addr           = omap44xx_timer9_addrs,
5733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5734 };
5735
5736 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5737         {
5738                 .pa_start       = 0x48086000,
5739                 .pa_end         = 0x4808607f,
5740                 .flags          = ADDR_TYPE_RT
5741         },
5742         { }
5743 };
5744
5745 /* l4_per -> timer10 */
5746 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5747         .master         = &omap44xx_l4_per_hwmod,
5748         .slave          = &omap44xx_timer10_hwmod,
5749         .clk            = "l4_div_ck",
5750         .addr           = omap44xx_timer10_addrs,
5751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5752 };
5753
5754 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5755         {
5756                 .pa_start       = 0x48088000,
5757                 .pa_end         = 0x4808807f,
5758                 .flags          = ADDR_TYPE_RT
5759         },
5760         { }
5761 };
5762
5763 /* l4_per -> timer11 */
5764 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5765         .master         = &omap44xx_l4_per_hwmod,
5766         .slave          = &omap44xx_timer11_hwmod,
5767         .clk            = "l4_div_ck",
5768         .addr           = omap44xx_timer11_addrs,
5769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5770 };
5771
5772 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5773         {
5774                 .pa_start       = 0x4806a000,
5775                 .pa_end         = 0x4806a0ff,
5776                 .flags          = ADDR_TYPE_RT
5777         },
5778         { }
5779 };
5780
5781 /* l4_per -> uart1 */
5782 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5783         .master         = &omap44xx_l4_per_hwmod,
5784         .slave          = &omap44xx_uart1_hwmod,
5785         .clk            = "l4_div_ck",
5786         .addr           = omap44xx_uart1_addrs,
5787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5788 };
5789
5790 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5791         {
5792                 .pa_start       = 0x4806c000,
5793                 .pa_end         = 0x4806c0ff,
5794                 .flags          = ADDR_TYPE_RT
5795         },
5796         { }
5797 };
5798
5799 /* l4_per -> uart2 */
5800 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5801         .master         = &omap44xx_l4_per_hwmod,
5802         .slave          = &omap44xx_uart2_hwmod,
5803         .clk            = "l4_div_ck",
5804         .addr           = omap44xx_uart2_addrs,
5805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5806 };
5807
5808 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5809         {
5810                 .pa_start       = 0x48020000,
5811                 .pa_end         = 0x480200ff,
5812                 .flags          = ADDR_TYPE_RT
5813         },
5814         { }
5815 };
5816
5817 /* l4_per -> uart3 */
5818 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5819         .master         = &omap44xx_l4_per_hwmod,
5820         .slave          = &omap44xx_uart3_hwmod,
5821         .clk            = "l4_div_ck",
5822         .addr           = omap44xx_uart3_addrs,
5823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5824 };
5825
5826 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5827         {
5828                 .pa_start       = 0x4806e000,
5829                 .pa_end         = 0x4806e0ff,
5830                 .flags          = ADDR_TYPE_RT
5831         },
5832         { }
5833 };
5834
5835 /* l4_per -> uart4 */
5836 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5837         .master         = &omap44xx_l4_per_hwmod,
5838         .slave          = &omap44xx_uart4_hwmod,
5839         .clk            = "l4_div_ck",
5840         .addr           = omap44xx_uart4_addrs,
5841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5842 };
5843
5844 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5845         {
5846                 .pa_start       = 0x4a0a9000,
5847                 .pa_end         = 0x4a0a93ff,
5848                 .flags          = ADDR_TYPE_RT
5849         },
5850         { }
5851 };
5852
5853 /* l4_cfg -> usb_host_fs */
5854 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5855         .master         = &omap44xx_l4_cfg_hwmod,
5856         .slave          = &omap44xx_usb_host_fs_hwmod,
5857         .clk            = "l4_div_ck",
5858         .addr           = omap44xx_usb_host_fs_addrs,
5859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5860 };
5861
5862 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5863         {
5864                 .name           = "uhh",
5865                 .pa_start       = 0x4a064000,
5866                 .pa_end         = 0x4a0647ff,
5867                 .flags          = ADDR_TYPE_RT
5868         },
5869         {
5870                 .name           = "ohci",
5871                 .pa_start       = 0x4a064800,
5872                 .pa_end         = 0x4a064bff,
5873         },
5874         {
5875                 .name           = "ehci",
5876                 .pa_start       = 0x4a064c00,
5877                 .pa_end         = 0x4a064fff,
5878         },
5879         {}
5880 };
5881
5882 /* l4_cfg -> usb_host_hs */
5883 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5884         .master         = &omap44xx_l4_cfg_hwmod,
5885         .slave          = &omap44xx_usb_host_hs_hwmod,
5886         .clk            = "l4_div_ck",
5887         .addr           = omap44xx_usb_host_hs_addrs,
5888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5889 };
5890
5891 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5892         {
5893                 .pa_start       = 0x4a0ab000,
5894                 .pa_end         = 0x4a0ab003,
5895                 .flags          = ADDR_TYPE_RT
5896         },
5897         { }
5898 };
5899
5900 /* l4_cfg -> usb_otg_hs */
5901 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5902         .master         = &omap44xx_l4_cfg_hwmod,
5903         .slave          = &omap44xx_usb_otg_hs_hwmod,
5904         .clk            = "l4_div_ck",
5905         .addr           = omap44xx_usb_otg_hs_addrs,
5906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5907 };
5908
5909 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5910         {
5911                 .name           = "tll",
5912                 .pa_start       = 0x4a062000,
5913                 .pa_end         = 0x4a063fff,
5914                 .flags          = ADDR_TYPE_RT
5915         },
5916         {}
5917 };
5918
5919 /* l4_cfg -> usb_tll_hs */
5920 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5921         .master         = &omap44xx_l4_cfg_hwmod,
5922         .slave          = &omap44xx_usb_tll_hs_hwmod,
5923         .clk            = "l4_div_ck",
5924         .addr           = omap44xx_usb_tll_hs_addrs,
5925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5926 };
5927
5928 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5929         {
5930                 .pa_start       = 0x4a314000,
5931                 .pa_end         = 0x4a31407f,
5932                 .flags          = ADDR_TYPE_RT
5933         },
5934         { }
5935 };
5936
5937 /* l4_wkup -> wd_timer2 */
5938 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5939         .master         = &omap44xx_l4_wkup_hwmod,
5940         .slave          = &omap44xx_wd_timer2_hwmod,
5941         .clk            = "l4_wkup_clk_mux_ck",
5942         .addr           = omap44xx_wd_timer2_addrs,
5943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5944 };
5945
5946 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5947         {
5948                 .pa_start       = 0x40130000,
5949                 .pa_end         = 0x4013007f,
5950                 .flags          = ADDR_TYPE_RT
5951         },
5952         { }
5953 };
5954
5955 /* l4_abe -> wd_timer3 */
5956 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5957         .master         = &omap44xx_l4_abe_hwmod,
5958         .slave          = &omap44xx_wd_timer3_hwmod,
5959         .clk            = "ocp_abe_iclk",
5960         .addr           = omap44xx_wd_timer3_addrs,
5961         .user           = OCP_USER_MPU,
5962 };
5963
5964 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5965         {
5966                 .pa_start       = 0x49030000,
5967                 .pa_end         = 0x4903007f,
5968                 .flags          = ADDR_TYPE_RT
5969         },
5970         { }
5971 };
5972
5973 /* l4_abe -> wd_timer3 (dma) */
5974 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5975         .master         = &omap44xx_l4_abe_hwmod,
5976         .slave          = &omap44xx_wd_timer3_hwmod,
5977         .clk            = "ocp_abe_iclk",
5978         .addr           = omap44xx_wd_timer3_dma_addrs,
5979         .user           = OCP_USER_SDMA,
5980 };
5981
5982 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5983         &omap44xx_c2c__c2c_target_fw,
5984         &omap44xx_l4_cfg__c2c_target_fw,
5985         &omap44xx_l3_main_1__dmm,
5986         &omap44xx_mpu__dmm,
5987         &omap44xx_c2c__emif_fw,
5988         &omap44xx_dmm__emif_fw,
5989         &omap44xx_l4_cfg__emif_fw,
5990         &omap44xx_iva__l3_instr,
5991         &omap44xx_l3_main_3__l3_instr,
5992         &omap44xx_ocp_wp_noc__l3_instr,
5993         &omap44xx_dsp__l3_main_1,
5994         &omap44xx_dss__l3_main_1,
5995         &omap44xx_l3_main_2__l3_main_1,
5996         &omap44xx_l4_cfg__l3_main_1,
5997         &omap44xx_mmc1__l3_main_1,
5998         &omap44xx_mmc2__l3_main_1,
5999         &omap44xx_mpu__l3_main_1,
6000         &omap44xx_c2c_target_fw__l3_main_2,
6001         &omap44xx_debugss__l3_main_2,
6002         &omap44xx_dma_system__l3_main_2,
6003         &omap44xx_fdif__l3_main_2,
6004         &omap44xx_gpu__l3_main_2,
6005         &omap44xx_hsi__l3_main_2,
6006         &omap44xx_ipu__l3_main_2,
6007         &omap44xx_iss__l3_main_2,
6008         &omap44xx_iva__l3_main_2,
6009         &omap44xx_l3_main_1__l3_main_2,
6010         &omap44xx_l4_cfg__l3_main_2,
6011         /* &omap44xx_usb_host_fs__l3_main_2, */
6012         &omap44xx_usb_host_hs__l3_main_2,
6013         &omap44xx_usb_otg_hs__l3_main_2,
6014         &omap44xx_l3_main_1__l3_main_3,
6015         &omap44xx_l3_main_2__l3_main_3,
6016         &omap44xx_l4_cfg__l3_main_3,
6017         /* &omap44xx_aess__l4_abe, */
6018         &omap44xx_dsp__l4_abe,
6019         &omap44xx_l3_main_1__l4_abe,
6020         &omap44xx_mpu__l4_abe,
6021         &omap44xx_l3_main_1__l4_cfg,
6022         &omap44xx_l3_main_2__l4_per,
6023         &omap44xx_l4_cfg__l4_wkup,
6024         &omap44xx_mpu__mpu_private,
6025         &omap44xx_l4_cfg__ocp_wp_noc,
6026         /* &omap44xx_l4_abe__aess, */
6027         /* &omap44xx_l4_abe__aess_dma, */
6028         &omap44xx_l3_main_2__c2c,
6029         &omap44xx_l4_wkup__counter_32k,
6030         &omap44xx_l4_cfg__ctrl_module_core,
6031         &omap44xx_l4_cfg__ctrl_module_pad_core,
6032         &omap44xx_l4_wkup__ctrl_module_wkup,
6033         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6034         &omap44xx_l3_instr__debugss,
6035         &omap44xx_l4_cfg__dma_system,
6036         &omap44xx_l4_abe__dmic,
6037         &omap44xx_l4_abe__dmic_dma,
6038         &omap44xx_dsp__iva,
6039         &omap44xx_dsp__sl2if,
6040         &omap44xx_l4_cfg__dsp,
6041         &omap44xx_l3_main_2__dss,
6042         &omap44xx_l4_per__dss,
6043         &omap44xx_l3_main_2__dss_dispc,
6044         &omap44xx_l4_per__dss_dispc,
6045         &omap44xx_l3_main_2__dss_dsi1,
6046         &omap44xx_l4_per__dss_dsi1,
6047         &omap44xx_l3_main_2__dss_dsi2,
6048         &omap44xx_l4_per__dss_dsi2,
6049         &omap44xx_l3_main_2__dss_hdmi,
6050         &omap44xx_l4_per__dss_hdmi,
6051         &omap44xx_l3_main_2__dss_rfbi,
6052         &omap44xx_l4_per__dss_rfbi,
6053         &omap44xx_l3_main_2__dss_venc,
6054         &omap44xx_l4_per__dss_venc,
6055         &omap44xx_l4_per__elm,
6056         &omap44xx_emif_fw__emif1,
6057         &omap44xx_emif_fw__emif2,
6058         &omap44xx_l4_cfg__fdif,
6059         &omap44xx_l4_wkup__gpio1,
6060         &omap44xx_l4_per__gpio2,
6061         &omap44xx_l4_per__gpio3,
6062         &omap44xx_l4_per__gpio4,
6063         &omap44xx_l4_per__gpio5,
6064         &omap44xx_l4_per__gpio6,
6065         &omap44xx_l3_main_2__gpmc,
6066         &omap44xx_l3_main_2__gpu,
6067         &omap44xx_l4_per__hdq1w,
6068         &omap44xx_l4_cfg__hsi,
6069         &omap44xx_l4_per__i2c1,
6070         &omap44xx_l4_per__i2c2,
6071         &omap44xx_l4_per__i2c3,
6072         &omap44xx_l4_per__i2c4,
6073         &omap44xx_l3_main_2__ipu,
6074         &omap44xx_l3_main_2__iss,
6075         &omap44xx_iva__sl2if,
6076         &omap44xx_l3_main_2__iva,
6077         &omap44xx_l4_wkup__kbd,
6078         &omap44xx_l4_cfg__mailbox,
6079         &omap44xx_l4_abe__mcasp,
6080         &omap44xx_l4_abe__mcasp_dma,
6081         &omap44xx_l4_abe__mcbsp1,
6082         &omap44xx_l4_abe__mcbsp1_dma,
6083         &omap44xx_l4_abe__mcbsp2,
6084         &omap44xx_l4_abe__mcbsp2_dma,
6085         &omap44xx_l4_abe__mcbsp3,
6086         &omap44xx_l4_abe__mcbsp3_dma,
6087         &omap44xx_l4_per__mcbsp4,
6088         &omap44xx_l4_abe__mcpdm,
6089         &omap44xx_l4_abe__mcpdm_dma,
6090         &omap44xx_l4_per__mcspi1,
6091         &omap44xx_l4_per__mcspi2,
6092         &omap44xx_l4_per__mcspi3,
6093         &omap44xx_l4_per__mcspi4,
6094         &omap44xx_l4_per__mmc1,
6095         &omap44xx_l4_per__mmc2,
6096         &omap44xx_l4_per__mmc3,
6097         &omap44xx_l4_per__mmc4,
6098         &omap44xx_l4_per__mmc5,
6099         &omap44xx_l3_main_2__ocmc_ram,
6100         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6101         &omap44xx_mpu_private__prcm_mpu,
6102         &omap44xx_l4_wkup__cm_core_aon,
6103         &omap44xx_l4_cfg__cm_core,
6104         &omap44xx_l4_wkup__prm,
6105         &omap44xx_l4_wkup__scrm,
6106         &omap44xx_l3_main_2__sl2if,
6107         &omap44xx_l4_abe__slimbus1,
6108         &omap44xx_l4_abe__slimbus1_dma,
6109         &omap44xx_l4_per__slimbus2,
6110         &omap44xx_l4_cfg__smartreflex_core,
6111         &omap44xx_l4_cfg__smartreflex_iva,
6112         &omap44xx_l4_cfg__smartreflex_mpu,
6113         &omap44xx_l4_cfg__spinlock,
6114         &omap44xx_l4_wkup__timer1,
6115         &omap44xx_l4_per__timer2,
6116         &omap44xx_l4_per__timer3,
6117         &omap44xx_l4_per__timer4,
6118         &omap44xx_l4_abe__timer5,
6119         &omap44xx_l4_abe__timer5_dma,
6120         &omap44xx_l4_abe__timer6,
6121         &omap44xx_l4_abe__timer6_dma,
6122         &omap44xx_l4_abe__timer7,
6123         &omap44xx_l4_abe__timer7_dma,
6124         &omap44xx_l4_abe__timer8,
6125         &omap44xx_l4_abe__timer8_dma,
6126         &omap44xx_l4_per__timer9,
6127         &omap44xx_l4_per__timer10,
6128         &omap44xx_l4_per__timer11,
6129         &omap44xx_l4_per__uart1,
6130         &omap44xx_l4_per__uart2,
6131         &omap44xx_l4_per__uart3,
6132         &omap44xx_l4_per__uart4,
6133         /* &omap44xx_l4_cfg__usb_host_fs, */
6134         &omap44xx_l4_cfg__usb_host_hs,
6135         &omap44xx_l4_cfg__usb_otg_hs,
6136         &omap44xx_l4_cfg__usb_tll_hs,
6137         &omap44xx_l4_wkup__wd_timer2,
6138         &omap44xx_l4_abe__wd_timer3,
6139         &omap44xx_l4_abe__wd_timer3_dma,
6140         NULL,
6141 };
6142
6143 int __init omap44xx_hwmod_init(void)
6144 {
6145         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6146 }
6147