arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/mcbsp.h>
  29 #include <plat/mmc.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "prm44xx.h"
  36 #include "prm-regbits-44xx.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP4 interrupts external to MPUSS */
  40 #define OMAP44XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP4 dma requests */
  43 #define OMAP44XX_DMA_REQ_START  1
  44
  45 /* Backward references (IPs with Bus Master capability) */
  46 static struct omap_hwmod omap44xx_aess_hwmod;
  47 static struct omap_hwmod omap44xx_dma_system_hwmod;
  48 static struct omap_hwmod omap44xx_dmm_hwmod;
  49 static struct omap_hwmod omap44xx_dsp_hwmod;
  50 static struct omap_hwmod omap44xx_dss_hwmod;
  51 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  52 static struct omap_hwmod omap44xx_hsi_hwmod;
  53 static struct omap_hwmod omap44xx_ipu_hwmod;
  54 static struct omap_hwmod omap44xx_iss_hwmod;
  55 static struct omap_hwmod omap44xx_iva_hwmod;
  56 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  57 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  58 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  60 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  61 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  62 static struct omap_hwmod omap44xx_l4_per_hwmod;
  63 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  64 static struct omap_hwmod omap44xx_mmc1_hwmod;
  65 static struct omap_hwmod omap44xx_mmc2_hwmod;
  66 static struct omap_hwmod omap44xx_mpu_hwmod;
  67 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  68 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  69
  70 /*
  71  * Interconnects omap_hwmod structures
  72  * hwmods that compose the global OMAP interconnect
  73  */
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 /* l3_main_1 -> dmm */
  90 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  91         .master         = &omap44xx_l3_main_1_hwmod,
  92         .slave          = &omap44xx_dmm_hwmod,
  93         .clk            = "l3_div_ck",
  94         .user           = OCP_USER_SDMA,
  95 };
  96
  97 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  98         {
  99                 .pa_start       = 0x4e000000,
 100                 .pa_end         = 0x4e0007ff,
 101                 .flags          = ADDR_TYPE_RT
 102         },
 103         { }
 104 };
 105
 106 /* mpu -> dmm */
 107 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 108         .master         = &omap44xx_mpu_hwmod,
 109         .slave          = &omap44xx_dmm_hwmod,
 110         .clk            = "l3_div_ck",
 111         .addr           = omap44xx_dmm_addrs,
 112         .user           = OCP_USER_MPU,
 113 };
 114
 115 /* dmm slave ports */
 116 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 117         &omap44xx_l3_main_1__dmm,
 118         &omap44xx_mpu__dmm,
 119 };
 120
 121 static struct omap_hwmod omap44xx_dmm_hwmod = {
 122         .name           = "dmm",
 123         .class          = &omap44xx_dmm_hwmod_class,
 124         .mpu_irqs       = omap44xx_dmm_irqs,
 125         .slaves         = omap44xx_dmm_slaves,
 126         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 127         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 128 };
 129
 130 /*
 131  * 'emif_fw' class
 132  * instance(s): emif_fw
 133  */
 134 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 135         .name   = "emif_fw",
 136 };
 137
 138 /* emif_fw */
 139 /* dmm -> emif_fw */
 140 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 141         .master         = &omap44xx_dmm_hwmod,
 142         .slave          = &omap44xx_emif_fw_hwmod,
 143         .clk            = "l3_div_ck",
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 148         {
 149                 .pa_start       = 0x4a20c000,
 150                 .pa_end         = 0x4a20c0ff,
 151                 .flags          = ADDR_TYPE_RT
 152         },
 153         { }
 154 };
 155
 156 /* l4_cfg -> emif_fw */
 157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 158         .master         = &omap44xx_l4_cfg_hwmod,
 159         .slave          = &omap44xx_emif_fw_hwmod,
 160         .clk            = "l4_div_ck",
 161         .addr           = omap44xx_emif_fw_addrs,
 162         .user           = OCP_USER_MPU,
 163 };
 164
 165 /* emif_fw slave ports */
 166 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 167         &omap44xx_dmm__emif_fw,
 168         &omap44xx_l4_cfg__emif_fw,
 169 };
 170
 171 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 172         .name           = "emif_fw",
 173         .class          = &omap44xx_emif_fw_hwmod_class,
 174         .slaves         = omap44xx_emif_fw_slaves,
 175         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 177 };
 178
 179 /*
 180  * 'l3' class
 181  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 182  */
 183 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 184         .name   = "l3",
 185 };
 186
 187 /* l3_instr */
 188 /* iva -> l3_instr */
 189 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 190         .master         = &omap44xx_iva_hwmod,
 191         .slave          = &omap44xx_l3_instr_hwmod,
 192         .clk            = "l3_div_ck",
 193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 194 };
 195
 196 /* l3_main_3 -> l3_instr */
 197 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 198         .master         = &omap44xx_l3_main_3_hwmod,
 199         .slave          = &omap44xx_l3_instr_hwmod,
 200         .clk            = "l3_div_ck",
 201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 202 };
 203
 204 /* l3_instr slave ports */
 205 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 206         &omap44xx_iva__l3_instr,
 207         &omap44xx_l3_main_3__l3_instr,
 208 };
 209
 210 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 211         .name           = "l3_instr",
 212         .class          = &omap44xx_l3_hwmod_class,
 213         .slaves         = omap44xx_l3_instr_slaves,
 214         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 215         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 216 };
 217
 218 /* l3_main_1 */
 219 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 220         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 221         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 222         { .irq = -1 }
 223 };
 224
 225 /* dsp -> l3_main_1 */
 226 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 227         .master         = &omap44xx_dsp_hwmod,
 228         .slave          = &omap44xx_l3_main_1_hwmod,
 229         .clk            = "l3_div_ck",
 230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 231 };
 232
 233 /* dss -> l3_main_1 */
 234 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 235         .master         = &omap44xx_dss_hwmod,
 236         .slave          = &omap44xx_l3_main_1_hwmod,
 237         .clk            = "l3_div_ck",
 238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 239 };
 240
 241 /* l3_main_2 -> l3_main_1 */
 242 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 243         .master         = &omap44xx_l3_main_2_hwmod,
 244         .slave          = &omap44xx_l3_main_1_hwmod,
 245         .clk            = "l3_div_ck",
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* l4_cfg -> l3_main_1 */
 250 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 251         .master         = &omap44xx_l4_cfg_hwmod,
 252         .slave          = &omap44xx_l3_main_1_hwmod,
 253         .clk            = "l4_div_ck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 /* mmc1 -> l3_main_1 */
 258 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 259         .master         = &omap44xx_mmc1_hwmod,
 260         .slave          = &omap44xx_l3_main_1_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* mmc2 -> l3_main_1 */
 266 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 267         .master         = &omap44xx_mmc2_hwmod,
 268         .slave          = &omap44xx_l3_main_1_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 274         {
 275                 .pa_start       = 0x44000000,
 276                 .pa_end         = 0x44000fff,
 277                 .flags          = ADDR_TYPE_RT
 278         },
 279         { }
 280 };
 281
 282 /* mpu -> l3_main_1 */
 283 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 284         .master         = &omap44xx_mpu_hwmod,
 285         .slave          = &omap44xx_l3_main_1_hwmod,
 286         .clk            = "l3_div_ck",
 287         .addr           = omap44xx_l3_main_1_addrs,
 288         .user           = OCP_USER_MPU,
 289 };
 290
 291 /* l3_main_1 slave ports */
 292 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 293         &omap44xx_dsp__l3_main_1,
 294         &omap44xx_dss__l3_main_1,
 295         &omap44xx_l3_main_2__l3_main_1,
 296         &omap44xx_l4_cfg__l3_main_1,
 297         &omap44xx_mmc1__l3_main_1,
 298         &omap44xx_mmc2__l3_main_1,
 299         &omap44xx_mpu__l3_main_1,
 300 };
 301
 302 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 303         .name           = "l3_main_1",
 304         .class          = &omap44xx_l3_hwmod_class,
 305         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 306         .slaves         = omap44xx_l3_main_1_slaves,
 307         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 308         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 309 };
 310
 311 /* l3_main_2 */
 312 /* dma_system -> l3_main_2 */
 313 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 314         .master         = &omap44xx_dma_system_hwmod,
 315         .slave          = &omap44xx_l3_main_2_hwmod,
 316         .clk            = "l3_div_ck",
 317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 318 };
 319
 320 /* hsi -> l3_main_2 */
 321 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 322         .master         = &omap44xx_hsi_hwmod,
 323         .slave          = &omap44xx_l3_main_2_hwmod,
 324         .clk            = "l3_div_ck",
 325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 326 };
 327
 328 /* ipu -> l3_main_2 */
 329 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 330         .master         = &omap44xx_ipu_hwmod,
 331         .slave          = &omap44xx_l3_main_2_hwmod,
 332         .clk            = "l3_div_ck",
 333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 334 };
 335
 336 /* iss -> l3_main_2 */
 337 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 338         .master         = &omap44xx_iss_hwmod,
 339         .slave          = &omap44xx_l3_main_2_hwmod,
 340         .clk            = "l3_div_ck",
 341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 342 };
 343
 344 /* iva -> l3_main_2 */
 345 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 346         .master         = &omap44xx_iva_hwmod,
 347         .slave          = &omap44xx_l3_main_2_hwmod,
 348         .clk            = "l3_div_ck",
 349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 350 };
 351
 352 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 353         {
 354                 .pa_start       = 0x44800000,
 355                 .pa_end         = 0x44801fff,
 356                 .flags          = ADDR_TYPE_RT
 357         },
 358         { }
 359 };
 360
 361 /* l3_main_1 -> l3_main_2 */
 362 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 363         .master         = &omap44xx_l3_main_1_hwmod,
 364         .slave          = &omap44xx_l3_main_2_hwmod,
 365         .clk            = "l3_div_ck",
 366         .addr           = omap44xx_l3_main_2_addrs,
 367         .user           = OCP_USER_MPU,
 368 };
 369
 370 /* l4_cfg -> l3_main_2 */
 371 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 372         .master         = &omap44xx_l4_cfg_hwmod,
 373         .slave          = &omap44xx_l3_main_2_hwmod,
 374         .clk            = "l4_div_ck",
 375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 376 };
 377
 378 /* usb_otg_hs -> l3_main_2 */
 379 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 380         .master         = &omap44xx_usb_otg_hs_hwmod,
 381         .slave          = &omap44xx_l3_main_2_hwmod,
 382         .clk            = "l3_div_ck",
 383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 384 };
 385
 386 /* l3_main_2 slave ports */
 387 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 388         &omap44xx_dma_system__l3_main_2,
 389         &omap44xx_hsi__l3_main_2,
 390         &omap44xx_ipu__l3_main_2,
 391         &omap44xx_iss__l3_main_2,
 392         &omap44xx_iva__l3_main_2,
 393         &omap44xx_l3_main_1__l3_main_2,
 394         &omap44xx_l4_cfg__l3_main_2,
 395         &omap44xx_usb_otg_hs__l3_main_2,
 396 };
 397
 398 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 399         .name           = "l3_main_2",
 400         .class          = &omap44xx_l3_hwmod_class,
 401         .slaves         = omap44xx_l3_main_2_slaves,
 402         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 403         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 404 };
 405
 406 /* l3_main_3 */
 407 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 408         {
 409                 .pa_start       = 0x45000000,
 410                 .pa_end         = 0x45000fff,
 411                 .flags          = ADDR_TYPE_RT
 412         },
 413         { }
 414 };
 415
 416 /* l3_main_1 -> l3_main_3 */
 417 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 418         .master         = &omap44xx_l3_main_1_hwmod,
 419         .slave          = &omap44xx_l3_main_3_hwmod,
 420         .clk            = "l3_div_ck",
 421         .addr           = omap44xx_l3_main_3_addrs,
 422         .user           = OCP_USER_MPU,
 423 };
 424
 425 /* l3_main_2 -> l3_main_3 */
 426 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 427         .master         = &omap44xx_l3_main_2_hwmod,
 428         .slave          = &omap44xx_l3_main_3_hwmod,
 429         .clk            = "l3_div_ck",
 430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 431 };
 432
 433 /* l4_cfg -> l3_main_3 */
 434 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 435         .master         = &omap44xx_l4_cfg_hwmod,
 436         .slave          = &omap44xx_l3_main_3_hwmod,
 437         .clk            = "l4_div_ck",
 438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 439 };
 440
 441 /* l3_main_3 slave ports */
 442 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 443         &omap44xx_l3_main_1__l3_main_3,
 444         &omap44xx_l3_main_2__l3_main_3,
 445         &omap44xx_l4_cfg__l3_main_3,
 446 };
 447
 448 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 449         .name           = "l3_main_3",
 450         .class          = &omap44xx_l3_hwmod_class,
 451         .slaves         = omap44xx_l3_main_3_slaves,
 452         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 453         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 454 };
 455
 456 /*
 457  * 'l4' class
 458  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 459  */
 460 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 461         .name   = "l4",
 462 };
 463
 464 /* l4_abe */
 465 /* aess -> l4_abe */
 466 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 467         .master         = &omap44xx_aess_hwmod,
 468         .slave          = &omap44xx_l4_abe_hwmod,
 469         .clk            = "ocp_abe_iclk",
 470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 471 };
 472
 473 /* dsp -> l4_abe */
 474 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 475         .master         = &omap44xx_dsp_hwmod,
 476         .slave          = &omap44xx_l4_abe_hwmod,
 477         .clk            = "ocp_abe_iclk",
 478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 479 };
 480
 481 /* l3_main_1 -> l4_abe */
 482 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 483         .master         = &omap44xx_l3_main_1_hwmod,
 484         .slave          = &omap44xx_l4_abe_hwmod,
 485         .clk            = "l3_div_ck",
 486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 487 };
 488
 489 /* mpu -> l4_abe */
 490 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 491         .master         = &omap44xx_mpu_hwmod,
 492         .slave          = &omap44xx_l4_abe_hwmod,
 493         .clk            = "ocp_abe_iclk",
 494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 495 };
 496
 497 /* l4_abe slave ports */
 498 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 499         &omap44xx_aess__l4_abe,
 500         &omap44xx_dsp__l4_abe,
 501         &omap44xx_l3_main_1__l4_abe,
 502         &omap44xx_mpu__l4_abe,
 503 };
 504
 505 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 506         .name           = "l4_abe",
 507         .class          = &omap44xx_l4_hwmod_class,
 508         .slaves         = omap44xx_l4_abe_slaves,
 509         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 510         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 511 };
 512
 513 /* l4_cfg */
 514 /* l3_main_1 -> l4_cfg */
 515 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 516         .master         = &omap44xx_l3_main_1_hwmod,
 517         .slave          = &omap44xx_l4_cfg_hwmod,
 518         .clk            = "l3_div_ck",
 519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 520 };
 521
 522 /* l4_cfg slave ports */
 523 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 524         &omap44xx_l3_main_1__l4_cfg,
 525 };
 526
 527 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 528         .name           = "l4_cfg",
 529         .class          = &omap44xx_l4_hwmod_class,
 530         .slaves         = omap44xx_l4_cfg_slaves,
 531         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 532         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 533 };
 534
 535 /* l4_per */
 536 /* l3_main_2 -> l4_per */
 537 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 538         .master         = &omap44xx_l3_main_2_hwmod,
 539         .slave          = &omap44xx_l4_per_hwmod,
 540         .clk            = "l3_div_ck",
 541         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 542 };
 543
 544 /* l4_per slave ports */
 545 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 546         &omap44xx_l3_main_2__l4_per,
 547 };
 548
 549 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 550         .name           = "l4_per",
 551         .class          = &omap44xx_l4_hwmod_class,
 552         .slaves         = omap44xx_l4_per_slaves,
 553         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 554         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 555 };
 556
 557 /* l4_wkup */
 558 /* l4_cfg -> l4_wkup */
 559 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 560         .master         = &omap44xx_l4_cfg_hwmod,
 561         .slave          = &omap44xx_l4_wkup_hwmod,
 562         .clk            = "l4_div_ck",
 563         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 564 };
 565
 566 /* l4_wkup slave ports */
 567 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 568         &omap44xx_l4_cfg__l4_wkup,
 569 };
 570
 571 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 572         .name           = "l4_wkup",
 573         .class          = &omap44xx_l4_hwmod_class,
 574         .slaves         = omap44xx_l4_wkup_slaves,
 575         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 577 };
 578
 579 /*
 580  * 'mpu_bus' class
 581  * instance(s): mpu_private
 582  */
 583 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 584         .name   = "mpu_bus",
 585 };
 586
 587 /* mpu_private */
 588 /* mpu -> mpu_private */
 589 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 590         .master         = &omap44xx_mpu_hwmod,
 591         .slave          = &omap44xx_mpu_private_hwmod,
 592         .clk            = "l3_div_ck",
 593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 594 };
 595
 596 /* mpu_private slave ports */
 597 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 598         &omap44xx_mpu__mpu_private,
 599 };
 600
 601 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 602         .name           = "mpu_private",
 603         .class          = &omap44xx_mpu_bus_hwmod_class,
 604         .slaves         = omap44xx_mpu_private_slaves,
 605         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 606         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 607 };
 608
 609 /*
 610  * Modules omap_hwmod structures
 611  *
 612  * The following IPs are excluded for the moment because:
 613  * - They do not need an explicit SW control using omap_hwmod API.
 614  * - They still need to be validated with the driver
 615  *   properly adapted to omap_hwmod / omap_device
 616  *
 617  *  c2c
 618  *  c2c_target_fw
 619  *  cm_core
 620  *  cm_core_aon
 621  *  ctrl_module_core
 622  *  ctrl_module_pad_core
 623  *  ctrl_module_pad_wkup
 624  *  ctrl_module_wkup
 625  *  debugss
 626  *  efuse_ctrl_cust
 627  *  efuse_ctrl_std
 628  *  elm
 629  *  emif1
 630  *  emif2
 631  *  fdif
 632  *  gpmc
 633  *  gpu
 634  *  hdq1w
 635  *  mcasp
 636  *  mpu_c0
 637  *  mpu_c1
 638  *  ocmc_ram
 639  *  ocp2scp_usb_phy
 640  *  ocp_wp_noc
 641  *  prcm_mpu
 642  *  prm
 643  *  scrm
 644  *  sl2if
 645  *  slimbus1
 646  *  slimbus2
 647  *  usb_host_fs
 648  *  usb_host_hs
 649  *  usb_phy_cm
 650  *  usb_tll_hs
 651  *  usim
 652  */
 653
 654 /*
 655  * 'aess' class
 656  * audio engine sub system
 657  */
 658
 659 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 660         .rev_offs       = 0x0000,
 661         .sysc_offs      = 0x0010,
 662         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 663         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 664                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 665         .sysc_fields    = &omap_hwmod_sysc_type2,
 666 };
 667
 668 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 669         .name   = "aess",
 670         .sysc   = &omap44xx_aess_sysc,
 671 };
 672
 673 /* aess */
 674 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 675         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 676         { .irq = -1 }
 677 };
 678
 679 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 680         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 681         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 682         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 683         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 684         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 685         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 686         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 687         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 688         { .dma_req = -1 }
 689 };
 690
 691 /* aess master ports */
 692 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 693         &omap44xx_aess__l4_abe,
 694 };
 695
 696 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 697         {
 698                 .pa_start       = 0x401f1000,
 699                 .pa_end         = 0x401f13ff,
 700                 .flags          = ADDR_TYPE_RT
 701         },
 702         { }
 703 };
 704
 705 /* l4_abe -> aess */
 706 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 707         .master         = &omap44xx_l4_abe_hwmod,
 708         .slave          = &omap44xx_aess_hwmod,
 709         .clk            = "ocp_abe_iclk",
 710         .addr           = omap44xx_aess_addrs,
 711         .user           = OCP_USER_MPU,
 712 };
 713
 714 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 715         {
 716                 .pa_start       = 0x490f1000,
 717                 .pa_end         = 0x490f13ff,
 718                 .flags          = ADDR_TYPE_RT
 719         },
 720         { }
 721 };
 722
 723 /* l4_abe -> aess (dma) */
 724 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 725         .master         = &omap44xx_l4_abe_hwmod,
 726         .slave          = &omap44xx_aess_hwmod,
 727         .clk            = "ocp_abe_iclk",
 728         .addr           = omap44xx_aess_dma_addrs,
 729         .user           = OCP_USER_SDMA,
 730 };
 731
 732 /* aess slave ports */
 733 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 734         &omap44xx_l4_abe__aess,
 735         &omap44xx_l4_abe__aess_dma,
 736 };
 737
 738 static struct omap_hwmod omap44xx_aess_hwmod = {
 739         .name           = "aess",
 740         .class          = &omap44xx_aess_hwmod_class,
 741         .mpu_irqs       = omap44xx_aess_irqs,
 742         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 743         .main_clk       = "aess_fck",
 744         .prcm = {
 745                 .omap4 = {
 746                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 747                 },
 748         },
 749         .slaves         = omap44xx_aess_slaves,
 750         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 751         .masters        = omap44xx_aess_masters,
 752         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 753         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 754 };
 755
 756 /*
 757  * 'bandgap' class
 758  * bangap reference for ldo regulators
 759  */
 760
 761 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 762         .name   = "bandgap",
 763 };
 764
 765 /* bandgap */
 766 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 767         { .role = "fclk", .clk = "bandgap_fclk" },
 768 };
 769
 770 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 771         .name           = "bandgap",
 772         .class          = &omap44xx_bandgap_hwmod_class,
 773         .prcm = {
 774                 .omap4 = {
 775                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 776                 },
 777         },
 778         .opt_clks       = bandgap_opt_clks,
 779         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 780         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 781 };
 782
 783 /*
 784  * 'counter' class
 785  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 786  */
 787
 788 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 789         .rev_offs       = 0x0000,
 790         .sysc_offs      = 0x0004,
 791         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 792         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 793                            SIDLE_SMART_WKUP),
 794         .sysc_fields    = &omap_hwmod_sysc_type1,
 795 };
 796
 797 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 798         .name   = "counter",
 799         .sysc   = &omap44xx_counter_sysc,
 800 };
 801
 802 /* counter_32k */
 803 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 804 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 805         {
 806                 .pa_start       = 0x4a304000,
 807                 .pa_end         = 0x4a30401f,
 808                 .flags          = ADDR_TYPE_RT
 809         },
 810         { }
 811 };
 812
 813 /* l4_wkup -> counter_32k */
 814 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 815         .master         = &omap44xx_l4_wkup_hwmod,
 816         .slave          = &omap44xx_counter_32k_hwmod,
 817         .clk            = "l4_wkup_clk_mux_ck",
 818         .addr           = omap44xx_counter_32k_addrs,
 819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 820 };
 821
 822 /* counter_32k slave ports */
 823 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 824         &omap44xx_l4_wkup__counter_32k,
 825 };
 826
 827 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 828         .name           = "counter_32k",
 829         .class          = &omap44xx_counter_hwmod_class,
 830         .flags          = HWMOD_SWSUP_SIDLE,
 831         .main_clk       = "sys_32k_ck",
 832         .prcm = {
 833                 .omap4 = {
 834                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 835                 },
 836         },
 837         .slaves         = omap44xx_counter_32k_slaves,
 838         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 839         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 840 };
 841
 842 /*
 843  * 'dma' class
 844  * dma controller for data exchange between memory to memory (i.e. internal or
 845  * external memory) and gp peripherals to memory or memory to gp peripherals
 846  */
 847
 848 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 849         .rev_offs       = 0x0000,
 850         .sysc_offs      = 0x002c,
 851         .syss_offs      = 0x0028,
 852         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 853                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 854                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 855                            SYSS_HAS_RESET_STATUS),
 856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 857                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 858         .sysc_fields    = &omap_hwmod_sysc_type1,
 859 };
 860
 861 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 862         .name   = "dma",
 863         .sysc   = &omap44xx_dma_sysc,
 864 };
 865
 866 /* dma dev_attr */
 867 static struct omap_dma_dev_attr dma_dev_attr = {
 868         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 869                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 870         .lch_count      = 32,
 871 };
 872
 873 /* dma_system */
 874 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 875         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 876         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 877         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 878         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 879         { .irq = -1 }
 880 };
 881
 882 /* dma_system master ports */
 883 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 884         &omap44xx_dma_system__l3_main_2,
 885 };
 886
 887 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 888         {
 889                 .pa_start       = 0x4a056000,
 890                 .pa_end         = 0x4a056fff,
 891                 .flags          = ADDR_TYPE_RT
 892         },
 893         { }
 894 };
 895
 896 /* l4_cfg -> dma_system */
 897 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 898         .master         = &omap44xx_l4_cfg_hwmod,
 899         .slave          = &omap44xx_dma_system_hwmod,
 900         .clk            = "l4_div_ck",
 901         .addr           = omap44xx_dma_system_addrs,
 902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 903 };
 904
 905 /* dma_system slave ports */
 906 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 907         &omap44xx_l4_cfg__dma_system,
 908 };
 909
 910 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 911         .name           = "dma_system",
 912         .class          = &omap44xx_dma_hwmod_class,
 913         .mpu_irqs       = omap44xx_dma_system_irqs,
 914         .main_clk       = "l3_div_ck",
 915         .prcm = {
 916                 .omap4 = {
 917                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 918                 },
 919         },
 920         .dev_attr       = &dma_dev_attr,
 921         .slaves         = omap44xx_dma_system_slaves,
 922         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 923         .masters        = omap44xx_dma_system_masters,
 924         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 925         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 926 };
 927
 928 /*
 929  * 'dmic' class
 930  * digital microphone controller
 931  */
 932
 933 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 934         .rev_offs       = 0x0000,
 935         .sysc_offs      = 0x0010,
 936         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 937                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 938         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 939                            SIDLE_SMART_WKUP),
 940         .sysc_fields    = &omap_hwmod_sysc_type2,
 941 };
 942
 943 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 944         .name   = "dmic",
 945         .sysc   = &omap44xx_dmic_sysc,
 946 };
 947
 948 /* dmic */
 949 static struct omap_hwmod omap44xx_dmic_hwmod;
 950 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 951         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 952         { .irq = -1 }
 953 };
 954
 955 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 956         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 957         { .dma_req = -1 }
 958 };
 959
 960 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 961         {
 962                 .pa_start       = 0x4012e000,
 963                 .pa_end         = 0x4012e07f,
 964                 .flags          = ADDR_TYPE_RT
 965         },
 966         { }
 967 };
 968
 969 /* l4_abe -> dmic */
 970 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 971         .master         = &omap44xx_l4_abe_hwmod,
 972         .slave          = &omap44xx_dmic_hwmod,
 973         .clk            = "ocp_abe_iclk",
 974         .addr           = omap44xx_dmic_addrs,
 975         .user           = OCP_USER_MPU,
 976 };
 977
 978 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 979         {
 980                 .pa_start       = 0x4902e000,
 981                 .pa_end         = 0x4902e07f,
 982                 .flags          = ADDR_TYPE_RT
 983         },
 984         { }
 985 };
 986
 987 /* l4_abe -> dmic (dma) */
 988 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 989         .master         = &omap44xx_l4_abe_hwmod,
 990         .slave          = &omap44xx_dmic_hwmod,
 991         .clk            = "ocp_abe_iclk",
 992         .addr           = omap44xx_dmic_dma_addrs,
 993         .user           = OCP_USER_SDMA,
 994 };
 995
 996 /* dmic slave ports */
 997 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 998         &omap44xx_l4_abe__dmic,
 999         &omap44xx_l4_abe__dmic_dma,
1000 };
1001
1002 static struct omap_hwmod omap44xx_dmic_hwmod = {
1003         .name           = "dmic",
1004         .class          = &omap44xx_dmic_hwmod_class,
1005         .mpu_irqs       = omap44xx_dmic_irqs,
1006         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1007         .main_clk       = "dmic_fck",
1008         .prcm = {
1009                 .omap4 = {
1010                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1011                 },
1012         },
1013         .slaves         = omap44xx_dmic_slaves,
1014         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1015         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1016 };
1017
1018 /*
1019  * 'dsp' class
1020  * dsp sub-system
1021  */
1022
1023 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1024         .name   = "dsp",
1025 };
1026
1027 /* dsp */
1028 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1029         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1030         { .irq = -1 }
1031 };
1032
1033 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1034         { .name = "mmu_cache", .rst_shift = 1 },
1035 };
1036
1037 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1038         { .name = "dsp", .rst_shift = 0 },
1039 };
1040
1041 /* dsp -> iva */
1042 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1043         .master         = &omap44xx_dsp_hwmod,
1044         .slave          = &omap44xx_iva_hwmod,
1045         .clk            = "dpll_iva_m5x2_ck",
1046 };
1047
1048 /* dsp master ports */
1049 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1050         &omap44xx_dsp__l3_main_1,
1051         &omap44xx_dsp__l4_abe,
1052         &omap44xx_dsp__iva,
1053 };
1054
1055 /* l4_cfg -> dsp */
1056 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1057         .master         = &omap44xx_l4_cfg_hwmod,
1058         .slave          = &omap44xx_dsp_hwmod,
1059         .clk            = "l4_div_ck",
1060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1061 };
1062
1063 /* dsp slave ports */
1064 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1065         &omap44xx_l4_cfg__dsp,
1066 };
1067
1068 /* Pseudo hwmod for reset control purpose only */
1069 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1070         .name           = "dsp_c0",
1071         .class          = &omap44xx_dsp_hwmod_class,
1072         .flags          = HWMOD_INIT_NO_RESET,
1073         .rst_lines      = omap44xx_dsp_c0_resets,
1074         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1075         .prcm = {
1076                 .omap4 = {
1077                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1078                 },
1079         },
1080         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1081 };
1082
1083 static struct omap_hwmod omap44xx_dsp_hwmod = {
1084         .name           = "dsp",
1085         .class          = &omap44xx_dsp_hwmod_class,
1086         .mpu_irqs       = omap44xx_dsp_irqs,
1087         .rst_lines      = omap44xx_dsp_resets,
1088         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1089         .main_clk       = "dsp_fck",
1090         .prcm = {
1091                 .omap4 = {
1092                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1093                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1094                 },
1095         },
1096         .slaves         = omap44xx_dsp_slaves,
1097         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1098         .masters        = omap44xx_dsp_masters,
1099         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1100         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1101 };
1102
1103 /*
1104  * 'dss' class
1105  * display sub-system
1106  */
1107
1108 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1109         .rev_offs       = 0x0000,
1110         .syss_offs      = 0x0014,
1111         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1112 };
1113
1114 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1115         .name   = "dss",
1116         .sysc   = &omap44xx_dss_sysc,
1117 };
1118
1119 /* dss */
1120 /* dss master ports */
1121 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1122         &omap44xx_dss__l3_main_1,
1123 };
1124
1125 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1126         {
1127                 .pa_start       = 0x58000000,
1128                 .pa_end         = 0x5800007f,
1129                 .flags          = ADDR_TYPE_RT
1130         },
1131         { }
1132 };
1133
1134 /* l3_main_2 -> dss */
1135 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1136         .master         = &omap44xx_l3_main_2_hwmod,
1137         .slave          = &omap44xx_dss_hwmod,
1138         .clk            = "l3_div_ck",
1139         .addr           = omap44xx_dss_dma_addrs,
1140         .user           = OCP_USER_SDMA,
1141 };
1142
1143 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1144         {
1145                 .pa_start       = 0x48040000,
1146                 .pa_end         = 0x4804007f,
1147                 .flags          = ADDR_TYPE_RT
1148         },
1149         { }
1150 };
1151
1152 /* l4_per -> dss */
1153 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1154         .master         = &omap44xx_l4_per_hwmod,
1155         .slave          = &omap44xx_dss_hwmod,
1156         .clk            = "l4_div_ck",
1157         .addr           = omap44xx_dss_addrs,
1158         .user           = OCP_USER_MPU,
1159 };
1160
1161 /* dss slave ports */
1162 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1163         &omap44xx_l3_main_2__dss,
1164         &omap44xx_l4_per__dss,
1165 };
1166
1167 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1168         { .role = "sys_clk", .clk = "dss_sys_clk" },
1169         { .role = "tv_clk", .clk = "dss_tv_clk" },
1170         { .role = "dss_clk", .clk = "dss_dss_clk" },
1171         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1172 };
1173
1174 static struct omap_hwmod omap44xx_dss_hwmod = {
1175         .name           = "dss_core",
1176         .class          = &omap44xx_dss_hwmod_class,
1177         .main_clk       = "dss_fck",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1181                 },
1182         },
1183         .opt_clks       = dss_opt_clks,
1184         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1185         .slaves         = omap44xx_dss_slaves,
1186         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1187         .masters        = omap44xx_dss_masters,
1188         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1189         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1190 };
1191
1192 /*
1193  * 'dispc' class
1194  * display controller
1195  */
1196
1197 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1198         .rev_offs       = 0x0000,
1199         .sysc_offs      = 0x0010,
1200         .syss_offs      = 0x0014,
1201         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1202                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1203                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1204                            SYSS_HAS_RESET_STATUS),
1205         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1206                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1207         .sysc_fields    = &omap_hwmod_sysc_type1,
1208 };
1209
1210 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1211         .name   = "dispc",
1212         .sysc   = &omap44xx_dispc_sysc,
1213 };
1214
1215 /* dss_dispc */
1216 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1217 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1218         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1219         { .irq = -1 }
1220 };
1221
1222 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1223         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1224         { .dma_req = -1 }
1225 };
1226
1227 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1228         {
1229                 .pa_start       = 0x58001000,
1230                 .pa_end         = 0x58001fff,
1231                 .flags          = ADDR_TYPE_RT
1232         },
1233         { }
1234 };
1235
1236 /* l3_main_2 -> dss_dispc */
1237 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1238         .master         = &omap44xx_l3_main_2_hwmod,
1239         .slave          = &omap44xx_dss_dispc_hwmod,
1240         .clk            = "l3_div_ck",
1241         .addr           = omap44xx_dss_dispc_dma_addrs,
1242         .user           = OCP_USER_SDMA,
1243 };
1244
1245 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1246         {
1247                 .pa_start       = 0x48041000,
1248                 .pa_end         = 0x48041fff,
1249                 .flags          = ADDR_TYPE_RT
1250         },
1251         { }
1252 };
1253
1254 /* l4_per -> dss_dispc */
1255 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1256         .master         = &omap44xx_l4_per_hwmod,
1257         .slave          = &omap44xx_dss_dispc_hwmod,
1258         .clk            = "l4_div_ck",
1259         .addr           = omap44xx_dss_dispc_addrs,
1260         .user           = OCP_USER_MPU,
1261 };
1262
1263 /* dss_dispc slave ports */
1264 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1265         &omap44xx_l3_main_2__dss_dispc,
1266         &omap44xx_l4_per__dss_dispc,
1267 };
1268
1269 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1270         .name           = "dss_dispc",
1271         .class          = &omap44xx_dispc_hwmod_class,
1272         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1273         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1274         .main_clk       = "dss_fck",
1275         .prcm = {
1276                 .omap4 = {
1277                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1278                 },
1279         },
1280         .slaves         = omap44xx_dss_dispc_slaves,
1281         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1282         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1283 };
1284
1285 /*
1286  * 'dsi' class
1287  * display serial interface controller
1288  */
1289
1290 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1291         .rev_offs       = 0x0000,
1292         .sysc_offs      = 0x0010,
1293         .syss_offs      = 0x0014,
1294         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1295                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1296                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1297         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1298         .sysc_fields    = &omap_hwmod_sysc_type1,
1299 };
1300
1301 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1302         .name   = "dsi",
1303         .sysc   = &omap44xx_dsi_sysc,
1304 };
1305
1306 /* dss_dsi1 */
1307 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1308 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1309         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1310         { .irq = -1 }
1311 };
1312
1313 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1314         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1315         { .dma_req = -1 }
1316 };
1317
1318 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1319         {
1320                 .pa_start       = 0x58004000,
1321                 .pa_end         = 0x580041ff,
1322                 .flags          = ADDR_TYPE_RT
1323         },
1324         { }
1325 };
1326
1327 /* l3_main_2 -> dss_dsi1 */
1328 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1329         .master         = &omap44xx_l3_main_2_hwmod,
1330         .slave          = &omap44xx_dss_dsi1_hwmod,
1331         .clk            = "l3_div_ck",
1332         .addr           = omap44xx_dss_dsi1_dma_addrs,
1333         .user           = OCP_USER_SDMA,
1334 };
1335
1336 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1337         {
1338                 .pa_start       = 0x48044000,
1339                 .pa_end         = 0x480441ff,
1340                 .flags          = ADDR_TYPE_RT
1341         },
1342         { }
1343 };
1344
1345 /* l4_per -> dss_dsi1 */
1346 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1347         .master         = &omap44xx_l4_per_hwmod,
1348         .slave          = &omap44xx_dss_dsi1_hwmod,
1349         .clk            = "l4_div_ck",
1350         .addr           = omap44xx_dss_dsi1_addrs,
1351         .user           = OCP_USER_MPU,
1352 };
1353
1354 /* dss_dsi1 slave ports */
1355 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1356         &omap44xx_l3_main_2__dss_dsi1,
1357         &omap44xx_l4_per__dss_dsi1,
1358 };
1359
1360 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1361         .name           = "dss_dsi1",
1362         .class          = &omap44xx_dsi_hwmod_class,
1363         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1364         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1365         .main_clk       = "dss_fck",
1366         .prcm = {
1367                 .omap4 = {
1368                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1369                 },
1370         },
1371         .slaves         = omap44xx_dss_dsi1_slaves,
1372         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1373         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1374 };
1375
1376 /* dss_dsi2 */
1377 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1378 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1379         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1380         { .irq = -1 }
1381 };
1382
1383 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1384         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1385         { .dma_req = -1 }
1386 };
1387
1388 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1389         {
1390                 .pa_start       = 0x58005000,
1391                 .pa_end         = 0x580051ff,
1392                 .flags          = ADDR_TYPE_RT
1393         },
1394         { }
1395 };
1396
1397 /* l3_main_2 -> dss_dsi2 */
1398 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1399         .master         = &omap44xx_l3_main_2_hwmod,
1400         .slave          = &omap44xx_dss_dsi2_hwmod,
1401         .clk            = "l3_div_ck",
1402         .addr           = omap44xx_dss_dsi2_dma_addrs,
1403         .user           = OCP_USER_SDMA,
1404 };
1405
1406 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1407         {
1408                 .pa_start       = 0x48045000,
1409                 .pa_end         = 0x480451ff,
1410                 .flags          = ADDR_TYPE_RT
1411         },
1412         { }
1413 };
1414
1415 /* l4_per -> dss_dsi2 */
1416 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1417         .master         = &omap44xx_l4_per_hwmod,
1418         .slave          = &omap44xx_dss_dsi2_hwmod,
1419         .clk            = "l4_div_ck",
1420         .addr           = omap44xx_dss_dsi2_addrs,
1421         .user           = OCP_USER_MPU,
1422 };
1423
1424 /* dss_dsi2 slave ports */
1425 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1426         &omap44xx_l3_main_2__dss_dsi2,
1427         &omap44xx_l4_per__dss_dsi2,
1428 };
1429
1430 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1431         .name           = "dss_dsi2",
1432         .class          = &omap44xx_dsi_hwmod_class,
1433         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1434         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1435         .main_clk       = "dss_fck",
1436         .prcm = {
1437                 .omap4 = {
1438                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1439                 },
1440         },
1441         .slaves         = omap44xx_dss_dsi2_slaves,
1442         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1443         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1444 };
1445
1446 /*
1447  * 'hdmi' class
1448  * hdmi controller
1449  */
1450
1451 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1452         .rev_offs       = 0x0000,
1453         .sysc_offs      = 0x0010,
1454         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1455                            SYSC_HAS_SOFTRESET),
1456         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1457                            SIDLE_SMART_WKUP),
1458         .sysc_fields    = &omap_hwmod_sysc_type2,
1459 };
1460
1461 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1462         .name   = "hdmi",
1463         .sysc   = &omap44xx_hdmi_sysc,
1464 };
1465
1466 /* dss_hdmi */
1467 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1468 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1469         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1470         { .irq = -1 }
1471 };
1472
1473 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1474         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1475         { .dma_req = -1 }
1476 };
1477
1478 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1479         {
1480                 .pa_start       = 0x58006000,
1481                 .pa_end         = 0x58006fff,
1482                 .flags          = ADDR_TYPE_RT
1483         },
1484         { }
1485 };
1486
1487 /* l3_main_2 -> dss_hdmi */
1488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1489         .master         = &omap44xx_l3_main_2_hwmod,
1490         .slave          = &omap44xx_dss_hdmi_hwmod,
1491         .clk            = "l3_div_ck",
1492         .addr           = omap44xx_dss_hdmi_dma_addrs,
1493         .user           = OCP_USER_SDMA,
1494 };
1495
1496 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1497         {
1498                 .pa_start       = 0x48046000,
1499                 .pa_end         = 0x48046fff,
1500                 .flags          = ADDR_TYPE_RT
1501         },
1502         { }
1503 };
1504
1505 /* l4_per -> dss_hdmi */
1506 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1507         .master         = &omap44xx_l4_per_hwmod,
1508         .slave          = &omap44xx_dss_hdmi_hwmod,
1509         .clk            = "l4_div_ck",
1510         .addr           = omap44xx_dss_hdmi_addrs,
1511         .user           = OCP_USER_MPU,
1512 };
1513
1514 /* dss_hdmi slave ports */
1515 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1516         &omap44xx_l3_main_2__dss_hdmi,
1517         &omap44xx_l4_per__dss_hdmi,
1518 };
1519
1520 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1521         .name           = "dss_hdmi",
1522         .class          = &omap44xx_hdmi_hwmod_class,
1523         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1524         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1525         .main_clk       = "dss_fck",
1526         .prcm = {
1527                 .omap4 = {
1528                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1529                 },
1530         },
1531         .slaves         = omap44xx_dss_hdmi_slaves,
1532         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1533         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1534 };
1535
1536 /*
1537  * 'rfbi' class
1538  * remote frame buffer interface
1539  */
1540
1541 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1542         .rev_offs       = 0x0000,
1543         .sysc_offs      = 0x0010,
1544         .syss_offs      = 0x0014,
1545         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1546                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1548         .sysc_fields    = &omap_hwmod_sysc_type1,
1549 };
1550
1551 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1552         .name   = "rfbi",
1553         .sysc   = &omap44xx_rfbi_sysc,
1554 };
1555
1556 /* dss_rfbi */
1557 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1558 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1559         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1560         { .dma_req = -1 }
1561 };
1562
1563 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1564         {
1565                 .pa_start       = 0x58002000,
1566                 .pa_end         = 0x580020ff,
1567                 .flags          = ADDR_TYPE_RT
1568         },
1569         { }
1570 };
1571
1572 /* l3_main_2 -> dss_rfbi */
1573 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1574         .master         = &omap44xx_l3_main_2_hwmod,
1575         .slave          = &omap44xx_dss_rfbi_hwmod,
1576         .clk            = "l3_div_ck",
1577         .addr           = omap44xx_dss_rfbi_dma_addrs,
1578         .user           = OCP_USER_SDMA,
1579 };
1580
1581 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1582         {
1583                 .pa_start       = 0x48042000,
1584                 .pa_end         = 0x480420ff,
1585                 .flags          = ADDR_TYPE_RT
1586         },
1587         { }
1588 };
1589
1590 /* l4_per -> dss_rfbi */
1591 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1592         .master         = &omap44xx_l4_per_hwmod,
1593         .slave          = &omap44xx_dss_rfbi_hwmod,
1594         .clk            = "l4_div_ck",
1595         .addr           = omap44xx_dss_rfbi_addrs,
1596         .user           = OCP_USER_MPU,
1597 };
1598
1599 /* dss_rfbi slave ports */
1600 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1601         &omap44xx_l3_main_2__dss_rfbi,
1602         &omap44xx_l4_per__dss_rfbi,
1603 };
1604
1605 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1606         .name           = "dss_rfbi",
1607         .class          = &omap44xx_rfbi_hwmod_class,
1608         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1609         .main_clk       = "dss_fck",
1610         .prcm = {
1611                 .omap4 = {
1612                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1613                 },
1614         },
1615         .slaves         = omap44xx_dss_rfbi_slaves,
1616         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1617         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1618 };
1619
1620 /*
1621  * 'venc' class
1622  * video encoder
1623  */
1624
1625 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1626         .name   = "venc",
1627 };
1628
1629 /* dss_venc */
1630 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1631 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1632         {
1633                 .pa_start       = 0x58003000,
1634                 .pa_end         = 0x580030ff,
1635                 .flags          = ADDR_TYPE_RT
1636         },
1637         { }
1638 };
1639
1640 /* l3_main_2 -> dss_venc */
1641 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1642         .master         = &omap44xx_l3_main_2_hwmod,
1643         .slave          = &omap44xx_dss_venc_hwmod,
1644         .clk            = "l3_div_ck",
1645         .addr           = omap44xx_dss_venc_dma_addrs,
1646         .user           = OCP_USER_SDMA,
1647 };
1648
1649 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1650         {
1651                 .pa_start       = 0x48043000,
1652                 .pa_end         = 0x480430ff,
1653                 .flags          = ADDR_TYPE_RT
1654         },
1655         { }
1656 };
1657
1658 /* l4_per -> dss_venc */
1659 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1660         .master         = &omap44xx_l4_per_hwmod,
1661         .slave          = &omap44xx_dss_venc_hwmod,
1662         .clk            = "l4_div_ck",
1663         .addr           = omap44xx_dss_venc_addrs,
1664         .user           = OCP_USER_MPU,
1665 };
1666
1667 /* dss_venc slave ports */
1668 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1669         &omap44xx_l3_main_2__dss_venc,
1670         &omap44xx_l4_per__dss_venc,
1671 };
1672
1673 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1674         .name           = "dss_venc",
1675         .class          = &omap44xx_venc_hwmod_class,
1676         .main_clk       = "dss_fck",
1677         .prcm = {
1678                 .omap4 = {
1679                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1680                 },
1681         },
1682         .slaves         = omap44xx_dss_venc_slaves,
1683         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1684         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1685 };
1686
1687 /*
1688  * 'gpio' class
1689  * general purpose io module
1690  */
1691
1692 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1693         .rev_offs       = 0x0000,
1694         .sysc_offs      = 0x0010,
1695         .syss_offs      = 0x0114,
1696         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1697                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1698                            SYSS_HAS_RESET_STATUS),
1699         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1700                            SIDLE_SMART_WKUP),
1701         .sysc_fields    = &omap_hwmod_sysc_type1,
1702 };
1703
1704 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1705         .name   = "gpio",
1706         .sysc   = &omap44xx_gpio_sysc,
1707         .rev    = 2,
1708 };
1709
1710 /* gpio dev_attr */
1711 static struct omap_gpio_dev_attr gpio_dev_attr = {
1712         .bank_width     = 32,
1713         .dbck_flag      = true,
1714 };
1715
1716 /* gpio1 */
1717 static struct omap_hwmod omap44xx_gpio1_hwmod;
1718 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1719         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1720         { .irq = -1 }
1721 };
1722
1723 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1724         {
1725                 .pa_start       = 0x4a310000,
1726                 .pa_end         = 0x4a3101ff,
1727                 .flags          = ADDR_TYPE_RT
1728         },
1729         { }
1730 };
1731
1732 /* l4_wkup -> gpio1 */
1733 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1734         .master         = &omap44xx_l4_wkup_hwmod,
1735         .slave          = &omap44xx_gpio1_hwmod,
1736         .clk            = "l4_wkup_clk_mux_ck",
1737         .addr           = omap44xx_gpio1_addrs,
1738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1739 };
1740
1741 /* gpio1 slave ports */
1742 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1743         &omap44xx_l4_wkup__gpio1,
1744 };
1745
1746 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1747         { .role = "dbclk", .clk = "gpio1_dbclk" },
1748 };
1749
1750 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1751         .name           = "gpio1",
1752         .class          = &omap44xx_gpio_hwmod_class,
1753         .mpu_irqs       = omap44xx_gpio1_irqs,
1754         .main_clk       = "gpio1_ick",
1755         .prcm = {
1756                 .omap4 = {
1757                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1758                 },
1759         },
1760         .opt_clks       = gpio1_opt_clks,
1761         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1762         .dev_attr       = &gpio_dev_attr,
1763         .slaves         = omap44xx_gpio1_slaves,
1764         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1765         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1766 };
1767
1768 /* gpio2 */
1769 static struct omap_hwmod omap44xx_gpio2_hwmod;
1770 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1771         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1776         {
1777                 .pa_start       = 0x48055000,
1778                 .pa_end         = 0x480551ff,
1779                 .flags          = ADDR_TYPE_RT
1780         },
1781         { }
1782 };
1783
1784 /* l4_per -> gpio2 */
1785 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1786         .master         = &omap44xx_l4_per_hwmod,
1787         .slave          = &omap44xx_gpio2_hwmod,
1788         .clk            = "l4_div_ck",
1789         .addr           = omap44xx_gpio2_addrs,
1790         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1791 };
1792
1793 /* gpio2 slave ports */
1794 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1795         &omap44xx_l4_per__gpio2,
1796 };
1797
1798 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1799         { .role = "dbclk", .clk = "gpio2_dbclk" },
1800 };
1801
1802 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1803         .name           = "gpio2",
1804         .class          = &omap44xx_gpio_hwmod_class,
1805         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1806         .mpu_irqs       = omap44xx_gpio2_irqs,
1807         .main_clk       = "gpio2_ick",
1808         .prcm = {
1809                 .omap4 = {
1810                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1811                 },
1812         },
1813         .opt_clks       = gpio2_opt_clks,
1814         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1815         .dev_attr       = &gpio_dev_attr,
1816         .slaves         = omap44xx_gpio2_slaves,
1817         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1818         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1819 };
1820
1821 /* gpio3 */
1822 static struct omap_hwmod omap44xx_gpio3_hwmod;
1823 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1824         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1829         {
1830                 .pa_start       = 0x48057000,
1831                 .pa_end         = 0x480571ff,
1832                 .flags          = ADDR_TYPE_RT
1833         },
1834         { }
1835 };
1836
1837 /* l4_per -> gpio3 */
1838 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1839         .master         = &omap44xx_l4_per_hwmod,
1840         .slave          = &omap44xx_gpio3_hwmod,
1841         .clk            = "l4_div_ck",
1842         .addr           = omap44xx_gpio3_addrs,
1843         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1844 };
1845
1846 /* gpio3 slave ports */
1847 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1848         &omap44xx_l4_per__gpio3,
1849 };
1850
1851 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1852         { .role = "dbclk", .clk = "gpio3_dbclk" },
1853 };
1854
1855 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1856         .name           = "gpio3",
1857         .class          = &omap44xx_gpio_hwmod_class,
1858         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1859         .mpu_irqs       = omap44xx_gpio3_irqs,
1860         .main_clk       = "gpio3_ick",
1861         .prcm = {
1862                 .omap4 = {
1863                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1864                 },
1865         },
1866         .opt_clks       = gpio3_opt_clks,
1867         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1868         .dev_attr       = &gpio_dev_attr,
1869         .slaves         = omap44xx_gpio3_slaves,
1870         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1871         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1872 };
1873
1874 /* gpio4 */
1875 static struct omap_hwmod omap44xx_gpio4_hwmod;
1876 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1877         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1878         { .irq = -1 }
1879 };
1880
1881 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1882         {
1883                 .pa_start       = 0x48059000,
1884                 .pa_end         = 0x480591ff,
1885                 .flags          = ADDR_TYPE_RT
1886         },
1887         { }
1888 };
1889
1890 /* l4_per -> gpio4 */
1891 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1892         .master         = &omap44xx_l4_per_hwmod,
1893         .slave          = &omap44xx_gpio4_hwmod,
1894         .clk            = "l4_div_ck",
1895         .addr           = omap44xx_gpio4_addrs,
1896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1897 };
1898
1899 /* gpio4 slave ports */
1900 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1901         &omap44xx_l4_per__gpio4,
1902 };
1903
1904 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1905         { .role = "dbclk", .clk = "gpio4_dbclk" },
1906 };
1907
1908 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1909         .name           = "gpio4",
1910         .class          = &omap44xx_gpio_hwmod_class,
1911         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1912         .mpu_irqs       = omap44xx_gpio4_irqs,
1913         .main_clk       = "gpio4_ick",
1914         .prcm = {
1915                 .omap4 = {
1916                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1917                 },
1918         },
1919         .opt_clks       = gpio4_opt_clks,
1920         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1921         .dev_attr       = &gpio_dev_attr,
1922         .slaves         = omap44xx_gpio4_slaves,
1923         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1924         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1925 };
1926
1927 /* gpio5 */
1928 static struct omap_hwmod omap44xx_gpio5_hwmod;
1929 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1930         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1931         { .irq = -1 }
1932 };
1933
1934 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1935         {
1936                 .pa_start       = 0x4805b000,
1937                 .pa_end         = 0x4805b1ff,
1938                 .flags          = ADDR_TYPE_RT
1939         },
1940         { }
1941 };
1942
1943 /* l4_per -> gpio5 */
1944 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1945         .master         = &omap44xx_l4_per_hwmod,
1946         .slave          = &omap44xx_gpio5_hwmod,
1947         .clk            = "l4_div_ck",
1948         .addr           = omap44xx_gpio5_addrs,
1949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1950 };
1951
1952 /* gpio5 slave ports */
1953 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1954         &omap44xx_l4_per__gpio5,
1955 };
1956
1957 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1958         { .role = "dbclk", .clk = "gpio5_dbclk" },
1959 };
1960
1961 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1962         .name           = "gpio5",
1963         .class          = &omap44xx_gpio_hwmod_class,
1964         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1965         .mpu_irqs       = omap44xx_gpio5_irqs,
1966         .main_clk       = "gpio5_ick",
1967         .prcm = {
1968                 .omap4 = {
1969                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1970                 },
1971         },
1972         .opt_clks       = gpio5_opt_clks,
1973         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1974         .dev_attr       = &gpio_dev_attr,
1975         .slaves         = omap44xx_gpio5_slaves,
1976         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1977         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1978 };
1979
1980 /* gpio6 */
1981 static struct omap_hwmod omap44xx_gpio6_hwmod;
1982 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1983         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1984         { .irq = -1 }
1985 };
1986
1987 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1988         {
1989                 .pa_start       = 0x4805d000,
1990                 .pa_end         = 0x4805d1ff,
1991                 .flags          = ADDR_TYPE_RT
1992         },
1993         { }
1994 };
1995
1996 /* l4_per -> gpio6 */
1997 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1998         .master         = &omap44xx_l4_per_hwmod,
1999         .slave          = &omap44xx_gpio6_hwmod,
2000         .clk            = "l4_div_ck",
2001         .addr           = omap44xx_gpio6_addrs,
2002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2003 };
2004
2005 /* gpio6 slave ports */
2006 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2007         &omap44xx_l4_per__gpio6,
2008 };
2009
2010 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2011         { .role = "dbclk", .clk = "gpio6_dbclk" },
2012 };
2013
2014 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2015         .name           = "gpio6",
2016         .class          = &omap44xx_gpio_hwmod_class,
2017         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2018         .mpu_irqs       = omap44xx_gpio6_irqs,
2019         .main_clk       = "gpio6_ick",
2020         .prcm = {
2021                 .omap4 = {
2022                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2023                 },
2024         },
2025         .opt_clks       = gpio6_opt_clks,
2026         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2027         .dev_attr       = &gpio_dev_attr,
2028         .slaves         = omap44xx_gpio6_slaves,
2029         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2030         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2031 };
2032
2033 /*
2034  * 'hsi' class
2035  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2036  * serial if)
2037  */
2038
2039 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2040         .rev_offs       = 0x0000,
2041         .sysc_offs      = 0x0010,
2042         .syss_offs      = 0x0014,
2043         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2044                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2045                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2046         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2047                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2048                            MSTANDBY_SMART),
2049         .sysc_fields    = &omap_hwmod_sysc_type1,
2050 };
2051
2052 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2053         .name   = "hsi",
2054         .sysc   = &omap44xx_hsi_sysc,
2055 };
2056
2057 /* hsi */
2058 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2059         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2060         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2061         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2062         { .irq = -1 }
2063 };
2064
2065 /* hsi master ports */
2066 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2067         &omap44xx_hsi__l3_main_2,
2068 };
2069
2070 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2071         {
2072                 .pa_start       = 0x4a058000,
2073                 .pa_end         = 0x4a05bfff,
2074                 .flags          = ADDR_TYPE_RT
2075         },
2076         { }
2077 };
2078
2079 /* l4_cfg -> hsi */
2080 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2081         .master         = &omap44xx_l4_cfg_hwmod,
2082         .slave          = &omap44xx_hsi_hwmod,
2083         .clk            = "l4_div_ck",
2084         .addr           = omap44xx_hsi_addrs,
2085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2086 };
2087
2088 /* hsi slave ports */
2089 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2090         &omap44xx_l4_cfg__hsi,
2091 };
2092
2093 static struct omap_hwmod omap44xx_hsi_hwmod = {
2094         .name           = "hsi",
2095         .class          = &omap44xx_hsi_hwmod_class,
2096         .mpu_irqs       = omap44xx_hsi_irqs,
2097         .main_clk       = "hsi_fck",
2098         .prcm = {
2099                 .omap4 = {
2100                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2101                 },
2102         },
2103         .slaves         = omap44xx_hsi_slaves,
2104         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2105         .masters        = omap44xx_hsi_masters,
2106         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2107         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2108 };
2109
2110 /*
2111  * 'i2c' class
2112  * multimaster high-speed i2c controller
2113  */
2114
2115 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2116         .sysc_offs      = 0x0010,
2117         .syss_offs      = 0x0090,
2118         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2119                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2120                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2121         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2122                            SIDLE_SMART_WKUP),
2123         .sysc_fields    = &omap_hwmod_sysc_type1,
2124 };
2125
2126 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2127         .name   = "i2c",
2128         .sysc   = &omap44xx_i2c_sysc,
2129 };
2130
2131 /* i2c1 */
2132 static struct omap_hwmod omap44xx_i2c1_hwmod;
2133 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2134         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2135         { .irq = -1 }
2136 };
2137
2138 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2139         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2140         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2141         { .dma_req = -1 }
2142 };
2143
2144 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2145         {
2146                 .pa_start       = 0x48070000,
2147                 .pa_end         = 0x480700ff,
2148                 .flags          = ADDR_TYPE_RT
2149         },
2150         { }
2151 };
2152
2153 /* l4_per -> i2c1 */
2154 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2155         .master         = &omap44xx_l4_per_hwmod,
2156         .slave          = &omap44xx_i2c1_hwmod,
2157         .clk            = "l4_div_ck",
2158         .addr           = omap44xx_i2c1_addrs,
2159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2160 };
2161
2162 /* i2c1 slave ports */
2163 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2164         &omap44xx_l4_per__i2c1,
2165 };
2166
2167 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2168         .name           = "i2c1",
2169         .class          = &omap44xx_i2c_hwmod_class,
2170         .flags          = HWMOD_INIT_NO_RESET,
2171         .mpu_irqs       = omap44xx_i2c1_irqs,
2172         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2173         .main_clk       = "i2c1_fck",
2174         .prcm = {
2175                 .omap4 = {
2176                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2177                 },
2178         },
2179         .slaves         = omap44xx_i2c1_slaves,
2180         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2181         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2182 };
2183
2184 /* i2c2 */
2185 static struct omap_hwmod omap44xx_i2c2_hwmod;
2186 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2187         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2188         { .irq = -1 }
2189 };
2190
2191 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2192         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2193         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2194         { .dma_req = -1 }
2195 };
2196
2197 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2198         {
2199                 .pa_start       = 0x48072000,
2200                 .pa_end         = 0x480720ff,
2201                 .flags          = ADDR_TYPE_RT
2202         },
2203         { }
2204 };
2205
2206 /* l4_per -> i2c2 */
2207 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2208         .master         = &omap44xx_l4_per_hwmod,
2209         .slave          = &omap44xx_i2c2_hwmod,
2210         .clk            = "l4_div_ck",
2211         .addr           = omap44xx_i2c2_addrs,
2212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2213 };
2214
2215 /* i2c2 slave ports */
2216 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2217         &omap44xx_l4_per__i2c2,
2218 };
2219
2220 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2221         .name           = "i2c2",
2222         .class          = &omap44xx_i2c_hwmod_class,
2223         .flags          = HWMOD_INIT_NO_RESET,
2224         .mpu_irqs       = omap44xx_i2c2_irqs,
2225         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2226         .main_clk       = "i2c2_fck",
2227         .prcm = {
2228                 .omap4 = {
2229                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2230                 },
2231         },
2232         .slaves         = omap44xx_i2c2_slaves,
2233         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2234         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2235 };
2236
2237 /* i2c3 */
2238 static struct omap_hwmod omap44xx_i2c3_hwmod;
2239 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2240         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2241         { .irq = -1 }
2242 };
2243
2244 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2245         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2246         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2247         { .dma_req = -1 }
2248 };
2249
2250 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2251         {
2252                 .pa_start       = 0x48060000,
2253                 .pa_end         = 0x480600ff,
2254                 .flags          = ADDR_TYPE_RT
2255         },
2256         { }
2257 };
2258
2259 /* l4_per -> i2c3 */
2260 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2261         .master         = &omap44xx_l4_per_hwmod,
2262         .slave          = &omap44xx_i2c3_hwmod,
2263         .clk            = "l4_div_ck",
2264         .addr           = omap44xx_i2c3_addrs,
2265         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2266 };
2267
2268 /* i2c3 slave ports */
2269 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2270         &omap44xx_l4_per__i2c3,
2271 };
2272
2273 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2274         .name           = "i2c3",
2275         .class          = &omap44xx_i2c_hwmod_class,
2276         .flags          = HWMOD_INIT_NO_RESET,
2277         .mpu_irqs       = omap44xx_i2c3_irqs,
2278         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2279         .main_clk       = "i2c3_fck",
2280         .prcm = {
2281                 .omap4 = {
2282                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2283                 },
2284         },
2285         .slaves         = omap44xx_i2c3_slaves,
2286         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2287         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2288 };
2289
2290 /* i2c4 */
2291 static struct omap_hwmod omap44xx_i2c4_hwmod;
2292 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2293         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2294         { .irq = -1 }
2295 };
2296
2297 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2298         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2299         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2300         { .dma_req = -1 }
2301 };
2302
2303 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2304         {
2305                 .pa_start       = 0x48350000,
2306                 .pa_end         = 0x483500ff,
2307                 .flags          = ADDR_TYPE_RT
2308         },
2309         { }
2310 };
2311
2312 /* l4_per -> i2c4 */
2313 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2314         .master         = &omap44xx_l4_per_hwmod,
2315         .slave          = &omap44xx_i2c4_hwmod,
2316         .clk            = "l4_div_ck",
2317         .addr           = omap44xx_i2c4_addrs,
2318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2319 };
2320
2321 /* i2c4 slave ports */
2322 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2323         &omap44xx_l4_per__i2c4,
2324 };
2325
2326 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2327         .name           = "i2c4",
2328         .class          = &omap44xx_i2c_hwmod_class,
2329         .flags          = HWMOD_INIT_NO_RESET,
2330         .mpu_irqs       = omap44xx_i2c4_irqs,
2331         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2332         .main_clk       = "i2c4_fck",
2333         .prcm = {
2334                 .omap4 = {
2335                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2336                 },
2337         },
2338         .slaves         = omap44xx_i2c4_slaves,
2339         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2340         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2341 };
2342
2343 /*
2344  * 'ipu' class
2345  * imaging processor unit
2346  */
2347
2348 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2349         .name   = "ipu",
2350 };
2351
2352 /* ipu */
2353 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2354         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2355         { .irq = -1 }
2356 };
2357
2358 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2359         { .name = "cpu0", .rst_shift = 0 },
2360 };
2361
2362 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2363         { .name = "cpu1", .rst_shift = 1 },
2364 };
2365
2366 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2367         { .name = "mmu_cache", .rst_shift = 2 },
2368 };
2369
2370 /* ipu master ports */
2371 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2372         &omap44xx_ipu__l3_main_2,
2373 };
2374
2375 /* l3_main_2 -> ipu */
2376 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2377         .master         = &omap44xx_l3_main_2_hwmod,
2378         .slave          = &omap44xx_ipu_hwmod,
2379         .clk            = "l3_div_ck",
2380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2381 };
2382
2383 /* ipu slave ports */
2384 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2385         &omap44xx_l3_main_2__ipu,
2386 };
2387
2388 /* Pseudo hwmod for reset control purpose only */
2389 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2390         .name           = "ipu_c0",
2391         .class          = &omap44xx_ipu_hwmod_class,
2392         .flags          = HWMOD_INIT_NO_RESET,
2393         .rst_lines      = omap44xx_ipu_c0_resets,
2394         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2395         .prcm = {
2396                 .omap4 = {
2397                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2398                 },
2399         },
2400         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2401 };
2402
2403 /* Pseudo hwmod for reset control purpose only */
2404 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2405         .name           = "ipu_c1",
2406         .class          = &omap44xx_ipu_hwmod_class,
2407         .flags          = HWMOD_INIT_NO_RESET,
2408         .rst_lines      = omap44xx_ipu_c1_resets,
2409         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2410         .prcm = {
2411                 .omap4 = {
2412                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2413                 },
2414         },
2415         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2416 };
2417
2418 static struct omap_hwmod omap44xx_ipu_hwmod = {
2419         .name           = "ipu",
2420         .class          = &omap44xx_ipu_hwmod_class,
2421         .mpu_irqs       = omap44xx_ipu_irqs,
2422         .rst_lines      = omap44xx_ipu_resets,
2423         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2424         .main_clk       = "ipu_fck",
2425         .prcm = {
2426                 .omap4 = {
2427                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2428                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2429                 },
2430         },
2431         .slaves         = omap44xx_ipu_slaves,
2432         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2433         .masters        = omap44xx_ipu_masters,
2434         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2435         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2436 };
2437
2438 /*
2439  * 'iss' class
2440  * external images sensor pixel data processor
2441  */
2442
2443 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2444         .rev_offs       = 0x0000,
2445         .sysc_offs      = 0x0010,
2446         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2447                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2448         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2449                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2450                            MSTANDBY_SMART),
2451         .sysc_fields    = &omap_hwmod_sysc_type2,
2452 };
2453
2454 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2455         .name   = "iss",
2456         .sysc   = &omap44xx_iss_sysc,
2457 };
2458
2459 /* iss */
2460 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2461         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2462         { .irq = -1 }
2463 };
2464
2465 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2466         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2467         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2468         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2469         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2470         { .dma_req = -1 }
2471 };
2472
2473 /* iss master ports */
2474 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2475         &omap44xx_iss__l3_main_2,
2476 };
2477
2478 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2479         {
2480                 .pa_start       = 0x52000000,
2481                 .pa_end         = 0x520000ff,
2482                 .flags          = ADDR_TYPE_RT
2483         },
2484         { }
2485 };
2486
2487 /* l3_main_2 -> iss */
2488 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2489         .master         = &omap44xx_l3_main_2_hwmod,
2490         .slave          = &omap44xx_iss_hwmod,
2491         .clk            = "l3_div_ck",
2492         .addr           = omap44xx_iss_addrs,
2493         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2495
2496 /* iss slave ports */
2497 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2498         &omap44xx_l3_main_2__iss,
2499 };
2500
2501 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2502         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2503 };
2504
2505 static struct omap_hwmod omap44xx_iss_hwmod = {
2506         .name           = "iss",
2507         .class          = &omap44xx_iss_hwmod_class,
2508         .mpu_irqs       = omap44xx_iss_irqs,
2509         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2510         .main_clk       = "iss_fck",
2511         .prcm = {
2512                 .omap4 = {
2513                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2514                 },
2515         },
2516         .opt_clks       = iss_opt_clks,
2517         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2518         .slaves         = omap44xx_iss_slaves,
2519         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2520         .masters        = omap44xx_iss_masters,
2521         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2522         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2523 };
2524
2525 /*
2526  * 'iva' class
2527  * multi-standard video encoder/decoder hardware accelerator
2528  */
2529
2530 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2531         .name   = "iva",
2532 };
2533
2534 /* iva */
2535 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2536         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2537         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2538         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2539         { .irq = -1 }
2540 };
2541
2542 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2543         { .name = "logic", .rst_shift = 2 },
2544 };
2545
2546 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2547         { .name = "seq0", .rst_shift = 0 },
2548 };
2549
2550 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2551         { .name = "seq1", .rst_shift = 1 },
2552 };
2553
2554 /* iva master ports */
2555 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2556         &omap44xx_iva__l3_main_2,
2557         &omap44xx_iva__l3_instr,
2558 };
2559
2560 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2561         {
2562                 .pa_start       = 0x5a000000,
2563                 .pa_end         = 0x5a07ffff,
2564                 .flags          = ADDR_TYPE_RT
2565         },
2566         { }
2567 };
2568
2569 /* l3_main_2 -> iva */
2570 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2571         .master         = &omap44xx_l3_main_2_hwmod,
2572         .slave          = &omap44xx_iva_hwmod,
2573         .clk            = "l3_div_ck",
2574         .addr           = omap44xx_iva_addrs,
2575         .user           = OCP_USER_MPU,
2576 };
2577
2578 /* iva slave ports */
2579 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2580         &omap44xx_dsp__iva,
2581         &omap44xx_l3_main_2__iva,
2582 };
2583
2584 /* Pseudo hwmod for reset control purpose only */
2585 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2586         .name           = "iva_seq0",
2587         .class          = &omap44xx_iva_hwmod_class,
2588         .flags          = HWMOD_INIT_NO_RESET,
2589         .rst_lines      = omap44xx_iva_seq0_resets,
2590         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2591         .prcm = {
2592                 .omap4 = {
2593                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2594                 },
2595         },
2596         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2597 };
2598
2599 /* Pseudo hwmod for reset control purpose only */
2600 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2601         .name           = "iva_seq1",
2602         .class          = &omap44xx_iva_hwmod_class,
2603         .flags          = HWMOD_INIT_NO_RESET,
2604         .rst_lines      = omap44xx_iva_seq1_resets,
2605         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2606         .prcm = {
2607                 .omap4 = {
2608                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2609                 },
2610         },
2611         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2612 };
2613
2614 static struct omap_hwmod omap44xx_iva_hwmod = {
2615         .name           = "iva",
2616         .class          = &omap44xx_iva_hwmod_class,
2617         .mpu_irqs       = omap44xx_iva_irqs,
2618         .rst_lines      = omap44xx_iva_resets,
2619         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2620         .main_clk       = "iva_fck",
2621         .prcm = {
2622                 .omap4 = {
2623                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2624                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2625                 },
2626         },
2627         .slaves         = omap44xx_iva_slaves,
2628         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2629         .masters        = omap44xx_iva_masters,
2630         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2631         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2632 };
2633
2634 /*
2635  * 'kbd' class
2636  * keyboard controller
2637  */
2638
2639 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2640         .rev_offs       = 0x0000,
2641         .sysc_offs      = 0x0010,
2642         .syss_offs      = 0x0014,
2643         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2644                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2645                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2646                            SYSS_HAS_RESET_STATUS),
2647         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2648         .sysc_fields    = &omap_hwmod_sysc_type1,
2649 };
2650
2651 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2652         .name   = "kbd",
2653         .sysc   = &omap44xx_kbd_sysc,
2654 };
2655
2656 /* kbd */
2657 static struct omap_hwmod omap44xx_kbd_hwmod;
2658 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2659         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2660         { .irq = -1 }
2661 };
2662
2663 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2664         {
2665                 .pa_start       = 0x4a31c000,
2666                 .pa_end         = 0x4a31c07f,
2667                 .flags          = ADDR_TYPE_RT
2668         },
2669         { }
2670 };
2671
2672 /* l4_wkup -> kbd */
2673 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2674         .master         = &omap44xx_l4_wkup_hwmod,
2675         .slave          = &omap44xx_kbd_hwmod,
2676         .clk            = "l4_wkup_clk_mux_ck",
2677         .addr           = omap44xx_kbd_addrs,
2678         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2679 };
2680
2681 /* kbd slave ports */
2682 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2683         &omap44xx_l4_wkup__kbd,
2684 };
2685
2686 static struct omap_hwmod omap44xx_kbd_hwmod = {
2687         .name           = "kbd",
2688         .class          = &omap44xx_kbd_hwmod_class,
2689         .mpu_irqs       = omap44xx_kbd_irqs,
2690         .main_clk       = "kbd_fck",
2691         .prcm = {
2692                 .omap4 = {
2693                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2694                 },
2695         },
2696         .slaves         = omap44xx_kbd_slaves,
2697         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2698         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2699 };
2700
2701 /*
2702  * 'mailbox' class
2703  * mailbox module allowing communication between the on-chip processors using a
2704  * queued mailbox-interrupt mechanism.
2705  */
2706
2707 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2708         .rev_offs       = 0x0000,
2709         .sysc_offs      = 0x0010,
2710         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2711                            SYSC_HAS_SOFTRESET),
2712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2713         .sysc_fields    = &omap_hwmod_sysc_type2,
2714 };
2715
2716 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2717         .name   = "mailbox",
2718         .sysc   = &omap44xx_mailbox_sysc,
2719 };
2720
2721 /* mailbox */
2722 static struct omap_hwmod omap44xx_mailbox_hwmod;
2723 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2724         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2725         { .irq = -1 }
2726 };
2727
2728 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2729         {
2730                 .pa_start       = 0x4a0f4000,
2731                 .pa_end         = 0x4a0f41ff,
2732                 .flags          = ADDR_TYPE_RT
2733         },
2734         { }
2735 };
2736
2737 /* l4_cfg -> mailbox */
2738 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2739         .master         = &omap44xx_l4_cfg_hwmod,
2740         .slave          = &omap44xx_mailbox_hwmod,
2741         .clk            = "l4_div_ck",
2742         .addr           = omap44xx_mailbox_addrs,
2743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2744 };
2745
2746 /* mailbox slave ports */
2747 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2748         &omap44xx_l4_cfg__mailbox,
2749 };
2750
2751 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2752         .name           = "mailbox",
2753         .class          = &omap44xx_mailbox_hwmod_class,
2754         .mpu_irqs       = omap44xx_mailbox_irqs,
2755         .prcm = {
2756                 .omap4 = {
2757                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2758                 },
2759         },
2760         .slaves         = omap44xx_mailbox_slaves,
2761         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2762         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2763 };
2764
2765 /*
2766  * 'mcbsp' class
2767  * multi channel buffered serial port controller
2768  */
2769
2770 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2771         .sysc_offs      = 0x008c,
2772         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2773                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2775         .sysc_fields    = &omap_hwmod_sysc_type1,
2776 };
2777
2778 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2779         .name   = "mcbsp",
2780         .sysc   = &omap44xx_mcbsp_sysc,
2781         .rev    = MCBSP_CONFIG_TYPE4,
2782 };
2783
2784 /* mcbsp1 */
2785 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2786 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2787         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2788         { .irq = -1 }
2789 };
2790
2791 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2792         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2793         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2794         { .dma_req = -1 }
2795 };
2796
2797 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2798         {
2799                 .name           = "mpu",
2800                 .pa_start       = 0x40122000,
2801                 .pa_end         = 0x401220ff,
2802                 .flags          = ADDR_TYPE_RT
2803         },
2804         { }
2805 };
2806
2807 /* l4_abe -> mcbsp1 */
2808 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2809         .master         = &omap44xx_l4_abe_hwmod,
2810         .slave          = &omap44xx_mcbsp1_hwmod,
2811         .clk            = "ocp_abe_iclk",
2812         .addr           = omap44xx_mcbsp1_addrs,
2813         .user           = OCP_USER_MPU,
2814 };
2815
2816 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2817         {
2818                 .name           = "dma",
2819                 .pa_start       = 0x49022000,
2820                 .pa_end         = 0x490220ff,
2821                 .flags          = ADDR_TYPE_RT
2822         },
2823         { }
2824 };
2825
2826 /* l4_abe -> mcbsp1 (dma) */
2827 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2828         .master         = &omap44xx_l4_abe_hwmod,
2829         .slave          = &omap44xx_mcbsp1_hwmod,
2830         .clk            = "ocp_abe_iclk",
2831         .addr           = omap44xx_mcbsp1_dma_addrs,
2832         .user           = OCP_USER_SDMA,
2833 };
2834
2835 /* mcbsp1 slave ports */
2836 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2837         &omap44xx_l4_abe__mcbsp1,
2838         &omap44xx_l4_abe__mcbsp1_dma,
2839 };
2840
2841 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2842         .name           = "mcbsp1",
2843         .class          = &omap44xx_mcbsp_hwmod_class,
2844         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2845         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2846         .main_clk       = "mcbsp1_fck",
2847         .prcm = {
2848                 .omap4 = {
2849                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2850                 },
2851         },
2852         .slaves         = omap44xx_mcbsp1_slaves,
2853         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2854         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2855 };
2856
2857 /* mcbsp2 */
2858 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2859 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2860         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2861         { .irq = -1 }
2862 };
2863
2864 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2865         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2866         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2867         { .dma_req = -1 }
2868 };
2869
2870 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2871         {
2872                 .name           = "mpu",
2873                 .pa_start       = 0x40124000,
2874                 .pa_end         = 0x401240ff,
2875                 .flags          = ADDR_TYPE_RT
2876         },
2877         { }
2878 };
2879
2880 /* l4_abe -> mcbsp2 */
2881 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2882         .master         = &omap44xx_l4_abe_hwmod,
2883         .slave          = &omap44xx_mcbsp2_hwmod,
2884         .clk            = "ocp_abe_iclk",
2885         .addr           = omap44xx_mcbsp2_addrs,
2886         .user           = OCP_USER_MPU,
2887 };
2888
2889 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2890         {
2891                 .name           = "dma",
2892                 .pa_start       = 0x49024000,
2893                 .pa_end         = 0x490240ff,
2894                 .flags          = ADDR_TYPE_RT
2895         },
2896         { }
2897 };
2898
2899 /* l4_abe -> mcbsp2 (dma) */
2900 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2901         .master         = &omap44xx_l4_abe_hwmod,
2902         .slave          = &omap44xx_mcbsp2_hwmod,
2903         .clk            = "ocp_abe_iclk",
2904         .addr           = omap44xx_mcbsp2_dma_addrs,
2905         .user           = OCP_USER_SDMA,
2906 };
2907
2908 /* mcbsp2 slave ports */
2909 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2910         &omap44xx_l4_abe__mcbsp2,
2911         &omap44xx_l4_abe__mcbsp2_dma,
2912 };
2913
2914 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2915         .name           = "mcbsp2",
2916         .class          = &omap44xx_mcbsp_hwmod_class,
2917         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2918         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2919         .main_clk       = "mcbsp2_fck",
2920         .prcm = {
2921                 .omap4 = {
2922                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2923                 },
2924         },
2925         .slaves         = omap44xx_mcbsp2_slaves,
2926         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2927         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2928 };
2929
2930 /* mcbsp3 */
2931 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2932 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2933         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2934         { .irq = -1 }
2935 };
2936
2937 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2938         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2939         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2940         { .dma_req = -1 }
2941 };
2942
2943 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2944         {
2945                 .name           = "mpu",
2946                 .pa_start       = 0x40126000,
2947                 .pa_end         = 0x401260ff,
2948                 .flags          = ADDR_TYPE_RT
2949         },
2950         { }
2951 };
2952
2953 /* l4_abe -> mcbsp3 */
2954 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2955         .master         = &omap44xx_l4_abe_hwmod,
2956         .slave          = &omap44xx_mcbsp3_hwmod,
2957         .clk            = "ocp_abe_iclk",
2958         .addr           = omap44xx_mcbsp3_addrs,
2959         .user           = OCP_USER_MPU,
2960 };
2961
2962 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2963         {
2964                 .name           = "dma",
2965                 .pa_start       = 0x49026000,
2966                 .pa_end         = 0x490260ff,
2967                 .flags          = ADDR_TYPE_RT
2968         },
2969         { }
2970 };
2971
2972 /* l4_abe -> mcbsp3 (dma) */
2973 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2974         .master         = &omap44xx_l4_abe_hwmod,
2975         .slave          = &omap44xx_mcbsp3_hwmod,
2976         .clk            = "ocp_abe_iclk",
2977         .addr           = omap44xx_mcbsp3_dma_addrs,
2978         .user           = OCP_USER_SDMA,
2979 };
2980
2981 /* mcbsp3 slave ports */
2982 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2983         &omap44xx_l4_abe__mcbsp3,
2984         &omap44xx_l4_abe__mcbsp3_dma,
2985 };
2986
2987 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2988         .name           = "mcbsp3",
2989         .class          = &omap44xx_mcbsp_hwmod_class,
2990         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2991         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2992         .main_clk       = "mcbsp3_fck",
2993         .prcm = {
2994                 .omap4 = {
2995                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2996                 },
2997         },
2998         .slaves         = omap44xx_mcbsp3_slaves,
2999         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3000         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3001 };
3002
3003 /* mcbsp4 */
3004 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3005 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3006         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3007         { .irq = -1 }
3008 };
3009
3010 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3011         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3012         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3013         { .dma_req = -1 }
3014 };
3015
3016 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3017         {
3018                 .pa_start       = 0x48096000,
3019                 .pa_end         = 0x480960ff,
3020                 .flags          = ADDR_TYPE_RT
3021         },
3022         { }
3023 };
3024
3025 /* l4_per -> mcbsp4 */
3026 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3027         .master         = &omap44xx_l4_per_hwmod,
3028         .slave          = &omap44xx_mcbsp4_hwmod,
3029         .clk            = "l4_div_ck",
3030         .addr           = omap44xx_mcbsp4_addrs,
3031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3032 };
3033
3034 /* mcbsp4 slave ports */
3035 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3036         &omap44xx_l4_per__mcbsp4,
3037 };
3038
3039 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3040         .name           = "mcbsp4",
3041         .class          = &omap44xx_mcbsp_hwmod_class,
3042         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3043         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3044         .main_clk       = "mcbsp4_fck",
3045         .prcm = {
3046                 .omap4 = {
3047                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3048                 },
3049         },
3050         .slaves         = omap44xx_mcbsp4_slaves,
3051         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3052         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3053 };
3054
3055 /*
3056  * 'mcpdm' class
3057  * multi channel pdm controller (proprietary interface with phoenix power
3058  * ic)
3059  */
3060
3061 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3062         .rev_offs       = 0x0000,
3063         .sysc_offs      = 0x0010,
3064         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3065                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3066         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3067                            SIDLE_SMART_WKUP),
3068         .sysc_fields    = &omap_hwmod_sysc_type2,
3069 };
3070
3071 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3072         .name   = "mcpdm",
3073         .sysc   = &omap44xx_mcpdm_sysc,
3074 };
3075
3076 /* mcpdm */
3077 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3078 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3079         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3080         { .irq = -1 }
3081 };
3082
3083 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3084         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3085         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3086         { .dma_req = -1 }
3087 };
3088
3089 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3090         {
3091                 .pa_start       = 0x40132000,
3092                 .pa_end         = 0x4013207f,
3093                 .flags          = ADDR_TYPE_RT
3094         },
3095         { }
3096 };
3097
3098 /* l4_abe -> mcpdm */
3099 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3100         .master         = &omap44xx_l4_abe_hwmod,
3101         .slave          = &omap44xx_mcpdm_hwmod,
3102         .clk            = "ocp_abe_iclk",
3103         .addr           = omap44xx_mcpdm_addrs,
3104         .user           = OCP_USER_MPU,
3105 };
3106
3107 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3108         {
3109                 .pa_start       = 0x49032000,
3110                 .pa_end         = 0x4903207f,
3111                 .flags          = ADDR_TYPE_RT
3112         },
3113         { }
3114 };
3115
3116 /* l4_abe -> mcpdm (dma) */
3117 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3118         .master         = &omap44xx_l4_abe_hwmod,
3119         .slave          = &omap44xx_mcpdm_hwmod,
3120         .clk            = "ocp_abe_iclk",
3121         .addr           = omap44xx_mcpdm_dma_addrs,
3122         .user           = OCP_USER_SDMA,
3123 };
3124
3125 /* mcpdm slave ports */
3126 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3127         &omap44xx_l4_abe__mcpdm,
3128         &omap44xx_l4_abe__mcpdm_dma,
3129 };
3130
3131 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3132         .name           = "mcpdm",
3133         .class          = &omap44xx_mcpdm_hwmod_class,
3134         .mpu_irqs       = omap44xx_mcpdm_irqs,
3135         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3136         .main_clk       = "mcpdm_fck",
3137         .prcm = {
3138                 .omap4 = {
3139                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3140                 },
3141         },
3142         .slaves         = omap44xx_mcpdm_slaves,
3143         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3144         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3145 };
3146
3147 /*
3148  * 'mcspi' class
3149  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3150  * bus
3151  */
3152
3153 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3154         .rev_offs       = 0x0000,
3155         .sysc_offs      = 0x0010,
3156         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3157                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3158         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3159                            SIDLE_SMART_WKUP),
3160         .sysc_fields    = &omap_hwmod_sysc_type2,
3161 };
3162
3163 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3164         .name   = "mcspi",
3165         .sysc   = &omap44xx_mcspi_sysc,
3166         .rev    = OMAP4_MCSPI_REV,
3167 };
3168
3169 /* mcspi1 */
3170 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3171 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3172         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3173         { .irq = -1 }
3174 };
3175
3176 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3177         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3178         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3179         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3180         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3181         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3182         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3183         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3184         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3185         { .dma_req = -1 }
3186 };
3187
3188 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3189         {
3190                 .pa_start       = 0x48098000,
3191                 .pa_end         = 0x480981ff,
3192                 .flags          = ADDR_TYPE_RT
3193         },
3194         { }
3195 };
3196
3197 /* l4_per -> mcspi1 */
3198 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3199         .master         = &omap44xx_l4_per_hwmod,
3200         .slave          = &omap44xx_mcspi1_hwmod,
3201         .clk            = "l4_div_ck",
3202         .addr           = omap44xx_mcspi1_addrs,
3203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3204 };
3205
3206 /* mcspi1 slave ports */
3207 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3208         &omap44xx_l4_per__mcspi1,
3209 };
3210
3211 /* mcspi1 dev_attr */
3212 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3213         .num_chipselect = 4,
3214 };
3215
3216 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3217         .name           = "mcspi1",
3218         .class          = &omap44xx_mcspi_hwmod_class,
3219         .mpu_irqs       = omap44xx_mcspi1_irqs,
3220         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3221         .main_clk       = "mcspi1_fck",
3222         .prcm = {
3223                 .omap4 = {
3224                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3225                 },
3226         },
3227         .dev_attr       = &mcspi1_dev_attr,
3228         .slaves         = omap44xx_mcspi1_slaves,
3229         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3231 };
3232
3233 /* mcspi2 */
3234 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3235 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3236         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3237         { .irq = -1 }
3238 };
3239
3240 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3241         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3242         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3243         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3244         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3245         { .dma_req = -1 }
3246 };
3247
3248 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3249         {
3250                 .pa_start       = 0x4809a000,
3251                 .pa_end         = 0x4809a1ff,
3252                 .flags          = ADDR_TYPE_RT
3253         },
3254         { }
3255 };
3256
3257 /* l4_per -> mcspi2 */
3258 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3259         .master         = &omap44xx_l4_per_hwmod,
3260         .slave          = &omap44xx_mcspi2_hwmod,
3261         .clk            = "l4_div_ck",
3262         .addr           = omap44xx_mcspi2_addrs,
3263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3265
3266 /* mcspi2 slave ports */
3267 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3268         &omap44xx_l4_per__mcspi2,
3269 };
3270
3271 /* mcspi2 dev_attr */
3272 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3273         .num_chipselect = 2,
3274 };
3275
3276 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3277         .name           = "mcspi2",
3278         .class          = &omap44xx_mcspi_hwmod_class,
3279         .mpu_irqs       = omap44xx_mcspi2_irqs,
3280         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3281         .main_clk       = "mcspi2_fck",
3282         .prcm = {
3283                 .omap4 = {
3284                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3285                 },
3286         },
3287         .dev_attr       = &mcspi2_dev_attr,
3288         .slaves         = omap44xx_mcspi2_slaves,
3289         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3290         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3291 };
3292
3293 /* mcspi3 */
3294 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3295 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3296         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3297         { .irq = -1 }
3298 };
3299
3300 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3301         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3302         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3303         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3304         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3305         { .dma_req = -1 }
3306 };
3307
3308 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3309         {
3310                 .pa_start       = 0x480b8000,
3311                 .pa_end         = 0x480b81ff,
3312                 .flags          = ADDR_TYPE_RT
3313         },
3314         { }
3315 };
3316
3317 /* l4_per -> mcspi3 */
3318 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3319         .master         = &omap44xx_l4_per_hwmod,
3320         .slave          = &omap44xx_mcspi3_hwmod,
3321         .clk            = "l4_div_ck",
3322         .addr           = omap44xx_mcspi3_addrs,
3323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3324 };
3325
3326 /* mcspi3 slave ports */
3327 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3328         &omap44xx_l4_per__mcspi3,
3329 };
3330
3331 /* mcspi3 dev_attr */
3332 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3333         .num_chipselect = 2,
3334 };
3335
3336 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3337         .name           = "mcspi3",
3338         .class          = &omap44xx_mcspi_hwmod_class,
3339         .mpu_irqs       = omap44xx_mcspi3_irqs,
3340         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3341         .main_clk       = "mcspi3_fck",
3342         .prcm = {
3343                 .omap4 = {
3344                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3345                 },
3346         },
3347         .dev_attr       = &mcspi3_dev_attr,
3348         .slaves         = omap44xx_mcspi3_slaves,
3349         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3350         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3351 };
3352
3353 /* mcspi4 */
3354 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3355 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3356         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3357         { .irq = -1 }
3358 };
3359
3360 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3361         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3362         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3363         { .dma_req = -1 }
3364 };
3365
3366 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3367         {
3368                 .pa_start       = 0x480ba000,
3369                 .pa_end         = 0x480ba1ff,
3370                 .flags          = ADDR_TYPE_RT
3371         },
3372         { }
3373 };
3374
3375 /* l4_per -> mcspi4 */
3376 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3377         .master         = &omap44xx_l4_per_hwmod,
3378         .slave          = &omap44xx_mcspi4_hwmod,
3379         .clk            = "l4_div_ck",
3380         .addr           = omap44xx_mcspi4_addrs,
3381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3382 };
3383
3384 /* mcspi4 slave ports */
3385 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3386         &omap44xx_l4_per__mcspi4,
3387 };
3388
3389 /* mcspi4 dev_attr */
3390 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3391         .num_chipselect = 1,
3392 };
3393
3394 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3395         .name           = "mcspi4",
3396         .class          = &omap44xx_mcspi_hwmod_class,
3397         .mpu_irqs       = omap44xx_mcspi4_irqs,
3398         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3399         .main_clk       = "mcspi4_fck",
3400         .prcm = {
3401                 .omap4 = {
3402                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3403                 },
3404         },
3405         .dev_attr       = &mcspi4_dev_attr,
3406         .slaves         = omap44xx_mcspi4_slaves,
3407         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3408         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3409 };
3410
3411 /*
3412  * 'mmc' class
3413  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3414  */
3415
3416 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3417         .rev_offs       = 0x0000,
3418         .sysc_offs      = 0x0010,
3419         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3420                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3421                            SYSC_HAS_SOFTRESET),
3422         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3423                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3424                            MSTANDBY_SMART),
3425         .sysc_fields    = &omap_hwmod_sysc_type2,
3426 };
3427
3428 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3429         .name   = "mmc",
3430         .sysc   = &omap44xx_mmc_sysc,
3431 };
3432
3433 /* mmc1 */
3434 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3435         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3436         { .irq = -1 }
3437 };
3438
3439 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3440         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3441         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3442         { .dma_req = -1 }
3443 };
3444
3445 /* mmc1 master ports */
3446 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3447         &omap44xx_mmc1__l3_main_1,
3448 };
3449
3450 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3451         {
3452                 .pa_start       = 0x4809c000,
3453                 .pa_end         = 0x4809c3ff,
3454                 .flags          = ADDR_TYPE_RT
3455         },
3456         { }
3457 };
3458
3459 /* l4_per -> mmc1 */
3460 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3461         .master         = &omap44xx_l4_per_hwmod,
3462         .slave          = &omap44xx_mmc1_hwmod,
3463         .clk            = "l4_div_ck",
3464         .addr           = omap44xx_mmc1_addrs,
3465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3466 };
3467
3468 /* mmc1 slave ports */
3469 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3470         &omap44xx_l4_per__mmc1,
3471 };
3472
3473 /* mmc1 dev_attr */
3474 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3475         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3476 };
3477
3478 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3479         .name           = "mmc1",
3480         .class          = &omap44xx_mmc_hwmod_class,
3481         .mpu_irqs       = omap44xx_mmc1_irqs,
3482         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3483         .main_clk       = "mmc1_fck",
3484         .prcm = {
3485                 .omap4 = {
3486                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3487                 },
3488         },
3489         .dev_attr       = &mmc1_dev_attr,
3490         .slaves         = omap44xx_mmc1_slaves,
3491         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3492         .masters        = omap44xx_mmc1_masters,
3493         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3494         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3495 };
3496
3497 /* mmc2 */
3498 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3499         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3500         { .irq = -1 }
3501 };
3502
3503 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3504         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3505         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3506         { .dma_req = -1 }
3507 };
3508
3509 /* mmc2 master ports */
3510 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3511         &omap44xx_mmc2__l3_main_1,
3512 };
3513
3514 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3515         {
3516                 .pa_start       = 0x480b4000,
3517                 .pa_end         = 0x480b43ff,
3518                 .flags          = ADDR_TYPE_RT
3519         },
3520         { }
3521 };
3522
3523 /* l4_per -> mmc2 */
3524 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3525         .master         = &omap44xx_l4_per_hwmod,
3526         .slave          = &omap44xx_mmc2_hwmod,
3527         .clk            = "l4_div_ck",
3528         .addr           = omap44xx_mmc2_addrs,
3529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3530 };
3531
3532 /* mmc2 slave ports */
3533 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3534         &omap44xx_l4_per__mmc2,
3535 };
3536
3537 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3538         .name           = "mmc2",
3539         .class          = &omap44xx_mmc_hwmod_class,
3540         .mpu_irqs       = omap44xx_mmc2_irqs,
3541         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3542         .main_clk       = "mmc2_fck",
3543         .prcm = {
3544                 .omap4 = {
3545                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3546                 },
3547         },
3548         .slaves         = omap44xx_mmc2_slaves,
3549         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3550         .masters        = omap44xx_mmc2_masters,
3551         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3552         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3553 };
3554
3555 /* mmc3 */
3556 static struct omap_hwmod omap44xx_mmc3_hwmod;
3557 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3558         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3559         { .irq = -1 }
3560 };
3561
3562 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3563         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3564         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3565         { .dma_req = -1 }
3566 };
3567
3568 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3569         {
3570                 .pa_start       = 0x480ad000,
3571                 .pa_end         = 0x480ad3ff,
3572                 .flags          = ADDR_TYPE_RT
3573         },
3574         { }
3575 };
3576
3577 /* l4_per -> mmc3 */
3578 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3579         .master         = &omap44xx_l4_per_hwmod,
3580         .slave          = &omap44xx_mmc3_hwmod,
3581         .clk            = "l4_div_ck",
3582         .addr           = omap44xx_mmc3_addrs,
3583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3584 };
3585
3586 /* mmc3 slave ports */
3587 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3588         &omap44xx_l4_per__mmc3,
3589 };
3590
3591 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3592         .name           = "mmc3",
3593         .class          = &omap44xx_mmc_hwmod_class,
3594         .mpu_irqs       = omap44xx_mmc3_irqs,
3595         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3596         .main_clk       = "mmc3_fck",
3597         .prcm = {
3598                 .omap4 = {
3599                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3600                 },
3601         },
3602         .slaves         = omap44xx_mmc3_slaves,
3603         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3604         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3605 };
3606
3607 /* mmc4 */
3608 static struct omap_hwmod omap44xx_mmc4_hwmod;
3609 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3610         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3611         { .irq = -1 }
3612 };
3613
3614 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3615         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3616         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3617         { .dma_req = -1 }
3618 };
3619
3620 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3621         {
3622                 .pa_start       = 0x480d1000,
3623                 .pa_end         = 0x480d13ff,
3624                 .flags          = ADDR_TYPE_RT
3625         },
3626         { }
3627 };
3628
3629 /* l4_per -> mmc4 */
3630 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3631         .master         = &omap44xx_l4_per_hwmod,
3632         .slave          = &omap44xx_mmc4_hwmod,
3633         .clk            = "l4_div_ck",
3634         .addr           = omap44xx_mmc4_addrs,
3635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3636 };
3637
3638 /* mmc4 slave ports */
3639 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3640         &omap44xx_l4_per__mmc4,
3641 };
3642
3643 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3644         .name           = "mmc4",
3645         .class          = &omap44xx_mmc_hwmod_class,
3646         .mpu_irqs       = omap44xx_mmc4_irqs,
3647
3648         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3649         .main_clk       = "mmc4_fck",
3650         .prcm = {
3651                 .omap4 = {
3652                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3653                 },
3654         },
3655         .slaves         = omap44xx_mmc4_slaves,
3656         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3657         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3658 };
3659
3660 /* mmc5 */
3661 static struct omap_hwmod omap44xx_mmc5_hwmod;
3662 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3663         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3664         { .irq = -1 }
3665 };
3666
3667 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3668         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3669         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3670         { .dma_req = -1 }
3671 };
3672
3673 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3674         {
3675                 .pa_start       = 0x480d5000,
3676                 .pa_end         = 0x480d53ff,
3677                 .flags          = ADDR_TYPE_RT
3678         },
3679         { }
3680 };
3681
3682 /* l4_per -> mmc5 */
3683 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3684         .master         = &omap44xx_l4_per_hwmod,
3685         .slave          = &omap44xx_mmc5_hwmod,
3686         .clk            = "l4_div_ck",
3687         .addr           = omap44xx_mmc5_addrs,
3688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3689 };
3690
3691 /* mmc5 slave ports */
3692 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3693         &omap44xx_l4_per__mmc5,
3694 };
3695
3696 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3697         .name           = "mmc5",
3698         .class          = &omap44xx_mmc_hwmod_class,
3699         .mpu_irqs       = omap44xx_mmc5_irqs,
3700         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3701         .main_clk       = "mmc5_fck",
3702         .prcm = {
3703                 .omap4 = {
3704                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3705                 },
3706         },
3707         .slaves         = omap44xx_mmc5_slaves,
3708         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3710 };
3711
3712 /*
3713  * 'mpu' class
3714  * mpu sub-system
3715  */
3716
3717 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3718         .name   = "mpu",
3719 };
3720
3721 /* mpu */
3722 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3723         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3724         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3725         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3726         { .irq = -1 }
3727 };
3728
3729 /* mpu master ports */
3730 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3731         &omap44xx_mpu__l3_main_1,
3732         &omap44xx_mpu__l4_abe,
3733         &omap44xx_mpu__dmm,
3734 };
3735
3736 static struct omap_hwmod omap44xx_mpu_hwmod = {
3737         .name           = "mpu",
3738         .class          = &omap44xx_mpu_hwmod_class,
3739         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3740         .mpu_irqs       = omap44xx_mpu_irqs,
3741         .main_clk       = "dpll_mpu_m2_ck",
3742         .prcm = {
3743                 .omap4 = {
3744                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3745                 },
3746         },
3747         .masters        = omap44xx_mpu_masters,
3748         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3749         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3750 };
3751
3752 /*
3753  * 'smartreflex' class
3754  * smartreflex module (monitor silicon performance and outputs a measure of
3755  * performance error)
3756  */
3757
3758 /* The IP is not compliant to type1 / type2 scheme */
3759 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3760         .sidle_shift    = 24,
3761         .enwkup_shift   = 26,
3762 };
3763
3764 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3765         .sysc_offs      = 0x0038,
3766         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3767         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3768                            SIDLE_SMART_WKUP),
3769         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3770 };
3771
3772 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3773         .name   = "smartreflex",
3774         .sysc   = &omap44xx_smartreflex_sysc,
3775         .rev    = 2,
3776 };
3777
3778 /* smartreflex_core */
3779 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3780 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3781         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3782         { .irq = -1 }
3783 };
3784
3785 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3786         {
3787                 .pa_start       = 0x4a0dd000,
3788                 .pa_end         = 0x4a0dd03f,
3789                 .flags          = ADDR_TYPE_RT
3790         },
3791         { }
3792 };
3793
3794 /* l4_cfg -> smartreflex_core */
3795 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3796         .master         = &omap44xx_l4_cfg_hwmod,
3797         .slave          = &omap44xx_smartreflex_core_hwmod,
3798         .clk            = "l4_div_ck",
3799         .addr           = omap44xx_smartreflex_core_addrs,
3800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3801 };
3802
3803 /* smartreflex_core slave ports */
3804 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3805         &omap44xx_l4_cfg__smartreflex_core,
3806 };
3807
3808 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3809         .name           = "smartreflex_core",
3810         .class          = &omap44xx_smartreflex_hwmod_class,
3811         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3812
3813         .main_clk       = "smartreflex_core_fck",
3814         .vdd_name       = "core",
3815         .prcm = {
3816                 .omap4 = {
3817                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3818                 },
3819         },
3820         .slaves         = omap44xx_smartreflex_core_slaves,
3821         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3822         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3823 };
3824
3825 /* smartreflex_iva */
3826 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3827 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3828         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3829         { .irq = -1 }
3830 };
3831
3832 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3833         {
3834                 .pa_start       = 0x4a0db000,
3835                 .pa_end         = 0x4a0db03f,
3836                 .flags          = ADDR_TYPE_RT
3837         },
3838         { }
3839 };
3840
3841 /* l4_cfg -> smartreflex_iva */
3842 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3843         .master         = &omap44xx_l4_cfg_hwmod,
3844         .slave          = &omap44xx_smartreflex_iva_hwmod,
3845         .clk            = "l4_div_ck",
3846         .addr           = omap44xx_smartreflex_iva_addrs,
3847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3848 };
3849
3850 /* smartreflex_iva slave ports */
3851 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3852         &omap44xx_l4_cfg__smartreflex_iva,
3853 };
3854
3855 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3856         .name           = "smartreflex_iva",
3857         .class          = &omap44xx_smartreflex_hwmod_class,
3858         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3859         .main_clk       = "smartreflex_iva_fck",
3860         .vdd_name       = "iva",
3861         .prcm = {
3862                 .omap4 = {
3863                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3864                 },
3865         },
3866         .slaves         = omap44xx_smartreflex_iva_slaves,
3867         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3868         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3869 };
3870
3871 /* smartreflex_mpu */
3872 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3873 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3874         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3875         { .irq = -1 }
3876 };
3877
3878 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3879         {
3880                 .pa_start       = 0x4a0d9000,
3881                 .pa_end         = 0x4a0d903f,
3882                 .flags          = ADDR_TYPE_RT
3883         },
3884         { }
3885 };
3886
3887 /* l4_cfg -> smartreflex_mpu */
3888 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3889         .master         = &omap44xx_l4_cfg_hwmod,
3890         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3891         .clk            = "l4_div_ck",
3892         .addr           = omap44xx_smartreflex_mpu_addrs,
3893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3894 };
3895
3896 /* smartreflex_mpu slave ports */
3897 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3898         &omap44xx_l4_cfg__smartreflex_mpu,
3899 };
3900
3901 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3902         .name           = "smartreflex_mpu",
3903         .class          = &omap44xx_smartreflex_hwmod_class,
3904         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3905         .main_clk       = "smartreflex_mpu_fck",
3906         .vdd_name       = "mpu",
3907         .prcm = {
3908                 .omap4 = {
3909                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3910                 },
3911         },
3912         .slaves         = omap44xx_smartreflex_mpu_slaves,
3913         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3914         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3915 };
3916
3917 /*
3918  * 'spinlock' class
3919  * spinlock provides hardware assistance for synchronizing the processes
3920  * running on multiple processors
3921  */
3922
3923 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3924         .rev_offs       = 0x0000,
3925         .sysc_offs      = 0x0010,
3926         .syss_offs      = 0x0014,
3927         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3928                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3929                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3930         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3931                            SIDLE_SMART_WKUP),
3932         .sysc_fields    = &omap_hwmod_sysc_type1,
3933 };
3934
3935 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3936         .name   = "spinlock",
3937         .sysc   = &omap44xx_spinlock_sysc,
3938 };
3939
3940 /* spinlock */
3941 static struct omap_hwmod omap44xx_spinlock_hwmod;
3942 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3943         {
3944                 .pa_start       = 0x4a0f6000,
3945                 .pa_end         = 0x4a0f6fff,
3946                 .flags          = ADDR_TYPE_RT
3947         },
3948         { }
3949 };
3950
3951 /* l4_cfg -> spinlock */
3952 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3953         .master         = &omap44xx_l4_cfg_hwmod,
3954         .slave          = &omap44xx_spinlock_hwmod,
3955         .clk            = "l4_div_ck",
3956         .addr           = omap44xx_spinlock_addrs,
3957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3958 };
3959
3960 /* spinlock slave ports */
3961 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3962         &omap44xx_l4_cfg__spinlock,
3963 };
3964
3965 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3966         .name           = "spinlock",
3967         .class          = &omap44xx_spinlock_hwmod_class,
3968         .prcm = {
3969                 .omap4 = {
3970                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3971                 },
3972         },
3973         .slaves         = omap44xx_spinlock_slaves,
3974         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3975         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3976 };
3977
3978 /*
3979  * 'timer' class
3980  * general purpose timer module with accurate 1ms tick
3981  * This class contains several variants: ['timer_1ms', 'timer']
3982  */
3983
3984 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3985         .rev_offs       = 0x0000,
3986         .sysc_offs      = 0x0010,
3987         .syss_offs      = 0x0014,
3988         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3989                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3990                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3991                            SYSS_HAS_RESET_STATUS),
3992         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3993         .sysc_fields    = &omap_hwmod_sysc_type1,
3994 };
3995
3996 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3997         .name   = "timer",
3998         .sysc   = &omap44xx_timer_1ms_sysc,
3999 };
4000
4001 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4002         .rev_offs       = 0x0000,
4003         .sysc_offs      = 0x0010,
4004         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4005                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4007                            SIDLE_SMART_WKUP),
4008         .sysc_fields    = &omap_hwmod_sysc_type2,
4009 };
4010
4011 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4012         .name   = "timer",
4013         .sysc   = &omap44xx_timer_sysc,
4014 };
4015
4016 /* timer1 */
4017 static struct omap_hwmod omap44xx_timer1_hwmod;
4018 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4019         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4020         { .irq = -1 }
4021 };
4022
4023 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4024         {
4025                 .pa_start       = 0x4a318000,
4026                 .pa_end         = 0x4a31807f,
4027                 .flags          = ADDR_TYPE_RT
4028         },
4029         { }
4030 };
4031
4032 /* l4_wkup -> timer1 */
4033 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4034         .master         = &omap44xx_l4_wkup_hwmod,
4035         .slave          = &omap44xx_timer1_hwmod,
4036         .clk            = "l4_wkup_clk_mux_ck",
4037         .addr           = omap44xx_timer1_addrs,
4038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4039 };
4040
4041 /* timer1 slave ports */
4042 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4043         &omap44xx_l4_wkup__timer1,
4044 };
4045
4046 static struct omap_hwmod omap44xx_timer1_hwmod = {
4047         .name           = "timer1",
4048         .class          = &omap44xx_timer_1ms_hwmod_class,
4049         .mpu_irqs       = omap44xx_timer1_irqs,
4050         .main_clk       = "timer1_fck",
4051         .prcm = {
4052                 .omap4 = {
4053                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4054                 },
4055         },
4056         .slaves         = omap44xx_timer1_slaves,
4057         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4059 };
4060
4061 /* timer2 */
4062 static struct omap_hwmod omap44xx_timer2_hwmod;
4063 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4064         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4065         { .irq = -1 }
4066 };
4067
4068 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4069         {
4070                 .pa_start       = 0x48032000,
4071                 .pa_end         = 0x4803207f,
4072                 .flags          = ADDR_TYPE_RT
4073         },
4074         { }
4075 };
4076
4077 /* l4_per -> timer2 */
4078 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4079         .master         = &omap44xx_l4_per_hwmod,
4080         .slave          = &omap44xx_timer2_hwmod,
4081         .clk            = "l4_div_ck",
4082         .addr           = omap44xx_timer2_addrs,
4083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4084 };
4085
4086 /* timer2 slave ports */
4087 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4088         &omap44xx_l4_per__timer2,
4089 };
4090
4091 static struct omap_hwmod omap44xx_timer2_hwmod = {
4092         .name           = "timer2",
4093         .class          = &omap44xx_timer_1ms_hwmod_class,
4094         .mpu_irqs       = omap44xx_timer2_irqs,
4095         .main_clk       = "timer2_fck",
4096         .prcm = {
4097                 .omap4 = {
4098                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4099                 },
4100         },
4101         .slaves         = omap44xx_timer2_slaves,
4102         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4104 };
4105
4106 /* timer3 */
4107 static struct omap_hwmod omap44xx_timer3_hwmod;
4108 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4109         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4110         { .irq = -1 }
4111 };
4112
4113 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4114         {
4115                 .pa_start       = 0x48034000,
4116                 .pa_end         = 0x4803407f,
4117                 .flags          = ADDR_TYPE_RT
4118         },
4119         { }
4120 };
4121
4122 /* l4_per -> timer3 */
4123 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4124         .master         = &omap44xx_l4_per_hwmod,
4125         .slave          = &omap44xx_timer3_hwmod,
4126         .clk            = "l4_div_ck",
4127         .addr           = omap44xx_timer3_addrs,
4128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4129 };
4130
4131 /* timer3 slave ports */
4132 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4133         &omap44xx_l4_per__timer3,
4134 };
4135
4136 static struct omap_hwmod omap44xx_timer3_hwmod = {
4137         .name           = "timer3",
4138         .class          = &omap44xx_timer_hwmod_class,
4139         .mpu_irqs       = omap44xx_timer3_irqs,
4140         .main_clk       = "timer3_fck",
4141         .prcm = {
4142                 .omap4 = {
4143                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4144                 },
4145         },
4146         .slaves         = omap44xx_timer3_slaves,
4147         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4148         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4149 };
4150
4151 /* timer4 */
4152 static struct omap_hwmod omap44xx_timer4_hwmod;
4153 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4154         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4155         { .irq = -1 }
4156 };
4157
4158 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4159         {
4160                 .pa_start       = 0x48036000,
4161                 .pa_end         = 0x4803607f,
4162                 .flags          = ADDR_TYPE_RT
4163         },
4164         { }
4165 };
4166
4167 /* l4_per -> timer4 */
4168 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4169         .master         = &omap44xx_l4_per_hwmod,
4170         .slave          = &omap44xx_timer4_hwmod,
4171         .clk            = "l4_div_ck",
4172         .addr           = omap44xx_timer4_addrs,
4173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4174 };
4175
4176 /* timer4 slave ports */
4177 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4178         &omap44xx_l4_per__timer4,
4179 };
4180
4181 static struct omap_hwmod omap44xx_timer4_hwmod = {
4182         .name           = "timer4",
4183         .class          = &omap44xx_timer_hwmod_class,
4184         .mpu_irqs       = omap44xx_timer4_irqs,
4185         .main_clk       = "timer4_fck",
4186         .prcm = {
4187                 .omap4 = {
4188                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4189                 },
4190         },
4191         .slaves         = omap44xx_timer4_slaves,
4192         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4193         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4194 };
4195
4196 /* timer5 */
4197 static struct omap_hwmod omap44xx_timer5_hwmod;
4198 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4199         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4200         { .irq = -1 }
4201 };
4202
4203 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4204         {
4205                 .pa_start       = 0x40138000,
4206                 .pa_end         = 0x4013807f,
4207                 .flags          = ADDR_TYPE_RT
4208         },
4209         { }
4210 };
4211
4212 /* l4_abe -> timer5 */
4213 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4214         .master         = &omap44xx_l4_abe_hwmod,
4215         .slave          = &omap44xx_timer5_hwmod,
4216         .clk            = "ocp_abe_iclk",
4217         .addr           = omap44xx_timer5_addrs,
4218         .user           = OCP_USER_MPU,
4219 };
4220
4221 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4222         {
4223                 .pa_start       = 0x49038000,
4224                 .pa_end         = 0x4903807f,
4225                 .flags          = ADDR_TYPE_RT
4226         },
4227         { }
4228 };
4229
4230 /* l4_abe -> timer5 (dma) */
4231 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4232         .master         = &omap44xx_l4_abe_hwmod,
4233         .slave          = &omap44xx_timer5_hwmod,
4234         .clk            = "ocp_abe_iclk",
4235         .addr           = omap44xx_timer5_dma_addrs,
4236         .user           = OCP_USER_SDMA,
4237 };
4238
4239 /* timer5 slave ports */
4240 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4241         &omap44xx_l4_abe__timer5,
4242         &omap44xx_l4_abe__timer5_dma,
4243 };
4244
4245 static struct omap_hwmod omap44xx_timer5_hwmod = {
4246         .name           = "timer5",
4247         .class          = &omap44xx_timer_hwmod_class,
4248         .mpu_irqs       = omap44xx_timer5_irqs,
4249         .main_clk       = "timer5_fck",
4250         .prcm = {
4251                 .omap4 = {
4252                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4253                 },
4254         },
4255         .slaves         = omap44xx_timer5_slaves,
4256         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4257         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4258 };
4259
4260 /* timer6 */
4261 static struct omap_hwmod omap44xx_timer6_hwmod;
4262 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4263         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4264         { .irq = -1 }
4265 };
4266
4267 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4268         {
4269                 .pa_start       = 0x4013a000,
4270                 .pa_end         = 0x4013a07f,
4271                 .flags          = ADDR_TYPE_RT
4272         },
4273         { }
4274 };
4275
4276 /* l4_abe -> timer6 */
4277 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4278         .master         = &omap44xx_l4_abe_hwmod,
4279         .slave          = &omap44xx_timer6_hwmod,
4280         .clk            = "ocp_abe_iclk",
4281         .addr           = omap44xx_timer6_addrs,
4282         .user           = OCP_USER_MPU,
4283 };
4284
4285 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4286         {
4287                 .pa_start       = 0x4903a000,
4288                 .pa_end         = 0x4903a07f,
4289                 .flags          = ADDR_TYPE_RT
4290         },
4291         { }
4292 };
4293
4294 /* l4_abe -> timer6 (dma) */
4295 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4296         .master         = &omap44xx_l4_abe_hwmod,
4297         .slave          = &omap44xx_timer6_hwmod,
4298         .clk            = "ocp_abe_iclk",
4299         .addr           = omap44xx_timer6_dma_addrs,
4300         .user           = OCP_USER_SDMA,
4301 };
4302
4303 /* timer6 slave ports */
4304 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4305         &omap44xx_l4_abe__timer6,
4306         &omap44xx_l4_abe__timer6_dma,
4307 };
4308
4309 static struct omap_hwmod omap44xx_timer6_hwmod = {
4310         .name           = "timer6",
4311         .class          = &omap44xx_timer_hwmod_class,
4312         .mpu_irqs       = omap44xx_timer6_irqs,
4313
4314         .main_clk       = "timer6_fck",
4315         .prcm = {
4316                 .omap4 = {
4317                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4318                 },
4319         },
4320         .slaves         = omap44xx_timer6_slaves,
4321         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4322         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4323 };
4324
4325 /* timer7 */
4326 static struct omap_hwmod omap44xx_timer7_hwmod;
4327 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4328         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4329         { .irq = -1 }
4330 };
4331
4332 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4333         {
4334                 .pa_start       = 0x4013c000,
4335                 .pa_end         = 0x4013c07f,
4336                 .flags          = ADDR_TYPE_RT
4337         },
4338         { }
4339 };
4340
4341 /* l4_abe -> timer7 */
4342 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4343         .master         = &omap44xx_l4_abe_hwmod,
4344         .slave          = &omap44xx_timer7_hwmod,
4345         .clk            = "ocp_abe_iclk",
4346         .addr           = omap44xx_timer7_addrs,
4347         .user           = OCP_USER_MPU,
4348 };
4349
4350 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4351         {
4352                 .pa_start       = 0x4903c000,
4353                 .pa_end         = 0x4903c07f,
4354                 .flags          = ADDR_TYPE_RT
4355         },
4356         { }
4357 };
4358
4359 /* l4_abe -> timer7 (dma) */
4360 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4361         .master         = &omap44xx_l4_abe_hwmod,
4362         .slave          = &omap44xx_timer7_hwmod,
4363         .clk            = "ocp_abe_iclk",
4364         .addr           = omap44xx_timer7_dma_addrs,
4365         .user           = OCP_USER_SDMA,
4366 };
4367
4368 /* timer7 slave ports */
4369 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4370         &omap44xx_l4_abe__timer7,
4371         &omap44xx_l4_abe__timer7_dma,
4372 };
4373
4374 static struct omap_hwmod omap44xx_timer7_hwmod = {
4375         .name           = "timer7",
4376         .class          = &omap44xx_timer_hwmod_class,
4377         .mpu_irqs       = omap44xx_timer7_irqs,
4378         .main_clk       = "timer7_fck",
4379         .prcm = {
4380                 .omap4 = {
4381                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4382                 },
4383         },
4384         .slaves         = omap44xx_timer7_slaves,
4385         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4386         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4387 };
4388
4389 /* timer8 */
4390 static struct omap_hwmod omap44xx_timer8_hwmod;
4391 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4392         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4393         { .irq = -1 }
4394 };
4395
4396 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4397         {
4398                 .pa_start       = 0x4013e000,
4399                 .pa_end         = 0x4013e07f,
4400                 .flags          = ADDR_TYPE_RT
4401         },
4402         { }
4403 };
4404
4405 /* l4_abe -> timer8 */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4407         .master         = &omap44xx_l4_abe_hwmod,
4408         .slave          = &omap44xx_timer8_hwmod,
4409         .clk            = "ocp_abe_iclk",
4410         .addr           = omap44xx_timer8_addrs,
4411         .user           = OCP_USER_MPU,
4412 };
4413
4414 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4415         {
4416                 .pa_start       = 0x4903e000,
4417                 .pa_end         = 0x4903e07f,
4418                 .flags          = ADDR_TYPE_RT
4419         },
4420         { }
4421 };
4422
4423 /* l4_abe -> timer8 (dma) */
4424 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4425         .master         = &omap44xx_l4_abe_hwmod,
4426         .slave          = &omap44xx_timer8_hwmod,
4427         .clk            = "ocp_abe_iclk",
4428         .addr           = omap44xx_timer8_dma_addrs,
4429         .user           = OCP_USER_SDMA,
4430 };
4431
4432 /* timer8 slave ports */
4433 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4434         &omap44xx_l4_abe__timer8,
4435         &omap44xx_l4_abe__timer8_dma,
4436 };
4437
4438 static struct omap_hwmod omap44xx_timer8_hwmod = {
4439         .name           = "timer8",
4440         .class          = &omap44xx_timer_hwmod_class,
4441         .mpu_irqs       = omap44xx_timer8_irqs,
4442         .main_clk       = "timer8_fck",
4443         .prcm = {
4444                 .omap4 = {
4445                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4446                 },
4447         },
4448         .slaves         = omap44xx_timer8_slaves,
4449         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4450         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4451 };
4452
4453 /* timer9 */
4454 static struct omap_hwmod omap44xx_timer9_hwmod;
4455 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4456         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4457         { .irq = -1 }
4458 };
4459
4460 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4461         {
4462                 .pa_start       = 0x4803e000,
4463                 .pa_end         = 0x4803e07f,
4464                 .flags          = ADDR_TYPE_RT
4465         },
4466         { }
4467 };
4468
4469 /* l4_per -> timer9 */
4470 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4471         .master         = &omap44xx_l4_per_hwmod,
4472         .slave          = &omap44xx_timer9_hwmod,
4473         .clk            = "l4_div_ck",
4474         .addr           = omap44xx_timer9_addrs,
4475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4476 };
4477
4478 /* timer9 slave ports */
4479 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4480         &omap44xx_l4_per__timer9,
4481 };
4482
4483 static struct omap_hwmod omap44xx_timer9_hwmod = {
4484         .name           = "timer9",
4485         .class          = &omap44xx_timer_hwmod_class,
4486         .mpu_irqs       = omap44xx_timer9_irqs,
4487         .main_clk       = "timer9_fck",
4488         .prcm = {
4489                 .omap4 = {
4490                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4491                 },
4492         },
4493         .slaves         = omap44xx_timer9_slaves,
4494         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4495         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4496 };
4497
4498 /* timer10 */
4499 static struct omap_hwmod omap44xx_timer10_hwmod;
4500 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4501         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4502         { .irq = -1 }
4503 };
4504
4505 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4506         {
4507                 .pa_start       = 0x48086000,
4508                 .pa_end         = 0x4808607f,
4509                 .flags          = ADDR_TYPE_RT
4510         },
4511         { }
4512 };
4513
4514 /* l4_per -> timer10 */
4515 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4516         .master         = &omap44xx_l4_per_hwmod,
4517         .slave          = &omap44xx_timer10_hwmod,
4518         .clk            = "l4_div_ck",
4519         .addr           = omap44xx_timer10_addrs,
4520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4521 };
4522
4523 /* timer10 slave ports */
4524 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4525         &omap44xx_l4_per__timer10,
4526 };
4527
4528 static struct omap_hwmod omap44xx_timer10_hwmod = {
4529         .name           = "timer10",
4530         .class          = &omap44xx_timer_1ms_hwmod_class,
4531         .mpu_irqs       = omap44xx_timer10_irqs,
4532         .main_clk       = "timer10_fck",
4533         .prcm = {
4534                 .omap4 = {
4535                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4536                 },
4537         },
4538         .slaves         = omap44xx_timer10_slaves,
4539         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4540         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4541 };
4542
4543 /* timer11 */
4544 static struct omap_hwmod omap44xx_timer11_hwmod;
4545 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4546         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4547         { .irq = -1 }
4548 };
4549
4550 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4551         {
4552                 .pa_start       = 0x48088000,
4553                 .pa_end         = 0x4808807f,
4554                 .flags          = ADDR_TYPE_RT
4555         },
4556         { }
4557 };
4558
4559 /* l4_per -> timer11 */
4560 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4561         .master         = &omap44xx_l4_per_hwmod,
4562         .slave          = &omap44xx_timer11_hwmod,
4563         .clk            = "l4_div_ck",
4564         .addr           = omap44xx_timer11_addrs,
4565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4566 };
4567
4568 /* timer11 slave ports */
4569 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4570         &omap44xx_l4_per__timer11,
4571 };
4572
4573 static struct omap_hwmod omap44xx_timer11_hwmod = {
4574         .name           = "timer11",
4575         .class          = &omap44xx_timer_hwmod_class,
4576         .mpu_irqs       = omap44xx_timer11_irqs,
4577         .main_clk       = "timer11_fck",
4578         .prcm = {
4579                 .omap4 = {
4580                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4581                 },
4582         },
4583         .slaves         = omap44xx_timer11_slaves,
4584         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4585         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4586 };
4587
4588 /*
4589  * 'uart' class
4590  * universal asynchronous receiver/transmitter (uart)
4591  */
4592
4593 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4594         .rev_offs       = 0x0050,
4595         .sysc_offs      = 0x0054,
4596         .syss_offs      = 0x0058,
4597         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4598                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4599                            SYSS_HAS_RESET_STATUS),
4600         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4601                            SIDLE_SMART_WKUP),
4602         .sysc_fields    = &omap_hwmod_sysc_type1,
4603 };
4604
4605 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4606         .name   = "uart",
4607         .sysc   = &omap44xx_uart_sysc,
4608 };
4609
4610 /* uart1 */
4611 static struct omap_hwmod omap44xx_uart1_hwmod;
4612 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4613         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4614         { .irq = -1 }
4615 };
4616
4617 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4618         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4619         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4620         { .dma_req = -1 }
4621 };
4622
4623 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4624         {
4625                 .pa_start       = 0x4806a000,
4626                 .pa_end         = 0x4806a0ff,
4627                 .flags          = ADDR_TYPE_RT
4628         },
4629         { }
4630 };
4631
4632 /* l4_per -> uart1 */
4633 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4634         .master         = &omap44xx_l4_per_hwmod,
4635         .slave          = &omap44xx_uart1_hwmod,
4636         .clk            = "l4_div_ck",
4637         .addr           = omap44xx_uart1_addrs,
4638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4639 };
4640
4641 /* uart1 slave ports */
4642 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4643         &omap44xx_l4_per__uart1,
4644 };
4645
4646 static struct omap_hwmod omap44xx_uart1_hwmod = {
4647         .name           = "uart1",
4648         .class          = &omap44xx_uart_hwmod_class,
4649         .mpu_irqs       = omap44xx_uart1_irqs,
4650         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4651         .main_clk       = "uart1_fck",
4652         .prcm = {
4653                 .omap4 = {
4654                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4655                 },
4656         },
4657         .slaves         = omap44xx_uart1_slaves,
4658         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4660 };
4661
4662 /* uart2 */
4663 static struct omap_hwmod omap44xx_uart2_hwmod;
4664 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4665         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4666         { .irq = -1 }
4667 };
4668
4669 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4670         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4671         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4672         { .dma_req = -1 }
4673 };
4674
4675 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4676         {
4677                 .pa_start       = 0x4806c000,
4678                 .pa_end         = 0x4806c0ff,
4679                 .flags          = ADDR_TYPE_RT
4680         },
4681         { }
4682 };
4683
4684 /* l4_per -> uart2 */
4685 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4686         .master         = &omap44xx_l4_per_hwmod,
4687         .slave          = &omap44xx_uart2_hwmod,
4688         .clk            = "l4_div_ck",
4689         .addr           = omap44xx_uart2_addrs,
4690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4691 };
4692
4693 /* uart2 slave ports */
4694 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4695         &omap44xx_l4_per__uart2,
4696 };
4697
4698 static struct omap_hwmod omap44xx_uart2_hwmod = {
4699         .name           = "uart2",
4700         .class          = &omap44xx_uart_hwmod_class,
4701         .mpu_irqs       = omap44xx_uart2_irqs,
4702         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4703         .main_clk       = "uart2_fck",
4704         .prcm = {
4705                 .omap4 = {
4706                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4707                 },
4708         },
4709         .slaves         = omap44xx_uart2_slaves,
4710         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4711         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4712 };
4713
4714 /* uart3 */
4715 static struct omap_hwmod omap44xx_uart3_hwmod;
4716 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4717         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4718         { .irq = -1 }
4719 };
4720
4721 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4722         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4723         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4724         { .dma_req = -1 }
4725 };
4726
4727 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4728         {
4729                 .pa_start       = 0x48020000,
4730                 .pa_end         = 0x480200ff,
4731                 .flags          = ADDR_TYPE_RT
4732         },
4733         { }
4734 };
4735
4736 /* l4_per -> uart3 */
4737 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4738         .master         = &omap44xx_l4_per_hwmod,
4739         .slave          = &omap44xx_uart3_hwmod,
4740         .clk            = "l4_div_ck",
4741         .addr           = omap44xx_uart3_addrs,
4742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4743 };
4744
4745 /* uart3 slave ports */
4746 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4747         &omap44xx_l4_per__uart3,
4748 };
4749
4750 static struct omap_hwmod omap44xx_uart3_hwmod = {
4751         .name           = "uart3",
4752         .class          = &omap44xx_uart_hwmod_class,
4753         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4754         .mpu_irqs       = omap44xx_uart3_irqs,
4755         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4756         .main_clk       = "uart3_fck",
4757         .prcm = {
4758                 .omap4 = {
4759                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4760                 },
4761         },
4762         .slaves         = omap44xx_uart3_slaves,
4763         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4764         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4765 };
4766
4767 /* uart4 */
4768 static struct omap_hwmod omap44xx_uart4_hwmod;
4769 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4770         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4771         { .irq = -1 }
4772 };
4773
4774 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4775         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4776         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4777         { .dma_req = -1 }
4778 };
4779
4780 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4781         {
4782                 .pa_start       = 0x4806e000,
4783                 .pa_end         = 0x4806e0ff,
4784                 .flags          = ADDR_TYPE_RT
4785         },
4786         { }
4787 };
4788
4789 /* l4_per -> uart4 */
4790 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4791         .master         = &omap44xx_l4_per_hwmod,
4792         .slave          = &omap44xx_uart4_hwmod,
4793         .clk            = "l4_div_ck",
4794         .addr           = omap44xx_uart4_addrs,
4795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4796 };
4797
4798 /* uart4 slave ports */
4799 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4800         &omap44xx_l4_per__uart4,
4801 };
4802
4803 static struct omap_hwmod omap44xx_uart4_hwmod = {
4804         .name           = "uart4",
4805         .class          = &omap44xx_uart_hwmod_class,
4806         .mpu_irqs       = omap44xx_uart4_irqs,
4807         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4808         .main_clk       = "uart4_fck",
4809         .prcm = {
4810                 .omap4 = {
4811                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4812                 },
4813         },
4814         .slaves         = omap44xx_uart4_slaves,
4815         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4816         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4817 };
4818
4819 /*
4820  * 'usb_otg_hs' class
4821  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4822  */
4823
4824 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4825         .rev_offs       = 0x0400,
4826         .sysc_offs      = 0x0404,
4827         .syss_offs      = 0x0408,
4828         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4829                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4830                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4831         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4832                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4833                            MSTANDBY_SMART),
4834         .sysc_fields    = &omap_hwmod_sysc_type1,
4835 };
4836
4837 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4838         .name   = "usb_otg_hs",
4839         .sysc   = &omap44xx_usb_otg_hs_sysc,
4840 };
4841
4842 /* usb_otg_hs */
4843 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4844         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4845         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4846         { .irq = -1 }
4847 };
4848
4849 /* usb_otg_hs master ports */
4850 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4851         &omap44xx_usb_otg_hs__l3_main_2,
4852 };
4853
4854 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4855         {
4856                 .pa_start       = 0x4a0ab000,
4857                 .pa_end         = 0x4a0ab003,
4858                 .flags          = ADDR_TYPE_RT
4859         },
4860         { }
4861 };
4862
4863 /* l4_cfg -> usb_otg_hs */
4864 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4865         .master         = &omap44xx_l4_cfg_hwmod,
4866         .slave          = &omap44xx_usb_otg_hs_hwmod,
4867         .clk            = "l4_div_ck",
4868         .addr           = omap44xx_usb_otg_hs_addrs,
4869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4870 };
4871
4872 /* usb_otg_hs slave ports */
4873 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4874         &omap44xx_l4_cfg__usb_otg_hs,
4875 };
4876
4877 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4878         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4879 };
4880
4881 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4882         .name           = "usb_otg_hs",
4883         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4884         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4885         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4886         .main_clk       = "usb_otg_hs_ick",
4887         .prcm = {
4888                 .omap4 = {
4889                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4890                 },
4891         },
4892         .opt_clks       = usb_otg_hs_opt_clks,
4893         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
4894         .slaves         = omap44xx_usb_otg_hs_slaves,
4895         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4896         .masters        = omap44xx_usb_otg_hs_masters,
4897         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4898         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4899 };
4900
4901 /*
4902  * 'wd_timer' class
4903  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4904  * overflow condition
4905  */
4906
4907 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4908         .rev_offs       = 0x0000,
4909         .sysc_offs      = 0x0010,
4910         .syss_offs      = 0x0014,
4911         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4912                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4914                            SIDLE_SMART_WKUP),
4915         .sysc_fields    = &omap_hwmod_sysc_type1,
4916 };
4917
4918 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4919         .name           = "wd_timer",
4920         .sysc           = &omap44xx_wd_timer_sysc,
4921         .pre_shutdown   = &omap2_wd_timer_disable,
4922 };
4923
4924 /* wd_timer2 */
4925 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4926 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4927         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4928         { .irq = -1 }
4929 };
4930
4931 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4932         {
4933                 .pa_start       = 0x4a314000,
4934                 .pa_end         = 0x4a31407f,
4935                 .flags          = ADDR_TYPE_RT
4936         },
4937         { }
4938 };
4939
4940 /* l4_wkup -> wd_timer2 */
4941 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4942         .master         = &omap44xx_l4_wkup_hwmod,
4943         .slave          = &omap44xx_wd_timer2_hwmod,
4944         .clk            = "l4_wkup_clk_mux_ck",
4945         .addr           = omap44xx_wd_timer2_addrs,
4946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4947 };
4948
4949 /* wd_timer2 slave ports */
4950 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4951         &omap44xx_l4_wkup__wd_timer2,
4952 };
4953
4954 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4955         .name           = "wd_timer2",
4956         .class          = &omap44xx_wd_timer_hwmod_class,
4957         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4958         .main_clk       = "wd_timer2_fck",
4959         .prcm = {
4960                 .omap4 = {
4961                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4962                 },
4963         },
4964         .slaves         = omap44xx_wd_timer2_slaves,
4965         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4966         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4967 };
4968
4969 /* wd_timer3 */
4970 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4971 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4972         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4973         { .irq = -1 }
4974 };
4975
4976 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4977         {
4978                 .pa_start       = 0x40130000,
4979                 .pa_end         = 0x4013007f,
4980                 .flags          = ADDR_TYPE_RT
4981         },
4982         { }
4983 };
4984
4985 /* l4_abe -> wd_timer3 */
4986 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4987         .master         = &omap44xx_l4_abe_hwmod,
4988         .slave          = &omap44xx_wd_timer3_hwmod,
4989         .clk            = "ocp_abe_iclk",
4990         .addr           = omap44xx_wd_timer3_addrs,
4991         .user           = OCP_USER_MPU,
4992 };
4993
4994 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4995         {
4996                 .pa_start       = 0x49030000,
4997                 .pa_end         = 0x4903007f,
4998                 .flags          = ADDR_TYPE_RT
4999         },
5000         { }
5001 };
5002
5003 /* l4_abe -> wd_timer3 (dma) */
5004 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5005         .master         = &omap44xx_l4_abe_hwmod,
5006         .slave          = &omap44xx_wd_timer3_hwmod,
5007         .clk            = "ocp_abe_iclk",
5008         .addr           = omap44xx_wd_timer3_dma_addrs,
5009         .user           = OCP_USER_SDMA,
5010 };
5011
5012 /* wd_timer3 slave ports */
5013 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5014         &omap44xx_l4_abe__wd_timer3,
5015         &omap44xx_l4_abe__wd_timer3_dma,
5016 };
5017
5018 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5019         .name           = "wd_timer3",
5020         .class          = &omap44xx_wd_timer_hwmod_class,
5021         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5022         .main_clk       = "wd_timer3_fck",
5023         .prcm = {
5024                 .omap4 = {
5025                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
5026                 },
5027         },
5028         .slaves         = omap44xx_wd_timer3_slaves,
5029         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5030         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5031 };
5032
5033 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5034
5035         /* dmm class */
5036         &omap44xx_dmm_hwmod,
5037
5038         /* emif_fw class */
5039         &omap44xx_emif_fw_hwmod,
5040
5041         /* l3 class */
5042         &omap44xx_l3_instr_hwmod,
5043         &omap44xx_l3_main_1_hwmod,
5044         &omap44xx_l3_main_2_hwmod,
5045         &omap44xx_l3_main_3_hwmod,
5046
5047         /* l4 class */
5048         &omap44xx_l4_abe_hwmod,
5049         &omap44xx_l4_cfg_hwmod,
5050         &omap44xx_l4_per_hwmod,
5051         &omap44xx_l4_wkup_hwmod,
5052
5053         /* mpu_bus class */
5054         &omap44xx_mpu_private_hwmod,
5055
5056         /* aess class */
5057 /*      &omap44xx_aess_hwmod, */
5058
5059         /* bandgap class */
5060         &omap44xx_bandgap_hwmod,
5061
5062         /* counter class */
5063 /*      &omap44xx_counter_32k_hwmod, */
5064
5065         /* dma class */
5066         &omap44xx_dma_system_hwmod,
5067
5068         /* dmic class */
5069         &omap44xx_dmic_hwmod,
5070
5071         /* dsp class */
5072         &omap44xx_dsp_hwmod,
5073         &omap44xx_dsp_c0_hwmod,
5074
5075         /* dss class */
5076         &omap44xx_dss_hwmod,
5077         &omap44xx_dss_dispc_hwmod,
5078         &omap44xx_dss_dsi1_hwmod,
5079         &omap44xx_dss_dsi2_hwmod,
5080         &omap44xx_dss_hdmi_hwmod,
5081         &omap44xx_dss_rfbi_hwmod,
5082         &omap44xx_dss_venc_hwmod,
5083
5084         /* gpio class */
5085         &omap44xx_gpio1_hwmod,
5086         &omap44xx_gpio2_hwmod,
5087         &omap44xx_gpio3_hwmod,
5088         &omap44xx_gpio4_hwmod,
5089         &omap44xx_gpio5_hwmod,
5090         &omap44xx_gpio6_hwmod,
5091
5092         /* hsi class */
5093 /*      &omap44xx_hsi_hwmod, */
5094
5095         /* i2c class */
5096         &omap44xx_i2c1_hwmod,
5097         &omap44xx_i2c2_hwmod,
5098         &omap44xx_i2c3_hwmod,
5099         &omap44xx_i2c4_hwmod,
5100
5101         /* ipu class */
5102         &omap44xx_ipu_hwmod,
5103         &omap44xx_ipu_c0_hwmod,
5104         &omap44xx_ipu_c1_hwmod,
5105
5106         /* iss class */
5107 /*      &omap44xx_iss_hwmod, */
5108
5109         /* iva class */
5110         &omap44xx_iva_hwmod,
5111         &omap44xx_iva_seq0_hwmod,
5112         &omap44xx_iva_seq1_hwmod,
5113
5114         /* kbd class */
5115         &omap44xx_kbd_hwmod,
5116
5117         /* mailbox class */
5118         &omap44xx_mailbox_hwmod,
5119
5120         /* mcbsp class */
5121         &omap44xx_mcbsp1_hwmod,
5122         &omap44xx_mcbsp2_hwmod,
5123         &omap44xx_mcbsp3_hwmod,
5124         &omap44xx_mcbsp4_hwmod,
5125
5126         /* mcpdm class */
5127 /*      &omap44xx_mcpdm_hwmod, */
5128
5129         /* mcspi class */
5130         &omap44xx_mcspi1_hwmod,
5131         &omap44xx_mcspi2_hwmod,
5132         &omap44xx_mcspi3_hwmod,
5133         &omap44xx_mcspi4_hwmod,
5134
5135         /* mmc class */
5136         &omap44xx_mmc1_hwmod,
5137         &omap44xx_mmc2_hwmod,
5138         &omap44xx_mmc3_hwmod,
5139         &omap44xx_mmc4_hwmod,
5140         &omap44xx_mmc5_hwmod,
5141
5142         /* mpu class */
5143         &omap44xx_mpu_hwmod,
5144
5145         /* smartreflex class */
5146         &omap44xx_smartreflex_core_hwmod,
5147         &omap44xx_smartreflex_iva_hwmod,
5148         &omap44xx_smartreflex_mpu_hwmod,
5149
5150         /* spinlock class */
5151         &omap44xx_spinlock_hwmod,
5152
5153         /* timer class */
5154         &omap44xx_timer1_hwmod,
5155         &omap44xx_timer2_hwmod,
5156         &omap44xx_timer3_hwmod,
5157         &omap44xx_timer4_hwmod,
5158         &omap44xx_timer5_hwmod,
5159         &omap44xx_timer6_hwmod,
5160         &omap44xx_timer7_hwmod,
5161         &omap44xx_timer8_hwmod,
5162         &omap44xx_timer9_hwmod,
5163         &omap44xx_timer10_hwmod,
5164         &omap44xx_timer11_hwmod,
5165
5166         /* uart class */
5167         &omap44xx_uart1_hwmod,
5168         &omap44xx_uart2_hwmod,
5169         &omap44xx_uart3_hwmod,
5170         &omap44xx_uart4_hwmod,
5171
5172         /* usb_otg_hs class */
5173         &omap44xx_usb_otg_hs_hwmod,
5174
5175         /* wd_timer class */
5176         &omap44xx_wd_timer2_hwmod,
5177         &omap44xx_wd_timer3_hwmod,
5178
5179         NULL,
5180 };
5181
5182 int __init omap44xx_hwmod_init(void)
5183 {
5184         return omap_hwmod_register(omap44xx_hwmods);
5185 }
5186