2 * Hardware modules present on the OMAP54xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
39 /* Base offset for all OMAP5 interrupts external to MPUSS */
40 #define OMAP54XX_IRQ_GIC_START 32
42 /* Base offset for all OMAP5 dma requests */
43 #define OMAP54XX_DMA_REQ_START 1
54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
59 static struct omap_hwmod omap54xx_dmm_hwmod = {
61 .class = &omap54xx_dmm_hwmod_class,
62 .clkdm_name = "emif_clkdm",
65 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
66 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
73 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
82 .class = &omap54xx_l3_hwmod_class,
83 .clkdm_name = "l3instr_clkdm",
86 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
87 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
88 .modulemode = MODULEMODE_HWCTRL,
94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
96 .class = &omap54xx_l3_hwmod_class,
97 .clkdm_name = "l3main1_clkdm",
100 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
101 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
109 .class = &omap54xx_l3_hwmod_class,
110 .clkdm_name = "l3main2_clkdm",
113 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
114 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
122 .class = &omap54xx_l3_hwmod_class,
123 .clkdm_name = "l3instr_clkdm",
126 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
127 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
128 .modulemode = MODULEMODE_HWCTRL,
135 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
144 .class = &omap54xx_l4_hwmod_class,
145 .clkdm_name = "abe_clkdm",
148 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
149 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
157 .class = &omap54xx_l4_hwmod_class,
158 .clkdm_name = "l4cfg_clkdm",
161 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
162 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
170 .class = &omap54xx_l4_hwmod_class,
171 .clkdm_name = "l4per_clkdm",
174 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
175 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
183 .class = &omap54xx_l4_hwmod_class,
184 .clkdm_name = "wkupaon_clkdm",
187 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
188 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
195 * instance(s): mpu_private
197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
203 .name = "mpu_private",
204 .class = &omap54xx_mpu_bus_hwmod_class,
205 .clkdm_name = "mpu_clkdm",
208 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
215 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
221 .sysc_flags = SYSC_HAS_SIDLEMODE,
222 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
223 .sysc_fields = &omap_hwmod_sysc_type1,
226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
228 .sysc = &omap54xx_counter_sysc,
232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
233 .name = "counter_32k",
234 .class = &omap54xx_counter_hwmod_class,
235 .clkdm_name = "wkupaon_clkdm",
236 .flags = HWMOD_SWSUP_SIDLE,
237 .main_clk = "wkupaon_iclk_mux",
240 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
241 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
248 * dma controller for data exchange between memory to memory (i.e. internal or
249 * external memory) and gp peripherals to memory or memory to gp peripherals
252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
256 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
257 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
258 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
259 SYSS_HAS_RESET_STATUS),
260 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
261 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
262 .sysc_fields = &omap_hwmod_sysc_type1,
265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
267 .sysc = &omap54xx_dma_sysc,
271 static struct omap_dma_dev_attr dma_dev_attr = {
272 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
273 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
279 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
280 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
281 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
282 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
286 static struct omap_hwmod omap54xx_dma_system_hwmod = {
287 .name = "dma_system",
288 .class = &omap54xx_dma_hwmod_class,
289 .clkdm_name = "dma_clkdm",
290 .mpu_irqs = omap54xx_dma_system_irqs,
291 .main_clk = "l3_iclk_div",
294 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
295 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
298 .dev_attr = &dma_dev_attr,
303 * digital microphone controller
306 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
309 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
310 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
313 .sysc_fields = &omap_hwmod_sysc_type2,
316 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
318 .sysc = &omap54xx_dmic_sysc,
322 static struct omap_hwmod omap54xx_dmic_hwmod = {
324 .class = &omap54xx_dmic_hwmod_class,
325 .clkdm_name = "abe_clkdm",
326 .main_clk = "dmic_gfclk",
329 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
330 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
331 .modulemode = MODULEMODE_SWCTRL,
338 * external memory interface no1 (wrapper)
341 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
345 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
347 .sysc = &omap54xx_emif_sysc,
351 static struct omap_hwmod omap54xx_emif1_hwmod = {
353 .class = &omap54xx_emif_hwmod_class,
354 .clkdm_name = "emif_clkdm",
355 .flags = HWMOD_INIT_NO_IDLE,
356 .main_clk = "dpll_core_h11x2_ck",
359 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
360 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
367 static struct omap_hwmod omap54xx_emif2_hwmod = {
369 .class = &omap54xx_emif_hwmod_class,
370 .clkdm_name = "emif_clkdm",
371 .flags = HWMOD_INIT_NO_IDLE,
372 .main_clk = "dpll_core_h11x2_ck",
375 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
376 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
377 .modulemode = MODULEMODE_HWCTRL,
384 * general purpose io module
387 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
391 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
392 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
393 SYSS_HAS_RESET_STATUS),
394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
396 .sysc_fields = &omap_hwmod_sysc_type1,
399 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
401 .sysc = &omap54xx_gpio_sysc,
406 static struct omap_gpio_dev_attr gpio_dev_attr = {
412 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
413 { .role = "dbclk", .clk = "gpio1_dbclk" },
416 static struct omap_hwmod omap54xx_gpio1_hwmod = {
418 .class = &omap54xx_gpio_hwmod_class,
419 .clkdm_name = "wkupaon_clkdm",
420 .main_clk = "wkupaon_iclk_mux",
423 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
424 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
425 .modulemode = MODULEMODE_HWCTRL,
428 .opt_clks = gpio1_opt_clks,
429 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
430 .dev_attr = &gpio_dev_attr,
434 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
435 { .role = "dbclk", .clk = "gpio2_dbclk" },
438 static struct omap_hwmod omap54xx_gpio2_hwmod = {
440 .class = &omap54xx_gpio_hwmod_class,
441 .clkdm_name = "l4per_clkdm",
442 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
443 .main_clk = "l4_root_clk_div",
446 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
447 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
448 .modulemode = MODULEMODE_HWCTRL,
451 .opt_clks = gpio2_opt_clks,
452 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
453 .dev_attr = &gpio_dev_attr,
457 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
458 { .role = "dbclk", .clk = "gpio3_dbclk" },
461 static struct omap_hwmod omap54xx_gpio3_hwmod = {
463 .class = &omap54xx_gpio_hwmod_class,
464 .clkdm_name = "l4per_clkdm",
465 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
466 .main_clk = "l4_root_clk_div",
469 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
470 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
471 .modulemode = MODULEMODE_HWCTRL,
474 .opt_clks = gpio3_opt_clks,
475 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
476 .dev_attr = &gpio_dev_attr,
480 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
481 { .role = "dbclk", .clk = "gpio4_dbclk" },
484 static struct omap_hwmod omap54xx_gpio4_hwmod = {
486 .class = &omap54xx_gpio_hwmod_class,
487 .clkdm_name = "l4per_clkdm",
488 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
489 .main_clk = "l4_root_clk_div",
492 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
493 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
494 .modulemode = MODULEMODE_HWCTRL,
497 .opt_clks = gpio4_opt_clks,
498 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
499 .dev_attr = &gpio_dev_attr,
503 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
504 { .role = "dbclk", .clk = "gpio5_dbclk" },
507 static struct omap_hwmod omap54xx_gpio5_hwmod = {
509 .class = &omap54xx_gpio_hwmod_class,
510 .clkdm_name = "l4per_clkdm",
511 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512 .main_clk = "l4_root_clk_div",
515 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
516 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
517 .modulemode = MODULEMODE_HWCTRL,
520 .opt_clks = gpio5_opt_clks,
521 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
522 .dev_attr = &gpio_dev_attr,
526 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
527 { .role = "dbclk", .clk = "gpio6_dbclk" },
530 static struct omap_hwmod omap54xx_gpio6_hwmod = {
532 .class = &omap54xx_gpio_hwmod_class,
533 .clkdm_name = "l4per_clkdm",
534 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
535 .main_clk = "l4_root_clk_div",
538 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
539 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
540 .modulemode = MODULEMODE_HWCTRL,
543 .opt_clks = gpio6_opt_clks,
544 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
545 .dev_attr = &gpio_dev_attr,
549 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
550 { .role = "dbclk", .clk = "gpio7_dbclk" },
553 static struct omap_hwmod omap54xx_gpio7_hwmod = {
555 .class = &omap54xx_gpio_hwmod_class,
556 .clkdm_name = "l4per_clkdm",
557 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
558 .main_clk = "l4_root_clk_div",
561 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
562 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
563 .modulemode = MODULEMODE_HWCTRL,
566 .opt_clks = gpio7_opt_clks,
567 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
568 .dev_attr = &gpio_dev_attr,
572 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
573 { .role = "dbclk", .clk = "gpio8_dbclk" },
576 static struct omap_hwmod omap54xx_gpio8_hwmod = {
578 .class = &omap54xx_gpio_hwmod_class,
579 .clkdm_name = "l4per_clkdm",
580 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
581 .main_clk = "l4_root_clk_div",
584 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
585 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
586 .modulemode = MODULEMODE_HWCTRL,
589 .opt_clks = gpio8_opt_clks,
590 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
591 .dev_attr = &gpio_dev_attr,
596 * multimaster high-speed i2c controller
599 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
602 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
603 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
604 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
605 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
607 .clockact = CLOCKACT_TEST_ICLK,
608 .sysc_fields = &omap_hwmod_sysc_type1,
611 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
613 .sysc = &omap54xx_i2c_sysc,
614 .reset = &omap_i2c_reset,
615 .rev = OMAP_I2C_IP_VERSION_2,
619 static struct omap_i2c_dev_attr i2c_dev_attr = {
620 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
624 static struct omap_hwmod omap54xx_i2c1_hwmod = {
626 .class = &omap54xx_i2c_hwmod_class,
627 .clkdm_name = "l4per_clkdm",
628 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
629 .main_clk = "func_96m_fclk",
632 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
633 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
634 .modulemode = MODULEMODE_SWCTRL,
637 .dev_attr = &i2c_dev_attr,
641 static struct omap_hwmod omap54xx_i2c2_hwmod = {
643 .class = &omap54xx_i2c_hwmod_class,
644 .clkdm_name = "l4per_clkdm",
645 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
646 .main_clk = "func_96m_fclk",
649 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
650 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
651 .modulemode = MODULEMODE_SWCTRL,
654 .dev_attr = &i2c_dev_attr,
658 static struct omap_hwmod omap54xx_i2c3_hwmod = {
660 .class = &omap54xx_i2c_hwmod_class,
661 .clkdm_name = "l4per_clkdm",
662 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
663 .main_clk = "func_96m_fclk",
666 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
667 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
668 .modulemode = MODULEMODE_SWCTRL,
671 .dev_attr = &i2c_dev_attr,
675 static struct omap_hwmod omap54xx_i2c4_hwmod = {
677 .class = &omap54xx_i2c_hwmod_class,
678 .clkdm_name = "l4per_clkdm",
679 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
680 .main_clk = "func_96m_fclk",
683 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
684 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
685 .modulemode = MODULEMODE_SWCTRL,
688 .dev_attr = &i2c_dev_attr,
692 static struct omap_hwmod omap54xx_i2c5_hwmod = {
694 .class = &omap54xx_i2c_hwmod_class,
695 .clkdm_name = "l4per_clkdm",
696 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
697 .main_clk = "func_96m_fclk",
700 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
701 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
702 .modulemode = MODULEMODE_SWCTRL,
705 .dev_attr = &i2c_dev_attr,
710 * keyboard controller
713 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
716 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
718 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
719 .sysc_fields = &omap_hwmod_sysc_type1,
722 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
724 .sysc = &omap54xx_kbd_sysc,
728 static struct omap_hwmod omap54xx_kbd_hwmod = {
730 .class = &omap54xx_kbd_hwmod_class,
731 .clkdm_name = "wkupaon_clkdm",
732 .main_clk = "sys_32k_ck",
735 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
736 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
737 .modulemode = MODULEMODE_SWCTRL,
744 * mailbox module allowing communication between the on-chip processors using a
745 * queued mailbox-interrupt mechanism.
748 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
751 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
754 .sysc_fields = &omap_hwmod_sysc_type2,
757 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
759 .sysc = &omap54xx_mailbox_sysc,
763 static struct omap_hwmod omap54xx_mailbox_hwmod = {
765 .class = &omap54xx_mailbox_hwmod_class,
766 .clkdm_name = "l4cfg_clkdm",
769 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
770 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
777 * multi channel buffered serial port controller
780 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
782 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
783 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
784 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
785 .sysc_fields = &omap_hwmod_sysc_type1,
788 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
790 .sysc = &omap54xx_mcbsp_sysc,
791 .rev = MCBSP_CONFIG_TYPE4,
795 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
796 { .role = "pad_fck", .clk = "pad_clks_ck" },
797 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
800 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
802 .class = &omap54xx_mcbsp_hwmod_class,
803 .clkdm_name = "abe_clkdm",
804 .main_clk = "mcbsp1_gfclk",
807 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
808 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
809 .modulemode = MODULEMODE_SWCTRL,
812 .opt_clks = mcbsp1_opt_clks,
813 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
817 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
818 { .role = "pad_fck", .clk = "pad_clks_ck" },
819 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
822 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
824 .class = &omap54xx_mcbsp_hwmod_class,
825 .clkdm_name = "abe_clkdm",
826 .main_clk = "mcbsp2_gfclk",
829 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
830 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
831 .modulemode = MODULEMODE_SWCTRL,
834 .opt_clks = mcbsp2_opt_clks,
835 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
839 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
840 { .role = "pad_fck", .clk = "pad_clks_ck" },
841 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
844 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
846 .class = &omap54xx_mcbsp_hwmod_class,
847 .clkdm_name = "abe_clkdm",
848 .main_clk = "mcbsp3_gfclk",
851 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
852 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
853 .modulemode = MODULEMODE_SWCTRL,
856 .opt_clks = mcbsp3_opt_clks,
857 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
862 * multi channel pdm controller (proprietary interface with phoenix power
866 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
869 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
870 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
871 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
873 .sysc_fields = &omap_hwmod_sysc_type2,
876 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
878 .sysc = &omap54xx_mcpdm_sysc,
882 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
884 .class = &omap54xx_mcpdm_hwmod_class,
885 .clkdm_name = "abe_clkdm",
887 * It's suspected that the McPDM requires an off-chip main
888 * functional clock, controlled via I2C. This IP block is
889 * currently reset very early during boot, before I2C is
890 * available, so it doesn't seem that we have any choice in
891 * the kernel other than to avoid resetting it. XXX This is
892 * really a hardware issue workaround: every IP block should
893 * be able to source its main functional clock from either
894 * on-chip or off-chip sources. McPDM seems to be the only
898 .flags = HWMOD_EXT_OPT_MAIN_CLK,
899 .main_clk = "pad_clks_ck",
902 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
903 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
904 .modulemode = MODULEMODE_SWCTRL,
911 * multichannel serial port interface (mcspi) / master/slave synchronous serial
915 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
918 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
919 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
922 .sysc_fields = &omap_hwmod_sysc_type2,
925 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
927 .sysc = &omap54xx_mcspi_sysc,
928 .rev = OMAP4_MCSPI_REV,
932 /* mcspi1 dev_attr */
933 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
937 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
939 .class = &omap54xx_mcspi_hwmod_class,
940 .clkdm_name = "l4per_clkdm",
941 .main_clk = "func_48m_fclk",
944 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
945 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
946 .modulemode = MODULEMODE_SWCTRL,
949 .dev_attr = &mcspi1_dev_attr,
953 /* mcspi2 dev_attr */
954 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
958 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
960 .class = &omap54xx_mcspi_hwmod_class,
961 .clkdm_name = "l4per_clkdm",
962 .main_clk = "func_48m_fclk",
965 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
966 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
970 .dev_attr = &mcspi2_dev_attr,
974 /* mcspi3 dev_attr */
975 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
979 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
981 .class = &omap54xx_mcspi_hwmod_class,
982 .clkdm_name = "l4per_clkdm",
983 .main_clk = "func_48m_fclk",
986 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
987 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
988 .modulemode = MODULEMODE_SWCTRL,
991 .dev_attr = &mcspi3_dev_attr,
995 /* mcspi4 dev_attr */
996 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1000 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1002 .class = &omap54xx_mcspi_hwmod_class,
1003 .clkdm_name = "l4per_clkdm",
1004 .main_clk = "func_48m_fclk",
1007 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1008 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1009 .modulemode = MODULEMODE_SWCTRL,
1012 .dev_attr = &mcspi4_dev_attr,
1017 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1020 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1022 .sysc_offs = 0x0010,
1023 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1024 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1025 SYSC_HAS_SOFTRESET),
1026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1027 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1028 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1029 .sysc_fields = &omap_hwmod_sysc_type2,
1032 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1034 .sysc = &omap54xx_mmc_sysc,
1038 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1039 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1043 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1044 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1047 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1049 .class = &omap54xx_mmc_hwmod_class,
1050 .clkdm_name = "l3init_clkdm",
1051 .main_clk = "mmc1_fclk",
1054 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1055 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1056 .modulemode = MODULEMODE_SWCTRL,
1059 .opt_clks = mmc1_opt_clks,
1060 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1061 .dev_attr = &mmc1_dev_attr,
1065 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1067 .class = &omap54xx_mmc_hwmod_class,
1068 .clkdm_name = "l3init_clkdm",
1069 .main_clk = "mmc2_fclk",
1072 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1073 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1074 .modulemode = MODULEMODE_SWCTRL,
1080 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1082 .class = &omap54xx_mmc_hwmod_class,
1083 .clkdm_name = "l4per_clkdm",
1084 .main_clk = "func_48m_fclk",
1087 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1088 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1089 .modulemode = MODULEMODE_SWCTRL,
1095 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1097 .class = &omap54xx_mmc_hwmod_class,
1098 .clkdm_name = "l4per_clkdm",
1099 .main_clk = "func_48m_fclk",
1102 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1103 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1104 .modulemode = MODULEMODE_SWCTRL,
1110 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1112 .class = &omap54xx_mmc_hwmod_class,
1113 .clkdm_name = "l4per_clkdm",
1114 .main_clk = "func_96m_fclk",
1117 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1118 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1119 .modulemode = MODULEMODE_SWCTRL,
1129 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1134 static struct omap_hwmod omap54xx_mpu_hwmod = {
1136 .class = &omap54xx_mpu_hwmod_class,
1137 .clkdm_name = "mpu_clkdm",
1138 .flags = HWMOD_INIT_NO_IDLE,
1139 .main_clk = "dpll_mpu_m2_ck",
1142 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1143 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1150 * spinlock provides hardware assistance for synchronizing the processes
1151 * running on multiple processors
1154 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1156 .sysc_offs = 0x0010,
1157 .syss_offs = 0x0014,
1158 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1159 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1160 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1161 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1162 .sysc_fields = &omap_hwmod_sysc_type1,
1165 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1167 .sysc = &omap54xx_spinlock_sysc,
1171 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1173 .class = &omap54xx_spinlock_hwmod_class,
1174 .clkdm_name = "l4cfg_clkdm",
1177 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1178 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1185 * bridge to transform ocp interface protocol to scp (serial control port)
1189 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1191 .sysc_offs = 0x0010,
1192 .syss_offs = 0x0014,
1193 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1194 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1195 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1196 .sysc_fields = &omap_hwmod_sysc_type1,
1199 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1201 .sysc = &omap54xx_ocp2scp_sysc,
1205 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1207 .class = &omap54xx_ocp2scp_hwmod_class,
1208 .clkdm_name = "l3init_clkdm",
1209 .main_clk = "l4_root_clk_div",
1212 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1213 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1214 .modulemode = MODULEMODE_HWCTRL,
1221 * general purpose timer module with accurate 1ms tick
1222 * This class contains several variants: ['timer_1ms', 'timer']
1225 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1227 .sysc_offs = 0x0010,
1228 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1229 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1232 .sysc_fields = &omap_hwmod_sysc_type2,
1233 .clockact = CLOCKACT_TEST_ICLK,
1236 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1238 .sysc = &omap54xx_timer_1ms_sysc,
1241 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1243 .sysc_offs = 0x0010,
1244 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1245 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1246 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1248 .sysc_fields = &omap_hwmod_sysc_type2,
1251 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1253 .sysc = &omap54xx_timer_sysc,
1257 static struct omap_hwmod omap54xx_timer1_hwmod = {
1259 .class = &omap54xx_timer_1ms_hwmod_class,
1260 .clkdm_name = "wkupaon_clkdm",
1261 .main_clk = "timer1_gfclk_mux",
1262 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1265 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1266 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1267 .modulemode = MODULEMODE_SWCTRL,
1273 static struct omap_hwmod omap54xx_timer2_hwmod = {
1275 .class = &omap54xx_timer_1ms_hwmod_class,
1276 .clkdm_name = "l4per_clkdm",
1277 .main_clk = "timer2_gfclk_mux",
1278 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1281 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1282 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1283 .modulemode = MODULEMODE_SWCTRL,
1289 static struct omap_hwmod omap54xx_timer3_hwmod = {
1291 .class = &omap54xx_timer_hwmod_class,
1292 .clkdm_name = "l4per_clkdm",
1293 .main_clk = "timer3_gfclk_mux",
1296 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1297 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1298 .modulemode = MODULEMODE_SWCTRL,
1304 static struct omap_hwmod omap54xx_timer4_hwmod = {
1306 .class = &omap54xx_timer_hwmod_class,
1307 .clkdm_name = "l4per_clkdm",
1308 .main_clk = "timer4_gfclk_mux",
1311 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1312 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1313 .modulemode = MODULEMODE_SWCTRL,
1319 static struct omap_hwmod omap54xx_timer5_hwmod = {
1321 .class = &omap54xx_timer_hwmod_class,
1322 .clkdm_name = "abe_clkdm",
1323 .main_clk = "timer5_gfclk_mux",
1326 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1327 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1328 .modulemode = MODULEMODE_SWCTRL,
1334 static struct omap_hwmod omap54xx_timer6_hwmod = {
1336 .class = &omap54xx_timer_hwmod_class,
1337 .clkdm_name = "abe_clkdm",
1338 .main_clk = "timer6_gfclk_mux",
1341 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1342 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1343 .modulemode = MODULEMODE_SWCTRL,
1349 static struct omap_hwmod omap54xx_timer7_hwmod = {
1351 .class = &omap54xx_timer_hwmod_class,
1352 .clkdm_name = "abe_clkdm",
1353 .main_clk = "timer7_gfclk_mux",
1356 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1357 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1358 .modulemode = MODULEMODE_SWCTRL,
1364 static struct omap_hwmod omap54xx_timer8_hwmod = {
1366 .class = &omap54xx_timer_hwmod_class,
1367 .clkdm_name = "abe_clkdm",
1368 .main_clk = "timer8_gfclk_mux",
1371 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1372 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1373 .modulemode = MODULEMODE_SWCTRL,
1379 static struct omap_hwmod omap54xx_timer9_hwmod = {
1381 .class = &omap54xx_timer_hwmod_class,
1382 .clkdm_name = "l4per_clkdm",
1383 .main_clk = "timer9_gfclk_mux",
1386 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1387 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1388 .modulemode = MODULEMODE_SWCTRL,
1394 static struct omap_hwmod omap54xx_timer10_hwmod = {
1396 .class = &omap54xx_timer_1ms_hwmod_class,
1397 .clkdm_name = "l4per_clkdm",
1398 .main_clk = "timer10_gfclk_mux",
1399 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1402 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1403 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1404 .modulemode = MODULEMODE_SWCTRL,
1410 static struct omap_hwmod omap54xx_timer11_hwmod = {
1412 .class = &omap54xx_timer_hwmod_class,
1413 .clkdm_name = "l4per_clkdm",
1414 .main_clk = "timer11_gfclk_mux",
1417 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1418 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1419 .modulemode = MODULEMODE_SWCTRL,
1426 * universal asynchronous receiver/transmitter (uart)
1429 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1431 .sysc_offs = 0x0054,
1432 .syss_offs = 0x0058,
1433 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1434 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1435 SYSS_HAS_RESET_STATUS),
1436 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1438 .sysc_fields = &omap_hwmod_sysc_type1,
1441 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1443 .sysc = &omap54xx_uart_sysc,
1447 static struct omap_hwmod omap54xx_uart1_hwmod = {
1449 .class = &omap54xx_uart_hwmod_class,
1450 .clkdm_name = "l4per_clkdm",
1451 .main_clk = "func_48m_fclk",
1454 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1455 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1456 .modulemode = MODULEMODE_SWCTRL,
1462 static struct omap_hwmod omap54xx_uart2_hwmod = {
1464 .class = &omap54xx_uart_hwmod_class,
1465 .clkdm_name = "l4per_clkdm",
1466 .main_clk = "func_48m_fclk",
1469 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1470 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1471 .modulemode = MODULEMODE_SWCTRL,
1477 static struct omap_hwmod omap54xx_uart3_hwmod = {
1479 .class = &omap54xx_uart_hwmod_class,
1480 .clkdm_name = "l4per_clkdm",
1481 .flags = DEBUG_OMAP4UART3_FLAGS,
1482 .main_clk = "func_48m_fclk",
1485 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1486 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1487 .modulemode = MODULEMODE_SWCTRL,
1493 static struct omap_hwmod omap54xx_uart4_hwmod = {
1495 .class = &omap54xx_uart_hwmod_class,
1496 .clkdm_name = "l4per_clkdm",
1497 .flags = DEBUG_OMAP4UART4_FLAGS,
1498 .main_clk = "func_48m_fclk",
1501 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1502 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1503 .modulemode = MODULEMODE_SWCTRL,
1509 static struct omap_hwmod omap54xx_uart5_hwmod = {
1511 .class = &omap54xx_uart_hwmod_class,
1512 .clkdm_name = "l4per_clkdm",
1513 .main_clk = "func_48m_fclk",
1516 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1517 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1518 .modulemode = MODULEMODE_SWCTRL,
1524 static struct omap_hwmod omap54xx_uart6_hwmod = {
1526 .class = &omap54xx_uart_hwmod_class,
1527 .clkdm_name = "l4per_clkdm",
1528 .main_clk = "func_48m_fclk",
1531 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1532 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1533 .modulemode = MODULEMODE_SWCTRL,
1539 * 'usb_host_hs' class
1540 * high-speed multi-port usb host controller
1543 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1545 .sysc_offs = 0x0010,
1546 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1547 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1548 SYSC_HAS_RESET_STATUS),
1549 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1550 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1551 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1552 .sysc_fields = &omap_hwmod_sysc_type2,
1555 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1556 .name = "usb_host_hs",
1557 .sysc = &omap54xx_usb_host_hs_sysc,
1560 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1561 .name = "usb_host_hs",
1562 .class = &omap54xx_usb_host_hs_hwmod_class,
1563 .clkdm_name = "l3init_clkdm",
1565 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1569 * In the following configuration :
1570 * - USBHOST module is set to smart-idle mode
1571 * - PRCM asserts idle_req to the USBHOST module ( This typically
1572 * happens when the system is going to a low power mode : all ports
1573 * have been suspended, the master part of the USBHOST module has
1574 * entered the standby state, and SW has cut the functional clocks)
1575 * - an USBHOST interrupt occurs before the module is able to answer
1576 * idle_ack, typically a remote wakeup IRQ.
1577 * Then the USB HOST module will enter a deadlock situation where it
1578 * is no more accessible nor functional.
1581 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1585 * Errata: USB host EHCI may stall when entering smart-standby mode
1589 * When the USBHOST module is set to smart-standby mode, and when it is
1590 * ready to enter the standby state (i.e. all ports are suspended and
1591 * all attached devices are in suspend mode), then it can wrongly assert
1592 * the Mstandby signal too early while there are still some residual OCP
1593 * transactions ongoing. If this condition occurs, the internal state
1594 * machine may go to an undefined state and the USB link may be stuck
1595 * upon the next resume.
1598 * Don't use smart standby; use only force standby,
1599 * hence HWMOD_SWSUP_MSTANDBY
1602 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1603 .main_clk = "l3init_60m_fclk",
1606 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1607 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1608 .modulemode = MODULEMODE_SWCTRL,
1614 * 'usb_tll_hs' class
1615 * usb_tll_hs module is the adapter on the usb_host_hs ports
1618 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1620 .sysc_offs = 0x0010,
1621 .syss_offs = 0x0014,
1622 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1623 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1624 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1625 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1626 .sysc_fields = &omap_hwmod_sysc_type1,
1629 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1630 .name = "usb_tll_hs",
1631 .sysc = &omap54xx_usb_tll_hs_sysc,
1634 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1635 .name = "usb_tll_hs",
1636 .class = &omap54xx_usb_tll_hs_hwmod_class,
1637 .clkdm_name = "l3init_clkdm",
1638 .main_clk = "l4_root_clk_div",
1641 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1642 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1643 .modulemode = MODULEMODE_HWCTRL,
1649 * 'usb_otg_ss' class
1650 * 2.0 super speed (usb_otg_ss) controller
1653 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1655 .sysc_offs = 0x0010,
1656 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1657 SYSC_HAS_SIDLEMODE),
1658 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1659 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1660 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1661 .sysc_fields = &omap_hwmod_sysc_type2,
1664 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1665 .name = "usb_otg_ss",
1666 .sysc = &omap54xx_usb_otg_ss_sysc,
1670 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1671 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1674 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1675 .name = "usb_otg_ss",
1676 .class = &omap54xx_usb_otg_ss_hwmod_class,
1677 .clkdm_name = "l3init_clkdm",
1678 .flags = HWMOD_SWSUP_SIDLE,
1679 .main_clk = "dpll_core_h13x2_ck",
1682 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1683 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1684 .modulemode = MODULEMODE_HWCTRL,
1687 .opt_clks = usb_otg_ss_opt_clks,
1688 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1693 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1694 * overflow condition
1697 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1699 .sysc_offs = 0x0010,
1700 .syss_offs = 0x0014,
1701 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1702 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1703 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1705 .sysc_fields = &omap_hwmod_sysc_type1,
1708 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1710 .sysc = &omap54xx_wd_timer_sysc,
1711 .pre_shutdown = &omap2_wd_timer_disable,
1715 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1716 .name = "wd_timer2",
1717 .class = &omap54xx_wd_timer_hwmod_class,
1718 .clkdm_name = "wkupaon_clkdm",
1719 .main_clk = "sys_32k_ck",
1722 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1723 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1724 .modulemode = MODULEMODE_SWCTRL,
1734 /* l3_main_1 -> dmm */
1735 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1736 .master = &omap54xx_l3_main_1_hwmod,
1737 .slave = &omap54xx_dmm_hwmod,
1738 .clk = "l3_iclk_div",
1739 .user = OCP_USER_SDMA,
1742 /* l3_main_3 -> l3_instr */
1743 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1744 .master = &omap54xx_l3_main_3_hwmod,
1745 .slave = &omap54xx_l3_instr_hwmod,
1746 .clk = "l3_iclk_div",
1747 .user = OCP_USER_MPU | OCP_USER_SDMA,
1750 /* l3_main_2 -> l3_main_1 */
1751 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1752 .master = &omap54xx_l3_main_2_hwmod,
1753 .slave = &omap54xx_l3_main_1_hwmod,
1754 .clk = "l3_iclk_div",
1755 .user = OCP_USER_MPU | OCP_USER_SDMA,
1758 /* l4_cfg -> l3_main_1 */
1759 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1760 .master = &omap54xx_l4_cfg_hwmod,
1761 .slave = &omap54xx_l3_main_1_hwmod,
1762 .clk = "l3_iclk_div",
1763 .user = OCP_USER_MPU | OCP_USER_SDMA,
1766 /* mpu -> l3_main_1 */
1767 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1768 .master = &omap54xx_mpu_hwmod,
1769 .slave = &omap54xx_l3_main_1_hwmod,
1770 .clk = "l3_iclk_div",
1771 .user = OCP_USER_MPU,
1774 /* l3_main_1 -> l3_main_2 */
1775 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1776 .master = &omap54xx_l3_main_1_hwmod,
1777 .slave = &omap54xx_l3_main_2_hwmod,
1778 .clk = "l3_iclk_div",
1779 .user = OCP_USER_MPU,
1782 /* l4_cfg -> l3_main_2 */
1783 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1784 .master = &omap54xx_l4_cfg_hwmod,
1785 .slave = &omap54xx_l3_main_2_hwmod,
1786 .clk = "l3_iclk_div",
1787 .user = OCP_USER_MPU | OCP_USER_SDMA,
1790 /* l3_main_1 -> l3_main_3 */
1791 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1792 .master = &omap54xx_l3_main_1_hwmod,
1793 .slave = &omap54xx_l3_main_3_hwmod,
1794 .clk = "l3_iclk_div",
1795 .user = OCP_USER_MPU,
1798 /* l3_main_2 -> l3_main_3 */
1799 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1800 .master = &omap54xx_l3_main_2_hwmod,
1801 .slave = &omap54xx_l3_main_3_hwmod,
1802 .clk = "l3_iclk_div",
1803 .user = OCP_USER_MPU | OCP_USER_SDMA,
1806 /* l4_cfg -> l3_main_3 */
1807 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1808 .master = &omap54xx_l4_cfg_hwmod,
1809 .slave = &omap54xx_l3_main_3_hwmod,
1810 .clk = "l3_iclk_div",
1811 .user = OCP_USER_MPU | OCP_USER_SDMA,
1814 /* l3_main_1 -> l4_abe */
1815 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1816 .master = &omap54xx_l3_main_1_hwmod,
1817 .slave = &omap54xx_l4_abe_hwmod,
1819 .user = OCP_USER_MPU | OCP_USER_SDMA,
1823 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1824 .master = &omap54xx_mpu_hwmod,
1825 .slave = &omap54xx_l4_abe_hwmod,
1827 .user = OCP_USER_MPU | OCP_USER_SDMA,
1830 /* l3_main_1 -> l4_cfg */
1831 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1832 .master = &omap54xx_l3_main_1_hwmod,
1833 .slave = &omap54xx_l4_cfg_hwmod,
1834 .clk = "l4_root_clk_div",
1835 .user = OCP_USER_MPU | OCP_USER_SDMA,
1838 /* l3_main_2 -> l4_per */
1839 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1840 .master = &omap54xx_l3_main_2_hwmod,
1841 .slave = &omap54xx_l4_per_hwmod,
1842 .clk = "l4_root_clk_div",
1843 .user = OCP_USER_MPU | OCP_USER_SDMA,
1846 /* l3_main_1 -> l4_wkup */
1847 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1848 .master = &omap54xx_l3_main_1_hwmod,
1849 .slave = &omap54xx_l4_wkup_hwmod,
1850 .clk = "wkupaon_iclk_mux",
1851 .user = OCP_USER_MPU | OCP_USER_SDMA,
1854 /* mpu -> mpu_private */
1855 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1856 .master = &omap54xx_mpu_hwmod,
1857 .slave = &omap54xx_mpu_private_hwmod,
1858 .clk = "l3_iclk_div",
1859 .user = OCP_USER_MPU | OCP_USER_SDMA,
1862 /* l4_wkup -> counter_32k */
1863 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1864 .master = &omap54xx_l4_wkup_hwmod,
1865 .slave = &omap54xx_counter_32k_hwmod,
1866 .clk = "wkupaon_iclk_mux",
1867 .user = OCP_USER_MPU | OCP_USER_SDMA,
1870 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1872 .pa_start = 0x4a056000,
1873 .pa_end = 0x4a056fff,
1874 .flags = ADDR_TYPE_RT
1879 /* l4_cfg -> dma_system */
1880 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1881 .master = &omap54xx_l4_cfg_hwmod,
1882 .slave = &omap54xx_dma_system_hwmod,
1883 .clk = "l4_root_clk_div",
1884 .addr = omap54xx_dma_system_addrs,
1885 .user = OCP_USER_MPU | OCP_USER_SDMA,
1888 /* l4_abe -> dmic */
1889 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1890 .master = &omap54xx_l4_abe_hwmod,
1891 .slave = &omap54xx_dmic_hwmod,
1893 .user = OCP_USER_MPU,
1897 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1898 .master = &omap54xx_mpu_hwmod,
1899 .slave = &omap54xx_emif1_hwmod,
1900 .clk = "dpll_core_h11x2_ck",
1901 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1906 .master = &omap54xx_mpu_hwmod,
1907 .slave = &omap54xx_emif2_hwmod,
1908 .clk = "dpll_core_h11x2_ck",
1909 .user = OCP_USER_MPU | OCP_USER_SDMA,
1912 /* l4_wkup -> gpio1 */
1913 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1914 .master = &omap54xx_l4_wkup_hwmod,
1915 .slave = &omap54xx_gpio1_hwmod,
1916 .clk = "wkupaon_iclk_mux",
1917 .user = OCP_USER_MPU | OCP_USER_SDMA,
1920 /* l4_per -> gpio2 */
1921 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1922 .master = &omap54xx_l4_per_hwmod,
1923 .slave = &omap54xx_gpio2_hwmod,
1924 .clk = "l4_root_clk_div",
1925 .user = OCP_USER_MPU | OCP_USER_SDMA,
1928 /* l4_per -> gpio3 */
1929 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1930 .master = &omap54xx_l4_per_hwmod,
1931 .slave = &omap54xx_gpio3_hwmod,
1932 .clk = "l4_root_clk_div",
1933 .user = OCP_USER_MPU | OCP_USER_SDMA,
1936 /* l4_per -> gpio4 */
1937 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1938 .master = &omap54xx_l4_per_hwmod,
1939 .slave = &omap54xx_gpio4_hwmod,
1940 .clk = "l4_root_clk_div",
1941 .user = OCP_USER_MPU | OCP_USER_SDMA,
1944 /* l4_per -> gpio5 */
1945 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1946 .master = &omap54xx_l4_per_hwmod,
1947 .slave = &omap54xx_gpio5_hwmod,
1948 .clk = "l4_root_clk_div",
1949 .user = OCP_USER_MPU | OCP_USER_SDMA,
1952 /* l4_per -> gpio6 */
1953 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1954 .master = &omap54xx_l4_per_hwmod,
1955 .slave = &omap54xx_gpio6_hwmod,
1956 .clk = "l4_root_clk_div",
1957 .user = OCP_USER_MPU | OCP_USER_SDMA,
1960 /* l4_per -> gpio7 */
1961 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1962 .master = &omap54xx_l4_per_hwmod,
1963 .slave = &omap54xx_gpio7_hwmod,
1964 .clk = "l4_root_clk_div",
1965 .user = OCP_USER_MPU | OCP_USER_SDMA,
1968 /* l4_per -> gpio8 */
1969 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1970 .master = &omap54xx_l4_per_hwmod,
1971 .slave = &omap54xx_gpio8_hwmod,
1972 .clk = "l4_root_clk_div",
1973 .user = OCP_USER_MPU | OCP_USER_SDMA,
1976 /* l4_per -> i2c1 */
1977 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1978 .master = &omap54xx_l4_per_hwmod,
1979 .slave = &omap54xx_i2c1_hwmod,
1980 .clk = "l4_root_clk_div",
1981 .user = OCP_USER_MPU | OCP_USER_SDMA,
1984 /* l4_per -> i2c2 */
1985 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1986 .master = &omap54xx_l4_per_hwmod,
1987 .slave = &omap54xx_i2c2_hwmod,
1988 .clk = "l4_root_clk_div",
1989 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992 /* l4_per -> i2c3 */
1993 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1994 .master = &omap54xx_l4_per_hwmod,
1995 .slave = &omap54xx_i2c3_hwmod,
1996 .clk = "l4_root_clk_div",
1997 .user = OCP_USER_MPU | OCP_USER_SDMA,
2000 /* l4_per -> i2c4 */
2001 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2002 .master = &omap54xx_l4_per_hwmod,
2003 .slave = &omap54xx_i2c4_hwmod,
2004 .clk = "l4_root_clk_div",
2005 .user = OCP_USER_MPU | OCP_USER_SDMA,
2008 /* l4_per -> i2c5 */
2009 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2010 .master = &omap54xx_l4_per_hwmod,
2011 .slave = &omap54xx_i2c5_hwmod,
2012 .clk = "l4_root_clk_div",
2013 .user = OCP_USER_MPU | OCP_USER_SDMA,
2016 /* l4_wkup -> kbd */
2017 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2018 .master = &omap54xx_l4_wkup_hwmod,
2019 .slave = &omap54xx_kbd_hwmod,
2020 .clk = "wkupaon_iclk_mux",
2021 .user = OCP_USER_MPU | OCP_USER_SDMA,
2024 /* l4_cfg -> mailbox */
2025 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2026 .master = &omap54xx_l4_cfg_hwmod,
2027 .slave = &omap54xx_mailbox_hwmod,
2028 .clk = "l4_root_clk_div",
2029 .user = OCP_USER_MPU | OCP_USER_SDMA,
2032 /* l4_abe -> mcbsp1 */
2033 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2034 .master = &omap54xx_l4_abe_hwmod,
2035 .slave = &omap54xx_mcbsp1_hwmod,
2037 .user = OCP_USER_MPU,
2040 /* l4_abe -> mcbsp2 */
2041 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2042 .master = &omap54xx_l4_abe_hwmod,
2043 .slave = &omap54xx_mcbsp2_hwmod,
2045 .user = OCP_USER_MPU,
2048 /* l4_abe -> mcbsp3 */
2049 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2050 .master = &omap54xx_l4_abe_hwmod,
2051 .slave = &omap54xx_mcbsp3_hwmod,
2053 .user = OCP_USER_MPU,
2056 /* l4_abe -> mcpdm */
2057 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2058 .master = &omap54xx_l4_abe_hwmod,
2059 .slave = &omap54xx_mcpdm_hwmod,
2061 .user = OCP_USER_MPU,
2064 /* l4_per -> mcspi1 */
2065 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2066 .master = &omap54xx_l4_per_hwmod,
2067 .slave = &omap54xx_mcspi1_hwmod,
2068 .clk = "l4_root_clk_div",
2069 .user = OCP_USER_MPU | OCP_USER_SDMA,
2072 /* l4_per -> mcspi2 */
2073 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2074 .master = &omap54xx_l4_per_hwmod,
2075 .slave = &omap54xx_mcspi2_hwmod,
2076 .clk = "l4_root_clk_div",
2077 .user = OCP_USER_MPU | OCP_USER_SDMA,
2080 /* l4_per -> mcspi3 */
2081 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2082 .master = &omap54xx_l4_per_hwmod,
2083 .slave = &omap54xx_mcspi3_hwmod,
2084 .clk = "l4_root_clk_div",
2085 .user = OCP_USER_MPU | OCP_USER_SDMA,
2088 /* l4_per -> mcspi4 */
2089 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2090 .master = &omap54xx_l4_per_hwmod,
2091 .slave = &omap54xx_mcspi4_hwmod,
2092 .clk = "l4_root_clk_div",
2093 .user = OCP_USER_MPU | OCP_USER_SDMA,
2096 /* l4_per -> mmc1 */
2097 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2098 .master = &omap54xx_l4_per_hwmod,
2099 .slave = &omap54xx_mmc1_hwmod,
2100 .clk = "l3_iclk_div",
2101 .user = OCP_USER_MPU | OCP_USER_SDMA,
2104 /* l4_per -> mmc2 */
2105 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2106 .master = &omap54xx_l4_per_hwmod,
2107 .slave = &omap54xx_mmc2_hwmod,
2108 .clk = "l3_iclk_div",
2109 .user = OCP_USER_MPU | OCP_USER_SDMA,
2112 /* l4_per -> mmc3 */
2113 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2114 .master = &omap54xx_l4_per_hwmod,
2115 .slave = &omap54xx_mmc3_hwmod,
2116 .clk = "l4_root_clk_div",
2117 .user = OCP_USER_MPU | OCP_USER_SDMA,
2120 /* l4_per -> mmc4 */
2121 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2122 .master = &omap54xx_l4_per_hwmod,
2123 .slave = &omap54xx_mmc4_hwmod,
2124 .clk = "l4_root_clk_div",
2125 .user = OCP_USER_MPU | OCP_USER_SDMA,
2128 /* l4_per -> mmc5 */
2129 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2130 .master = &omap54xx_l4_per_hwmod,
2131 .slave = &omap54xx_mmc5_hwmod,
2132 .clk = "l4_root_clk_div",
2133 .user = OCP_USER_MPU | OCP_USER_SDMA,
2137 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2138 .master = &omap54xx_l4_cfg_hwmod,
2139 .slave = &omap54xx_mpu_hwmod,
2140 .clk = "l4_root_clk_div",
2141 .user = OCP_USER_MPU | OCP_USER_SDMA,
2144 /* l4_cfg -> spinlock */
2145 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2146 .master = &omap54xx_l4_cfg_hwmod,
2147 .slave = &omap54xx_spinlock_hwmod,
2148 .clk = "l4_root_clk_div",
2149 .user = OCP_USER_MPU | OCP_USER_SDMA,
2152 /* l4_cfg -> ocp2scp1 */
2153 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2154 .master = &omap54xx_l4_cfg_hwmod,
2155 .slave = &omap54xx_ocp2scp1_hwmod,
2156 .clk = "l4_root_clk_div",
2157 .user = OCP_USER_MPU | OCP_USER_SDMA,
2160 /* l4_wkup -> timer1 */
2161 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2162 .master = &omap54xx_l4_wkup_hwmod,
2163 .slave = &omap54xx_timer1_hwmod,
2164 .clk = "wkupaon_iclk_mux",
2165 .user = OCP_USER_MPU | OCP_USER_SDMA,
2168 /* l4_per -> timer2 */
2169 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2170 .master = &omap54xx_l4_per_hwmod,
2171 .slave = &omap54xx_timer2_hwmod,
2172 .clk = "l4_root_clk_div",
2173 .user = OCP_USER_MPU | OCP_USER_SDMA,
2176 /* l4_per -> timer3 */
2177 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2178 .master = &omap54xx_l4_per_hwmod,
2179 .slave = &omap54xx_timer3_hwmod,
2180 .clk = "l4_root_clk_div",
2181 .user = OCP_USER_MPU | OCP_USER_SDMA,
2184 /* l4_per -> timer4 */
2185 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2186 .master = &omap54xx_l4_per_hwmod,
2187 .slave = &omap54xx_timer4_hwmod,
2188 .clk = "l4_root_clk_div",
2189 .user = OCP_USER_MPU | OCP_USER_SDMA,
2192 /* l4_abe -> timer5 */
2193 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2194 .master = &omap54xx_l4_abe_hwmod,
2195 .slave = &omap54xx_timer5_hwmod,
2197 .user = OCP_USER_MPU,
2200 /* l4_abe -> timer6 */
2201 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2202 .master = &omap54xx_l4_abe_hwmod,
2203 .slave = &omap54xx_timer6_hwmod,
2205 .user = OCP_USER_MPU,
2208 /* l4_abe -> timer7 */
2209 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2210 .master = &omap54xx_l4_abe_hwmod,
2211 .slave = &omap54xx_timer7_hwmod,
2213 .user = OCP_USER_MPU,
2216 /* l4_abe -> timer8 */
2217 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2218 .master = &omap54xx_l4_abe_hwmod,
2219 .slave = &omap54xx_timer8_hwmod,
2221 .user = OCP_USER_MPU,
2224 /* l4_per -> timer9 */
2225 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2226 .master = &omap54xx_l4_per_hwmod,
2227 .slave = &omap54xx_timer9_hwmod,
2228 .clk = "l4_root_clk_div",
2229 .user = OCP_USER_MPU | OCP_USER_SDMA,
2232 /* l4_per -> timer10 */
2233 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2234 .master = &omap54xx_l4_per_hwmod,
2235 .slave = &omap54xx_timer10_hwmod,
2236 .clk = "l4_root_clk_div",
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240 /* l4_per -> timer11 */
2241 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2242 .master = &omap54xx_l4_per_hwmod,
2243 .slave = &omap54xx_timer11_hwmod,
2244 .clk = "l4_root_clk_div",
2245 .user = OCP_USER_MPU | OCP_USER_SDMA,
2248 /* l4_per -> uart1 */
2249 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2250 .master = &omap54xx_l4_per_hwmod,
2251 .slave = &omap54xx_uart1_hwmod,
2252 .clk = "l4_root_clk_div",
2253 .user = OCP_USER_MPU | OCP_USER_SDMA,
2256 /* l4_per -> uart2 */
2257 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2258 .master = &omap54xx_l4_per_hwmod,
2259 .slave = &omap54xx_uart2_hwmod,
2260 .clk = "l4_root_clk_div",
2261 .user = OCP_USER_MPU | OCP_USER_SDMA,
2264 /* l4_per -> uart3 */
2265 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2266 .master = &omap54xx_l4_per_hwmod,
2267 .slave = &omap54xx_uart3_hwmod,
2268 .clk = "l4_root_clk_div",
2269 .user = OCP_USER_MPU | OCP_USER_SDMA,
2272 /* l4_per -> uart4 */
2273 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2274 .master = &omap54xx_l4_per_hwmod,
2275 .slave = &omap54xx_uart4_hwmod,
2276 .clk = "l4_root_clk_div",
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280 /* l4_per -> uart5 */
2281 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2282 .master = &omap54xx_l4_per_hwmod,
2283 .slave = &omap54xx_uart5_hwmod,
2284 .clk = "l4_root_clk_div",
2285 .user = OCP_USER_MPU | OCP_USER_SDMA,
2288 /* l4_per -> uart6 */
2289 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2290 .master = &omap54xx_l4_per_hwmod,
2291 .slave = &omap54xx_uart6_hwmod,
2292 .clk = "l4_root_clk_div",
2293 .user = OCP_USER_MPU | OCP_USER_SDMA,
2296 /* l4_cfg -> usb_host_hs */
2297 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2298 .master = &omap54xx_l4_cfg_hwmod,
2299 .slave = &omap54xx_usb_host_hs_hwmod,
2300 .clk = "l3_iclk_div",
2301 .user = OCP_USER_MPU | OCP_USER_SDMA,
2304 /* l4_cfg -> usb_tll_hs */
2305 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2306 .master = &omap54xx_l4_cfg_hwmod,
2307 .slave = &omap54xx_usb_tll_hs_hwmod,
2308 .clk = "l4_root_clk_div",
2309 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312 /* l4_cfg -> usb_otg_ss */
2313 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2314 .master = &omap54xx_l4_cfg_hwmod,
2315 .slave = &omap54xx_usb_otg_ss_hwmod,
2316 .clk = "dpll_core_h13x2_ck",
2317 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320 /* l4_wkup -> wd_timer2 */
2321 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2322 .master = &omap54xx_l4_wkup_hwmod,
2323 .slave = &omap54xx_wd_timer2_hwmod,
2324 .clk = "wkupaon_iclk_mux",
2325 .user = OCP_USER_MPU | OCP_USER_SDMA,
2328 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2329 &omap54xx_l3_main_1__dmm,
2330 &omap54xx_l3_main_3__l3_instr,
2331 &omap54xx_l3_main_2__l3_main_1,
2332 &omap54xx_l4_cfg__l3_main_1,
2333 &omap54xx_mpu__l3_main_1,
2334 &omap54xx_l3_main_1__l3_main_2,
2335 &omap54xx_l4_cfg__l3_main_2,
2336 &omap54xx_l3_main_1__l3_main_3,
2337 &omap54xx_l3_main_2__l3_main_3,
2338 &omap54xx_l4_cfg__l3_main_3,
2339 &omap54xx_l3_main_1__l4_abe,
2340 &omap54xx_mpu__l4_abe,
2341 &omap54xx_l3_main_1__l4_cfg,
2342 &omap54xx_l3_main_2__l4_per,
2343 &omap54xx_l3_main_1__l4_wkup,
2344 &omap54xx_mpu__mpu_private,
2345 &omap54xx_l4_wkup__counter_32k,
2346 &omap54xx_l4_cfg__dma_system,
2347 &omap54xx_l4_abe__dmic,
2348 &omap54xx_mpu__emif1,
2349 &omap54xx_mpu__emif2,
2350 &omap54xx_l4_wkup__gpio1,
2351 &omap54xx_l4_per__gpio2,
2352 &omap54xx_l4_per__gpio3,
2353 &omap54xx_l4_per__gpio4,
2354 &omap54xx_l4_per__gpio5,
2355 &omap54xx_l4_per__gpio6,
2356 &omap54xx_l4_per__gpio7,
2357 &omap54xx_l4_per__gpio8,
2358 &omap54xx_l4_per__i2c1,
2359 &omap54xx_l4_per__i2c2,
2360 &omap54xx_l4_per__i2c3,
2361 &omap54xx_l4_per__i2c4,
2362 &omap54xx_l4_per__i2c5,
2363 &omap54xx_l4_wkup__kbd,
2364 &omap54xx_l4_cfg__mailbox,
2365 &omap54xx_l4_abe__mcbsp1,
2366 &omap54xx_l4_abe__mcbsp2,
2367 &omap54xx_l4_abe__mcbsp3,
2368 &omap54xx_l4_abe__mcpdm,
2369 &omap54xx_l4_per__mcspi1,
2370 &omap54xx_l4_per__mcspi2,
2371 &omap54xx_l4_per__mcspi3,
2372 &omap54xx_l4_per__mcspi4,
2373 &omap54xx_l4_per__mmc1,
2374 &omap54xx_l4_per__mmc2,
2375 &omap54xx_l4_per__mmc3,
2376 &omap54xx_l4_per__mmc4,
2377 &omap54xx_l4_per__mmc5,
2378 &omap54xx_l4_cfg__mpu,
2379 &omap54xx_l4_cfg__spinlock,
2380 &omap54xx_l4_cfg__ocp2scp1,
2381 &omap54xx_l4_wkup__timer1,
2382 &omap54xx_l4_per__timer2,
2383 &omap54xx_l4_per__timer3,
2384 &omap54xx_l4_per__timer4,
2385 &omap54xx_l4_abe__timer5,
2386 &omap54xx_l4_abe__timer6,
2387 &omap54xx_l4_abe__timer7,
2388 &omap54xx_l4_abe__timer8,
2389 &omap54xx_l4_per__timer9,
2390 &omap54xx_l4_per__timer10,
2391 &omap54xx_l4_per__timer11,
2392 &omap54xx_l4_per__uart1,
2393 &omap54xx_l4_per__uart2,
2394 &omap54xx_l4_per__uart3,
2395 &omap54xx_l4_per__uart4,
2396 &omap54xx_l4_per__uart5,
2397 &omap54xx_l4_per__uart6,
2398 &omap54xx_l4_cfg__usb_host_hs,
2399 &omap54xx_l4_cfg__usb_tll_hs,
2400 &omap54xx_l4_cfg__usb_otg_ss,
2401 &omap54xx_l4_wkup__wd_timer2,
2405 int __init omap54xx_hwmod_init(void)
2408 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);