2 * Hardware modules present on the OMAP54xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
39 /* Base offset for all OMAP5 interrupts external to MPUSS */
40 #define OMAP54XX_IRQ_GIC_START 32
42 /* Base offset for all OMAP5 dma requests */
43 #define OMAP54XX_DMA_REQ_START 1
54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
59 static struct omap_hwmod omap54xx_dmm_hwmod = {
61 .class = &omap54xx_dmm_hwmod_class,
62 .clkdm_name = "emif_clkdm",
65 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
66 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
73 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
75 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
80 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
82 .class = &omap54xx_l3_hwmod_class,
83 .clkdm_name = "l3instr_clkdm",
86 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
87 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
88 .modulemode = MODULEMODE_HWCTRL,
94 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
96 .class = &omap54xx_l3_hwmod_class,
97 .clkdm_name = "l3main1_clkdm",
100 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
101 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
107 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
109 .class = &omap54xx_l3_hwmod_class,
110 .clkdm_name = "l3main2_clkdm",
113 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
114 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
120 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
122 .class = &omap54xx_l3_hwmod_class,
123 .clkdm_name = "l3instr_clkdm",
126 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
127 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
128 .modulemode = MODULEMODE_HWCTRL,
135 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
137 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
142 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
144 .class = &omap54xx_l4_hwmod_class,
145 .clkdm_name = "abe_clkdm",
148 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
149 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
157 .class = &omap54xx_l4_hwmod_class,
158 .clkdm_name = "l4cfg_clkdm",
161 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
162 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
168 static struct omap_hwmod omap54xx_l4_per_hwmod = {
170 .class = &omap54xx_l4_hwmod_class,
171 .clkdm_name = "l4per_clkdm",
174 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
175 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
181 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
183 .class = &omap54xx_l4_hwmod_class,
184 .clkdm_name = "wkupaon_clkdm",
187 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
188 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
195 * instance(s): mpu_private
197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
202 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
203 .name = "mpu_private",
204 .class = &omap54xx_mpu_bus_hwmod_class,
205 .clkdm_name = "mpu_clkdm",
208 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
215 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
221 .sysc_flags = SYSC_HAS_SIDLEMODE,
222 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
223 .sysc_fields = &omap_hwmod_sysc_type1,
226 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
228 .sysc = &omap54xx_counter_sysc,
232 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
233 .name = "counter_32k",
234 .class = &omap54xx_counter_hwmod_class,
235 .clkdm_name = "wkupaon_clkdm",
236 .flags = HWMOD_SWSUP_SIDLE,
237 .main_clk = "wkupaon_iclk_mux",
240 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
241 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
248 * dma controller for data exchange between memory to memory (i.e. internal or
249 * external memory) and gp peripherals to memory or memory to gp peripherals
252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
256 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
257 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
258 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
259 SYSS_HAS_RESET_STATUS),
260 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
261 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
262 .sysc_fields = &omap_hwmod_sysc_type1,
265 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
267 .sysc = &omap54xx_dma_sysc,
271 static struct omap_dma_dev_attr dma_dev_attr = {
272 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
273 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
279 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
280 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
281 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
282 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
286 static struct omap_hwmod omap54xx_dma_system_hwmod = {
287 .name = "dma_system",
288 .class = &omap54xx_dma_hwmod_class,
289 .clkdm_name = "dma_clkdm",
290 .mpu_irqs = omap54xx_dma_system_irqs,
291 .main_clk = "l3_iclk_div",
294 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
295 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
298 .dev_attr = &dma_dev_attr,
303 * digital microphone controller
306 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
309 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
310 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
313 .sysc_fields = &omap_hwmod_sysc_type2,
316 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
318 .sysc = &omap54xx_dmic_sysc,
322 static struct omap_hwmod omap54xx_dmic_hwmod = {
324 .class = &omap54xx_dmic_hwmod_class,
325 .clkdm_name = "abe_clkdm",
326 .main_clk = "dmic_gfclk",
329 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
330 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
331 .modulemode = MODULEMODE_SWCTRL,
338 * external memory interface no1 (wrapper)
341 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
345 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
347 .sysc = &omap54xx_emif_sysc,
351 static struct omap_hwmod omap54xx_emif1_hwmod = {
353 .class = &omap54xx_emif_hwmod_class,
354 .clkdm_name = "emif_clkdm",
355 .flags = HWMOD_INIT_NO_IDLE,
356 .main_clk = "dpll_core_h11x2_ck",
359 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
360 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
367 static struct omap_hwmod omap54xx_emif2_hwmod = {
369 .class = &omap54xx_emif_hwmod_class,
370 .clkdm_name = "emif_clkdm",
371 .flags = HWMOD_INIT_NO_IDLE,
372 .main_clk = "dpll_core_h11x2_ck",
375 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
376 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
377 .modulemode = MODULEMODE_HWCTRL,
384 * general purpose io module
387 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
391 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
392 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
393 SYSS_HAS_RESET_STATUS),
394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
396 .sysc_fields = &omap_hwmod_sysc_type1,
399 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
401 .sysc = &omap54xx_gpio_sysc,
406 static struct omap_gpio_dev_attr gpio_dev_attr = {
412 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
413 { .role = "dbclk", .clk = "gpio1_dbclk" },
416 static struct omap_hwmod omap54xx_gpio1_hwmod = {
418 .class = &omap54xx_gpio_hwmod_class,
419 .clkdm_name = "wkupaon_clkdm",
420 .main_clk = "wkupaon_iclk_mux",
423 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
424 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
425 .modulemode = MODULEMODE_HWCTRL,
428 .opt_clks = gpio1_opt_clks,
429 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
430 .dev_attr = &gpio_dev_attr,
434 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
435 { .role = "dbclk", .clk = "gpio2_dbclk" },
438 static struct omap_hwmod omap54xx_gpio2_hwmod = {
440 .class = &omap54xx_gpio_hwmod_class,
441 .clkdm_name = "l4per_clkdm",
442 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
443 .main_clk = "l4_root_clk_div",
446 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
447 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
448 .modulemode = MODULEMODE_HWCTRL,
451 .opt_clks = gpio2_opt_clks,
452 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
453 .dev_attr = &gpio_dev_attr,
457 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
458 { .role = "dbclk", .clk = "gpio3_dbclk" },
461 static struct omap_hwmod omap54xx_gpio3_hwmod = {
463 .class = &omap54xx_gpio_hwmod_class,
464 .clkdm_name = "l4per_clkdm",
465 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
466 .main_clk = "l4_root_clk_div",
469 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
470 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
471 .modulemode = MODULEMODE_HWCTRL,
474 .opt_clks = gpio3_opt_clks,
475 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
476 .dev_attr = &gpio_dev_attr,
480 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
481 { .role = "dbclk", .clk = "gpio4_dbclk" },
484 static struct omap_hwmod omap54xx_gpio4_hwmod = {
486 .class = &omap54xx_gpio_hwmod_class,
487 .clkdm_name = "l4per_clkdm",
488 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
489 .main_clk = "l4_root_clk_div",
492 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
493 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
494 .modulemode = MODULEMODE_HWCTRL,
497 .opt_clks = gpio4_opt_clks,
498 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
499 .dev_attr = &gpio_dev_attr,
503 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
504 { .role = "dbclk", .clk = "gpio5_dbclk" },
507 static struct omap_hwmod omap54xx_gpio5_hwmod = {
509 .class = &omap54xx_gpio_hwmod_class,
510 .clkdm_name = "l4per_clkdm",
511 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512 .main_clk = "l4_root_clk_div",
515 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
516 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
517 .modulemode = MODULEMODE_HWCTRL,
520 .opt_clks = gpio5_opt_clks,
521 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
522 .dev_attr = &gpio_dev_attr,
526 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
527 { .role = "dbclk", .clk = "gpio6_dbclk" },
530 static struct omap_hwmod omap54xx_gpio6_hwmod = {
532 .class = &omap54xx_gpio_hwmod_class,
533 .clkdm_name = "l4per_clkdm",
534 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
535 .main_clk = "l4_root_clk_div",
538 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
539 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
540 .modulemode = MODULEMODE_HWCTRL,
543 .opt_clks = gpio6_opt_clks,
544 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
545 .dev_attr = &gpio_dev_attr,
549 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
550 { .role = "dbclk", .clk = "gpio7_dbclk" },
553 static struct omap_hwmod omap54xx_gpio7_hwmod = {
555 .class = &omap54xx_gpio_hwmod_class,
556 .clkdm_name = "l4per_clkdm",
557 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
558 .main_clk = "l4_root_clk_div",
561 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
562 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
563 .modulemode = MODULEMODE_HWCTRL,
566 .opt_clks = gpio7_opt_clks,
567 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
568 .dev_attr = &gpio_dev_attr,
572 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
573 { .role = "dbclk", .clk = "gpio8_dbclk" },
576 static struct omap_hwmod omap54xx_gpio8_hwmod = {
578 .class = &omap54xx_gpio_hwmod_class,
579 .clkdm_name = "l4per_clkdm",
580 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
581 .main_clk = "l4_root_clk_div",
584 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
585 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
586 .modulemode = MODULEMODE_HWCTRL,
589 .opt_clks = gpio8_opt_clks,
590 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
591 .dev_attr = &gpio_dev_attr,
596 * multimaster high-speed i2c controller
599 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
602 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
603 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
604 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
605 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
607 .clockact = CLOCKACT_TEST_ICLK,
608 .sysc_fields = &omap_hwmod_sysc_type1,
611 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
613 .sysc = &omap54xx_i2c_sysc,
614 .reset = &omap_i2c_reset,
615 .rev = OMAP_I2C_IP_VERSION_2,
619 static struct omap_i2c_dev_attr i2c_dev_attr = {
620 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
624 static struct omap_hwmod omap54xx_i2c1_hwmod = {
626 .class = &omap54xx_i2c_hwmod_class,
627 .clkdm_name = "l4per_clkdm",
628 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
629 .main_clk = "func_96m_fclk",
632 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
633 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
634 .modulemode = MODULEMODE_SWCTRL,
637 .dev_attr = &i2c_dev_attr,
641 static struct omap_hwmod omap54xx_i2c2_hwmod = {
643 .class = &omap54xx_i2c_hwmod_class,
644 .clkdm_name = "l4per_clkdm",
645 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
646 .main_clk = "func_96m_fclk",
649 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
650 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
651 .modulemode = MODULEMODE_SWCTRL,
654 .dev_attr = &i2c_dev_attr,
658 static struct omap_hwmod omap54xx_i2c3_hwmod = {
660 .class = &omap54xx_i2c_hwmod_class,
661 .clkdm_name = "l4per_clkdm",
662 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
663 .main_clk = "func_96m_fclk",
666 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
667 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
668 .modulemode = MODULEMODE_SWCTRL,
671 .dev_attr = &i2c_dev_attr,
675 static struct omap_hwmod omap54xx_i2c4_hwmod = {
677 .class = &omap54xx_i2c_hwmod_class,
678 .clkdm_name = "l4per_clkdm",
679 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
680 .main_clk = "func_96m_fclk",
683 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
684 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
685 .modulemode = MODULEMODE_SWCTRL,
688 .dev_attr = &i2c_dev_attr,
692 static struct omap_hwmod omap54xx_i2c5_hwmod = {
694 .class = &omap54xx_i2c_hwmod_class,
695 .clkdm_name = "l4per_clkdm",
696 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
697 .main_clk = "func_96m_fclk",
700 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
701 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
702 .modulemode = MODULEMODE_SWCTRL,
705 .dev_attr = &i2c_dev_attr,
710 * keyboard controller
713 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
716 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
718 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
719 .sysc_fields = &omap_hwmod_sysc_type1,
722 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
724 .sysc = &omap54xx_kbd_sysc,
728 static struct omap_hwmod omap54xx_kbd_hwmod = {
730 .class = &omap54xx_kbd_hwmod_class,
731 .clkdm_name = "wkupaon_clkdm",
732 .main_clk = "sys_32k_ck",
735 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
736 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
737 .modulemode = MODULEMODE_SWCTRL,
744 * mailbox module allowing communication between the on-chip processors using a
745 * queued mailbox-interrupt mechanism.
748 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
751 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
754 .sysc_fields = &omap_hwmod_sysc_type2,
757 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
759 .sysc = &omap54xx_mailbox_sysc,
763 static struct omap_hwmod omap54xx_mailbox_hwmod = {
765 .class = &omap54xx_mailbox_hwmod_class,
766 .clkdm_name = "l4cfg_clkdm",
769 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
770 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
777 * multi channel buffered serial port controller
780 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
782 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
783 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
784 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
785 .sysc_fields = &omap_hwmod_sysc_type1,
788 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
790 .sysc = &omap54xx_mcbsp_sysc,
791 .rev = MCBSP_CONFIG_TYPE4,
795 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
796 { .role = "pad_fck", .clk = "pad_clks_ck" },
797 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
800 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
802 .class = &omap54xx_mcbsp_hwmod_class,
803 .clkdm_name = "abe_clkdm",
804 .main_clk = "mcbsp1_gfclk",
807 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
808 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
809 .modulemode = MODULEMODE_SWCTRL,
812 .opt_clks = mcbsp1_opt_clks,
813 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
817 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
818 { .role = "pad_fck", .clk = "pad_clks_ck" },
819 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
822 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
824 .class = &omap54xx_mcbsp_hwmod_class,
825 .clkdm_name = "abe_clkdm",
826 .main_clk = "mcbsp2_gfclk",
829 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
830 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
831 .modulemode = MODULEMODE_SWCTRL,
834 .opt_clks = mcbsp2_opt_clks,
835 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
839 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
840 { .role = "pad_fck", .clk = "pad_clks_ck" },
841 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
844 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
846 .class = &omap54xx_mcbsp_hwmod_class,
847 .clkdm_name = "abe_clkdm",
848 .main_clk = "mcbsp3_gfclk",
851 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
852 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
853 .modulemode = MODULEMODE_SWCTRL,
856 .opt_clks = mcbsp3_opt_clks,
857 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
862 * multi channel pdm controller (proprietary interface with phoenix power
866 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
869 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
870 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
871 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
873 .sysc_fields = &omap_hwmod_sysc_type2,
876 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
878 .sysc = &omap54xx_mcpdm_sysc,
882 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
884 .class = &omap54xx_mcpdm_hwmod_class,
885 .clkdm_name = "abe_clkdm",
887 * It's suspected that the McPDM requires an off-chip main
888 * functional clock, controlled via I2C. This IP block is
889 * currently reset very early during boot, before I2C is
890 * available, so it doesn't seem that we have any choice in
891 * the kernel other than to avoid resetting it. XXX This is
892 * really a hardware issue workaround: every IP block should
893 * be able to source its main functional clock from either
894 * on-chip or off-chip sources. McPDM seems to be the only
898 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
899 .main_clk = "pad_clks_ck",
902 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
903 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
904 .modulemode = MODULEMODE_SWCTRL,
911 * multichannel serial port interface (mcspi) / master/slave synchronous serial
915 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
918 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
919 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
922 .sysc_fields = &omap_hwmod_sysc_type2,
925 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
927 .sysc = &omap54xx_mcspi_sysc,
928 .rev = OMAP4_MCSPI_REV,
932 /* mcspi1 dev_attr */
933 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
937 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
939 .class = &omap54xx_mcspi_hwmod_class,
940 .clkdm_name = "l4per_clkdm",
941 .main_clk = "func_48m_fclk",
944 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
945 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
946 .modulemode = MODULEMODE_SWCTRL,
949 .dev_attr = &mcspi1_dev_attr,
953 /* mcspi2 dev_attr */
954 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
958 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
960 .class = &omap54xx_mcspi_hwmod_class,
961 .clkdm_name = "l4per_clkdm",
962 .main_clk = "func_48m_fclk",
965 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
966 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
970 .dev_attr = &mcspi2_dev_attr,
974 /* mcspi3 dev_attr */
975 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
979 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
981 .class = &omap54xx_mcspi_hwmod_class,
982 .clkdm_name = "l4per_clkdm",
983 .main_clk = "func_48m_fclk",
986 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
987 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
988 .modulemode = MODULEMODE_SWCTRL,
991 .dev_attr = &mcspi3_dev_attr,
995 /* mcspi4 dev_attr */
996 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1000 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1002 .class = &omap54xx_mcspi_hwmod_class,
1003 .clkdm_name = "l4per_clkdm",
1004 .main_clk = "func_48m_fclk",
1007 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1008 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1009 .modulemode = MODULEMODE_SWCTRL,
1012 .dev_attr = &mcspi4_dev_attr,
1017 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1020 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1022 .sysc_offs = 0x0010,
1023 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1024 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1025 SYSC_HAS_SOFTRESET),
1026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1027 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1028 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1029 .sysc_fields = &omap_hwmod_sysc_type2,
1032 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1034 .sysc = &omap54xx_mmc_sysc,
1038 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1039 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1043 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1044 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1047 static struct omap_hwmod omap54xx_mmc1_hwmod = {
1049 .class = &omap54xx_mmc_hwmod_class,
1050 .clkdm_name = "l3init_clkdm",
1051 .main_clk = "mmc1_fclk",
1054 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1055 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1056 .modulemode = MODULEMODE_SWCTRL,
1059 .opt_clks = mmc1_opt_clks,
1060 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1061 .dev_attr = &mmc1_dev_attr,
1065 static struct omap_hwmod omap54xx_mmc2_hwmod = {
1067 .class = &omap54xx_mmc_hwmod_class,
1068 .clkdm_name = "l3init_clkdm",
1069 .main_clk = "mmc2_fclk",
1072 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1073 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1074 .modulemode = MODULEMODE_SWCTRL,
1080 static struct omap_hwmod omap54xx_mmc3_hwmod = {
1082 .class = &omap54xx_mmc_hwmod_class,
1083 .clkdm_name = "l4per_clkdm",
1084 .main_clk = "func_48m_fclk",
1087 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1088 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1089 .modulemode = MODULEMODE_SWCTRL,
1095 static struct omap_hwmod omap54xx_mmc4_hwmod = {
1097 .class = &omap54xx_mmc_hwmod_class,
1098 .clkdm_name = "l4per_clkdm",
1099 .main_clk = "func_48m_fclk",
1102 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1103 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1104 .modulemode = MODULEMODE_SWCTRL,
1110 static struct omap_hwmod omap54xx_mmc5_hwmod = {
1112 .class = &omap54xx_mmc_hwmod_class,
1113 .clkdm_name = "l4per_clkdm",
1114 .main_clk = "func_96m_fclk",
1117 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1118 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1119 .modulemode = MODULEMODE_SWCTRL,
1126 * The memory management unit performs virtual to physical address translation
1127 * for its requestors.
1130 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
1132 .sysc_offs = 0x0010,
1133 .syss_offs = 0x0014,
1134 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1135 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1136 SYSS_HAS_RESET_STATUS),
1137 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1138 .sysc_fields = &omap_hwmod_sysc_type1,
1141 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
1143 .sysc = &omap54xx_mmu_sysc,
1146 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
1147 { .name = "mmu_cache", .rst_shift = 1 },
1150 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
1152 .class = &omap54xx_mmu_hwmod_class,
1153 .clkdm_name = "dsp_clkdm",
1154 .rst_lines = omap54xx_mmu_dsp_resets,
1155 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
1156 .main_clk = "dpll_iva_h11x2_ck",
1159 .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
1160 .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
1161 .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
1162 .modulemode = MODULEMODE_HWCTRL,
1168 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
1169 { .name = "mmu_cache", .rst_shift = 2 },
1172 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
1174 .class = &omap54xx_mmu_hwmod_class,
1175 .clkdm_name = "ipu_clkdm",
1176 .rst_lines = omap54xx_mmu_ipu_resets,
1177 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
1178 .main_clk = "dpll_core_h22x2_ck",
1181 .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1182 .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1183 .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1184 .modulemode = MODULEMODE_HWCTRL,
1194 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1199 static struct omap_hwmod omap54xx_mpu_hwmod = {
1201 .class = &omap54xx_mpu_hwmod_class,
1202 .clkdm_name = "mpu_clkdm",
1203 .flags = HWMOD_INIT_NO_IDLE,
1204 .main_clk = "dpll_mpu_m2_ck",
1207 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1208 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1215 * spinlock provides hardware assistance for synchronizing the processes
1216 * running on multiple processors
1219 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1221 .sysc_offs = 0x0010,
1222 .syss_offs = 0x0014,
1223 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1224 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1225 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1227 .sysc_fields = &omap_hwmod_sysc_type1,
1230 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1232 .sysc = &omap54xx_spinlock_sysc,
1236 static struct omap_hwmod omap54xx_spinlock_hwmod = {
1238 .class = &omap54xx_spinlock_hwmod_class,
1239 .clkdm_name = "l4cfg_clkdm",
1242 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1243 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1250 * bridge to transform ocp interface protocol to scp (serial control port)
1254 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1256 .sysc_offs = 0x0010,
1257 .syss_offs = 0x0014,
1258 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1259 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1260 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1261 .sysc_fields = &omap_hwmod_sysc_type1,
1264 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1266 .sysc = &omap54xx_ocp2scp_sysc,
1270 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1272 .class = &omap54xx_ocp2scp_hwmod_class,
1273 .clkdm_name = "l3init_clkdm",
1274 .main_clk = "l4_root_clk_div",
1277 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1278 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1279 .modulemode = MODULEMODE_HWCTRL,
1286 * general purpose timer module with accurate 1ms tick
1287 * This class contains several variants: ['timer_1ms', 'timer']
1290 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1292 .sysc_offs = 0x0010,
1293 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1294 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1295 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1297 .sysc_fields = &omap_hwmod_sysc_type2,
1298 .clockact = CLOCKACT_TEST_ICLK,
1301 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1303 .sysc = &omap54xx_timer_1ms_sysc,
1306 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1308 .sysc_offs = 0x0010,
1309 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1310 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1313 .sysc_fields = &omap_hwmod_sysc_type2,
1316 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1318 .sysc = &omap54xx_timer_sysc,
1322 static struct omap_hwmod omap54xx_timer1_hwmod = {
1324 .class = &omap54xx_timer_1ms_hwmod_class,
1325 .clkdm_name = "wkupaon_clkdm",
1326 .main_clk = "timer1_gfclk_mux",
1327 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1330 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1331 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1338 static struct omap_hwmod omap54xx_timer2_hwmod = {
1340 .class = &omap54xx_timer_1ms_hwmod_class,
1341 .clkdm_name = "l4per_clkdm",
1342 .main_clk = "timer2_gfclk_mux",
1343 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1346 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1347 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1348 .modulemode = MODULEMODE_SWCTRL,
1354 static struct omap_hwmod omap54xx_timer3_hwmod = {
1356 .class = &omap54xx_timer_hwmod_class,
1357 .clkdm_name = "l4per_clkdm",
1358 .main_clk = "timer3_gfclk_mux",
1361 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1362 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1363 .modulemode = MODULEMODE_SWCTRL,
1369 static struct omap_hwmod omap54xx_timer4_hwmod = {
1371 .class = &omap54xx_timer_hwmod_class,
1372 .clkdm_name = "l4per_clkdm",
1373 .main_clk = "timer4_gfclk_mux",
1376 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1377 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1378 .modulemode = MODULEMODE_SWCTRL,
1384 static struct omap_hwmod omap54xx_timer5_hwmod = {
1386 .class = &omap54xx_timer_hwmod_class,
1387 .clkdm_name = "abe_clkdm",
1388 .main_clk = "timer5_gfclk_mux",
1391 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1392 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1393 .modulemode = MODULEMODE_SWCTRL,
1399 static struct omap_hwmod omap54xx_timer6_hwmod = {
1401 .class = &omap54xx_timer_hwmod_class,
1402 .clkdm_name = "abe_clkdm",
1403 .main_clk = "timer6_gfclk_mux",
1406 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1407 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1408 .modulemode = MODULEMODE_SWCTRL,
1414 static struct omap_hwmod omap54xx_timer7_hwmod = {
1416 .class = &omap54xx_timer_hwmod_class,
1417 .clkdm_name = "abe_clkdm",
1418 .main_clk = "timer7_gfclk_mux",
1421 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1422 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1423 .modulemode = MODULEMODE_SWCTRL,
1429 static struct omap_hwmod omap54xx_timer8_hwmod = {
1431 .class = &omap54xx_timer_hwmod_class,
1432 .clkdm_name = "abe_clkdm",
1433 .main_clk = "timer8_gfclk_mux",
1436 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1437 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1438 .modulemode = MODULEMODE_SWCTRL,
1444 static struct omap_hwmod omap54xx_timer9_hwmod = {
1446 .class = &omap54xx_timer_hwmod_class,
1447 .clkdm_name = "l4per_clkdm",
1448 .main_clk = "timer9_gfclk_mux",
1451 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1452 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1453 .modulemode = MODULEMODE_SWCTRL,
1459 static struct omap_hwmod omap54xx_timer10_hwmod = {
1461 .class = &omap54xx_timer_1ms_hwmod_class,
1462 .clkdm_name = "l4per_clkdm",
1463 .main_clk = "timer10_gfclk_mux",
1464 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1467 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1468 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1469 .modulemode = MODULEMODE_SWCTRL,
1475 static struct omap_hwmod omap54xx_timer11_hwmod = {
1477 .class = &omap54xx_timer_hwmod_class,
1478 .clkdm_name = "l4per_clkdm",
1479 .main_clk = "timer11_gfclk_mux",
1482 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1483 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1484 .modulemode = MODULEMODE_SWCTRL,
1491 * universal asynchronous receiver/transmitter (uart)
1494 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1496 .sysc_offs = 0x0054,
1497 .syss_offs = 0x0058,
1498 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1499 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1500 SYSS_HAS_RESET_STATUS),
1501 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1503 .sysc_fields = &omap_hwmod_sysc_type1,
1506 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1508 .sysc = &omap54xx_uart_sysc,
1512 static struct omap_hwmod omap54xx_uart1_hwmod = {
1514 .class = &omap54xx_uart_hwmod_class,
1515 .clkdm_name = "l4per_clkdm",
1516 .main_clk = "func_48m_fclk",
1519 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1520 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1521 .modulemode = MODULEMODE_SWCTRL,
1527 static struct omap_hwmod omap54xx_uart2_hwmod = {
1529 .class = &omap54xx_uart_hwmod_class,
1530 .clkdm_name = "l4per_clkdm",
1531 .main_clk = "func_48m_fclk",
1534 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1535 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1536 .modulemode = MODULEMODE_SWCTRL,
1542 static struct omap_hwmod omap54xx_uart3_hwmod = {
1544 .class = &omap54xx_uart_hwmod_class,
1545 .clkdm_name = "l4per_clkdm",
1546 .flags = DEBUG_OMAP4UART3_FLAGS,
1547 .main_clk = "func_48m_fclk",
1550 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1551 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1552 .modulemode = MODULEMODE_SWCTRL,
1558 static struct omap_hwmod omap54xx_uart4_hwmod = {
1560 .class = &omap54xx_uart_hwmod_class,
1561 .clkdm_name = "l4per_clkdm",
1562 .flags = DEBUG_OMAP4UART4_FLAGS,
1563 .main_clk = "func_48m_fclk",
1566 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1567 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1568 .modulemode = MODULEMODE_SWCTRL,
1574 static struct omap_hwmod omap54xx_uart5_hwmod = {
1576 .class = &omap54xx_uart_hwmod_class,
1577 .clkdm_name = "l4per_clkdm",
1578 .main_clk = "func_48m_fclk",
1581 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1582 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1583 .modulemode = MODULEMODE_SWCTRL,
1589 static struct omap_hwmod omap54xx_uart6_hwmod = {
1591 .class = &omap54xx_uart_hwmod_class,
1592 .clkdm_name = "l4per_clkdm",
1593 .main_clk = "func_48m_fclk",
1596 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1597 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1598 .modulemode = MODULEMODE_SWCTRL,
1604 * 'usb_host_hs' class
1605 * high-speed multi-port usb host controller
1608 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1610 .sysc_offs = 0x0010,
1611 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1612 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1613 SYSC_HAS_RESET_STATUS),
1614 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1615 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1616 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1617 .sysc_fields = &omap_hwmod_sysc_type2,
1620 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1621 .name = "usb_host_hs",
1622 .sysc = &omap54xx_usb_host_hs_sysc,
1625 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1626 .name = "usb_host_hs",
1627 .class = &omap54xx_usb_host_hs_hwmod_class,
1628 .clkdm_name = "l3init_clkdm",
1630 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1634 * In the following configuration :
1635 * - USBHOST module is set to smart-idle mode
1636 * - PRCM asserts idle_req to the USBHOST module ( This typically
1637 * happens when the system is going to a low power mode : all ports
1638 * have been suspended, the master part of the USBHOST module has
1639 * entered the standby state, and SW has cut the functional clocks)
1640 * - an USBHOST interrupt occurs before the module is able to answer
1641 * idle_ack, typically a remote wakeup IRQ.
1642 * Then the USB HOST module will enter a deadlock situation where it
1643 * is no more accessible nor functional.
1646 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1650 * Errata: USB host EHCI may stall when entering smart-standby mode
1654 * When the USBHOST module is set to smart-standby mode, and when it is
1655 * ready to enter the standby state (i.e. all ports are suspended and
1656 * all attached devices are in suspend mode), then it can wrongly assert
1657 * the Mstandby signal too early while there are still some residual OCP
1658 * transactions ongoing. If this condition occurs, the internal state
1659 * machine may go to an undefined state and the USB link may be stuck
1660 * upon the next resume.
1663 * Don't use smart standby; use only force standby,
1664 * hence HWMOD_SWSUP_MSTANDBY
1667 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1668 .main_clk = "l3init_60m_fclk",
1671 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1672 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1673 .modulemode = MODULEMODE_SWCTRL,
1679 * 'usb_tll_hs' class
1680 * usb_tll_hs module is the adapter on the usb_host_hs ports
1683 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1685 .sysc_offs = 0x0010,
1686 .syss_offs = 0x0014,
1687 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1688 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1689 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1690 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1691 .sysc_fields = &omap_hwmod_sysc_type1,
1694 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1695 .name = "usb_tll_hs",
1696 .sysc = &omap54xx_usb_tll_hs_sysc,
1699 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1700 .name = "usb_tll_hs",
1701 .class = &omap54xx_usb_tll_hs_hwmod_class,
1702 .clkdm_name = "l3init_clkdm",
1703 .main_clk = "l4_root_clk_div",
1706 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1707 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1708 .modulemode = MODULEMODE_HWCTRL,
1714 * 'usb_otg_ss' class
1715 * 2.0 super speed (usb_otg_ss) controller
1718 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1720 .sysc_offs = 0x0010,
1721 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1722 SYSC_HAS_SIDLEMODE),
1723 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1724 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1725 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1726 .sysc_fields = &omap_hwmod_sysc_type2,
1729 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1730 .name = "usb_otg_ss",
1731 .sysc = &omap54xx_usb_otg_ss_sysc,
1735 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1736 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1739 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1740 .name = "usb_otg_ss",
1741 .class = &omap54xx_usb_otg_ss_hwmod_class,
1742 .clkdm_name = "l3init_clkdm",
1743 .flags = HWMOD_SWSUP_SIDLE,
1744 .main_clk = "dpll_core_h13x2_ck",
1747 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1748 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1749 .modulemode = MODULEMODE_HWCTRL,
1752 .opt_clks = usb_otg_ss_opt_clks,
1753 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1758 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1759 * overflow condition
1762 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1764 .sysc_offs = 0x0010,
1765 .syss_offs = 0x0014,
1766 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1767 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1768 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1770 .sysc_fields = &omap_hwmod_sysc_type1,
1773 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1775 .sysc = &omap54xx_wd_timer_sysc,
1776 .pre_shutdown = &omap2_wd_timer_disable,
1780 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1781 .name = "wd_timer2",
1782 .class = &omap54xx_wd_timer_hwmod_class,
1783 .clkdm_name = "wkupaon_clkdm",
1784 .main_clk = "sys_32k_ck",
1787 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1788 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1789 .modulemode = MODULEMODE_SWCTRL,
1799 /* l3_main_1 -> dmm */
1800 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1801 .master = &omap54xx_l3_main_1_hwmod,
1802 .slave = &omap54xx_dmm_hwmod,
1803 .clk = "l3_iclk_div",
1804 .user = OCP_USER_SDMA,
1807 /* l3_main_3 -> l3_instr */
1808 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1809 .master = &omap54xx_l3_main_3_hwmod,
1810 .slave = &omap54xx_l3_instr_hwmod,
1811 .clk = "l3_iclk_div",
1812 .user = OCP_USER_MPU | OCP_USER_SDMA,
1815 /* l3_main_2 -> l3_main_1 */
1816 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1817 .master = &omap54xx_l3_main_2_hwmod,
1818 .slave = &omap54xx_l3_main_1_hwmod,
1819 .clk = "l3_iclk_div",
1820 .user = OCP_USER_MPU | OCP_USER_SDMA,
1823 /* l4_cfg -> l3_main_1 */
1824 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1825 .master = &omap54xx_l4_cfg_hwmod,
1826 .slave = &omap54xx_l3_main_1_hwmod,
1827 .clk = "l3_iclk_div",
1828 .user = OCP_USER_MPU | OCP_USER_SDMA,
1831 /* l4_cfg -> mmu_dsp */
1832 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
1833 .master = &omap54xx_l4_cfg_hwmod,
1834 .slave = &omap54xx_mmu_dsp_hwmod,
1835 .clk = "l4_root_clk_div",
1836 .user = OCP_USER_MPU | OCP_USER_SDMA,
1839 /* mpu -> l3_main_1 */
1840 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1841 .master = &omap54xx_mpu_hwmod,
1842 .slave = &omap54xx_l3_main_1_hwmod,
1843 .clk = "l3_iclk_div",
1844 .user = OCP_USER_MPU,
1847 /* l3_main_1 -> l3_main_2 */
1848 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1849 .master = &omap54xx_l3_main_1_hwmod,
1850 .slave = &omap54xx_l3_main_2_hwmod,
1851 .clk = "l3_iclk_div",
1852 .user = OCP_USER_MPU,
1855 /* l4_cfg -> l3_main_2 */
1856 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1857 .master = &omap54xx_l4_cfg_hwmod,
1858 .slave = &omap54xx_l3_main_2_hwmod,
1859 .clk = "l3_iclk_div",
1860 .user = OCP_USER_MPU | OCP_USER_SDMA,
1863 /* l3_main_2 -> mmu_ipu */
1864 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
1865 .master = &omap54xx_l3_main_2_hwmod,
1866 .slave = &omap54xx_mmu_ipu_hwmod,
1867 .clk = "l3_iclk_div",
1868 .user = OCP_USER_MPU | OCP_USER_SDMA,
1871 /* l3_main_1 -> l3_main_3 */
1872 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1873 .master = &omap54xx_l3_main_1_hwmod,
1874 .slave = &omap54xx_l3_main_3_hwmod,
1875 .clk = "l3_iclk_div",
1876 .user = OCP_USER_MPU,
1879 /* l3_main_2 -> l3_main_3 */
1880 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1881 .master = &omap54xx_l3_main_2_hwmod,
1882 .slave = &omap54xx_l3_main_3_hwmod,
1883 .clk = "l3_iclk_div",
1884 .user = OCP_USER_MPU | OCP_USER_SDMA,
1887 /* l4_cfg -> l3_main_3 */
1888 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1889 .master = &omap54xx_l4_cfg_hwmod,
1890 .slave = &omap54xx_l3_main_3_hwmod,
1891 .clk = "l3_iclk_div",
1892 .user = OCP_USER_MPU | OCP_USER_SDMA,
1895 /* l3_main_1 -> l4_abe */
1896 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1897 .master = &omap54xx_l3_main_1_hwmod,
1898 .slave = &omap54xx_l4_abe_hwmod,
1900 .user = OCP_USER_MPU | OCP_USER_SDMA,
1904 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1905 .master = &omap54xx_mpu_hwmod,
1906 .slave = &omap54xx_l4_abe_hwmod,
1908 .user = OCP_USER_MPU | OCP_USER_SDMA,
1911 /* l3_main_1 -> l4_cfg */
1912 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1913 .master = &omap54xx_l3_main_1_hwmod,
1914 .slave = &omap54xx_l4_cfg_hwmod,
1915 .clk = "l4_root_clk_div",
1916 .user = OCP_USER_MPU | OCP_USER_SDMA,
1919 /* l3_main_2 -> l4_per */
1920 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1921 .master = &omap54xx_l3_main_2_hwmod,
1922 .slave = &omap54xx_l4_per_hwmod,
1923 .clk = "l4_root_clk_div",
1924 .user = OCP_USER_MPU | OCP_USER_SDMA,
1927 /* l3_main_1 -> l4_wkup */
1928 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1929 .master = &omap54xx_l3_main_1_hwmod,
1930 .slave = &omap54xx_l4_wkup_hwmod,
1931 .clk = "wkupaon_iclk_mux",
1932 .user = OCP_USER_MPU | OCP_USER_SDMA,
1935 /* mpu -> mpu_private */
1936 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1937 .master = &omap54xx_mpu_hwmod,
1938 .slave = &omap54xx_mpu_private_hwmod,
1939 .clk = "l3_iclk_div",
1940 .user = OCP_USER_MPU | OCP_USER_SDMA,
1943 /* l4_wkup -> counter_32k */
1944 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1945 .master = &omap54xx_l4_wkup_hwmod,
1946 .slave = &omap54xx_counter_32k_hwmod,
1947 .clk = "wkupaon_iclk_mux",
1948 .user = OCP_USER_MPU | OCP_USER_SDMA,
1951 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1953 .pa_start = 0x4a056000,
1954 .pa_end = 0x4a056fff,
1955 .flags = ADDR_TYPE_RT
1960 /* l4_cfg -> dma_system */
1961 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1962 .master = &omap54xx_l4_cfg_hwmod,
1963 .slave = &omap54xx_dma_system_hwmod,
1964 .clk = "l4_root_clk_div",
1965 .addr = omap54xx_dma_system_addrs,
1966 .user = OCP_USER_MPU | OCP_USER_SDMA,
1969 /* l4_abe -> dmic */
1970 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1971 .master = &omap54xx_l4_abe_hwmod,
1972 .slave = &omap54xx_dmic_hwmod,
1974 .user = OCP_USER_MPU,
1978 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1979 .master = &omap54xx_mpu_hwmod,
1980 .slave = &omap54xx_emif1_hwmod,
1981 .clk = "dpll_core_h11x2_ck",
1982 .user = OCP_USER_MPU | OCP_USER_SDMA,
1986 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1987 .master = &omap54xx_mpu_hwmod,
1988 .slave = &omap54xx_emif2_hwmod,
1989 .clk = "dpll_core_h11x2_ck",
1990 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993 /* l4_wkup -> gpio1 */
1994 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1995 .master = &omap54xx_l4_wkup_hwmod,
1996 .slave = &omap54xx_gpio1_hwmod,
1997 .clk = "wkupaon_iclk_mux",
1998 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001 /* l4_per -> gpio2 */
2002 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
2003 .master = &omap54xx_l4_per_hwmod,
2004 .slave = &omap54xx_gpio2_hwmod,
2005 .clk = "l4_root_clk_div",
2006 .user = OCP_USER_MPU | OCP_USER_SDMA,
2009 /* l4_per -> gpio3 */
2010 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
2011 .master = &omap54xx_l4_per_hwmod,
2012 .slave = &omap54xx_gpio3_hwmod,
2013 .clk = "l4_root_clk_div",
2014 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017 /* l4_per -> gpio4 */
2018 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
2019 .master = &omap54xx_l4_per_hwmod,
2020 .slave = &omap54xx_gpio4_hwmod,
2021 .clk = "l4_root_clk_div",
2022 .user = OCP_USER_MPU | OCP_USER_SDMA,
2025 /* l4_per -> gpio5 */
2026 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
2027 .master = &omap54xx_l4_per_hwmod,
2028 .slave = &omap54xx_gpio5_hwmod,
2029 .clk = "l4_root_clk_div",
2030 .user = OCP_USER_MPU | OCP_USER_SDMA,
2033 /* l4_per -> gpio6 */
2034 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
2035 .master = &omap54xx_l4_per_hwmod,
2036 .slave = &omap54xx_gpio6_hwmod,
2037 .clk = "l4_root_clk_div",
2038 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041 /* l4_per -> gpio7 */
2042 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
2043 .master = &omap54xx_l4_per_hwmod,
2044 .slave = &omap54xx_gpio7_hwmod,
2045 .clk = "l4_root_clk_div",
2046 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049 /* l4_per -> gpio8 */
2050 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
2051 .master = &omap54xx_l4_per_hwmod,
2052 .slave = &omap54xx_gpio8_hwmod,
2053 .clk = "l4_root_clk_div",
2054 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057 /* l4_per -> i2c1 */
2058 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
2059 .master = &omap54xx_l4_per_hwmod,
2060 .slave = &omap54xx_i2c1_hwmod,
2061 .clk = "l4_root_clk_div",
2062 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065 /* l4_per -> i2c2 */
2066 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
2067 .master = &omap54xx_l4_per_hwmod,
2068 .slave = &omap54xx_i2c2_hwmod,
2069 .clk = "l4_root_clk_div",
2070 .user = OCP_USER_MPU | OCP_USER_SDMA,
2073 /* l4_per -> i2c3 */
2074 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
2075 .master = &omap54xx_l4_per_hwmod,
2076 .slave = &omap54xx_i2c3_hwmod,
2077 .clk = "l4_root_clk_div",
2078 .user = OCP_USER_MPU | OCP_USER_SDMA,
2081 /* l4_per -> i2c4 */
2082 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
2083 .master = &omap54xx_l4_per_hwmod,
2084 .slave = &omap54xx_i2c4_hwmod,
2085 .clk = "l4_root_clk_div",
2086 .user = OCP_USER_MPU | OCP_USER_SDMA,
2089 /* l4_per -> i2c5 */
2090 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
2091 .master = &omap54xx_l4_per_hwmod,
2092 .slave = &omap54xx_i2c5_hwmod,
2093 .clk = "l4_root_clk_div",
2094 .user = OCP_USER_MPU | OCP_USER_SDMA,
2097 /* l4_wkup -> kbd */
2098 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
2099 .master = &omap54xx_l4_wkup_hwmod,
2100 .slave = &omap54xx_kbd_hwmod,
2101 .clk = "wkupaon_iclk_mux",
2102 .user = OCP_USER_MPU | OCP_USER_SDMA,
2105 /* l4_cfg -> mailbox */
2106 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
2107 .master = &omap54xx_l4_cfg_hwmod,
2108 .slave = &omap54xx_mailbox_hwmod,
2109 .clk = "l4_root_clk_div",
2110 .user = OCP_USER_MPU | OCP_USER_SDMA,
2113 /* l4_abe -> mcbsp1 */
2114 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2115 .master = &omap54xx_l4_abe_hwmod,
2116 .slave = &omap54xx_mcbsp1_hwmod,
2118 .user = OCP_USER_MPU,
2121 /* l4_abe -> mcbsp2 */
2122 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2123 .master = &omap54xx_l4_abe_hwmod,
2124 .slave = &omap54xx_mcbsp2_hwmod,
2126 .user = OCP_USER_MPU,
2129 /* l4_abe -> mcbsp3 */
2130 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2131 .master = &omap54xx_l4_abe_hwmod,
2132 .slave = &omap54xx_mcbsp3_hwmod,
2134 .user = OCP_USER_MPU,
2137 /* l4_abe -> mcpdm */
2138 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2139 .master = &omap54xx_l4_abe_hwmod,
2140 .slave = &omap54xx_mcpdm_hwmod,
2142 .user = OCP_USER_MPU,
2145 /* l4_per -> mcspi1 */
2146 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2147 .master = &omap54xx_l4_per_hwmod,
2148 .slave = &omap54xx_mcspi1_hwmod,
2149 .clk = "l4_root_clk_div",
2150 .user = OCP_USER_MPU | OCP_USER_SDMA,
2153 /* l4_per -> mcspi2 */
2154 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2155 .master = &omap54xx_l4_per_hwmod,
2156 .slave = &omap54xx_mcspi2_hwmod,
2157 .clk = "l4_root_clk_div",
2158 .user = OCP_USER_MPU | OCP_USER_SDMA,
2161 /* l4_per -> mcspi3 */
2162 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2163 .master = &omap54xx_l4_per_hwmod,
2164 .slave = &omap54xx_mcspi3_hwmod,
2165 .clk = "l4_root_clk_div",
2166 .user = OCP_USER_MPU | OCP_USER_SDMA,
2169 /* l4_per -> mcspi4 */
2170 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2171 .master = &omap54xx_l4_per_hwmod,
2172 .slave = &omap54xx_mcspi4_hwmod,
2173 .clk = "l4_root_clk_div",
2174 .user = OCP_USER_MPU | OCP_USER_SDMA,
2177 /* l4_per -> mmc1 */
2178 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2179 .master = &omap54xx_l4_per_hwmod,
2180 .slave = &omap54xx_mmc1_hwmod,
2181 .clk = "l3_iclk_div",
2182 .user = OCP_USER_MPU | OCP_USER_SDMA,
2185 /* l4_per -> mmc2 */
2186 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2187 .master = &omap54xx_l4_per_hwmod,
2188 .slave = &omap54xx_mmc2_hwmod,
2189 .clk = "l3_iclk_div",
2190 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193 /* l4_per -> mmc3 */
2194 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2195 .master = &omap54xx_l4_per_hwmod,
2196 .slave = &omap54xx_mmc3_hwmod,
2197 .clk = "l4_root_clk_div",
2198 .user = OCP_USER_MPU | OCP_USER_SDMA,
2201 /* l4_per -> mmc4 */
2202 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2203 .master = &omap54xx_l4_per_hwmod,
2204 .slave = &omap54xx_mmc4_hwmod,
2205 .clk = "l4_root_clk_div",
2206 .user = OCP_USER_MPU | OCP_USER_SDMA,
2209 /* l4_per -> mmc5 */
2210 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2211 .master = &omap54xx_l4_per_hwmod,
2212 .slave = &omap54xx_mmc5_hwmod,
2213 .clk = "l4_root_clk_div",
2214 .user = OCP_USER_MPU | OCP_USER_SDMA,
2218 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2219 .master = &omap54xx_l4_cfg_hwmod,
2220 .slave = &omap54xx_mpu_hwmod,
2221 .clk = "l4_root_clk_div",
2222 .user = OCP_USER_MPU | OCP_USER_SDMA,
2225 /* l4_cfg -> spinlock */
2226 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2227 .master = &omap54xx_l4_cfg_hwmod,
2228 .slave = &omap54xx_spinlock_hwmod,
2229 .clk = "l4_root_clk_div",
2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2233 /* l4_cfg -> ocp2scp1 */
2234 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
2235 .master = &omap54xx_l4_cfg_hwmod,
2236 .slave = &omap54xx_ocp2scp1_hwmod,
2237 .clk = "l4_root_clk_div",
2238 .user = OCP_USER_MPU | OCP_USER_SDMA,
2241 /* l4_wkup -> timer1 */
2242 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2243 .master = &omap54xx_l4_wkup_hwmod,
2244 .slave = &omap54xx_timer1_hwmod,
2245 .clk = "wkupaon_iclk_mux",
2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2249 /* l4_per -> timer2 */
2250 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2251 .master = &omap54xx_l4_per_hwmod,
2252 .slave = &omap54xx_timer2_hwmod,
2253 .clk = "l4_root_clk_div",
2254 .user = OCP_USER_MPU | OCP_USER_SDMA,
2257 /* l4_per -> timer3 */
2258 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2259 .master = &omap54xx_l4_per_hwmod,
2260 .slave = &omap54xx_timer3_hwmod,
2261 .clk = "l4_root_clk_div",
2262 .user = OCP_USER_MPU | OCP_USER_SDMA,
2265 /* l4_per -> timer4 */
2266 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2267 .master = &omap54xx_l4_per_hwmod,
2268 .slave = &omap54xx_timer4_hwmod,
2269 .clk = "l4_root_clk_div",
2270 .user = OCP_USER_MPU | OCP_USER_SDMA,
2273 /* l4_abe -> timer5 */
2274 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2275 .master = &omap54xx_l4_abe_hwmod,
2276 .slave = &omap54xx_timer5_hwmod,
2278 .user = OCP_USER_MPU,
2281 /* l4_abe -> timer6 */
2282 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2283 .master = &omap54xx_l4_abe_hwmod,
2284 .slave = &omap54xx_timer6_hwmod,
2286 .user = OCP_USER_MPU,
2289 /* l4_abe -> timer7 */
2290 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2291 .master = &omap54xx_l4_abe_hwmod,
2292 .slave = &omap54xx_timer7_hwmod,
2294 .user = OCP_USER_MPU,
2297 /* l4_abe -> timer8 */
2298 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2299 .master = &omap54xx_l4_abe_hwmod,
2300 .slave = &omap54xx_timer8_hwmod,
2302 .user = OCP_USER_MPU,
2305 /* l4_per -> timer9 */
2306 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2307 .master = &omap54xx_l4_per_hwmod,
2308 .slave = &omap54xx_timer9_hwmod,
2309 .clk = "l4_root_clk_div",
2310 .user = OCP_USER_MPU | OCP_USER_SDMA,
2313 /* l4_per -> timer10 */
2314 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2315 .master = &omap54xx_l4_per_hwmod,
2316 .slave = &omap54xx_timer10_hwmod,
2317 .clk = "l4_root_clk_div",
2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2321 /* l4_per -> timer11 */
2322 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2323 .master = &omap54xx_l4_per_hwmod,
2324 .slave = &omap54xx_timer11_hwmod,
2325 .clk = "l4_root_clk_div",
2326 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329 /* l4_per -> uart1 */
2330 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2331 .master = &omap54xx_l4_per_hwmod,
2332 .slave = &omap54xx_uart1_hwmod,
2333 .clk = "l4_root_clk_div",
2334 .user = OCP_USER_MPU | OCP_USER_SDMA,
2337 /* l4_per -> uart2 */
2338 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2339 .master = &omap54xx_l4_per_hwmod,
2340 .slave = &omap54xx_uart2_hwmod,
2341 .clk = "l4_root_clk_div",
2342 .user = OCP_USER_MPU | OCP_USER_SDMA,
2345 /* l4_per -> uart3 */
2346 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2347 .master = &omap54xx_l4_per_hwmod,
2348 .slave = &omap54xx_uart3_hwmod,
2349 .clk = "l4_root_clk_div",
2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353 /* l4_per -> uart4 */
2354 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2355 .master = &omap54xx_l4_per_hwmod,
2356 .slave = &omap54xx_uart4_hwmod,
2357 .clk = "l4_root_clk_div",
2358 .user = OCP_USER_MPU | OCP_USER_SDMA,
2361 /* l4_per -> uart5 */
2362 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2363 .master = &omap54xx_l4_per_hwmod,
2364 .slave = &omap54xx_uart5_hwmod,
2365 .clk = "l4_root_clk_div",
2366 .user = OCP_USER_MPU | OCP_USER_SDMA,
2369 /* l4_per -> uart6 */
2370 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2371 .master = &omap54xx_l4_per_hwmod,
2372 .slave = &omap54xx_uart6_hwmod,
2373 .clk = "l4_root_clk_div",
2374 .user = OCP_USER_MPU | OCP_USER_SDMA,
2377 /* l4_cfg -> usb_host_hs */
2378 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2379 .master = &omap54xx_l4_cfg_hwmod,
2380 .slave = &omap54xx_usb_host_hs_hwmod,
2381 .clk = "l3_iclk_div",
2382 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385 /* l4_cfg -> usb_tll_hs */
2386 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2387 .master = &omap54xx_l4_cfg_hwmod,
2388 .slave = &omap54xx_usb_tll_hs_hwmod,
2389 .clk = "l4_root_clk_div",
2390 .user = OCP_USER_MPU | OCP_USER_SDMA,
2393 /* l4_cfg -> usb_otg_ss */
2394 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2395 .master = &omap54xx_l4_cfg_hwmod,
2396 .slave = &omap54xx_usb_otg_ss_hwmod,
2397 .clk = "dpll_core_h13x2_ck",
2398 .user = OCP_USER_MPU | OCP_USER_SDMA,
2401 /* l4_wkup -> wd_timer2 */
2402 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2403 .master = &omap54xx_l4_wkup_hwmod,
2404 .slave = &omap54xx_wd_timer2_hwmod,
2405 .clk = "wkupaon_iclk_mux",
2406 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2410 &omap54xx_l3_main_1__dmm,
2411 &omap54xx_l3_main_3__l3_instr,
2412 &omap54xx_l3_main_2__l3_main_1,
2413 &omap54xx_l4_cfg__l3_main_1,
2414 &omap54xx_mpu__l3_main_1,
2415 &omap54xx_l3_main_1__l3_main_2,
2416 &omap54xx_l4_cfg__l3_main_2,
2417 &omap54xx_l3_main_1__l3_main_3,
2418 &omap54xx_l3_main_2__l3_main_3,
2419 &omap54xx_l4_cfg__l3_main_3,
2420 &omap54xx_l3_main_1__l4_abe,
2421 &omap54xx_mpu__l4_abe,
2422 &omap54xx_l3_main_1__l4_cfg,
2423 &omap54xx_l3_main_2__l4_per,
2424 &omap54xx_l3_main_1__l4_wkup,
2425 &omap54xx_mpu__mpu_private,
2426 &omap54xx_l4_wkup__counter_32k,
2427 &omap54xx_l4_cfg__dma_system,
2428 &omap54xx_l4_abe__dmic,
2429 &omap54xx_l4_cfg__mmu_dsp,
2430 &omap54xx_mpu__emif1,
2431 &omap54xx_mpu__emif2,
2432 &omap54xx_l4_wkup__gpio1,
2433 &omap54xx_l4_per__gpio2,
2434 &omap54xx_l4_per__gpio3,
2435 &omap54xx_l4_per__gpio4,
2436 &omap54xx_l4_per__gpio5,
2437 &omap54xx_l4_per__gpio6,
2438 &omap54xx_l4_per__gpio7,
2439 &omap54xx_l4_per__gpio8,
2440 &omap54xx_l4_per__i2c1,
2441 &omap54xx_l4_per__i2c2,
2442 &omap54xx_l4_per__i2c3,
2443 &omap54xx_l4_per__i2c4,
2444 &omap54xx_l4_per__i2c5,
2445 &omap54xx_l3_main_2__mmu_ipu,
2446 &omap54xx_l4_wkup__kbd,
2447 &omap54xx_l4_cfg__mailbox,
2448 &omap54xx_l4_abe__mcbsp1,
2449 &omap54xx_l4_abe__mcbsp2,
2450 &omap54xx_l4_abe__mcbsp3,
2451 &omap54xx_l4_abe__mcpdm,
2452 &omap54xx_l4_per__mcspi1,
2453 &omap54xx_l4_per__mcspi2,
2454 &omap54xx_l4_per__mcspi3,
2455 &omap54xx_l4_per__mcspi4,
2456 &omap54xx_l4_per__mmc1,
2457 &omap54xx_l4_per__mmc2,
2458 &omap54xx_l4_per__mmc3,
2459 &omap54xx_l4_per__mmc4,
2460 &omap54xx_l4_per__mmc5,
2461 &omap54xx_l4_cfg__mpu,
2462 &omap54xx_l4_cfg__spinlock,
2463 &omap54xx_l4_cfg__ocp2scp1,
2464 &omap54xx_l4_wkup__timer1,
2465 &omap54xx_l4_per__timer2,
2466 &omap54xx_l4_per__timer3,
2467 &omap54xx_l4_per__timer4,
2468 &omap54xx_l4_abe__timer5,
2469 &omap54xx_l4_abe__timer6,
2470 &omap54xx_l4_abe__timer7,
2471 &omap54xx_l4_abe__timer8,
2472 &omap54xx_l4_per__timer9,
2473 &omap54xx_l4_per__timer10,
2474 &omap54xx_l4_per__timer11,
2475 &omap54xx_l4_per__uart1,
2476 &omap54xx_l4_per__uart2,
2477 &omap54xx_l4_per__uart3,
2478 &omap54xx_l4_per__uart4,
2479 &omap54xx_l4_per__uart5,
2480 &omap54xx_l4_per__uart6,
2481 &omap54xx_l4_cfg__usb_host_hs,
2482 &omap54xx_l4_cfg__usb_tll_hs,
2483 &omap54xx_l4_cfg__usb_otg_ss,
2484 &omap54xx_l4_wkup__wd_timer2,
2488 int __init omap54xx_hwmod_init(void)
2491 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);