2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
60 static struct omap_hwmod dra7xx_dmm_hwmod = {
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
74 * instance(s): l3_instr, l3_main_1, l3_main_2
76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
204 static struct omap_hwmod dra7xx_atl_hwmod = {
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
253 .sysc_fields = &omap_hwmod_sysc_type1,
256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
258 .sysc = &dra7xx_counter_sysc,
262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
277 * 'ctrl_module' class
281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
285 /* ctrl_module_wkup */
286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
299 * cpsw/gmac sub system
301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
309 .sysc_fields = &omap_hwmod_sysc_type3,
312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
314 .sysc = &dra7xx_gmac_sysc,
317 static struct omap_hwmod dra7xx_gmac_hwmod = {
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
340 static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
391 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1,
405 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
407 .sysc = &dra7xx_dma_sysc,
411 static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
418 static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm",
422 .main_clk = "l3_iclk_div",
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
429 .dev_attr = &dma_dev_attr,
437 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
440 .sysc_flags = SYSS_HAS_RESET_STATUS,
443 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
445 .sysc = &dra7xx_dss_sysc,
446 .reset = omap_dss_reset,
450 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
451 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
455 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
456 { .role = "dss_clk", .clk = "dss_dss_clk" },
457 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
458 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
459 { .role = "video2_clk", .clk = "dss_video2_clk" },
460 { .role = "video1_clk", .clk = "dss_video1_clk" },
461 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
462 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
465 static struct omap_hwmod dra7xx_dss_hwmod = {
467 .class = &dra7xx_dss_hwmod_class,
468 .clkdm_name = "dss_clkdm",
469 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
470 .sdma_reqs = dra7xx_dss_sdma_reqs,
471 .main_clk = "dss_dss_clk",
474 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
475 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
488 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
494 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
495 SYSS_HAS_RESET_STATUS),
496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
498 .sysc_fields = &omap_hwmod_sysc_type1,
501 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
503 .sysc = &dra7xx_dispc_sysc,
507 /* dss_dispc dev_attr */
508 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
509 .has_framedonetv_irq = 1,
513 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
515 .class = &dra7xx_dispc_hwmod_class,
516 .clkdm_name = "dss_clkdm",
517 .main_clk = "dss_dss_clk",
520 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
521 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
524 .dev_attr = &dss_dispc_dev_attr,
525 .parent_hwmod = &dra7xx_dss_hwmod,
533 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
536 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
540 .sysc_fields = &omap_hwmod_sysc_type2,
543 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
545 .sysc = &dra7xx_hdmi_sysc,
550 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
551 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
554 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
556 .class = &dra7xx_hdmi_hwmod_class,
557 .clkdm_name = "dss_clkdm",
558 .main_clk = "dss_48mhz_clk",
561 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
562 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
565 .opt_clks = dss_hdmi_opt_clks,
566 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
567 .parent_hwmod = &dra7xx_dss_hwmod,
575 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
579 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
580 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
581 SYSS_HAS_RESET_STATUS),
582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
584 .sysc_fields = &omap_hwmod_sysc_type1,
587 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
589 .sysc = &dra7xx_elm_sysc,
594 static struct omap_hwmod dra7xx_elm_hwmod = {
596 .class = &dra7xx_elm_hwmod_class,
597 .clkdm_name = "l4per_clkdm",
598 .main_clk = "l3_iclk_div",
601 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
602 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
612 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
618 SYSS_HAS_RESET_STATUS),
619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
621 .sysc_fields = &omap_hwmod_sysc_type1,
624 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
626 .sysc = &dra7xx_gpio_sysc,
631 static struct omap_gpio_dev_attr gpio_dev_attr = {
637 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
638 { .role = "dbclk", .clk = "gpio1_dbclk" },
641 static struct omap_hwmod dra7xx_gpio1_hwmod = {
643 .class = &dra7xx_gpio_hwmod_class,
644 .clkdm_name = "wkupaon_clkdm",
645 .main_clk = "wkupaon_iclk_mux",
648 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
649 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
650 .modulemode = MODULEMODE_HWCTRL,
653 .opt_clks = gpio1_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
655 .dev_attr = &gpio_dev_attr,
659 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
660 { .role = "dbclk", .clk = "gpio2_dbclk" },
663 static struct omap_hwmod dra7xx_gpio2_hwmod = {
665 .class = &dra7xx_gpio_hwmod_class,
666 .clkdm_name = "l4per_clkdm",
667 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668 .main_clk = "l3_iclk_div",
671 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
672 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
673 .modulemode = MODULEMODE_HWCTRL,
676 .opt_clks = gpio2_opt_clks,
677 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
678 .dev_attr = &gpio_dev_attr,
682 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio3_dbclk" },
686 static struct omap_hwmod dra7xx_gpio3_hwmod = {
688 .class = &dra7xx_gpio_hwmod_class,
689 .clkdm_name = "l4per_clkdm",
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .main_clk = "l3_iclk_div",
694 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
695 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
696 .modulemode = MODULEMODE_HWCTRL,
699 .opt_clks = gpio3_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
701 .dev_attr = &gpio_dev_attr,
705 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
706 { .role = "dbclk", .clk = "gpio4_dbclk" },
709 static struct omap_hwmod dra7xx_gpio4_hwmod = {
711 .class = &dra7xx_gpio_hwmod_class,
712 .clkdm_name = "l4per_clkdm",
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .main_clk = "l3_iclk_div",
717 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
718 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
722 .opt_clks = gpio4_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
724 .dev_attr = &gpio_dev_attr,
728 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
729 { .role = "dbclk", .clk = "gpio5_dbclk" },
732 static struct omap_hwmod dra7xx_gpio5_hwmod = {
734 .class = &dra7xx_gpio_hwmod_class,
735 .clkdm_name = "l4per_clkdm",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "l3_iclk_div",
740 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
741 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_HWCTRL,
745 .opt_clks = gpio5_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
747 .dev_attr = &gpio_dev_attr,
751 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio6_dbclk" },
755 static struct omap_hwmod dra7xx_gpio6_hwmod = {
757 .class = &dra7xx_gpio_hwmod_class,
758 .clkdm_name = "l4per_clkdm",
759 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
760 .main_clk = "l3_iclk_div",
763 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
764 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
765 .modulemode = MODULEMODE_HWCTRL,
768 .opt_clks = gpio6_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
770 .dev_attr = &gpio_dev_attr,
774 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
775 { .role = "dbclk", .clk = "gpio7_dbclk" },
778 static struct omap_hwmod dra7xx_gpio7_hwmod = {
780 .class = &dra7xx_gpio_hwmod_class,
781 .clkdm_name = "l4per_clkdm",
782 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
783 .main_clk = "l3_iclk_div",
786 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
787 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
788 .modulemode = MODULEMODE_HWCTRL,
791 .opt_clks = gpio7_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
793 .dev_attr = &gpio_dev_attr,
797 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
798 { .role = "dbclk", .clk = "gpio8_dbclk" },
801 static struct omap_hwmod dra7xx_gpio8_hwmod = {
803 .class = &dra7xx_gpio_hwmod_class,
804 .clkdm_name = "l4per_clkdm",
805 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
806 .main_clk = "l3_iclk_div",
809 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
814 .opt_clks = gpio8_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
816 .dev_attr = &gpio_dev_attr,
824 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
828 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
830 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
831 .sysc_fields = &omap_hwmod_sysc_type1,
834 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
836 .sysc = &dra7xx_gpmc_sysc,
841 static struct omap_hwmod dra7xx_gpmc_hwmod = {
843 .class = &dra7xx_gpmc_hwmod_class,
844 .clkdm_name = "l3main1_clkdm",
845 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
846 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
847 .main_clk = "l3_iclk_div",
850 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
851 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
852 .modulemode = MODULEMODE_HWCTRL,
862 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
866 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
867 SYSS_HAS_RESET_STATUS),
868 .sysc_fields = &omap_hwmod_sysc_type1,
871 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
873 .sysc = &dra7xx_hdq1w_sysc,
878 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
880 .class = &dra7xx_hdq1w_hwmod_class,
881 .clkdm_name = "l4per_clkdm",
882 .flags = HWMOD_INIT_NO_RESET,
883 .main_clk = "func_12m_fclk",
886 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
888 .modulemode = MODULEMODE_SWCTRL,
898 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
901 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
902 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
903 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
904 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
906 .clockact = CLOCKACT_TEST_ICLK,
907 .sysc_fields = &omap_hwmod_sysc_type1,
910 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
912 .sysc = &dra7xx_i2c_sysc,
913 .reset = &omap_i2c_reset,
914 .rev = OMAP_I2C_IP_VERSION_2,
918 static struct omap_i2c_dev_attr i2c_dev_attr = {
919 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
923 static struct omap_hwmod dra7xx_i2c1_hwmod = {
925 .class = &dra7xx_i2c_hwmod_class,
926 .clkdm_name = "l4per_clkdm",
927 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
928 .main_clk = "func_96m_fclk",
931 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
932 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
933 .modulemode = MODULEMODE_SWCTRL,
936 .dev_attr = &i2c_dev_attr,
940 static struct omap_hwmod dra7xx_i2c2_hwmod = {
942 .class = &dra7xx_i2c_hwmod_class,
943 .clkdm_name = "l4per_clkdm",
944 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
945 .main_clk = "func_96m_fclk",
948 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
949 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
953 .dev_attr = &i2c_dev_attr,
957 static struct omap_hwmod dra7xx_i2c3_hwmod = {
959 .class = &dra7xx_i2c_hwmod_class,
960 .clkdm_name = "l4per_clkdm",
961 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
962 .main_clk = "func_96m_fclk",
965 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
966 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
970 .dev_attr = &i2c_dev_attr,
974 static struct omap_hwmod dra7xx_i2c4_hwmod = {
976 .class = &dra7xx_i2c_hwmod_class,
977 .clkdm_name = "l4per_clkdm",
978 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
979 .main_clk = "func_96m_fclk",
982 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
983 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
984 .modulemode = MODULEMODE_SWCTRL,
987 .dev_attr = &i2c_dev_attr,
991 static struct omap_hwmod dra7xx_i2c5_hwmod = {
993 .class = &dra7xx_i2c_hwmod_class,
994 .clkdm_name = "ipu_clkdm",
995 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
996 .main_clk = "func_96m_fclk",
999 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1000 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1004 .dev_attr = &i2c_dev_attr,
1012 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1014 .sysc_offs = 0x0010,
1015 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1016 SYSC_HAS_SOFTRESET),
1017 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1018 .sysc_fields = &omap_hwmod_sysc_type2,
1021 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1023 .sysc = &dra7xx_mailbox_sysc,
1027 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1029 .class = &dra7xx_mailbox_hwmod_class,
1030 .clkdm_name = "l4cfg_clkdm",
1033 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1034 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1040 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1042 .class = &dra7xx_mailbox_hwmod_class,
1043 .clkdm_name = "l4cfg_clkdm",
1046 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1047 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1053 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1055 .class = &dra7xx_mailbox_hwmod_class,
1056 .clkdm_name = "l4cfg_clkdm",
1059 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1060 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1066 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1068 .class = &dra7xx_mailbox_hwmod_class,
1069 .clkdm_name = "l4cfg_clkdm",
1072 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1073 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1079 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1081 .class = &dra7xx_mailbox_hwmod_class,
1082 .clkdm_name = "l4cfg_clkdm",
1085 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1092 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1094 .class = &dra7xx_mailbox_hwmod_class,
1095 .clkdm_name = "l4cfg_clkdm",
1098 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1099 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1105 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1107 .class = &dra7xx_mailbox_hwmod_class,
1108 .clkdm_name = "l4cfg_clkdm",
1111 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1112 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1118 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1120 .class = &dra7xx_mailbox_hwmod_class,
1121 .clkdm_name = "l4cfg_clkdm",
1124 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1125 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1131 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1133 .class = &dra7xx_mailbox_hwmod_class,
1134 .clkdm_name = "l4cfg_clkdm",
1137 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1138 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1144 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1145 .name = "mailbox10",
1146 .class = &dra7xx_mailbox_hwmod_class,
1147 .clkdm_name = "l4cfg_clkdm",
1150 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1151 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1157 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1158 .name = "mailbox11",
1159 .class = &dra7xx_mailbox_hwmod_class,
1160 .clkdm_name = "l4cfg_clkdm",
1163 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1164 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1170 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1171 .name = "mailbox12",
1172 .class = &dra7xx_mailbox_hwmod_class,
1173 .clkdm_name = "l4cfg_clkdm",
1176 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1183 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1184 .name = "mailbox13",
1185 .class = &dra7xx_mailbox_hwmod_class,
1186 .clkdm_name = "l4cfg_clkdm",
1189 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1190 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1200 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1202 .sysc_offs = 0x0010,
1203 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1204 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1205 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207 .sysc_fields = &omap_hwmod_sysc_type2,
1210 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1212 .sysc = &dra7xx_mcspi_sysc,
1213 .rev = OMAP4_MCSPI_REV,
1217 /* mcspi1 dev_attr */
1218 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1219 .num_chipselect = 4,
1222 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1224 .class = &dra7xx_mcspi_hwmod_class,
1225 .clkdm_name = "l4per_clkdm",
1226 .main_clk = "func_48m_fclk",
1229 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1234 .dev_attr = &mcspi1_dev_attr,
1238 /* mcspi2 dev_attr */
1239 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1240 .num_chipselect = 2,
1243 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1245 .class = &dra7xx_mcspi_hwmod_class,
1246 .clkdm_name = "l4per_clkdm",
1247 .main_clk = "func_48m_fclk",
1250 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1252 .modulemode = MODULEMODE_SWCTRL,
1255 .dev_attr = &mcspi2_dev_attr,
1259 /* mcspi3 dev_attr */
1260 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1261 .num_chipselect = 2,
1264 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1266 .class = &dra7xx_mcspi_hwmod_class,
1267 .clkdm_name = "l4per_clkdm",
1268 .main_clk = "func_48m_fclk",
1271 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1272 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1273 .modulemode = MODULEMODE_SWCTRL,
1276 .dev_attr = &mcspi3_dev_attr,
1280 /* mcspi4 dev_attr */
1281 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1282 .num_chipselect = 1,
1285 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1287 .class = &dra7xx_mcspi_hwmod_class,
1288 .clkdm_name = "l4per_clkdm",
1289 .main_clk = "func_48m_fclk",
1292 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1293 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1294 .modulemode = MODULEMODE_SWCTRL,
1297 .dev_attr = &mcspi4_dev_attr,
1305 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1307 .sysc_offs = 0x0010,
1308 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1309 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1310 SYSC_HAS_SOFTRESET),
1311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1312 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1313 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1314 .sysc_fields = &omap_hwmod_sysc_type2,
1317 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1319 .sysc = &dra7xx_mmc_sysc,
1323 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1324 { .role = "clk32k", .clk = "mmc1_clk32k" },
1328 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1329 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1332 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1334 .class = &dra7xx_mmc_hwmod_class,
1335 .clkdm_name = "l3init_clkdm",
1336 .main_clk = "mmc1_fclk_div",
1339 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1340 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1341 .modulemode = MODULEMODE_SWCTRL,
1344 .opt_clks = mmc1_opt_clks,
1345 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1346 .dev_attr = &mmc1_dev_attr,
1350 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1351 { .role = "clk32k", .clk = "mmc2_clk32k" },
1354 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1356 .class = &dra7xx_mmc_hwmod_class,
1357 .clkdm_name = "l3init_clkdm",
1358 .main_clk = "mmc2_fclk_div",
1361 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1362 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1363 .modulemode = MODULEMODE_SWCTRL,
1366 .opt_clks = mmc2_opt_clks,
1367 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1371 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1372 { .role = "clk32k", .clk = "mmc3_clk32k" },
1375 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1377 .class = &dra7xx_mmc_hwmod_class,
1378 .clkdm_name = "l4per_clkdm",
1379 .main_clk = "mmc3_gfclk_div",
1382 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1383 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1384 .modulemode = MODULEMODE_SWCTRL,
1387 .opt_clks = mmc3_opt_clks,
1388 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1392 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1393 { .role = "clk32k", .clk = "mmc4_clk32k" },
1396 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1398 .class = &dra7xx_mmc_hwmod_class,
1399 .clkdm_name = "l4per_clkdm",
1400 .main_clk = "mmc4_gfclk_div",
1403 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1404 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1405 .modulemode = MODULEMODE_SWCTRL,
1408 .opt_clks = mmc4_opt_clks,
1409 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1417 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1422 static struct omap_hwmod dra7xx_mpu_hwmod = {
1424 .class = &dra7xx_mpu_hwmod_class,
1425 .clkdm_name = "mpu_clkdm",
1426 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1427 .main_clk = "dpll_mpu_m2_ck",
1430 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1431 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1441 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1443 .sysc_offs = 0x0010,
1444 .syss_offs = 0x0014,
1445 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1446 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1449 .sysc_fields = &omap_hwmod_sysc_type1,
1452 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1454 .sysc = &dra7xx_ocp2scp_sysc,
1458 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1460 .class = &dra7xx_ocp2scp_hwmod_class,
1461 .clkdm_name = "l3init_clkdm",
1462 .main_clk = "l4_root_clk_div",
1465 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1466 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1467 .modulemode = MODULEMODE_HWCTRL,
1473 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1475 .class = &dra7xx_ocp2scp_hwmod_class,
1476 .clkdm_name = "l3init_clkdm",
1477 .main_clk = "l4_root_clk_div",
1480 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1481 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1482 .modulemode = MODULEMODE_HWCTRL,
1492 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1497 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1499 .class = &dra7xx_pciess_hwmod_class,
1500 .clkdm_name = "pcie_clkdm",
1501 .main_clk = "l4_root_clk_div",
1504 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1505 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1506 .modulemode = MODULEMODE_SWCTRL,
1512 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1514 .class = &dra7xx_pciess_hwmod_class,
1515 .clkdm_name = "pcie_clkdm",
1516 .main_clk = "l4_root_clk_div",
1519 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1520 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1521 .modulemode = MODULEMODE_SWCTRL,
1531 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1532 .sysc_offs = 0x0010,
1533 .sysc_flags = SYSC_HAS_SIDLEMODE,
1534 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1536 .sysc_fields = &omap_hwmod_sysc_type2,
1539 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1541 .sysc = &dra7xx_qspi_sysc,
1545 static struct omap_hwmod dra7xx_qspi_hwmod = {
1547 .class = &dra7xx_qspi_hwmod_class,
1548 .clkdm_name = "l4per2_clkdm",
1549 .main_clk = "qspi_gfclk_div",
1552 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1553 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1554 .modulemode = MODULEMODE_SWCTRL,
1563 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1564 .sysc_offs = 0x0078,
1565 .sysc_flags = SYSC_HAS_SIDLEMODE,
1566 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1568 .sysc_fields = &omap_hwmod_sysc_type3,
1571 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1573 .sysc = &dra7xx_rtcss_sysc,
1577 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1579 .class = &dra7xx_rtcss_hwmod_class,
1580 .clkdm_name = "rtc_clkdm",
1581 .main_clk = "sys_32k_ck",
1584 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1585 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1586 .modulemode = MODULEMODE_SWCTRL,
1596 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1597 .sysc_offs = 0x0000,
1598 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1600 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1601 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1602 .sysc_fields = &omap_hwmod_sysc_type2,
1605 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1607 .sysc = &dra7xx_sata_sysc,
1612 static struct omap_hwmod dra7xx_sata_hwmod = {
1614 .class = &dra7xx_sata_hwmod_class,
1615 .clkdm_name = "l3init_clkdm",
1616 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1617 .main_clk = "func_48m_fclk",
1621 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1622 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1623 .modulemode = MODULEMODE_SWCTRL,
1629 * 'smartreflex' class
1633 /* The IP is not compliant to type1 / type2 scheme */
1634 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1639 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1640 .sysc_offs = 0x0038,
1641 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1642 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1644 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1647 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1648 .name = "smartreflex",
1649 .sysc = &dra7xx_smartreflex_sysc,
1653 /* smartreflex_core */
1654 /* smartreflex_core dev_attr */
1655 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1656 .sensor_voltdm_name = "core",
1659 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1660 .name = "smartreflex_core",
1661 .class = &dra7xx_smartreflex_hwmod_class,
1662 .clkdm_name = "coreaon_clkdm",
1663 .main_clk = "wkupaon_iclk_mux",
1666 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1667 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1668 .modulemode = MODULEMODE_SWCTRL,
1671 .dev_attr = &smartreflex_core_dev_attr,
1674 /* smartreflex_mpu */
1675 /* smartreflex_mpu dev_attr */
1676 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1677 .sensor_voltdm_name = "mpu",
1680 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1681 .name = "smartreflex_mpu",
1682 .class = &dra7xx_smartreflex_hwmod_class,
1683 .clkdm_name = "coreaon_clkdm",
1684 .main_clk = "wkupaon_iclk_mux",
1687 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1688 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1689 .modulemode = MODULEMODE_SWCTRL,
1692 .dev_attr = &smartreflex_mpu_dev_attr,
1700 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1702 .sysc_offs = 0x0010,
1703 .syss_offs = 0x0014,
1704 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1705 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1706 SYSS_HAS_RESET_STATUS),
1707 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1708 .sysc_fields = &omap_hwmod_sysc_type1,
1711 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1713 .sysc = &dra7xx_spinlock_sysc,
1717 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1719 .class = &dra7xx_spinlock_hwmod_class,
1720 .clkdm_name = "l4cfg_clkdm",
1721 .main_clk = "l3_iclk_div",
1724 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1725 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1733 * This class contains several variants: ['timer_1ms', 'timer_secure',
1737 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1739 .sysc_offs = 0x0010,
1740 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1741 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1742 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1744 .sysc_fields = &omap_hwmod_sysc_type2,
1747 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1749 .sysc = &dra7xx_timer_1ms_sysc,
1752 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1754 .sysc_offs = 0x0010,
1755 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1756 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1757 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1759 .sysc_fields = &omap_hwmod_sysc_type2,
1762 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1764 .sysc = &dra7xx_timer_sysc,
1768 static struct omap_hwmod dra7xx_timer1_hwmod = {
1770 .class = &dra7xx_timer_1ms_hwmod_class,
1771 .clkdm_name = "wkupaon_clkdm",
1772 .main_clk = "timer1_gfclk_mux",
1775 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1776 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1777 .modulemode = MODULEMODE_SWCTRL,
1783 static struct omap_hwmod dra7xx_timer2_hwmod = {
1785 .class = &dra7xx_timer_1ms_hwmod_class,
1786 .clkdm_name = "l4per_clkdm",
1787 .main_clk = "timer2_gfclk_mux",
1790 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1791 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1792 .modulemode = MODULEMODE_SWCTRL,
1798 static struct omap_hwmod dra7xx_timer3_hwmod = {
1800 .class = &dra7xx_timer_hwmod_class,
1801 .clkdm_name = "l4per_clkdm",
1802 .main_clk = "timer3_gfclk_mux",
1805 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1806 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1807 .modulemode = MODULEMODE_SWCTRL,
1813 static struct omap_hwmod dra7xx_timer4_hwmod = {
1815 .class = &dra7xx_timer_hwmod_class,
1816 .clkdm_name = "l4per_clkdm",
1817 .main_clk = "timer4_gfclk_mux",
1820 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1821 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1822 .modulemode = MODULEMODE_SWCTRL,
1828 static struct omap_hwmod dra7xx_timer5_hwmod = {
1830 .class = &dra7xx_timer_hwmod_class,
1831 .clkdm_name = "ipu_clkdm",
1832 .main_clk = "timer5_gfclk_mux",
1835 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1836 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1837 .modulemode = MODULEMODE_SWCTRL,
1843 static struct omap_hwmod dra7xx_timer6_hwmod = {
1845 .class = &dra7xx_timer_hwmod_class,
1846 .clkdm_name = "ipu_clkdm",
1847 .main_clk = "timer6_gfclk_mux",
1850 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1851 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1852 .modulemode = MODULEMODE_SWCTRL,
1858 static struct omap_hwmod dra7xx_timer7_hwmod = {
1860 .class = &dra7xx_timer_hwmod_class,
1861 .clkdm_name = "ipu_clkdm",
1862 .main_clk = "timer7_gfclk_mux",
1865 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1866 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1867 .modulemode = MODULEMODE_SWCTRL,
1873 static struct omap_hwmod dra7xx_timer8_hwmod = {
1875 .class = &dra7xx_timer_hwmod_class,
1876 .clkdm_name = "ipu_clkdm",
1877 .main_clk = "timer8_gfclk_mux",
1880 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1881 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1882 .modulemode = MODULEMODE_SWCTRL,
1888 static struct omap_hwmod dra7xx_timer9_hwmod = {
1890 .class = &dra7xx_timer_hwmod_class,
1891 .clkdm_name = "l4per_clkdm",
1892 .main_clk = "timer9_gfclk_mux",
1895 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1896 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1897 .modulemode = MODULEMODE_SWCTRL,
1903 static struct omap_hwmod dra7xx_timer10_hwmod = {
1905 .class = &dra7xx_timer_1ms_hwmod_class,
1906 .clkdm_name = "l4per_clkdm",
1907 .main_clk = "timer10_gfclk_mux",
1910 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1911 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1912 .modulemode = MODULEMODE_SWCTRL,
1918 static struct omap_hwmod dra7xx_timer11_hwmod = {
1920 .class = &dra7xx_timer_hwmod_class,
1921 .clkdm_name = "l4per_clkdm",
1922 .main_clk = "timer11_gfclk_mux",
1925 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1926 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1927 .modulemode = MODULEMODE_SWCTRL,
1933 static struct omap_hwmod dra7xx_timer13_hwmod = {
1935 .class = &dra7xx_timer_hwmod_class,
1936 .clkdm_name = "l4per3_clkdm",
1937 .main_clk = "timer13_gfclk_mux",
1940 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1941 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1942 .modulemode = MODULEMODE_SWCTRL,
1948 static struct omap_hwmod dra7xx_timer14_hwmod = {
1950 .class = &dra7xx_timer_hwmod_class,
1951 .clkdm_name = "l4per3_clkdm",
1952 .main_clk = "timer14_gfclk_mux",
1955 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1956 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1957 .modulemode = MODULEMODE_SWCTRL,
1963 static struct omap_hwmod dra7xx_timer15_hwmod = {
1965 .class = &dra7xx_timer_hwmod_class,
1966 .clkdm_name = "l4per3_clkdm",
1967 .main_clk = "timer15_gfclk_mux",
1970 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1971 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1972 .modulemode = MODULEMODE_SWCTRL,
1978 static struct omap_hwmod dra7xx_timer16_hwmod = {
1980 .class = &dra7xx_timer_hwmod_class,
1981 .clkdm_name = "l4per3_clkdm",
1982 .main_clk = "timer16_gfclk_mux",
1985 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1986 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1987 .modulemode = MODULEMODE_SWCTRL,
1997 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1999 .sysc_offs = 0x0054,
2000 .syss_offs = 0x0058,
2001 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2002 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2003 SYSS_HAS_RESET_STATUS),
2004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2006 .sysc_fields = &omap_hwmod_sysc_type1,
2009 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2011 .sysc = &dra7xx_uart_sysc,
2015 static struct omap_hwmod dra7xx_uart1_hwmod = {
2017 .class = &dra7xx_uart_hwmod_class,
2018 .clkdm_name = "l4per_clkdm",
2019 .main_clk = "uart1_gfclk_mux",
2020 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2023 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2024 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2025 .modulemode = MODULEMODE_SWCTRL,
2031 static struct omap_hwmod dra7xx_uart2_hwmod = {
2033 .class = &dra7xx_uart_hwmod_class,
2034 .clkdm_name = "l4per_clkdm",
2035 .main_clk = "uart2_gfclk_mux",
2036 .flags = HWMOD_SWSUP_SIDLE_ACT,
2039 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2040 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2041 .modulemode = MODULEMODE_SWCTRL,
2047 static struct omap_hwmod dra7xx_uart3_hwmod = {
2049 .class = &dra7xx_uart_hwmod_class,
2050 .clkdm_name = "l4per_clkdm",
2051 .main_clk = "uart3_gfclk_mux",
2052 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2055 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2056 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2057 .modulemode = MODULEMODE_SWCTRL,
2063 static struct omap_hwmod dra7xx_uart4_hwmod = {
2065 .class = &dra7xx_uart_hwmod_class,
2066 .clkdm_name = "l4per_clkdm",
2067 .main_clk = "uart4_gfclk_mux",
2068 .flags = HWMOD_SWSUP_SIDLE_ACT,
2071 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2072 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2073 .modulemode = MODULEMODE_SWCTRL,
2079 static struct omap_hwmod dra7xx_uart5_hwmod = {
2081 .class = &dra7xx_uart_hwmod_class,
2082 .clkdm_name = "l4per_clkdm",
2083 .main_clk = "uart5_gfclk_mux",
2084 .flags = HWMOD_SWSUP_SIDLE_ACT,
2087 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2088 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2089 .modulemode = MODULEMODE_SWCTRL,
2095 static struct omap_hwmod dra7xx_uart6_hwmod = {
2097 .class = &dra7xx_uart_hwmod_class,
2098 .clkdm_name = "ipu_clkdm",
2099 .main_clk = "uart6_gfclk_mux",
2100 .flags = HWMOD_SWSUP_SIDLE_ACT,
2103 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2104 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2105 .modulemode = MODULEMODE_SWCTRL,
2111 static struct omap_hwmod dra7xx_uart7_hwmod = {
2113 .class = &dra7xx_uart_hwmod_class,
2114 .clkdm_name = "l4per2_clkdm",
2115 .main_clk = "uart7_gfclk_mux",
2116 .flags = HWMOD_SWSUP_SIDLE_ACT,
2119 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2120 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2121 .modulemode = MODULEMODE_SWCTRL,
2127 static struct omap_hwmod dra7xx_uart8_hwmod = {
2129 .class = &dra7xx_uart_hwmod_class,
2130 .clkdm_name = "l4per2_clkdm",
2131 .main_clk = "uart8_gfclk_mux",
2132 .flags = HWMOD_SWSUP_SIDLE_ACT,
2135 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2136 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2137 .modulemode = MODULEMODE_SWCTRL,
2143 static struct omap_hwmod dra7xx_uart9_hwmod = {
2145 .class = &dra7xx_uart_hwmod_class,
2146 .clkdm_name = "l4per2_clkdm",
2147 .main_clk = "uart9_gfclk_mux",
2148 .flags = HWMOD_SWSUP_SIDLE_ACT,
2151 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2152 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2153 .modulemode = MODULEMODE_SWCTRL,
2159 static struct omap_hwmod dra7xx_uart10_hwmod = {
2161 .class = &dra7xx_uart_hwmod_class,
2162 .clkdm_name = "wkupaon_clkdm",
2163 .main_clk = "uart10_gfclk_mux",
2164 .flags = HWMOD_SWSUP_SIDLE_ACT,
2167 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2168 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2169 .modulemode = MODULEMODE_SWCTRL,
2175 * 'usb_otg_ss' class
2179 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2181 .sysc_offs = 0x0010,
2182 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2183 SYSC_HAS_SIDLEMODE),
2184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2185 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2186 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2187 .sysc_fields = &omap_hwmod_sysc_type2,
2190 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2191 .name = "usb_otg_ss",
2192 .sysc = &dra7xx_usb_otg_ss_sysc,
2196 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2197 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2200 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2201 .name = "usb_otg_ss1",
2202 .class = &dra7xx_usb_otg_ss_hwmod_class,
2203 .clkdm_name = "l3init_clkdm",
2204 .main_clk = "dpll_core_h13x2_ck",
2207 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2208 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2209 .modulemode = MODULEMODE_HWCTRL,
2212 .opt_clks = usb_otg_ss1_opt_clks,
2213 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2217 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2218 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2221 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2222 .name = "usb_otg_ss2",
2223 .class = &dra7xx_usb_otg_ss_hwmod_class,
2224 .clkdm_name = "l3init_clkdm",
2225 .main_clk = "dpll_core_h13x2_ck",
2228 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2229 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2230 .modulemode = MODULEMODE_HWCTRL,
2233 .opt_clks = usb_otg_ss2_opt_clks,
2234 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2238 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2239 .name = "usb_otg_ss3",
2240 .class = &dra7xx_usb_otg_ss_hwmod_class,
2241 .clkdm_name = "l3init_clkdm",
2242 .main_clk = "dpll_core_h13x2_ck",
2245 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2246 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2247 .modulemode = MODULEMODE_HWCTRL,
2253 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2254 .name = "usb_otg_ss4",
2255 .class = &dra7xx_usb_otg_ss_hwmod_class,
2256 .clkdm_name = "l3init_clkdm",
2257 .main_clk = "dpll_core_h13x2_ck",
2260 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2261 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2262 .modulemode = MODULEMODE_HWCTRL,
2272 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2277 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2279 .class = &dra7xx_vcp_hwmod_class,
2280 .clkdm_name = "l3main1_clkdm",
2281 .main_clk = "l3_iclk_div",
2284 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2285 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2291 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2293 .class = &dra7xx_vcp_hwmod_class,
2294 .clkdm_name = "l3main1_clkdm",
2295 .main_clk = "l3_iclk_div",
2298 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2299 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2309 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2311 .sysc_offs = 0x0010,
2312 .syss_offs = 0x0014,
2313 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2314 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2315 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2317 .sysc_fields = &omap_hwmod_sysc_type1,
2320 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2322 .sysc = &dra7xx_wd_timer_sysc,
2323 .pre_shutdown = &omap2_wd_timer_disable,
2324 .reset = &omap2_wd_timer_reset,
2328 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2329 .name = "wd_timer2",
2330 .class = &dra7xx_wd_timer_hwmod_class,
2331 .clkdm_name = "wkupaon_clkdm",
2332 .main_clk = "sys_32k_ck",
2335 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2336 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2337 .modulemode = MODULEMODE_SWCTRL,
2347 /* l3_main_1 -> dmm */
2348 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2349 .master = &dra7xx_l3_main_1_hwmod,
2350 .slave = &dra7xx_dmm_hwmod,
2351 .clk = "l3_iclk_div",
2352 .user = OCP_USER_SDMA,
2355 /* l3_main_2 -> l3_instr */
2356 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2357 .master = &dra7xx_l3_main_2_hwmod,
2358 .slave = &dra7xx_l3_instr_hwmod,
2359 .clk = "l3_iclk_div",
2360 .user = OCP_USER_MPU | OCP_USER_SDMA,
2363 /* l4_cfg -> l3_main_1 */
2364 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2365 .master = &dra7xx_l4_cfg_hwmod,
2366 .slave = &dra7xx_l3_main_1_hwmod,
2367 .clk = "l3_iclk_div",
2368 .user = OCP_USER_MPU | OCP_USER_SDMA,
2371 /* mpu -> l3_main_1 */
2372 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2373 .master = &dra7xx_mpu_hwmod,
2374 .slave = &dra7xx_l3_main_1_hwmod,
2375 .clk = "l3_iclk_div",
2376 .user = OCP_USER_MPU,
2379 /* l3_main_1 -> l3_main_2 */
2380 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2381 .master = &dra7xx_l3_main_1_hwmod,
2382 .slave = &dra7xx_l3_main_2_hwmod,
2383 .clk = "l3_iclk_div",
2384 .user = OCP_USER_MPU,
2387 /* l4_cfg -> l3_main_2 */
2388 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2389 .master = &dra7xx_l4_cfg_hwmod,
2390 .slave = &dra7xx_l3_main_2_hwmod,
2391 .clk = "l3_iclk_div",
2392 .user = OCP_USER_MPU | OCP_USER_SDMA,
2395 /* l3_main_1 -> l4_cfg */
2396 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2397 .master = &dra7xx_l3_main_1_hwmod,
2398 .slave = &dra7xx_l4_cfg_hwmod,
2399 .clk = "l3_iclk_div",
2400 .user = OCP_USER_MPU | OCP_USER_SDMA,
2403 /* l3_main_1 -> l4_per1 */
2404 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2405 .master = &dra7xx_l3_main_1_hwmod,
2406 .slave = &dra7xx_l4_per1_hwmod,
2407 .clk = "l3_iclk_div",
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2411 /* l3_main_1 -> l4_per2 */
2412 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2413 .master = &dra7xx_l3_main_1_hwmod,
2414 .slave = &dra7xx_l4_per2_hwmod,
2415 .clk = "l3_iclk_div",
2416 .user = OCP_USER_MPU | OCP_USER_SDMA,
2419 /* l3_main_1 -> l4_per3 */
2420 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2421 .master = &dra7xx_l3_main_1_hwmod,
2422 .slave = &dra7xx_l4_per3_hwmod,
2423 .clk = "l3_iclk_div",
2424 .user = OCP_USER_MPU | OCP_USER_SDMA,
2427 /* l3_main_1 -> l4_wkup */
2428 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2429 .master = &dra7xx_l3_main_1_hwmod,
2430 .slave = &dra7xx_l4_wkup_hwmod,
2431 .clk = "wkupaon_iclk_mux",
2432 .user = OCP_USER_MPU | OCP_USER_SDMA,
2435 /* l4_per2 -> atl */
2436 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2437 .master = &dra7xx_l4_per2_hwmod,
2438 .slave = &dra7xx_atl_hwmod,
2439 .clk = "l3_iclk_div",
2440 .user = OCP_USER_MPU | OCP_USER_SDMA,
2443 /* l3_main_1 -> bb2d */
2444 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2445 .master = &dra7xx_l3_main_1_hwmod,
2446 .slave = &dra7xx_bb2d_hwmod,
2447 .clk = "l3_iclk_div",
2448 .user = OCP_USER_MPU | OCP_USER_SDMA,
2451 /* l4_wkup -> counter_32k */
2452 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2453 .master = &dra7xx_l4_wkup_hwmod,
2454 .slave = &dra7xx_counter_32k_hwmod,
2455 .clk = "wkupaon_iclk_mux",
2456 .user = OCP_USER_MPU | OCP_USER_SDMA,
2459 /* l4_wkup -> ctrl_module_wkup */
2460 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2461 .master = &dra7xx_l4_wkup_hwmod,
2462 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2463 .clk = "wkupaon_iclk_mux",
2464 .user = OCP_USER_MPU | OCP_USER_SDMA,
2467 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2468 .master = &dra7xx_l4_per2_hwmod,
2469 .slave = &dra7xx_gmac_hwmod,
2470 .clk = "dpll_gmac_ck",
2471 .user = OCP_USER_MPU,
2474 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2475 .master = &dra7xx_gmac_hwmod,
2476 .slave = &dra7xx_mdio_hwmod,
2477 .user = OCP_USER_MPU,
2480 /* l4_wkup -> dcan1 */
2481 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2482 .master = &dra7xx_l4_wkup_hwmod,
2483 .slave = &dra7xx_dcan1_hwmod,
2484 .clk = "wkupaon_iclk_mux",
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2488 /* l4_per2 -> dcan2 */
2489 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2490 .master = &dra7xx_l4_per2_hwmod,
2491 .slave = &dra7xx_dcan2_hwmod,
2492 .clk = "l3_iclk_div",
2493 .user = OCP_USER_MPU | OCP_USER_SDMA,
2496 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2498 .pa_start = 0x4a056000,
2499 .pa_end = 0x4a056fff,
2500 .flags = ADDR_TYPE_RT
2505 /* l4_cfg -> dma_system */
2506 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2507 .master = &dra7xx_l4_cfg_hwmod,
2508 .slave = &dra7xx_dma_system_hwmod,
2509 .clk = "l3_iclk_div",
2510 .addr = dra7xx_dma_system_addrs,
2511 .user = OCP_USER_MPU | OCP_USER_SDMA,
2514 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2517 .pa_start = 0x58000000,
2518 .pa_end = 0x5800007f,
2519 .flags = ADDR_TYPE_RT
2523 /* l3_main_1 -> dss */
2524 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2525 .master = &dra7xx_l3_main_1_hwmod,
2526 .slave = &dra7xx_dss_hwmod,
2527 .clk = "l3_iclk_div",
2528 .addr = dra7xx_dss_addrs,
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2535 .pa_start = 0x58001000,
2536 .pa_end = 0x58001fff,
2537 .flags = ADDR_TYPE_RT
2541 /* l3_main_1 -> dispc */
2542 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2543 .master = &dra7xx_l3_main_1_hwmod,
2544 .slave = &dra7xx_dss_dispc_hwmod,
2545 .clk = "l3_iclk_div",
2546 .addr = dra7xx_dss_dispc_addrs,
2547 .user = OCP_USER_MPU | OCP_USER_SDMA,
2550 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2553 .pa_start = 0x58040000,
2554 .pa_end = 0x580400ff,
2555 .flags = ADDR_TYPE_RT
2560 /* l3_main_1 -> dispc */
2561 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2562 .master = &dra7xx_l3_main_1_hwmod,
2563 .slave = &dra7xx_dss_hdmi_hwmod,
2564 .clk = "l3_iclk_div",
2565 .addr = dra7xx_dss_hdmi_addrs,
2566 .user = OCP_USER_MPU | OCP_USER_SDMA,
2569 /* l4_per1 -> elm */
2570 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2571 .master = &dra7xx_l4_per1_hwmod,
2572 .slave = &dra7xx_elm_hwmod,
2573 .clk = "l3_iclk_div",
2574 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577 /* l4_wkup -> gpio1 */
2578 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2579 .master = &dra7xx_l4_wkup_hwmod,
2580 .slave = &dra7xx_gpio1_hwmod,
2581 .clk = "wkupaon_iclk_mux",
2582 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585 /* l4_per1 -> gpio2 */
2586 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2587 .master = &dra7xx_l4_per1_hwmod,
2588 .slave = &dra7xx_gpio2_hwmod,
2589 .clk = "l3_iclk_div",
2590 .user = OCP_USER_MPU | OCP_USER_SDMA,
2593 /* l4_per1 -> gpio3 */
2594 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2595 .master = &dra7xx_l4_per1_hwmod,
2596 .slave = &dra7xx_gpio3_hwmod,
2597 .clk = "l3_iclk_div",
2598 .user = OCP_USER_MPU | OCP_USER_SDMA,
2601 /* l4_per1 -> gpio4 */
2602 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2603 .master = &dra7xx_l4_per1_hwmod,
2604 .slave = &dra7xx_gpio4_hwmod,
2605 .clk = "l3_iclk_div",
2606 .user = OCP_USER_MPU | OCP_USER_SDMA,
2609 /* l4_per1 -> gpio5 */
2610 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2611 .master = &dra7xx_l4_per1_hwmod,
2612 .slave = &dra7xx_gpio5_hwmod,
2613 .clk = "l3_iclk_div",
2614 .user = OCP_USER_MPU | OCP_USER_SDMA,
2617 /* l4_per1 -> gpio6 */
2618 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2619 .master = &dra7xx_l4_per1_hwmod,
2620 .slave = &dra7xx_gpio6_hwmod,
2621 .clk = "l3_iclk_div",
2622 .user = OCP_USER_MPU | OCP_USER_SDMA,
2625 /* l4_per1 -> gpio7 */
2626 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2627 .master = &dra7xx_l4_per1_hwmod,
2628 .slave = &dra7xx_gpio7_hwmod,
2629 .clk = "l3_iclk_div",
2630 .user = OCP_USER_MPU | OCP_USER_SDMA,
2633 /* l4_per1 -> gpio8 */
2634 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2635 .master = &dra7xx_l4_per1_hwmod,
2636 .slave = &dra7xx_gpio8_hwmod,
2637 .clk = "l3_iclk_div",
2638 .user = OCP_USER_MPU | OCP_USER_SDMA,
2641 /* l3_main_1 -> gpmc */
2642 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2643 .master = &dra7xx_l3_main_1_hwmod,
2644 .slave = &dra7xx_gpmc_hwmod,
2645 .clk = "l3_iclk_div",
2646 .user = OCP_USER_MPU | OCP_USER_SDMA,
2649 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2651 .pa_start = 0x480b2000,
2652 .pa_end = 0x480b201f,
2653 .flags = ADDR_TYPE_RT
2658 /* l4_per1 -> hdq1w */
2659 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2660 .master = &dra7xx_l4_per1_hwmod,
2661 .slave = &dra7xx_hdq1w_hwmod,
2662 .clk = "l3_iclk_div",
2663 .addr = dra7xx_hdq1w_addrs,
2664 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667 /* l4_per1 -> i2c1 */
2668 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2669 .master = &dra7xx_l4_per1_hwmod,
2670 .slave = &dra7xx_i2c1_hwmod,
2671 .clk = "l3_iclk_div",
2672 .user = OCP_USER_MPU | OCP_USER_SDMA,
2675 /* l4_per1 -> i2c2 */
2676 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2677 .master = &dra7xx_l4_per1_hwmod,
2678 .slave = &dra7xx_i2c2_hwmod,
2679 .clk = "l3_iclk_div",
2680 .user = OCP_USER_MPU | OCP_USER_SDMA,
2683 /* l4_per1 -> i2c3 */
2684 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2685 .master = &dra7xx_l4_per1_hwmod,
2686 .slave = &dra7xx_i2c3_hwmod,
2687 .clk = "l3_iclk_div",
2688 .user = OCP_USER_MPU | OCP_USER_SDMA,
2691 /* l4_per1 -> i2c4 */
2692 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2693 .master = &dra7xx_l4_per1_hwmod,
2694 .slave = &dra7xx_i2c4_hwmod,
2695 .clk = "l3_iclk_div",
2696 .user = OCP_USER_MPU | OCP_USER_SDMA,
2699 /* l4_per1 -> i2c5 */
2700 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2701 .master = &dra7xx_l4_per1_hwmod,
2702 .slave = &dra7xx_i2c5_hwmod,
2703 .clk = "l3_iclk_div",
2704 .user = OCP_USER_MPU | OCP_USER_SDMA,
2707 /* l4_cfg -> mailbox1 */
2708 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2709 .master = &dra7xx_l4_cfg_hwmod,
2710 .slave = &dra7xx_mailbox1_hwmod,
2711 .clk = "l3_iclk_div",
2712 .user = OCP_USER_MPU | OCP_USER_SDMA,
2715 /* l4_per3 -> mailbox2 */
2716 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2717 .master = &dra7xx_l4_per3_hwmod,
2718 .slave = &dra7xx_mailbox2_hwmod,
2719 .clk = "l3_iclk_div",
2720 .user = OCP_USER_MPU | OCP_USER_SDMA,
2723 /* l4_per3 -> mailbox3 */
2724 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2725 .master = &dra7xx_l4_per3_hwmod,
2726 .slave = &dra7xx_mailbox3_hwmod,
2727 .clk = "l3_iclk_div",
2728 .user = OCP_USER_MPU | OCP_USER_SDMA,
2731 /* l4_per3 -> mailbox4 */
2732 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2733 .master = &dra7xx_l4_per3_hwmod,
2734 .slave = &dra7xx_mailbox4_hwmod,
2735 .clk = "l3_iclk_div",
2736 .user = OCP_USER_MPU | OCP_USER_SDMA,
2739 /* l4_per3 -> mailbox5 */
2740 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2741 .master = &dra7xx_l4_per3_hwmod,
2742 .slave = &dra7xx_mailbox5_hwmod,
2743 .clk = "l3_iclk_div",
2744 .user = OCP_USER_MPU | OCP_USER_SDMA,
2747 /* l4_per3 -> mailbox6 */
2748 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2749 .master = &dra7xx_l4_per3_hwmod,
2750 .slave = &dra7xx_mailbox6_hwmod,
2751 .clk = "l3_iclk_div",
2752 .user = OCP_USER_MPU | OCP_USER_SDMA,
2755 /* l4_per3 -> mailbox7 */
2756 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2757 .master = &dra7xx_l4_per3_hwmod,
2758 .slave = &dra7xx_mailbox7_hwmod,
2759 .clk = "l3_iclk_div",
2760 .user = OCP_USER_MPU | OCP_USER_SDMA,
2763 /* l4_per3 -> mailbox8 */
2764 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2765 .master = &dra7xx_l4_per3_hwmod,
2766 .slave = &dra7xx_mailbox8_hwmod,
2767 .clk = "l3_iclk_div",
2768 .user = OCP_USER_MPU | OCP_USER_SDMA,
2771 /* l4_per3 -> mailbox9 */
2772 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2773 .master = &dra7xx_l4_per3_hwmod,
2774 .slave = &dra7xx_mailbox9_hwmod,
2775 .clk = "l3_iclk_div",
2776 .user = OCP_USER_MPU | OCP_USER_SDMA,
2779 /* l4_per3 -> mailbox10 */
2780 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2781 .master = &dra7xx_l4_per3_hwmod,
2782 .slave = &dra7xx_mailbox10_hwmod,
2783 .clk = "l3_iclk_div",
2784 .user = OCP_USER_MPU | OCP_USER_SDMA,
2787 /* l4_per3 -> mailbox11 */
2788 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2789 .master = &dra7xx_l4_per3_hwmod,
2790 .slave = &dra7xx_mailbox11_hwmod,
2791 .clk = "l3_iclk_div",
2792 .user = OCP_USER_MPU | OCP_USER_SDMA,
2795 /* l4_per3 -> mailbox12 */
2796 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2797 .master = &dra7xx_l4_per3_hwmod,
2798 .slave = &dra7xx_mailbox12_hwmod,
2799 .clk = "l3_iclk_div",
2800 .user = OCP_USER_MPU | OCP_USER_SDMA,
2803 /* l4_per3 -> mailbox13 */
2804 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2805 .master = &dra7xx_l4_per3_hwmod,
2806 .slave = &dra7xx_mailbox13_hwmod,
2807 .clk = "l3_iclk_div",
2808 .user = OCP_USER_MPU | OCP_USER_SDMA,
2811 /* l4_per1 -> mcspi1 */
2812 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2813 .master = &dra7xx_l4_per1_hwmod,
2814 .slave = &dra7xx_mcspi1_hwmod,
2815 .clk = "l3_iclk_div",
2816 .user = OCP_USER_MPU | OCP_USER_SDMA,
2819 /* l4_per1 -> mcspi2 */
2820 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2821 .master = &dra7xx_l4_per1_hwmod,
2822 .slave = &dra7xx_mcspi2_hwmod,
2823 .clk = "l3_iclk_div",
2824 .user = OCP_USER_MPU | OCP_USER_SDMA,
2827 /* l4_per1 -> mcspi3 */
2828 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2829 .master = &dra7xx_l4_per1_hwmod,
2830 .slave = &dra7xx_mcspi3_hwmod,
2831 .clk = "l3_iclk_div",
2832 .user = OCP_USER_MPU | OCP_USER_SDMA,
2835 /* l4_per1 -> mcspi4 */
2836 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2837 .master = &dra7xx_l4_per1_hwmod,
2838 .slave = &dra7xx_mcspi4_hwmod,
2839 .clk = "l3_iclk_div",
2840 .user = OCP_USER_MPU | OCP_USER_SDMA,
2843 /* l4_per1 -> mmc1 */
2844 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2845 .master = &dra7xx_l4_per1_hwmod,
2846 .slave = &dra7xx_mmc1_hwmod,
2847 .clk = "l3_iclk_div",
2848 .user = OCP_USER_MPU | OCP_USER_SDMA,
2851 /* l4_per1 -> mmc2 */
2852 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2853 .master = &dra7xx_l4_per1_hwmod,
2854 .slave = &dra7xx_mmc2_hwmod,
2855 .clk = "l3_iclk_div",
2856 .user = OCP_USER_MPU | OCP_USER_SDMA,
2859 /* l4_per1 -> mmc3 */
2860 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2861 .master = &dra7xx_l4_per1_hwmod,
2862 .slave = &dra7xx_mmc3_hwmod,
2863 .clk = "l3_iclk_div",
2864 .user = OCP_USER_MPU | OCP_USER_SDMA,
2867 /* l4_per1 -> mmc4 */
2868 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2869 .master = &dra7xx_l4_per1_hwmod,
2870 .slave = &dra7xx_mmc4_hwmod,
2871 .clk = "l3_iclk_div",
2872 .user = OCP_USER_MPU | OCP_USER_SDMA,
2876 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2877 .master = &dra7xx_l4_cfg_hwmod,
2878 .slave = &dra7xx_mpu_hwmod,
2879 .clk = "l3_iclk_div",
2880 .user = OCP_USER_MPU | OCP_USER_SDMA,
2883 /* l4_cfg -> ocp2scp1 */
2884 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2885 .master = &dra7xx_l4_cfg_hwmod,
2886 .slave = &dra7xx_ocp2scp1_hwmod,
2887 .clk = "l4_root_clk_div",
2888 .user = OCP_USER_MPU | OCP_USER_SDMA,
2891 /* l4_cfg -> ocp2scp3 */
2892 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2893 .master = &dra7xx_l4_cfg_hwmod,
2894 .slave = &dra7xx_ocp2scp3_hwmod,
2895 .clk = "l4_root_clk_div",
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2899 /* l3_main_1 -> pciess1 */
2900 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2901 .master = &dra7xx_l3_main_1_hwmod,
2902 .slave = &dra7xx_pciess1_hwmod,
2903 .clk = "l3_iclk_div",
2904 .user = OCP_USER_MPU | OCP_USER_SDMA,
2907 /* l4_cfg -> pciess1 */
2908 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2909 .master = &dra7xx_l4_cfg_hwmod,
2910 .slave = &dra7xx_pciess1_hwmod,
2911 .clk = "l4_root_clk_div",
2912 .user = OCP_USER_MPU | OCP_USER_SDMA,
2915 /* l3_main_1 -> pciess2 */
2916 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2917 .master = &dra7xx_l3_main_1_hwmod,
2918 .slave = &dra7xx_pciess2_hwmod,
2919 .clk = "l3_iclk_div",
2920 .user = OCP_USER_MPU | OCP_USER_SDMA,
2923 /* l4_cfg -> pciess2 */
2924 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2925 .master = &dra7xx_l4_cfg_hwmod,
2926 .slave = &dra7xx_pciess2_hwmod,
2927 .clk = "l4_root_clk_div",
2928 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2933 .pa_start = 0x4b300000,
2934 .pa_end = 0x4b30007f,
2935 .flags = ADDR_TYPE_RT
2940 /* l3_main_1 -> qspi */
2941 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2942 .master = &dra7xx_l3_main_1_hwmod,
2943 .slave = &dra7xx_qspi_hwmod,
2944 .clk = "l3_iclk_div",
2945 .addr = dra7xx_qspi_addrs,
2946 .user = OCP_USER_MPU | OCP_USER_SDMA,
2949 /* l4_per3 -> rtcss */
2950 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2951 .master = &dra7xx_l4_per3_hwmod,
2952 .slave = &dra7xx_rtcss_hwmod,
2953 .clk = "l4_root_clk_div",
2954 .user = OCP_USER_MPU | OCP_USER_SDMA,
2957 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2960 .pa_start = 0x4a141100,
2961 .pa_end = 0x4a141107,
2962 .flags = ADDR_TYPE_RT
2967 /* l4_cfg -> sata */
2968 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2969 .master = &dra7xx_l4_cfg_hwmod,
2970 .slave = &dra7xx_sata_hwmod,
2971 .clk = "l3_iclk_div",
2972 .addr = dra7xx_sata_addrs,
2973 .user = OCP_USER_MPU | OCP_USER_SDMA,
2976 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2978 .pa_start = 0x4a0dd000,
2979 .pa_end = 0x4a0dd07f,
2980 .flags = ADDR_TYPE_RT
2985 /* l4_cfg -> smartreflex_core */
2986 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2987 .master = &dra7xx_l4_cfg_hwmod,
2988 .slave = &dra7xx_smartreflex_core_hwmod,
2989 .clk = "l4_root_clk_div",
2990 .addr = dra7xx_smartreflex_core_addrs,
2991 .user = OCP_USER_MPU | OCP_USER_SDMA,
2994 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2996 .pa_start = 0x4a0d9000,
2997 .pa_end = 0x4a0d907f,
2998 .flags = ADDR_TYPE_RT
3003 /* l4_cfg -> smartreflex_mpu */
3004 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3005 .master = &dra7xx_l4_cfg_hwmod,
3006 .slave = &dra7xx_smartreflex_mpu_hwmod,
3007 .clk = "l4_root_clk_div",
3008 .addr = dra7xx_smartreflex_mpu_addrs,
3009 .user = OCP_USER_MPU | OCP_USER_SDMA,
3012 /* l4_cfg -> spinlock */
3013 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3014 .master = &dra7xx_l4_cfg_hwmod,
3015 .slave = &dra7xx_spinlock_hwmod,
3016 .clk = "l3_iclk_div",
3017 .user = OCP_USER_MPU | OCP_USER_SDMA,
3020 /* l4_wkup -> timer1 */
3021 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3022 .master = &dra7xx_l4_wkup_hwmod,
3023 .slave = &dra7xx_timer1_hwmod,
3024 .clk = "wkupaon_iclk_mux",
3025 .user = OCP_USER_MPU | OCP_USER_SDMA,
3028 /* l4_per1 -> timer2 */
3029 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3030 .master = &dra7xx_l4_per1_hwmod,
3031 .slave = &dra7xx_timer2_hwmod,
3032 .clk = "l3_iclk_div",
3033 .user = OCP_USER_MPU | OCP_USER_SDMA,
3036 /* l4_per1 -> timer3 */
3037 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3038 .master = &dra7xx_l4_per1_hwmod,
3039 .slave = &dra7xx_timer3_hwmod,
3040 .clk = "l3_iclk_div",
3041 .user = OCP_USER_MPU | OCP_USER_SDMA,
3044 /* l4_per1 -> timer4 */
3045 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3046 .master = &dra7xx_l4_per1_hwmod,
3047 .slave = &dra7xx_timer4_hwmod,
3048 .clk = "l3_iclk_div",
3049 .user = OCP_USER_MPU | OCP_USER_SDMA,
3052 /* l4_per3 -> timer5 */
3053 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3054 .master = &dra7xx_l4_per3_hwmod,
3055 .slave = &dra7xx_timer5_hwmod,
3056 .clk = "l3_iclk_div",
3057 .user = OCP_USER_MPU | OCP_USER_SDMA,
3060 /* l4_per3 -> timer6 */
3061 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3062 .master = &dra7xx_l4_per3_hwmod,
3063 .slave = &dra7xx_timer6_hwmod,
3064 .clk = "l3_iclk_div",
3065 .user = OCP_USER_MPU | OCP_USER_SDMA,
3068 /* l4_per3 -> timer7 */
3069 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3070 .master = &dra7xx_l4_per3_hwmod,
3071 .slave = &dra7xx_timer7_hwmod,
3072 .clk = "l3_iclk_div",
3073 .user = OCP_USER_MPU | OCP_USER_SDMA,
3076 /* l4_per3 -> timer8 */
3077 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3078 .master = &dra7xx_l4_per3_hwmod,
3079 .slave = &dra7xx_timer8_hwmod,
3080 .clk = "l3_iclk_div",
3081 .user = OCP_USER_MPU | OCP_USER_SDMA,
3084 /* l4_per1 -> timer9 */
3085 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3086 .master = &dra7xx_l4_per1_hwmod,
3087 .slave = &dra7xx_timer9_hwmod,
3088 .clk = "l3_iclk_div",
3089 .user = OCP_USER_MPU | OCP_USER_SDMA,
3092 /* l4_per1 -> timer10 */
3093 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3094 .master = &dra7xx_l4_per1_hwmod,
3095 .slave = &dra7xx_timer10_hwmod,
3096 .clk = "l3_iclk_div",
3097 .user = OCP_USER_MPU | OCP_USER_SDMA,
3100 /* l4_per1 -> timer11 */
3101 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3102 .master = &dra7xx_l4_per1_hwmod,
3103 .slave = &dra7xx_timer11_hwmod,
3104 .clk = "l3_iclk_div",
3105 .user = OCP_USER_MPU | OCP_USER_SDMA,
3108 /* l4_per3 -> timer13 */
3109 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3110 .master = &dra7xx_l4_per3_hwmod,
3111 .slave = &dra7xx_timer13_hwmod,
3112 .clk = "l3_iclk_div",
3113 .user = OCP_USER_MPU | OCP_USER_SDMA,
3116 /* l4_per3 -> timer14 */
3117 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3118 .master = &dra7xx_l4_per3_hwmod,
3119 .slave = &dra7xx_timer14_hwmod,
3120 .clk = "l3_iclk_div",
3121 .user = OCP_USER_MPU | OCP_USER_SDMA,
3124 /* l4_per3 -> timer15 */
3125 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3126 .master = &dra7xx_l4_per3_hwmod,
3127 .slave = &dra7xx_timer15_hwmod,
3128 .clk = "l3_iclk_div",
3129 .user = OCP_USER_MPU | OCP_USER_SDMA,
3132 /* l4_per3 -> timer16 */
3133 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3134 .master = &dra7xx_l4_per3_hwmod,
3135 .slave = &dra7xx_timer16_hwmod,
3136 .clk = "l3_iclk_div",
3137 .user = OCP_USER_MPU | OCP_USER_SDMA,
3140 /* l4_per1 -> uart1 */
3141 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3142 .master = &dra7xx_l4_per1_hwmod,
3143 .slave = &dra7xx_uart1_hwmod,
3144 .clk = "l3_iclk_div",
3145 .user = OCP_USER_MPU | OCP_USER_SDMA,
3148 /* l4_per1 -> uart2 */
3149 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3150 .master = &dra7xx_l4_per1_hwmod,
3151 .slave = &dra7xx_uart2_hwmod,
3152 .clk = "l3_iclk_div",
3153 .user = OCP_USER_MPU | OCP_USER_SDMA,
3156 /* l4_per1 -> uart3 */
3157 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3158 .master = &dra7xx_l4_per1_hwmod,
3159 .slave = &dra7xx_uart3_hwmod,
3160 .clk = "l3_iclk_div",
3161 .user = OCP_USER_MPU | OCP_USER_SDMA,
3164 /* l4_per1 -> uart4 */
3165 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3166 .master = &dra7xx_l4_per1_hwmod,
3167 .slave = &dra7xx_uart4_hwmod,
3168 .clk = "l3_iclk_div",
3169 .user = OCP_USER_MPU | OCP_USER_SDMA,
3172 /* l4_per1 -> uart5 */
3173 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3174 .master = &dra7xx_l4_per1_hwmod,
3175 .slave = &dra7xx_uart5_hwmod,
3176 .clk = "l3_iclk_div",
3177 .user = OCP_USER_MPU | OCP_USER_SDMA,
3180 /* l4_per1 -> uart6 */
3181 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3182 .master = &dra7xx_l4_per1_hwmod,
3183 .slave = &dra7xx_uart6_hwmod,
3184 .clk = "l3_iclk_div",
3185 .user = OCP_USER_MPU | OCP_USER_SDMA,
3188 /* l4_per2 -> uart7 */
3189 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3190 .master = &dra7xx_l4_per2_hwmod,
3191 .slave = &dra7xx_uart7_hwmod,
3192 .clk = "l3_iclk_div",
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3196 /* l4_per2 -> uart8 */
3197 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3198 .master = &dra7xx_l4_per2_hwmod,
3199 .slave = &dra7xx_uart8_hwmod,
3200 .clk = "l3_iclk_div",
3201 .user = OCP_USER_MPU | OCP_USER_SDMA,
3204 /* l4_per2 -> uart9 */
3205 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3206 .master = &dra7xx_l4_per2_hwmod,
3207 .slave = &dra7xx_uart9_hwmod,
3208 .clk = "l3_iclk_div",
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3212 /* l4_wkup -> uart10 */
3213 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3214 .master = &dra7xx_l4_wkup_hwmod,
3215 .slave = &dra7xx_uart10_hwmod,
3216 .clk = "wkupaon_iclk_mux",
3217 .user = OCP_USER_MPU | OCP_USER_SDMA,
3220 /* l4_per3 -> usb_otg_ss1 */
3221 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3222 .master = &dra7xx_l4_per3_hwmod,
3223 .slave = &dra7xx_usb_otg_ss1_hwmod,
3224 .clk = "dpll_core_h13x2_ck",
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3228 /* l4_per3 -> usb_otg_ss2 */
3229 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3230 .master = &dra7xx_l4_per3_hwmod,
3231 .slave = &dra7xx_usb_otg_ss2_hwmod,
3232 .clk = "dpll_core_h13x2_ck",
3233 .user = OCP_USER_MPU | OCP_USER_SDMA,
3236 /* l4_per3 -> usb_otg_ss3 */
3237 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3238 .master = &dra7xx_l4_per3_hwmod,
3239 .slave = &dra7xx_usb_otg_ss3_hwmod,
3240 .clk = "dpll_core_h13x2_ck",
3241 .user = OCP_USER_MPU | OCP_USER_SDMA,
3244 /* l4_per3 -> usb_otg_ss4 */
3245 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3246 .master = &dra7xx_l4_per3_hwmod,
3247 .slave = &dra7xx_usb_otg_ss4_hwmod,
3248 .clk = "dpll_core_h13x2_ck",
3249 .user = OCP_USER_MPU | OCP_USER_SDMA,
3252 /* l3_main_1 -> vcp1 */
3253 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3254 .master = &dra7xx_l3_main_1_hwmod,
3255 .slave = &dra7xx_vcp1_hwmod,
3256 .clk = "l3_iclk_div",
3257 .user = OCP_USER_MPU | OCP_USER_SDMA,
3260 /* l4_per2 -> vcp1 */
3261 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3262 .master = &dra7xx_l4_per2_hwmod,
3263 .slave = &dra7xx_vcp1_hwmod,
3264 .clk = "l3_iclk_div",
3265 .user = OCP_USER_MPU | OCP_USER_SDMA,
3268 /* l3_main_1 -> vcp2 */
3269 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3270 .master = &dra7xx_l3_main_1_hwmod,
3271 .slave = &dra7xx_vcp2_hwmod,
3272 .clk = "l3_iclk_div",
3273 .user = OCP_USER_MPU | OCP_USER_SDMA,
3276 /* l4_per2 -> vcp2 */
3277 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3278 .master = &dra7xx_l4_per2_hwmod,
3279 .slave = &dra7xx_vcp2_hwmod,
3280 .clk = "l3_iclk_div",
3281 .user = OCP_USER_MPU | OCP_USER_SDMA,
3284 /* l4_wkup -> wd_timer2 */
3285 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3286 .master = &dra7xx_l4_wkup_hwmod,
3287 .slave = &dra7xx_wd_timer2_hwmod,
3288 .clk = "wkupaon_iclk_mux",
3289 .user = OCP_USER_MPU | OCP_USER_SDMA,
3292 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3293 &dra7xx_l3_main_1__dmm,
3294 &dra7xx_l3_main_2__l3_instr,
3295 &dra7xx_l4_cfg__l3_main_1,
3296 &dra7xx_mpu__l3_main_1,
3297 &dra7xx_l3_main_1__l3_main_2,
3298 &dra7xx_l4_cfg__l3_main_2,
3299 &dra7xx_l3_main_1__l4_cfg,
3300 &dra7xx_l3_main_1__l4_per1,
3301 &dra7xx_l3_main_1__l4_per2,
3302 &dra7xx_l3_main_1__l4_per3,
3303 &dra7xx_l3_main_1__l4_wkup,
3304 &dra7xx_l4_per2__atl,
3305 &dra7xx_l3_main_1__bb2d,
3306 &dra7xx_l4_wkup__counter_32k,
3307 &dra7xx_l4_wkup__ctrl_module_wkup,
3308 &dra7xx_l4_wkup__dcan1,
3309 &dra7xx_l4_per2__dcan2,
3310 &dra7xx_l4_per2__cpgmac0,
3312 &dra7xx_l4_cfg__dma_system,
3313 &dra7xx_l3_main_1__dss,
3314 &dra7xx_l3_main_1__dispc,
3315 &dra7xx_l3_main_1__hdmi,
3316 &dra7xx_l4_per1__elm,
3317 &dra7xx_l4_wkup__gpio1,
3318 &dra7xx_l4_per1__gpio2,
3319 &dra7xx_l4_per1__gpio3,
3320 &dra7xx_l4_per1__gpio4,
3321 &dra7xx_l4_per1__gpio5,
3322 &dra7xx_l4_per1__gpio6,
3323 &dra7xx_l4_per1__gpio7,
3324 &dra7xx_l4_per1__gpio8,
3325 &dra7xx_l3_main_1__gpmc,
3326 &dra7xx_l4_per1__hdq1w,
3327 &dra7xx_l4_per1__i2c1,
3328 &dra7xx_l4_per1__i2c2,
3329 &dra7xx_l4_per1__i2c3,
3330 &dra7xx_l4_per1__i2c4,
3331 &dra7xx_l4_per1__i2c5,
3332 &dra7xx_l4_cfg__mailbox1,
3333 &dra7xx_l4_per3__mailbox2,
3334 &dra7xx_l4_per3__mailbox3,
3335 &dra7xx_l4_per3__mailbox4,
3336 &dra7xx_l4_per3__mailbox5,
3337 &dra7xx_l4_per3__mailbox6,
3338 &dra7xx_l4_per3__mailbox7,
3339 &dra7xx_l4_per3__mailbox8,
3340 &dra7xx_l4_per3__mailbox9,
3341 &dra7xx_l4_per3__mailbox10,
3342 &dra7xx_l4_per3__mailbox11,
3343 &dra7xx_l4_per3__mailbox12,
3344 &dra7xx_l4_per3__mailbox13,
3345 &dra7xx_l4_per1__mcspi1,
3346 &dra7xx_l4_per1__mcspi2,
3347 &dra7xx_l4_per1__mcspi3,
3348 &dra7xx_l4_per1__mcspi4,
3349 &dra7xx_l4_per1__mmc1,
3350 &dra7xx_l4_per1__mmc2,
3351 &dra7xx_l4_per1__mmc3,
3352 &dra7xx_l4_per1__mmc4,
3353 &dra7xx_l4_cfg__mpu,
3354 &dra7xx_l4_cfg__ocp2scp1,
3355 &dra7xx_l4_cfg__ocp2scp3,
3356 &dra7xx_l3_main_1__pciess1,
3357 &dra7xx_l4_cfg__pciess1,
3358 &dra7xx_l3_main_1__pciess2,
3359 &dra7xx_l4_cfg__pciess2,
3360 &dra7xx_l3_main_1__qspi,
3361 &dra7xx_l4_per3__rtcss,
3362 &dra7xx_l4_cfg__sata,
3363 &dra7xx_l4_cfg__smartreflex_core,
3364 &dra7xx_l4_cfg__smartreflex_mpu,
3365 &dra7xx_l4_cfg__spinlock,
3366 &dra7xx_l4_wkup__timer1,
3367 &dra7xx_l4_per1__timer2,
3368 &dra7xx_l4_per1__timer3,
3369 &dra7xx_l4_per1__timer4,
3370 &dra7xx_l4_per3__timer5,
3371 &dra7xx_l4_per3__timer6,
3372 &dra7xx_l4_per3__timer7,
3373 &dra7xx_l4_per3__timer8,
3374 &dra7xx_l4_per1__timer9,
3375 &dra7xx_l4_per1__timer10,
3376 &dra7xx_l4_per1__timer11,
3377 &dra7xx_l4_per3__timer13,
3378 &dra7xx_l4_per3__timer14,
3379 &dra7xx_l4_per3__timer15,
3380 &dra7xx_l4_per3__timer16,
3381 &dra7xx_l4_per1__uart1,
3382 &dra7xx_l4_per1__uart2,
3383 &dra7xx_l4_per1__uart3,
3384 &dra7xx_l4_per1__uart4,
3385 &dra7xx_l4_per1__uart5,
3386 &dra7xx_l4_per1__uart6,
3387 &dra7xx_l4_per2__uart7,
3388 &dra7xx_l4_per2__uart8,
3389 &dra7xx_l4_per2__uart9,
3390 &dra7xx_l4_wkup__uart10,
3391 &dra7xx_l4_per3__usb_otg_ss1,
3392 &dra7xx_l4_per3__usb_otg_ss2,
3393 &dra7xx_l4_per3__usb_otg_ss3,
3394 &dra7xx_l3_main_1__vcp1,
3395 &dra7xx_l4_per2__vcp1,
3396 &dra7xx_l3_main_1__vcp2,
3397 &dra7xx_l4_per2__vcp2,
3398 &dra7xx_l4_wkup__wd_timer2,
3402 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3403 &dra7xx_l4_per3__usb_otg_ss4,
3407 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3411 int __init dra7xx_hwmod_init(void)
3416 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3418 if (!ret && soc_is_dra74x())
3419 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3420 else if (!ret && soc_is_dra72x())
3421 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);