arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/irq.h>
  30 #include <linux/time.h>
  31 #include <linux/gpio.h>
  32 #include <linux/platform_data/gpio-omap.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/system_misc.h>
  38
  39 #include <plat/clock.h>
  40 #include <plat/sram.h>
  41 #include <plat/dma.h>
  42
  43 #include "common.h"
  44 #include "prm2xxx_3xxx.h"
  45 #include "prm-regbits-24xx.h"
  46 #include "cm2xxx_3xxx.h"
  47 #include "cm-regbits-24xx.h"
  48 #include "sdrc.h"
  49 #include "pm.h"
  50 #include "control.h"
  51 #include "powerdomain.h"
  52 #include "clockdomain.h"
  53
  54 static void (*omap2_sram_idle)(void);
  55 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  56                                   void __iomem *sdrc_power);
  57
  58 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  59 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  60
  61 static struct clk *osc_ck, *emul_ck;
  62
  63 static int omap2_fclks_active(void)
  64 {
  65         u32 f1, f2;
  66
  67         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  68         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  69
  70         return (f1 | f2) ? 1 : 0;
  71 }
  72
  73 static int omap2_enter_full_retention(void)
  74 {
  75         u32 l;
  76
  77         /* There is 1 reference hold for all children of the oscillator
  78          * clock, the following will remove it. If no one else uses the
  79          * oscillator itself it will be disabled if/when we enter retention
  80          * mode.
  81          */
  82         clk_disable(osc_ck);
  83
  84         /* Clear old wake-up events */
  85         /* REVISIT: These write to reserved bits? */
  86         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  87         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  88         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  89
  90         /*
  91          * Set MPU powerdomain's next power state to RETENTION;
  92          * preserve logic state during retention
  93          */
  94         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
  95         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
  96
  97         /* Workaround to kill USB */
  98         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
  99         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 100
 101         omap2_gpio_prepare_for_idle(0);
 102
 103         /* One last check for pending IRQs to avoid extra latency due
 104          * to sleeping unnecessarily. */
 105         if (omap_irq_pending())
 106                 goto no_sleep;
 107
 108         /* Jump to SRAM suspend code */
 109         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 110                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 111                            OMAP_SDRC_REGADDR(SDRC_POWER));
 112
 113 no_sleep:
 114         omap2_gpio_resume_after_idle();
 115
 116         clk_enable(osc_ck);
 117
 118         /* clear CORE wake-up events */
 119         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 120         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 121
 122         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 123         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 124
 125         /* MPU domain wake events */
 126         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 127         if (l & 0x01)
 128                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
 129                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 130         if (l & 0x20)
 131                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
 132                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 133
 134         /* Mask future PRCM-to-MPU interrupts */
 135         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 136
 137         return 0;
 138 }
 139
 140 static int omap2_i2c_active(void)
 141 {
 142         u32 l;
 143
 144         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 145         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 146 }
 147
 148 static int sti_console_enabled;
 149
 150 static int omap2_allow_mpu_retention(void)
 151 {
 152         u32 l;
 153
 154         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 155         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 156         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 157                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 158                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 159                 return 0;
 160         /* Check for UART3. */
 161         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 162         if (l & OMAP24XX_EN_UART3_MASK)
 163                 return 0;
 164         if (sti_console_enabled)
 165                 return 0;
 166
 167         return 1;
 168 }
 169
 170 static void omap2_enter_mpu_retention(void)
 171 {
 172         /* Putting MPU into the WFI state while a transfer is active
 173          * seems to cause the I2C block to timeout. Why? Good question. */
 174         if (omap2_i2c_active())
 175                 return;
 176
 177         /* The peripherals seem not to be able to wake up the MPU when
 178          * it is in retention mode. */
 179         if (omap2_allow_mpu_retention()) {
 180                 /* REVISIT: These write to reserved bits? */
 181                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 182                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 183                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 184
 185                 /* Try to enter MPU retention */
 186                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 187                                   OMAP_LOGICRETSTATE_MASK,
 188                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 189         } else {
 190                 /* Block MPU retention */
 191
 192                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 193                                                  OMAP2_PM_PWSTCTRL);
 194         }
 195
 196         omap2_sram_idle();
 197 }
 198
 199 static int omap2_can_sleep(void)
 200 {
 201         if (omap2_fclks_active())
 202                 return 0;
 203         if (osc_ck->usecount > 1)
 204                 return 0;
 205         if (omap_dma_running())
 206                 return 0;
 207
 208         return 1;
 209 }
 210
 211 static void omap2_pm_idle(void)
 212 {
 213         local_fiq_disable();
 214
 215         if (!omap2_can_sleep()) {
 216                 if (omap_irq_pending())
 217                         goto out;
 218                 omap2_enter_mpu_retention();
 219                 goto out;
 220         }
 221
 222         if (omap_irq_pending())
 223                 goto out;
 224
 225         omap2_enter_full_retention();
 226
 227 out:
 228         local_fiq_enable();
 229 }
 230
 231 static void __init prcm_setup_regs(void)
 232 {
 233         int i, num_mem_banks;
 234         struct powerdomain *pwrdm;
 235
 236         /*
 237          * Enable autoidle
 238          * XXX This should be handled by hwmod code or PRCM init code
 239          */
 240         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 241                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 242
 243         /*
 244          * Set CORE powerdomain memory banks to retain their contents
 245          * during RETENTION
 246          */
 247         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 248         for (i = 0; i < num_mem_banks; i++)
 249                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 250
 251         /* Set CORE powerdomain's next power state to RETENTION */
 252         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 253
 254         /*
 255          * Set MPU powerdomain's next power state to RETENTION;
 256          * preserve logic state during retention
 257          */
 258         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 259         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 260
 261         /* Force-power down DSP, GFX powerdomains */
 262
 263         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 264         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 265         clkdm_sleep(dsp_clkdm);
 266
 267         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 268         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 269         clkdm_sleep(gfx_clkdm);
 270
 271         /* Enable hardware-supervised idle for all clkdms */
 272         clkdm_for_each(omap_pm_clkdms_setup, NULL);
 273         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 274
 275 #ifdef CONFIG_SUSPEND
 276         omap_pm_suspend = omap2_enter_full_retention;
 277 #endif
 278
 279         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 280          * stabilisation */
 281         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 282                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
 283
 284         /* Configure automatic voltage transition */
 285         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 286                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
 287         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 288                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 289                                 OMAP24XX_MEMRETCTRL_MASK |
 290                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 291                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 292                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 293
 294         /* Enable wake-up events */
 295         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 296                                 WKUP_MOD, PM_WKEN);
 297 }
 298
 299 int __init omap2_pm_init(void)
 300 {
 301         u32 l;
 302
 303         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 304         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 305         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 306
 307         /* Look up important powerdomains */
 308
 309         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 310         if (!mpu_pwrdm)
 311                 pr_err("PM: mpu_pwrdm not found\n");
 312
 313         core_pwrdm = pwrdm_lookup("core_pwrdm");
 314         if (!core_pwrdm)
 315                 pr_err("PM: core_pwrdm not found\n");
 316
 317         /* Look up important clockdomains */
 318
 319         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 320         if (!mpu_clkdm)
 321                 pr_err("PM: mpu_clkdm not found\n");
 322
 323         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 324         if (!wkup_clkdm)
 325                 pr_err("PM: wkup_clkdm not found\n");
 326
 327         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 328         if (!dsp_clkdm)
 329                 pr_err("PM: dsp_clkdm not found\n");
 330
 331         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 332         if (!gfx_clkdm)
 333                 pr_err("PM: gfx_clkdm not found\n");
 334
 335
 336         osc_ck = clk_get(NULL, "osc_ck");
 337         if (IS_ERR(osc_ck)) {
 338                 printk(KERN_ERR "could not get osc_ck\n");
 339                 return -ENODEV;
 340         }
 341
 342         if (cpu_is_omap242x()) {
 343                 emul_ck = clk_get(NULL, "emul_ck");
 344                 if (IS_ERR(emul_ck)) {
 345                         printk(KERN_ERR "could not get emul_ck\n");
 346                         clk_put(osc_ck);
 347                         return -ENODEV;
 348                 }
 349         }
 350
 351         prcm_setup_regs();
 352
 353         /*
 354          * We copy the assembler sleep/wakeup routines to SRAM.
 355          * These routines need to be in SRAM as that's the only
 356          * memory the MPU can see when it wakes up.
 357          */
 358         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 359                                          omap24xx_idle_loop_suspend_sz);
 360
 361         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 362                                             omap24xx_cpu_suspend_sz);
 363
 364         arm_pm_idle = omap2_pm_idle;
 365
 366         return 0;
 367 }