arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <mach/irqs.h>
  39 #include <mach/clock.h>
  40 #include <mach/sram.h>
  41 #include <mach/control.h>
  42 #include <mach/mux.h>
  43 #include <mach/dma.h>
  44 #include <mach/board.h>
  45
  46 #include "prm.h"
  47 #include "prm-regbits-24xx.h"
  48 #include "cm.h"
  49 #include "cm-regbits-24xx.h"
  50 #include "sdrc.h"
  51 #include "pm.h"
  52
  53 #include <mach/powerdomain.h>
  54 #include <mach/clockdomain.h>
  55
  56 static void (*omap2_sram_idle)(void);
  57 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  58                                   void __iomem *sdrc_power);
  59
  60 static struct powerdomain *mpu_pwrdm;
  61 static struct powerdomain *core_pwrdm;
  62
  63 static struct clockdomain *dsp_clkdm;
  64 static struct clockdomain *gfx_clkdm;
  65
  66 static struct clk *osc_ck, *emul_ck;
  67
  68 static int omap2_fclks_active(void)
  69 {
  70         u32 f1, f2;
  71
  72         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  73         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  74         if (f1 | f2)
  75                 return 1;
  76         return 0;
  77 }
  78
  79 static void omap2_enter_full_retention(void)
  80 {
  81         u32 l;
  82         struct timespec ts_preidle, ts_postidle, ts_idle;
  83
  84         /* There is 1 reference hold for all children of the oscillator
  85          * clock, the following will remove it. If no one else uses the
  86          * oscillator itself it will be disabled if/when we enter retention
  87          * mode.
  88          */
  89         clk_disable(osc_ck);
  90
  91         /* Clear old wake-up events */
  92         /* REVISIT: These write to reserved bits? */
  93         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  94         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  95         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  96
  97         /*
  98          * Set MPU powerdomain's next power state to RETENTION;
  99          * preserve logic state during retention
 100          */
 101         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 102         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 103
 104         /* Workaround to kill USB */
 105         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 106         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 107
 108         omap2_gpio_prepare_for_retention();
 109
 110         if (omap2_pm_debug) {
 111                 omap2_pm_dump(0, 0, 0);
 112                 getnstimeofday(&ts_preidle);
 113         }
 114
 115         /* One last check for pending IRQs to avoid extra latency due
 116          * to sleeping unnecessarily. */
 117         if (omap_irq_pending())
 118                 goto no_sleep;
 119
 120         /* Jump to SRAM suspend code */
 121         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 122                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 123                            OMAP_SDRC_REGADDR(SDRC_POWER));
 124 no_sleep:
 125
 126         if (omap2_pm_debug) {
 127                 unsigned long long tmp;
 128
 129                 getnstimeofday(&ts_postidle);
 130                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 131                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 132                 omap2_pm_dump(0, 1, tmp);
 133         }
 134         omap2_gpio_resume_after_retention();
 135
 136         clk_enable(osc_ck);
 137
 138         /* clear CORE wake-up events */
 139         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 140         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 141
 142         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 143         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 144
 145         /* MPU domain wake events */
 146         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 147         if (l & 0x01)
 148                 prm_write_mod_reg(0x01, OCP_MOD,
 149                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 150         if (l & 0x20)
 151                 prm_write_mod_reg(0x20, OCP_MOD,
 152                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 153
 154         /* Mask future PRCM-to-MPU interrupts */
 155         prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 156 }
 157
 158 static int omap2_i2c_active(void)
 159 {
 160         u32 l;
 161
 162         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 163         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 164 }
 165
 166 static int sti_console_enabled;
 167
 168 static int omap2_allow_mpu_retention(void)
 169 {
 170         u32 l;
 171
 172         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 173         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 174         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 175                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 176                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 177                 return 0;
 178         /* Check for UART3. */
 179         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 180         if (l & OMAP24XX_EN_UART3)
 181                 return 0;
 182         if (sti_console_enabled)
 183                 return 0;
 184
 185         return 1;
 186 }
 187
 188 static void omap2_enter_mpu_retention(void)
 189 {
 190         int only_idle = 0;
 191         struct timespec ts_preidle, ts_postidle, ts_idle;
 192
 193         /* Putting MPU into the WFI state while a transfer is active
 194          * seems to cause the I2C block to timeout. Why? Good question. */
 195         if (omap2_i2c_active())
 196                 return;
 197
 198         /* The peripherals seem not to be able to wake up the MPU when
 199          * it is in retention mode. */
 200         if (omap2_allow_mpu_retention()) {
 201                 /* REVISIT: These write to reserved bits? */
 202                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 203                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 204                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 205
 206                 /* Try to enter MPU retention */
 207                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 208                                   OMAP_LOGICRETSTATE,
 209                                   MPU_MOD, PM_PWSTCTRL);
 210         } else {
 211                 /* Block MPU retention */
 212
 213                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 214                 only_idle = 1;
 215         }
 216
 217         if (omap2_pm_debug) {
 218                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 219                 getnstimeofday(&ts_preidle);
 220         }
 221
 222         omap2_sram_idle();
 223
 224         if (omap2_pm_debug) {
 225                 unsigned long long tmp;
 226
 227                 getnstimeofday(&ts_postidle);
 228                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 229                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 230                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
 231         }
 232 }
 233
 234 static int omap2_can_sleep(void)
 235 {
 236         if (omap2_fclks_active())
 237                 return 0;
 238         if (osc_ck->usecount > 1)
 239                 return 0;
 240         if (omap_dma_running())
 241                 return 0;
 242
 243         return 1;
 244 }
 245
 246 static void omap2_pm_idle(void)
 247 {
 248         local_irq_disable();
 249         local_fiq_disable();
 250
 251         if (!omap2_can_sleep()) {
 252                 if (omap_irq_pending())
 253                         goto out;
 254                 omap2_enter_mpu_retention();
 255                 goto out;
 256         }
 257
 258         if (omap_irq_pending())
 259                 goto out;
 260
 261         omap2_enter_full_retention();
 262
 263 out:
 264         local_fiq_enable();
 265         local_irq_enable();
 266 }
 267
 268 static int omap2_pm_prepare(void)
 269 {
 270         /* We cannot sleep in idle until we have resumed */
 271         disable_hlt();
 272         return 0;
 273 }
 274
 275 static int omap2_pm_suspend(void)
 276 {
 277         u32 wken_wkup, mir1;
 278
 279         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 280         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 281
 282         /* Mask GPT1 */
 283         mir1 = omap_readl(0x480fe0a4);
 284         omap_writel(1 << 5, 0x480fe0ac);
 285
 286         omap2_enter_full_retention();
 287
 288         omap_writel(mir1, 0x480fe0a4);
 289         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 290
 291         return 0;
 292 }
 293
 294 static int omap2_pm_enter(suspend_state_t state)
 295 {
 296         int ret = 0;
 297
 298         switch (state) {
 299         case PM_SUSPEND_STANDBY:
 300         case PM_SUSPEND_MEM:
 301                 ret = omap2_pm_suspend();
 302                 break;
 303         default:
 304                 ret = -EINVAL;
 305         }
 306
 307         return ret;
 308 }
 309
 310 static void omap2_pm_finish(void)
 311 {
 312         enable_hlt();
 313 }
 314
 315 static struct platform_suspend_ops omap_pm_ops = {
 316         .prepare        = omap2_pm_prepare,
 317         .enter          = omap2_pm_enter,
 318         .finish         = omap2_pm_finish,
 319         .valid          = suspend_valid_only_mem,
 320 };
 321
 322 static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
 323 {
 324         omap2_clkdm_allow_idle(clkdm);
 325         return 0;
 326 }
 327
 328 static void __init prcm_setup_regs(void)
 329 {
 330         int i, num_mem_banks;
 331         struct powerdomain *pwrdm;
 332
 333         /* Enable autoidle */
 334         prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
 335                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 336
 337         /* Set all domain wakeup dependencies */
 338         prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
 339         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 340         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 341         prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
 342         if (cpu_is_omap2430())
 343                 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
 344
 345         /*
 346          * Set CORE powerdomain memory banks to retain their contents
 347          * during RETENTION
 348          */
 349         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 350         for (i = 0; i < num_mem_banks; i++)
 351                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 352
 353         /* Set CORE powerdomain's next power state to RETENTION */
 354         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 355
 356         /*
 357          * Set MPU powerdomain's next power state to RETENTION;
 358          * preserve logic state during retention
 359          */
 360         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 361         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 362
 363         /* Force-power down DSP, GFX powerdomains */
 364
 365         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 366         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 367         omap2_clkdm_sleep(dsp_clkdm);
 368
 369         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 370         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 371         omap2_clkdm_sleep(gfx_clkdm);
 372
 373         /* Enable clockdomain hardware-supervised control for all clkdms */
 374         clkdm_for_each(_pm_clkdm_enable_hwsup);
 375
 376         /* Enable clock autoidle for all domains */
 377         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 378                          OMAP24XX_AUTO_MAILBOXES |
 379                          OMAP24XX_AUTO_WDT4 |
 380                          OMAP2420_AUTO_WDT3 |
 381                          OMAP24XX_AUTO_MSPRO |
 382                          OMAP2420_AUTO_MMC |
 383                          OMAP24XX_AUTO_FAC |
 384                          OMAP2420_AUTO_EAC |
 385                          OMAP24XX_AUTO_HDQ |
 386                          OMAP24XX_AUTO_UART2 |
 387                          OMAP24XX_AUTO_UART1 |
 388                          OMAP24XX_AUTO_I2C2 |
 389                          OMAP24XX_AUTO_I2C1 |
 390                          OMAP24XX_AUTO_MCSPI2 |
 391                          OMAP24XX_AUTO_MCSPI1 |
 392                          OMAP24XX_AUTO_MCBSP2 |
 393                          OMAP24XX_AUTO_MCBSP1 |
 394                          OMAP24XX_AUTO_GPT12 |
 395                          OMAP24XX_AUTO_GPT11 |
 396                          OMAP24XX_AUTO_GPT10 |
 397                          OMAP24XX_AUTO_GPT9 |
 398                          OMAP24XX_AUTO_GPT8 |
 399                          OMAP24XX_AUTO_GPT7 |
 400                          OMAP24XX_AUTO_GPT6 |
 401                          OMAP24XX_AUTO_GPT5 |
 402                          OMAP24XX_AUTO_GPT4 |
 403                          OMAP24XX_AUTO_GPT3 |
 404                          OMAP24XX_AUTO_GPT2 |
 405                          OMAP2420_AUTO_VLYNQ |
 406                          OMAP24XX_AUTO_DSS,
 407                          CORE_MOD, CM_AUTOIDLE1);
 408         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 409                          OMAP24XX_AUTO_SSI |
 410                          OMAP24XX_AUTO_USB,
 411                          CORE_MOD, CM_AUTOIDLE2);
 412         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 413                          OMAP24XX_AUTO_GPMC |
 414                          OMAP24XX_AUTO_SDMA,
 415                          CORE_MOD, CM_AUTOIDLE3);
 416         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 417                          OMAP24XX_AUTO_AES |
 418                          OMAP24XX_AUTO_RNG |
 419                          OMAP24XX_AUTO_SHA |
 420                          OMAP24XX_AUTO_DES,
 421                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 422
 423         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 424
 425         /* Put DPLL and both APLLs into autoidle mode */
 426         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 427                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 428                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 429                          PLL_MOD, CM_AUTOIDLE);
 430
 431         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 432                          OMAP24XX_AUTO_WDT1 |
 433                          OMAP24XX_AUTO_MPU_WDT |
 434                          OMAP24XX_AUTO_GPIOS |
 435                          OMAP24XX_AUTO_32KSYNC |
 436                          OMAP24XX_AUTO_GPT1,
 437                          WKUP_MOD, CM_AUTOIDLE);
 438
 439         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 440          * stabilisation */
 441         prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 442                           OMAP2_PRCM_CLKSSETUP_OFFSET);
 443
 444         /* Configure automatic voltage transition */
 445         prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 446                           OMAP2_PRCM_VOLTSETUP_OFFSET);
 447         prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
 448                           (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 449                           OMAP24XX_MEMRETCTRL |
 450                           (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 451                           (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 452                           OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 453
 454         /* Enable wake-up events */
 455         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 456                           WKUP_MOD, PM_WKEN);
 457 }
 458
 459 int __init omap2_pm_init(void)
 460 {
 461         u32 l;
 462
 463         if (!cpu_is_omap24xx())
 464                 return -ENODEV;
 465
 466         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 467         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 468         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 469
 470         /* Look up important powerdomains, clockdomains */
 471
 472         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 473         if (!mpu_pwrdm)
 474                 pr_err("PM: mpu_pwrdm not found\n");
 475
 476         core_pwrdm = pwrdm_lookup("core_pwrdm");
 477         if (!core_pwrdm)
 478                 pr_err("PM: core_pwrdm not found\n");
 479
 480         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 481         if (!dsp_clkdm)
 482                 pr_err("PM: mpu_clkdm not found\n");
 483
 484         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 485         if (!gfx_clkdm)
 486                 pr_err("PM: gfx_clkdm not found\n");
 487
 488
 489         osc_ck = clk_get(NULL, "osc_ck");
 490         if (IS_ERR(osc_ck)) {
 491                 printk(KERN_ERR "could not get osc_ck\n");
 492                 return -ENODEV;
 493         }
 494
 495         if (cpu_is_omap242x()) {
 496                 emul_ck = clk_get(NULL, "emul_ck");
 497                 if (IS_ERR(emul_ck)) {
 498                         printk(KERN_ERR "could not get emul_ck\n");
 499                         clk_put(osc_ck);
 500                         return -ENODEV;
 501                 }
 502         }
 503
 504         prcm_setup_regs();
 505
 506         /* Hack to prevent MPU retention when STI console is enabled. */
 507         {
 508                 const struct omap_sti_console_config *sti;
 509
 510                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 511                                       struct omap_sti_console_config);
 512                 if (sti != NULL && sti->enable)
 513                         sti_console_enabled = 1;
 514         }
 515
 516         /*
 517          * We copy the assembler sleep/wakeup routines to SRAM.
 518          * These routines need to be in SRAM as that's the only
 519          * memory the MPU can see when it wakes up.
 520          */
 521         if (cpu_is_omap24xx()) {
 522                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 523                                                  omap24xx_idle_loop_suspend_sz);
 524
 525                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 526                                                     omap24xx_cpu_suspend_sz);
 527         }
 528
 529         suspend_set_ops(&omap_pm_ops);
 530         pm_idle = omap2_pm_idle;
 531
 532         return 0;
 533 }
 534
 535 late_initcall(omap2_pm_init);