2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/console.h>
33 #include <plat/sram.h>
34 #include <plat/clockdomain.h>
35 #include <plat/powerdomain.h>
36 #include <plat/serial.h>
37 #include <plat/sdrc.h>
38 #include <plat/prcm.h>
39 #include <plat/gpmc.h>
42 #include <asm/tlbflush.h>
45 #include "cm-regbits-34xx.h"
46 #include "prm-regbits-34xx.h"
53 /* Scratchpad offsets */
54 #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
55 #define OMAP343X_TABLE_VALUE_OFFSET 0xc0
56 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
59 struct powerdomain *pwrdm;
64 struct list_head node;
67 static LIST_HEAD(pwrst_list);
69 static void (*_omap_sram_idle)(u32 *addr, int save_state);
71 static int (*_omap_save_secure_sram)(u32 *addr);
73 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
74 static struct powerdomain *core_pwrdm, *per_pwrdm;
75 static struct powerdomain *cam_pwrdm;
77 static inline void omap3_per_save_context(void)
79 omap_gpio_save_context();
82 static inline void omap3_per_restore_context(void)
84 omap_gpio_restore_context();
87 static void omap3_enable_io_chain(void)
91 if (omap_rev() >= OMAP3430_REV_ES3_1) {
92 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
94 /* Do a readback to assure write has been done */
95 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
97 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
98 OMAP3430_ST_IO_CHAIN_MASK)) {
100 if (timeout > 1000) {
101 printk(KERN_ERR "Wake up daisy chain "
102 "activation failed.\n");
105 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
111 static void omap3_disable_io_chain(void)
113 if (omap_rev() >= OMAP3430_REV_ES3_1)
114 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
118 static void omap3_core_save_context(void)
120 u32 control_padconf_off;
122 /* Save the padconf registers */
123 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
124 control_padconf_off |= START_PADCONF_SAVE;
125 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
126 /* wait for the save to complete */
127 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
128 & PADCONF_SAVE_DONE))
132 * Force write last pad into memory, as this can fail in some
133 * cases according to erratas 1.157, 1.185
135 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
136 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
138 /* Save the Interrupt controller context */
139 omap_intc_save_context();
140 /* Save the GPMC context */
141 omap3_gpmc_save_context();
142 /* Save the system control module context, padconf already save above*/
143 omap3_control_save_context();
144 omap_dma_global_context_save();
147 static void omap3_core_restore_context(void)
149 /* Restore the control module context, padconf restored by h/w */
150 omap3_control_restore_context();
151 /* Restore the GPMC context */
152 omap3_gpmc_restore_context();
153 /* Restore the interrupt controller context */
154 omap_intc_restore_context();
155 omap_dma_global_context_restore();
159 * FIXME: This function should be called before entering off-mode after
160 * OMAP3 secure services have been accessed. Currently it is only called
161 * once during boot sequence, but this works as we are not using secure
164 static void omap3_save_secure_ram_context(u32 target_mpu_state)
168 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
170 * MPU next state must be set to POWER_ON temporarily,
171 * otherwise the WFI executed inside the ROM code
172 * will hang the system.
174 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
175 ret = _omap_save_secure_sram((u32 *)
176 __pa(omap3_secure_ram_storage));
177 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
178 /* Following is for error tracking, it should not happen */
180 printk(KERN_ERR "save_secure_sram() returns %08x\n",
189 * PRCM Interrupt Handler Helper Function
191 * The purpose of this function is to clear any wake-up events latched
192 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
193 * may occur whilst attempting to clear a PM_WKST_x register and thus
194 * set another bit in this register. A while loop is used to ensure
195 * that any peripheral wake-up events occurring while attempting to
196 * clear the PM_WKST_x are detected and cleared.
198 static int prcm_clear_mod_irqs(s16 module, u8 regs)
200 u32 wkst, fclk, iclk, clken;
201 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
202 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
203 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
204 u16 grpsel_off = (regs == 3) ?
205 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
208 wkst = prm_read_mod_reg(module, wkst_off);
209 wkst &= prm_read_mod_reg(module, grpsel_off);
211 iclk = cm_read_mod_reg(module, iclk_off);
212 fclk = cm_read_mod_reg(module, fclk_off);
215 cm_set_mod_reg_bits(clken, module, iclk_off);
217 * For USBHOST, we don't know whether HOST1 or
218 * HOST2 woke us up, so enable both f-clocks
220 if (module == OMAP3430ES2_USBHOST_MOD)
221 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
222 cm_set_mod_reg_bits(clken, module, fclk_off);
223 prm_write_mod_reg(wkst, module, wkst_off);
224 wkst = prm_read_mod_reg(module, wkst_off);
227 cm_write_mod_reg(iclk, module, iclk_off);
228 cm_write_mod_reg(fclk, module, fclk_off);
234 static int _prcm_int_handle_wakeup(void)
238 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
239 c += prcm_clear_mod_irqs(CORE_MOD, 1);
240 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
241 if (omap_rev() > OMAP3430_REV_ES1_0) {
242 c += prcm_clear_mod_irqs(CORE_MOD, 3);
243 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
250 * PRCM Interrupt Handler
252 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
253 * interrupts from the PRCM for the MPU. These bits must be cleared in
254 * order to clear the PRCM interrupt. The PRCM interrupt handler is
255 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
256 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
257 * register indicates that a wake-up event is pending for the MPU and
258 * this bit can only be cleared if the all the wake-up events latched
259 * in the various PM_WKST_x registers have been cleared. The interrupt
260 * handler is implemented using a do-while loop so that if a wake-up
261 * event occurred during the processing of the prcm interrupt handler
262 * (setting a bit in the corresponding PM_WKST_x register and thus
263 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
264 * this would be handled.
266 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
268 u32 irqenable_mpu, irqstatus_mpu;
271 irqenable_mpu = prm_read_mod_reg(OCP_MOD,
272 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
273 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
274 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
275 irqstatus_mpu &= irqenable_mpu;
278 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
279 OMAP3430_IO_ST_MASK)) {
280 c = _prcm_int_handle_wakeup();
283 * Is the MPU PRCM interrupt handler racing with the
284 * IVA2 PRCM interrupt handler ?
286 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
287 "but no wakeup sources are marked\n");
289 /* XXX we need to expand our PRCM interrupt handler */
290 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
291 "no code to handle it (%08x)\n", irqstatus_mpu);
294 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
295 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
297 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
298 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
299 irqstatus_mpu &= irqenable_mpu;
301 } while (irqstatus_mpu);
306 static void restore_control_register(u32 val)
308 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
311 /* Function to restore the table entry that was modified for enabling MMU */
312 static void restore_table_entry(void)
314 void __iomem *scratchpad_address;
315 u32 previous_value, control_reg_value;
318 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
320 /* Get address of entry that was modified */
321 address = (u32 *)__raw_readl(scratchpad_address +
322 OMAP343X_TABLE_ADDRESS_OFFSET);
323 /* Get the previous value which needs to be restored */
324 previous_value = __raw_readl(scratchpad_address +
325 OMAP343X_TABLE_VALUE_OFFSET);
326 address = __va(address);
327 *address = previous_value;
329 control_reg_value = __raw_readl(scratchpad_address
330 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
331 /* This will enable caches and prediction */
332 restore_control_register(control_reg_value);
335 void omap_sram_idle(void)
337 /* Variable to tell what needs to be saved and restored
338 * in omap_sram_idle*/
339 /* save_state = 0 => Nothing to save and restored */
340 /* save_state = 1 => Only L1 and logic lost */
341 /* save_state = 2 => Only L2 lost */
342 /* save_state = 3 => L1, L2 and logic lost */
344 int mpu_next_state = PWRDM_POWER_ON;
345 int per_next_state = PWRDM_POWER_ON;
346 int core_next_state = PWRDM_POWER_ON;
347 int core_prev_state, per_prev_state;
350 if (!_omap_sram_idle)
353 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
354 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
355 pwrdm_clear_all_prev_pwrst(core_pwrdm);
356 pwrdm_clear_all_prev_pwrst(per_pwrdm);
358 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
359 switch (mpu_next_state) {
361 case PWRDM_POWER_RET:
362 /* No need to save context */
365 case PWRDM_POWER_OFF:
370 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
373 pwrdm_pre_transition();
376 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
377 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
379 /* Enable IO-PAD and IO-CHAIN wakeups */
380 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
381 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
382 if (omap3_has_io_wakeup() &&
383 (per_next_state < PWRDM_POWER_ON ||
384 core_next_state < PWRDM_POWER_ON)) {
385 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
386 omap3_enable_io_chain();
389 /* Block console output in case it is on one of the OMAP UARTs */
390 if (per_next_state < PWRDM_POWER_ON ||
391 core_next_state < PWRDM_POWER_ON)
392 if (try_acquire_console_sem())
393 goto console_still_active;
396 if (per_next_state < PWRDM_POWER_ON) {
397 omap_uart_prepare_idle(2);
398 omap_uart_prepare_idle(3);
399 omap2_gpio_prepare_for_idle(per_next_state);
400 if (per_next_state == PWRDM_POWER_OFF)
401 omap3_per_save_context();
405 if (core_next_state < PWRDM_POWER_ON) {
406 omap_uart_prepare_idle(0);
407 omap_uart_prepare_idle(1);
408 if (core_next_state == PWRDM_POWER_OFF) {
409 omap3_core_save_context();
410 omap3_prcm_save_context();
414 omap3_intc_prepare_idle();
417 * On EMU/HS devices ROM code restores a SRDC value
418 * from scratchpad which has automatic self refresh on timeout
419 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
420 * Hence store/restore the SDRC_POWER register here.
422 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
423 omap_type() != OMAP2_DEVICE_TYPE_GP &&
424 core_next_state == PWRDM_POWER_OFF)
425 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
428 * omap3_arm_context is the location where ARM registers
429 * get saved. The restore path then reads from this
430 * location and restores them back.
432 _omap_sram_idle(omap3_arm_context, save_state);
435 /* Restore normal SDRC POWER settings */
436 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
437 omap_type() != OMAP2_DEVICE_TYPE_GP &&
438 core_next_state == PWRDM_POWER_OFF)
439 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
441 /* Restore table entry modified during MMU restoration */
442 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
443 restore_table_entry();
446 if (core_next_state < PWRDM_POWER_ON) {
447 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
448 if (core_prev_state == PWRDM_POWER_OFF) {
449 omap3_core_restore_context();
450 omap3_prcm_restore_context();
451 omap3_sram_restore_context();
452 omap2_sms_restore_context();
454 omap_uart_resume_idle(0);
455 omap_uart_resume_idle(1);
456 if (core_next_state == PWRDM_POWER_OFF)
457 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
459 OMAP3_PRM_VOLTCTRL_OFFSET);
461 omap3_intc_resume_idle();
464 if (per_next_state < PWRDM_POWER_ON) {
465 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
466 omap2_gpio_resume_after_idle();
467 if (per_prev_state == PWRDM_POWER_OFF)
468 omap3_per_restore_context();
469 omap_uart_resume_idle(2);
470 omap_uart_resume_idle(3);
473 release_console_sem();
475 console_still_active:
476 /* Disable IO-PAD and IO-CHAIN wakeup */
477 if (omap3_has_io_wakeup() &&
478 (per_next_state < PWRDM_POWER_ON ||
479 core_next_state < PWRDM_POWER_ON)) {
480 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
481 omap3_disable_io_chain();
484 pwrdm_post_transition();
486 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
489 int omap3_can_sleep(void)
491 if (!sleep_while_idle)
493 if (!omap_uart_can_sleep())
498 static void omap3_pm_idle(void)
503 if (!omap3_can_sleep())
506 if (omap_irq_pending() || need_resched())
516 #ifdef CONFIG_SUSPEND
517 static suspend_state_t suspend_state;
519 static int omap3_pm_prepare(void)
525 static int omap3_pm_suspend(void)
527 struct power_state *pwrst;
530 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
531 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
532 wakeup_timer_milliseconds);
534 /* Read current next_pwrsts */
535 list_for_each_entry(pwrst, &pwrst_list, node)
536 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
537 /* Set ones wanted by suspend */
538 list_for_each_entry(pwrst, &pwrst_list, node) {
539 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
541 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
545 omap_uart_prepare_suspend();
546 omap3_intc_suspend();
551 /* Restore next_pwrsts */
552 list_for_each_entry(pwrst, &pwrst_list, node) {
553 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
554 if (state > pwrst->next_state) {
555 printk(KERN_INFO "Powerdomain (%s) didn't enter "
557 pwrst->pwrdm->name, pwrst->next_state);
560 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
563 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
565 printk(KERN_INFO "Successfully put all powerdomains "
566 "to target state\n");
571 static int omap3_pm_enter(suspend_state_t unused)
575 switch (suspend_state) {
576 case PM_SUSPEND_STANDBY:
578 ret = omap3_pm_suspend();
587 static void omap3_pm_finish(void)
592 /* Hooks to enable / disable UART interrupts during suspend */
593 static int omap3_pm_begin(suspend_state_t state)
595 suspend_state = state;
596 omap_uart_enable_irqs(0);
600 static void omap3_pm_end(void)
602 suspend_state = PM_SUSPEND_ON;
603 omap_uart_enable_irqs(1);
607 static struct platform_suspend_ops omap_pm_ops = {
608 .begin = omap3_pm_begin,
610 .prepare = omap3_pm_prepare,
611 .enter = omap3_pm_enter,
612 .finish = omap3_pm_finish,
613 .valid = suspend_valid_only_mem,
615 #endif /* CONFIG_SUSPEND */
619 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
622 * In cases where IVA2 is activated by bootcode, it may prevent
623 * full-chip retention or off-mode because it is not idle. This
624 * function forces the IVA2 into idle state so it can go
625 * into retention/off and thus allow full-chip retention/off.
628 static void __init omap3_iva_idle(void)
630 /* ensure IVA2 clock is disabled */
631 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
633 /* if no clock activity, nothing else to do */
634 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
635 OMAP3430_CLKACTIVITY_IVA2_MASK))
639 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
640 OMAP3430_RST2_IVA2_MASK |
641 OMAP3430_RST3_IVA2_MASK,
642 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
644 /* Enable IVA2 clock */
645 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
646 OMAP3430_IVA2_MOD, CM_FCLKEN);
648 /* Set IVA2 boot mode to 'idle' */
649 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
650 OMAP343X_CONTROL_IVA2_BOOTMOD);
653 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
655 /* Disable IVA2 clock */
656 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
659 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
660 OMAP3430_RST2_IVA2_MASK |
661 OMAP3430_RST3_IVA2_MASK,
662 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
665 static void __init omap3_d2d_idle(void)
669 /* In a stand alone OMAP3430 where there is not a stacked
670 * modem for the D2D Idle Ack and D2D MStandby must be pulled
671 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
672 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
673 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
674 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
676 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
678 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
680 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
683 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
684 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
685 CORE_MOD, OMAP2_RM_RSTCTRL);
686 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
689 static void __init prcm_setup_regs(void)
691 u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
692 OMAP3630_AUTO_UART4_MASK : 0;
693 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
694 OMAP3630_EN_UART4_MASK : 0;
695 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
696 OMAP3630_GRPSEL_UART4_MASK : 0;
699 /* XXX Reset all wkdeps. This should be done when initializing
701 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
702 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
703 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
704 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
705 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
706 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
707 if (omap_rev() > OMAP3430_REV_ES1_0) {
708 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
709 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
711 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
714 * Enable interface clock autoidle for all modules.
715 * Note that in the long run this should be done by clockfw
718 OMAP3430_AUTO_MODEM_MASK |
719 OMAP3430ES2_AUTO_MMC3_MASK |
720 OMAP3430ES2_AUTO_ICR_MASK |
721 OMAP3430_AUTO_AES2_MASK |
722 OMAP3430_AUTO_SHA12_MASK |
723 OMAP3430_AUTO_DES2_MASK |
724 OMAP3430_AUTO_MMC2_MASK |
725 OMAP3430_AUTO_MMC1_MASK |
726 OMAP3430_AUTO_MSPRO_MASK |
727 OMAP3430_AUTO_HDQ_MASK |
728 OMAP3430_AUTO_MCSPI4_MASK |
729 OMAP3430_AUTO_MCSPI3_MASK |
730 OMAP3430_AUTO_MCSPI2_MASK |
731 OMAP3430_AUTO_MCSPI1_MASK |
732 OMAP3430_AUTO_I2C3_MASK |
733 OMAP3430_AUTO_I2C2_MASK |
734 OMAP3430_AUTO_I2C1_MASK |
735 OMAP3430_AUTO_UART2_MASK |
736 OMAP3430_AUTO_UART1_MASK |
737 OMAP3430_AUTO_GPT11_MASK |
738 OMAP3430_AUTO_GPT10_MASK |
739 OMAP3430_AUTO_MCBSP5_MASK |
740 OMAP3430_AUTO_MCBSP1_MASK |
741 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
742 OMAP3430_AUTO_MAILBOXES_MASK |
743 OMAP3430_AUTO_OMAPCTRL_MASK |
744 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
745 OMAP3430_AUTO_HSOTGUSB_MASK |
746 OMAP3430_AUTO_SAD2D_MASK |
747 OMAP3430_AUTO_SSI_MASK,
748 CORE_MOD, CM_AUTOIDLE1);
751 OMAP3430_AUTO_PKA_MASK |
752 OMAP3430_AUTO_AES1_MASK |
753 OMAP3430_AUTO_RNG_MASK |
754 OMAP3430_AUTO_SHA11_MASK |
755 OMAP3430_AUTO_DES1_MASK,
756 CORE_MOD, CM_AUTOIDLE2);
758 if (omap_rev() > OMAP3430_REV_ES1_0) {
760 OMAP3430_AUTO_MAD2D_MASK |
761 OMAP3430ES2_AUTO_USBTLL_MASK,
762 CORE_MOD, CM_AUTOIDLE3);
766 OMAP3430_AUTO_WDT2_MASK |
767 OMAP3430_AUTO_WDT1_MASK |
768 OMAP3430_AUTO_GPIO1_MASK |
769 OMAP3430_AUTO_32KSYNC_MASK |
770 OMAP3430_AUTO_GPT12_MASK |
771 OMAP3430_AUTO_GPT1_MASK,
772 WKUP_MOD, CM_AUTOIDLE);
775 OMAP3430_AUTO_DSS_MASK,
780 OMAP3430_AUTO_CAM_MASK,
785 omap3630_auto_uart4_mask |
786 OMAP3430_AUTO_GPIO6_MASK |
787 OMAP3430_AUTO_GPIO5_MASK |
788 OMAP3430_AUTO_GPIO4_MASK |
789 OMAP3430_AUTO_GPIO3_MASK |
790 OMAP3430_AUTO_GPIO2_MASK |
791 OMAP3430_AUTO_WDT3_MASK |
792 OMAP3430_AUTO_UART3_MASK |
793 OMAP3430_AUTO_GPT9_MASK |
794 OMAP3430_AUTO_GPT8_MASK |
795 OMAP3430_AUTO_GPT7_MASK |
796 OMAP3430_AUTO_GPT6_MASK |
797 OMAP3430_AUTO_GPT5_MASK |
798 OMAP3430_AUTO_GPT4_MASK |
799 OMAP3430_AUTO_GPT3_MASK |
800 OMAP3430_AUTO_GPT2_MASK |
801 OMAP3430_AUTO_MCBSP4_MASK |
802 OMAP3430_AUTO_MCBSP3_MASK |
803 OMAP3430_AUTO_MCBSP2_MASK,
807 if (omap_rev() > OMAP3430_REV_ES1_0) {
809 OMAP3430ES2_AUTO_USBHOST_MASK,
810 OMAP3430ES2_USBHOST_MOD,
814 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
817 * Set all plls to autoidle. This is needed until autoidle is
820 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
821 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
822 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
825 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
826 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
829 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
834 * Enable control of expternal oscillator through
835 * sys_clkreq. In the long run clock framework should
838 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
839 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
841 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
843 /* setup wakup source */
844 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
845 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
847 /* No need to write EN_IO, that is always enabled */
848 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
849 OMAP3430_GRPSEL_GPT1_MASK |
850 OMAP3430_GRPSEL_GPT12_MASK,
851 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
852 /* For some reason IO doesn't generate wakeup event even if
853 * it is selected to mpu wakeup goup */
854 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
855 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
857 /* Enable PM_WKEN to support DSS LPR */
858 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
859 OMAP3430_DSS_MOD, PM_WKEN);
861 /* Enable wakeups in PER */
862 prm_write_mod_reg(omap3630_en_uart4_mask |
863 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
864 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
865 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
866 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
867 OMAP3430_EN_MCBSP4_MASK,
868 OMAP3430_PER_MOD, PM_WKEN);
869 /* and allow them to wake up MPU */
870 prm_write_mod_reg(omap3630_grpsel_uart4_mask |
871 OMAP3430_GRPSEL_GPIO2_MASK |
872 OMAP3430_GRPSEL_GPIO3_MASK |
873 OMAP3430_GRPSEL_GPIO4_MASK |
874 OMAP3430_GRPSEL_GPIO5_MASK |
875 OMAP3430_GRPSEL_GPIO6_MASK |
876 OMAP3430_GRPSEL_UART3_MASK |
877 OMAP3430_GRPSEL_MCBSP2_MASK |
878 OMAP3430_GRPSEL_MCBSP3_MASK |
879 OMAP3430_GRPSEL_MCBSP4_MASK,
880 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
882 /* Don't attach IVA interrupts */
883 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
884 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
885 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
886 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
888 /* Clear any pending 'reset' flags */
889 prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
890 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
891 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
892 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
893 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
894 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
895 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
897 /* Clear any pending PRCM interrupts */
898 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
904 void omap3_pm_off_mode_enable(int enable)
906 struct power_state *pwrst;
910 state = PWRDM_POWER_OFF;
912 state = PWRDM_POWER_RET;
914 #ifdef CONFIG_CPU_IDLE
915 omap3_cpuidle_update_states();
918 list_for_each_entry(pwrst, &pwrst_list, node) {
919 pwrst->next_state = state;
920 omap_set_pwrdm_state(pwrst->pwrdm, state);
924 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
926 struct power_state *pwrst;
928 list_for_each_entry(pwrst, &pwrst_list, node) {
929 if (pwrst->pwrdm == pwrdm)
930 return pwrst->next_state;
935 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
937 struct power_state *pwrst;
939 list_for_each_entry(pwrst, &pwrst_list, node) {
940 if (pwrst->pwrdm == pwrdm) {
941 pwrst->next_state = state;
948 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
950 struct power_state *pwrst;
955 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
958 pwrst->pwrdm = pwrdm;
959 pwrst->next_state = PWRDM_POWER_RET;
960 list_add(&pwrst->node, &pwrst_list);
962 if (pwrdm_has_hdwr_sar(pwrdm))
963 pwrdm_enable_hdwr_sar(pwrdm);
965 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
969 * Enable hw supervised mode for all clockdomains if it's
970 * supported. Initiate sleep transition for other clockdomains, if
973 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
975 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
976 omap2_clkdm_allow_idle(clkdm);
977 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
978 atomic_read(&clkdm->usecount) == 0)
979 omap2_clkdm_sleep(clkdm);
983 void omap_push_sram_idle(void)
985 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
986 omap34xx_cpu_suspend_sz);
987 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
988 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
989 save_secure_ram_context_sz);
992 static int __init omap3_pm_init(void)
994 struct power_state *pwrst, *tmp;
995 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
998 if (!cpu_is_omap34xx())
1001 printk(KERN_ERR "Power Management for TI OMAP3.\n");
1003 /* XXX prcm_setup_regs needs to be before enabling hw
1004 * supervised mode for powerdomains */
1007 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1008 (irq_handler_t)prcm_interrupt_handler,
1009 IRQF_DISABLED, "prcm", NULL);
1011 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1012 INT_34XX_PRCM_MPU_IRQ);
1016 ret = pwrdm_for_each(pwrdms_setup, NULL);
1018 printk(KERN_ERR "Failed to setup powerdomains\n");
1022 (void) clkdm_for_each(clkdms_setup, NULL);
1024 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1025 if (mpu_pwrdm == NULL) {
1026 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1030 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1031 per_pwrdm = pwrdm_lookup("per_pwrdm");
1032 core_pwrdm = pwrdm_lookup("core_pwrdm");
1033 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1035 neon_clkdm = clkdm_lookup("neon_clkdm");
1036 mpu_clkdm = clkdm_lookup("mpu_clkdm");
1037 per_clkdm = clkdm_lookup("per_clkdm");
1038 core_clkdm = clkdm_lookup("core_clkdm");
1040 omap_push_sram_idle();
1041 #ifdef CONFIG_SUSPEND
1042 suspend_set_ops(&omap_pm_ops);
1043 #endif /* CONFIG_SUSPEND */
1045 pm_idle = omap3_pm_idle;
1048 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1049 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1050 omap3_secure_ram_storage =
1051 kmalloc(0x803F, GFP_KERNEL);
1052 if (!omap3_secure_ram_storage)
1053 printk(KERN_ERR "Memory allocation failed when"
1054 "allocating for secure sram context\n");
1056 local_irq_disable();
1057 local_fiq_disable();
1059 omap_dma_global_context_save();
1060 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1061 omap_dma_global_context_restore();
1067 omap3_save_scratchpad_contents();
1071 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1072 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1073 list_del(&pwrst->node);
1079 late_initcall(omap3_pm_init);